2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2006-2015 LSI Corp.
5 * Copyright (c) 2013-2015 Avago Technologies
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9 * modification, are permitted provided that the following conditions
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29 * Avago Technologies (LSI) MPT-Fusion Host Adapter FreeBSD
35 * Copyright (c) 2006-2015 LSI Corporation.
36 * Copyright (c) 2013-2015 Avago Technologies
40 * Title: MPI Configuration messages and pages
41 * Creation Date: November 10, 2006
43 * mpi2_cnfg.h Version: 02.00.17
48 * Date Version Description
49 * -------- -------- ------------------------------------------------------
50 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
51 * 06-04-07 02.00.01 Added defines for SAS IO Unit Page 2 PhyFlags.
52 * Added Manufacturing Page 11.
53 * Added MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE
55 * 06-26-07 02.00.02 Adding generic structure for product-specific
56 * Manufacturing pages: MPI2_CONFIG_PAGE_MANUFACTURING_PS.
57 * Rework of BIOS Page 2 configuration page.
58 * Fixed MPI2_BIOSPAGE2_BOOT_DEVICE to be a union of the
60 * Added configuration pages IOC Page 8 and Driver
61 * Persistent Mapping Page 0.
62 * 08-31-07 02.00.03 Modified configuration pages dealing with Integrated
63 * RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1,
64 * RAID Physical Disk Pages 0 and 1, RAID Configuration
66 * Added new value for AccessStatus field of SAS Device
67 * Page 0 (_SATA_NEEDS_INITIALIZATION).
68 * 10-31-07 02.00.04 Added missing SEPDevHandle field to
69 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0.
70 * 12-18-07 02.00.05 Modified IO Unit Page 0 to use 32-bit version fields for
72 * Modified IOC Page 7 to use masks and added field for
73 * SASBroadcastPrimitiveMasks.
74 * Added MPI2_CONFIG_PAGE_BIOS_4.
75 * Added MPI2_CONFIG_PAGE_LOG_0.
76 * 02-29-08 02.00.06 Modified various names to make them 32-character unique.
77 * Added SAS Device IDs.
78 * Updated Integrated RAID configuration pages including
79 * Manufacturing Page 4, IOC Page 6, and RAID Configuration
81 * 05-21-08 02.00.07 Added define MPI2_MANPAGE4_MIX_SSD_SAS_SATA.
82 * Added define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION.
83 * Fixed define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING.
84 * Added missing MaxNumRoutedSasAddresses field to
85 * MPI2_CONFIG_PAGE_EXPANDER_0.
86 * Added SAS Port Page 0.
87 * Modified structure layout for
88 * MPI2_CONFIG_PAGE_DRIVER_MAPPING_0.
89 * 06-27-08 02.00.08 Changed MPI2_CONFIG_PAGE_RD_PDISK_1 to use
90 * MPI2_RAID_PHYS_DISK1_PATH_MAX to size the array.
91 * 10-02-08 02.00.09 Changed MPI2_RAID_PGAD_CONFIGNUM_MASK from 0x0000FFFF
93 * Added two new values for the Physical Disk Coercion Size
94 * bits in the Flags field of Manufacturing Page 4.
95 * Added product-specific Manufacturing pages 16 to 31.
96 * Modified Flags bits for controlling write cache on SATA
97 * drives in IO Unit Page 1.
98 * Added new bit to AdditionalControlFlags of SAS IO Unit
99 * Page 1 to control Invalid Topology Correction.
100 * Added additional defines for RAID Volume Page 0
101 * VolumeStatusFlags field.
102 * Modified meaning of RAID Volume Page 0 VolumeSettings
103 * define for auto-configure of hot-swap drives.
104 * Added SupportedPhysDisks field to RAID Volume Page 1 and
105 * added related defines.
106 * Added PhysDiskAttributes field (and related defines) to
107 * RAID Physical Disk Page 0.
108 * Added MPI2_SAS_PHYINFO_PHY_VACANT define.
109 * Added three new DiscoveryStatus bits for SAS IO Unit
110 * Page 0 and SAS Expander Page 0.
111 * Removed multiplexing information from SAS IO Unit pages.
112 * Added BootDeviceWaitTime field to SAS IO Unit Page 4.
113 * Removed Zone Address Resolved bit from PhyInfo and from
114 * Expander Page 0 Flags field.
115 * Added two new AccessStatus values to SAS Device Page 0
116 * for indicating routing problems. Added 3 reserved words
118 * 01-19-09 02.00.10 Fixed defines for GPIOVal field of IO Unit Page 3.
119 * Inserted missing reserved field into structure for IOC
121 * Added more pending task bits to RAID Volume Page 0
122 * VolumeStatusFlags defines.
123 * Added MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED define.
124 * Added a new DiscoveryStatus bit for SAS IO Unit Page 0
125 * and SAS Expander Page 0 to flag a downstream initiator
126 * when in simplified routing mode.
127 * Removed SATA Init Failure defines for DiscoveryStatus
128 * fields of SAS IO Unit Page 0 and SAS Expander Page 0.
129 * Added MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED define.
130 * Added PortGroups, DmaGroup, and ControlGroup fields to
132 * 05-06-09 02.00.11 Added structures and defines for IO Unit Page 5 and IO
134 * Added expander reduced functionality data to SAS
136 * Added SAS PHY Page 2 and SAS PHY Page 3.
137 * 07-30-09 02.00.12 Added IO Unit Page 7.
138 * Added new device ids.
139 * Added SAS IO Unit Page 5.
140 * Added partial and slumber power management capable flags
141 * to SAS Device Page 0 Flags field.
142 * Added PhyInfo defines for power condition.
143 * Added Ethernet configuration pages.
144 * 10-28-09 02.00.13 Added MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY.
145 * Added SAS PHY Page 4 structure and defines.
146 * 02-10-10 02.00.14 Modified the comments for the configuration page
147 * structures that contain an array of data. The host
148 * should use the "count" field in the page data (e.g. the
149 * NumPhys field) to determine the number of valid elements
151 * Added/modified some MPI2_MFGPAGE_DEVID_SAS defines.
152 * Added PowerManagementCapabilities to IO Unit Page 7.
153 * Added PortWidthModGroup field to
154 * MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS.
155 * Added MPI2_CONFIG_PAGE_SASIOUNIT_6 and related defines.
156 * Added MPI2_CONFIG_PAGE_SASIOUNIT_7 and related defines.
157 * Added MPI2_CONFIG_PAGE_SASIOUNIT_8 and related defines.
158 * 05-12-10 02.00.15 Added MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT
160 * Added MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE define.
161 * Added MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY define.
162 * 08-11-10 02.00.16 Removed IO Unit Page 1 device path (multi-pathing)
164 * 11-10-10 02.00.17 Added ReceptacleID field (replacing Reserved1) to
165 * MPI2_MANPAGE7_CONNECTOR_INFO and reworked defines for
167 * Added BoardTemperature and BoardTemperatureUnits fields
168 * to MPI2_CONFIG_PAGE_IO_UNIT_7.
169 * Added MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING define
170 * and MPI2_CONFIG_PAGE_EXT_MAN_PS structure.
171 * --------------------------------------------------------------------------
177 /*****************************************************************************
178 * Configuration Page Header and defines
179 *****************************************************************************/
181 /* Config Page Header */
182 typedef struct _MPI2_CONFIG_PAGE_HEADER
184 U8 PageVersion; /* 0x00 */
185 U8 PageLength; /* 0x01 */
186 U8 PageNumber; /* 0x02 */
187 U8 PageType; /* 0x03 */
188 } MPI2_CONFIG_PAGE_HEADER, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER,
189 Mpi2ConfigPageHeader_t, MPI2_POINTER pMpi2ConfigPageHeader_t;
191 typedef union _MPI2_CONFIG_PAGE_HEADER_UNION
193 MPI2_CONFIG_PAGE_HEADER Struct;
197 } MPI2_CONFIG_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER_UNION,
198 Mpi2ConfigPageHeaderUnion, MPI2_POINTER pMpi2ConfigPageHeaderUnion;
200 /* Extended Config Page Header */
201 typedef struct _MPI2_CONFIG_EXTENDED_PAGE_HEADER
203 U8 PageVersion; /* 0x00 */
204 U8 Reserved1; /* 0x01 */
205 U8 PageNumber; /* 0x02 */
206 U8 PageType; /* 0x03 */
207 U16 ExtPageLength; /* 0x04 */
208 U8 ExtPageType; /* 0x06 */
209 U8 Reserved2; /* 0x07 */
210 } MPI2_CONFIG_EXTENDED_PAGE_HEADER,
211 MPI2_POINTER PTR_MPI2_CONFIG_EXTENDED_PAGE_HEADER,
212 Mpi2ConfigExtendedPageHeader_t, MPI2_POINTER pMpi2ConfigExtendedPageHeader_t;
214 typedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION
216 MPI2_CONFIG_PAGE_HEADER Struct;
217 MPI2_CONFIG_EXTENDED_PAGE_HEADER Ext;
221 } MPI2_CONFIG_EXT_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_EXT_PAGE_HEADER_UNION,
222 Mpi2ConfigPageExtendedHeaderUnion, MPI2_POINTER pMpi2ConfigPageExtendedHeaderUnion;
225 /* PageType field values */
226 #define MPI2_CONFIG_PAGEATTR_READ_ONLY (0x00)
227 #define MPI2_CONFIG_PAGEATTR_CHANGEABLE (0x10)
228 #define MPI2_CONFIG_PAGEATTR_PERSISTENT (0x20)
229 #define MPI2_CONFIG_PAGEATTR_MASK (0xF0)
231 #define MPI2_CONFIG_PAGETYPE_IO_UNIT (0x00)
232 #define MPI2_CONFIG_PAGETYPE_IOC (0x01)
233 #define MPI2_CONFIG_PAGETYPE_BIOS (0x02)
234 #define MPI2_CONFIG_PAGETYPE_RAID_VOLUME (0x08)
235 #define MPI2_CONFIG_PAGETYPE_MANUFACTURING (0x09)
236 #define MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A)
237 #define MPI2_CONFIG_PAGETYPE_EXTENDED (0x0F)
238 #define MPI2_CONFIG_PAGETYPE_MASK (0x0F)
240 #define MPI2_CONFIG_TYPENUM_MASK (0x0FFF)
243 /* ExtPageType field values */
244 #define MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10)
245 #define MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11)
246 #define MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12)
247 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PHY (0x13)
248 #define MPI2_CONFIG_EXTPAGETYPE_LOG (0x14)
249 #define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15)
250 #define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG (0x16)
251 #define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING (0x17)
252 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT (0x18)
253 #define MPI2_CONFIG_EXTPAGETYPE_ETHERNET (0x19)
254 #define MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING (0x1A)
257 /*****************************************************************************
258 * PageAddress defines
259 *****************************************************************************/
261 /* RAID Volume PageAddress format */
262 #define MPI2_RAID_VOLUME_PGAD_FORM_MASK (0xF0000000)
263 #define MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
264 #define MPI2_RAID_VOLUME_PGAD_FORM_HANDLE (0x10000000)
266 #define MPI2_RAID_VOLUME_PGAD_HANDLE_MASK (0x0000FFFF)
269 /* RAID Physical Disk PageAddress format */
270 #define MPI2_PHYSDISK_PGAD_FORM_MASK (0xF0000000)
271 #define MPI2_PHYSDISK_PGAD_FORM_GET_NEXT_PHYSDISKNUM (0x00000000)
272 #define MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM (0x10000000)
273 #define MPI2_PHYSDISK_PGAD_FORM_DEVHANDLE (0x20000000)
275 #define MPI2_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF)
276 #define MPI2_PHYSDISK_PGAD_DEVHANDLE_MASK (0x0000FFFF)
279 /* SAS Expander PageAddress format */
280 #define MPI2_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000)
281 #define MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL (0x00000000)
282 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL_PHY_NUM (0x10000000)
283 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL (0x20000000)
285 #define MPI2_SAS_EXPAND_PGAD_HANDLE_MASK (0x0000FFFF)
286 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_MASK (0x00FF0000)
287 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_SHIFT (16)
290 /* SAS Device PageAddress format */
291 #define MPI2_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000)
292 #define MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
293 #define MPI2_SAS_DEVICE_PGAD_FORM_HANDLE (0x20000000)
295 #define MPI2_SAS_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF)
298 /* SAS PHY PageAddress format */
299 #define MPI2_SAS_PHY_PGAD_FORM_MASK (0xF0000000)
300 #define MPI2_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x00000000)
301 #define MPI2_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x10000000)
303 #define MPI2_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF)
304 #define MPI2_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF)
307 /* SAS Port PageAddress format */
308 #define MPI2_SASPORT_PGAD_FORM_MASK (0xF0000000)
309 #define MPI2_SASPORT_PGAD_FORM_GET_NEXT_PORT (0x00000000)
310 #define MPI2_SASPORT_PGAD_FORM_PORT_NUM (0x10000000)
312 #define MPI2_SASPORT_PGAD_PORTNUMBER_MASK (0x00000FFF)
315 /* SAS Enclosure PageAddress format */
316 #define MPI2_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000)
317 #define MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
318 #define MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE (0x10000000)
320 #define MPI2_SAS_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF)
323 /* RAID Configuration PageAddress format */
324 #define MPI2_RAID_PGAD_FORM_MASK (0xF0000000)
325 #define MPI2_RAID_PGAD_FORM_GET_NEXT_CONFIGNUM (0x00000000)
326 #define MPI2_RAID_PGAD_FORM_CONFIGNUM (0x10000000)
327 #define MPI2_RAID_PGAD_FORM_ACTIVE_CONFIG (0x20000000)
329 #define MPI2_RAID_PGAD_CONFIGNUM_MASK (0x000000FF)
332 /* Driver Persistent Mapping PageAddress format */
333 #define MPI2_DPM_PGAD_FORM_MASK (0xF0000000)
334 #define MPI2_DPM_PGAD_FORM_ENTRY_RANGE (0x00000000)
336 #define MPI2_DPM_PGAD_ENTRY_COUNT_MASK (0x0FFF0000)
337 #define MPI2_DPM_PGAD_ENTRY_COUNT_SHIFT (16)
338 #define MPI2_DPM_PGAD_START_ENTRY_MASK (0x0000FFFF)
341 /* Ethernet PageAddress format */
342 #define MPI2_ETHERNET_PGAD_FORM_MASK (0xF0000000)
343 #define MPI2_ETHERNET_PGAD_FORM_IF_NUM (0x00000000)
345 #define MPI2_ETHERNET_PGAD_IF_NUMBER_MASK (0x000000FF)
349 /****************************************************************************
350 * Configuration messages
351 ****************************************************************************/
353 /* Configuration Request Message */
354 typedef struct _MPI2_CONFIG_REQUEST
356 U8 Action; /* 0x00 */
357 U8 SGLFlags; /* 0x01 */
358 U8 ChainOffset; /* 0x02 */
359 U8 Function; /* 0x03 */
360 U16 ExtPageLength; /* 0x04 */
361 U8 ExtPageType; /* 0x06 */
362 U8 MsgFlags; /* 0x07 */
365 U16 Reserved1; /* 0x0A */
366 U32 Reserved2; /* 0x0C */
367 U32 Reserved3; /* 0x10 */
368 MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */
369 U32 PageAddress; /* 0x18 */
370 MPI2_SGE_IO_UNION PageBufferSGE; /* 0x1C */
371 } MPI2_CONFIG_REQUEST, MPI2_POINTER PTR_MPI2_CONFIG_REQUEST,
372 Mpi2ConfigRequest_t, MPI2_POINTER pMpi2ConfigRequest_t;
374 /* values for the Action field */
375 #define MPI2_CONFIG_ACTION_PAGE_HEADER (0x00)
376 #define MPI2_CONFIG_ACTION_PAGE_READ_CURRENT (0x01)
377 #define MPI2_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02)
378 #define MPI2_CONFIG_ACTION_PAGE_DEFAULT (0x03)
379 #define MPI2_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04)
380 #define MPI2_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05)
381 #define MPI2_CONFIG_ACTION_PAGE_READ_NVRAM (0x06)
382 #define MPI2_CONFIG_ACTION_PAGE_GET_CHANGEABLE (0x07)
384 /* use MPI2_SGLFLAGS_ defines from mpi2.h for the SGLFlags field */
387 /* Config Reply Message */
388 typedef struct _MPI2_CONFIG_REPLY
390 U8 Action; /* 0x00 */
391 U8 SGLFlags; /* 0x01 */
392 U8 MsgLength; /* 0x02 */
393 U8 Function; /* 0x03 */
394 U16 ExtPageLength; /* 0x04 */
395 U8 ExtPageType; /* 0x06 */
396 U8 MsgFlags; /* 0x07 */
399 U16 Reserved1; /* 0x0A */
400 U16 Reserved2; /* 0x0C */
401 U16 IOCStatus; /* 0x0E */
402 U32 IOCLogInfo; /* 0x10 */
403 MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */
404 } MPI2_CONFIG_REPLY, MPI2_POINTER PTR_MPI2_CONFIG_REPLY,
405 Mpi2ConfigReply_t, MPI2_POINTER pMpi2ConfigReply_t;
409 /*****************************************************************************
411 * C o n f i g u r a t i o n P a g e s
413 *****************************************************************************/
415 /****************************************************************************
416 * Manufacturing Config pages
417 ****************************************************************************/
419 #define MPI2_MFGPAGE_VENDORID_LSI (0x1000)
422 #define MPI2_MFGPAGE_DEVID_SAS2004 (0x0070)
423 #define MPI2_MFGPAGE_DEVID_SAS2008 (0x0072)
424 #define MPI2_MFGPAGE_DEVID_SAS2108_1 (0x0074)
425 #define MPI2_MFGPAGE_DEVID_SAS2108_2 (0x0076)
426 #define MPI2_MFGPAGE_DEVID_SAS2108_3 (0x0077)
427 #define MPI2_MFGPAGE_DEVID_SAS2116_1 (0x0064)
428 #define MPI2_MFGPAGE_DEVID_SAS2116_2 (0x0065)
430 #define MPI2_MFGPAGE_DEVID_SSS6200 (0x007E)
432 #define MPI2_MFGPAGE_DEVID_SAS2208_1 (0x0080)
433 #define MPI2_MFGPAGE_DEVID_SAS2208_2 (0x0081)
434 #define MPI2_MFGPAGE_DEVID_SAS2208_3 (0x0082)
435 #define MPI2_MFGPAGE_DEVID_SAS2208_4 (0x0083)
436 #define MPI2_MFGPAGE_DEVID_SAS2208_5 (0x0084)
437 #define MPI2_MFGPAGE_DEVID_SAS2208_6 (0x0085)
438 #define MPI2_MFGPAGE_DEVID_SAS2308_1 (0x0086)
439 #define MPI2_MFGPAGE_DEVID_SAS2308_2 (0x0087)
440 #define MPI2_MFGPAGE_DEVID_SAS2308_3 (0x006E)
445 /* Manufacturing Page 0 */
447 typedef struct _MPI2_CONFIG_PAGE_MAN_0
449 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
450 U8 ChipName[16]; /* 0x04 */
451 U8 ChipRevision[8]; /* 0x14 */
452 U8 BoardName[16]; /* 0x1C */
453 U8 BoardAssembly[16]; /* 0x2C */
454 U8 BoardTracerNumber[16]; /* 0x3C */
455 } MPI2_CONFIG_PAGE_MAN_0,
456 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_0,
457 Mpi2ManufacturingPage0_t, MPI2_POINTER pMpi2ManufacturingPage0_t;
459 #define MPI2_MANUFACTURING0_PAGEVERSION (0x00)
462 /* Manufacturing Page 1 */
464 typedef struct _MPI2_CONFIG_PAGE_MAN_1
466 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
467 U8 VPD[256]; /* 0x04 */
468 } MPI2_CONFIG_PAGE_MAN_1,
469 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_1,
470 Mpi2ManufacturingPage1_t, MPI2_POINTER pMpi2ManufacturingPage1_t;
472 #define MPI2_MANUFACTURING1_PAGEVERSION (0x00)
475 typedef struct _MPI2_CHIP_REVISION_ID
477 U16 DeviceID; /* 0x00 */
478 U8 PCIRevisionID; /* 0x02 */
479 U8 Reserved; /* 0x03 */
480 } MPI2_CHIP_REVISION_ID, MPI2_POINTER PTR_MPI2_CHIP_REVISION_ID,
481 Mpi2ChipRevisionId_t, MPI2_POINTER pMpi2ChipRevisionId_t;
484 /* Manufacturing Page 2 */
487 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
488 * one and check Header.PageLength at runtime.
490 #ifndef MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS
491 #define MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS (1)
494 typedef struct _MPI2_CONFIG_PAGE_MAN_2
496 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
497 MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */
498 U32 HwSettings[MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 0x08 */
499 } MPI2_CONFIG_PAGE_MAN_2,
500 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_2,
501 Mpi2ManufacturingPage2_t, MPI2_POINTER pMpi2ManufacturingPage2_t;
503 #define MPI2_MANUFACTURING2_PAGEVERSION (0x00)
506 /* Manufacturing Page 3 */
509 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
510 * one and check Header.PageLength at runtime.
512 #ifndef MPI2_MAN_PAGE_3_INFO_WORDS
513 #define MPI2_MAN_PAGE_3_INFO_WORDS (1)
516 typedef struct _MPI2_CONFIG_PAGE_MAN_3
518 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
519 MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */
520 U32 Info[MPI2_MAN_PAGE_3_INFO_WORDS];/* 0x08 */
521 } MPI2_CONFIG_PAGE_MAN_3,
522 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_3,
523 Mpi2ManufacturingPage3_t, MPI2_POINTER pMpi2ManufacturingPage3_t;
525 #define MPI2_MANUFACTURING3_PAGEVERSION (0x00)
528 /* Manufacturing Page 4 */
530 typedef struct _MPI2_MANPAGE4_PWR_SAVE_SETTINGS
532 U8 PowerSaveFlags; /* 0x00 */
533 U8 InternalOperationsSleepTime; /* 0x01 */
534 U8 InternalOperationsRunTime; /* 0x02 */
535 U8 HostIdleTime; /* 0x03 */
536 } MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
537 MPI2_POINTER PTR_MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
538 Mpi2ManPage4PwrSaveSettings_t, MPI2_POINTER pMpi2ManPage4PwrSaveSettings_t;
540 /* defines for the PowerSaveFlags field */
541 #define MPI2_MANPAGE4_MASK_POWERSAVE_MODE (0x03)
542 #define MPI2_MANPAGE4_POWERSAVE_MODE_DISABLED (0x00)
543 #define MPI2_MANPAGE4_CUSTOM_POWERSAVE_MODE (0x01)
544 #define MPI2_MANPAGE4_FULL_POWERSAVE_MODE (0x02)
546 typedef struct _MPI2_CONFIG_PAGE_MAN_4
548 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
549 U32 Reserved1; /* 0x04 */
550 U32 Flags; /* 0x08 */
551 U8 InquirySize; /* 0x0C */
552 U8 Reserved2; /* 0x0D */
553 U16 Reserved3; /* 0x0E */
554 U8 InquiryData[56]; /* 0x10 */
555 U32 RAID0VolumeSettings; /* 0x48 */
556 U32 RAID1EVolumeSettings; /* 0x4C */
557 U32 RAID1VolumeSettings; /* 0x50 */
558 U32 RAID10VolumeSettings; /* 0x54 */
559 U32 Reserved4; /* 0x58 */
560 U32 Reserved5; /* 0x5C */
561 MPI2_MANPAGE4_PWR_SAVE_SETTINGS PowerSaveSettings; /* 0x60 */
562 U8 MaxOCEDisks; /* 0x64 */
563 U8 ResyncRate; /* 0x65 */
564 U16 DataScrubDuration; /* 0x66 */
565 U8 MaxHotSpares; /* 0x68 */
566 U8 MaxPhysDisksPerVol; /* 0x69 */
567 U8 MaxPhysDisks; /* 0x6A */
568 U8 MaxVolumes; /* 0x6B */
569 } MPI2_CONFIG_PAGE_MAN_4,
570 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_4,
571 Mpi2ManufacturingPage4_t, MPI2_POINTER pMpi2ManufacturingPage4_t;
573 #define MPI2_MANUFACTURING4_PAGEVERSION (0x0A)
575 /* Manufacturing Page 4 Flags field */
576 #define MPI2_MANPAGE4_METADATA_SIZE_MASK (0x00030000)
577 #define MPI2_MANPAGE4_METADATA_512MB (0x00000000)
579 #define MPI2_MANPAGE4_MIX_SSD_SAS_SATA (0x00008000)
580 #define MPI2_MANPAGE4_MIX_SSD_AND_NON_SSD (0x00004000)
581 #define MPI2_MANPAGE4_HIDE_PHYSDISK_NON_IR (0x00002000)
583 #define MPI2_MANPAGE4_MASK_PHYSDISK_COERCION (0x00001C00)
584 #define MPI2_MANPAGE4_PHYSDISK_COERCION_1GB (0x00000000)
585 #define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION (0x00000400)
586 #define MPI2_MANPAGE4_PHYSDISK_ADAPTIVE_COERCION (0x00000800)
587 #define MPI2_MANPAGE4_PHYSDISK_ZERO_COERCION (0x00000C00)
589 #define MPI2_MANPAGE4_MASK_BAD_BLOCK_MARKING (0x00000300)
590 #define MPI2_MANPAGE4_DEFAULT_BAD_BLOCK_MARKING (0x00000000)
591 #define MPI2_MANPAGE4_TABLE_BAD_BLOCK_MARKING (0x00000100)
592 #define MPI2_MANPAGE4_WRITE_LONG_BAD_BLOCK_MARKING (0x00000200)
594 #define MPI2_MANPAGE4_FORCE_OFFLINE_FAILOVER (0x00000080)
595 #define MPI2_MANPAGE4_RAID10_DISABLE (0x00000040)
596 #define MPI2_MANPAGE4_RAID1E_DISABLE (0x00000020)
597 #define MPI2_MANPAGE4_RAID1_DISABLE (0x00000010)
598 #define MPI2_MANPAGE4_RAID0_DISABLE (0x00000008)
599 #define MPI2_MANPAGE4_IR_MODEPAGE8_DISABLE (0x00000004)
600 #define MPI2_MANPAGE4_IM_RESYNC_CACHE_ENABLE (0x00000002)
601 #define MPI2_MANPAGE4_IR_NO_MIX_SAS_SATA (0x00000001)
604 /* Manufacturing Page 5 */
607 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
608 * one and check the value returned for NumPhys at runtime.
610 #ifndef MPI2_MAN_PAGE_5_PHY_ENTRIES
611 #define MPI2_MAN_PAGE_5_PHY_ENTRIES (1)
614 typedef struct _MPI2_MANUFACTURING5_ENTRY
617 U64 DeviceName; /* 0x08 */
618 } MPI2_MANUFACTURING5_ENTRY, MPI2_POINTER PTR_MPI2_MANUFACTURING5_ENTRY,
619 Mpi2Manufacturing5Entry_t, MPI2_POINTER pMpi2Manufacturing5Entry_t;
621 typedef struct _MPI2_CONFIG_PAGE_MAN_5
623 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
624 U8 NumPhys; /* 0x04 */
625 U8 Reserved1; /* 0x05 */
626 U16 Reserved2; /* 0x06 */
627 U32 Reserved3; /* 0x08 */
628 U32 Reserved4; /* 0x0C */
629 MPI2_MANUFACTURING5_ENTRY Phy[MPI2_MAN_PAGE_5_PHY_ENTRIES];/* 0x08 */
630 } MPI2_CONFIG_PAGE_MAN_5,
631 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_5,
632 Mpi2ManufacturingPage5_t, MPI2_POINTER pMpi2ManufacturingPage5_t;
634 #define MPI2_MANUFACTURING5_PAGEVERSION (0x03)
637 /* Manufacturing Page 6 */
639 typedef struct _MPI2_CONFIG_PAGE_MAN_6
641 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
642 U32 ProductSpecificInfo;/* 0x04 */
643 } MPI2_CONFIG_PAGE_MAN_6,
644 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_6,
645 Mpi2ManufacturingPage6_t, MPI2_POINTER pMpi2ManufacturingPage6_t;
647 #define MPI2_MANUFACTURING6_PAGEVERSION (0x00)
650 /* Manufacturing Page 7 */
652 typedef struct _MPI2_MANPAGE7_CONNECTOR_INFO
654 U32 Pinout; /* 0x00 */
655 U8 Connector[16]; /* 0x04 */
656 U8 Location; /* 0x14 */
657 U8 ReceptacleID; /* 0x15 */
659 U32 Reserved2; /* 0x18 */
660 } MPI2_MANPAGE7_CONNECTOR_INFO, MPI2_POINTER PTR_MPI2_MANPAGE7_CONNECTOR_INFO,
661 Mpi2ManPage7ConnectorInfo_t, MPI2_POINTER pMpi2ManPage7ConnectorInfo_t;
663 /* defines for the Pinout field */
664 #define MPI2_MANPAGE7_PINOUT_LANE_MASK (0x0000FF00)
665 #define MPI2_MANPAGE7_PINOUT_LANE_SHIFT (8)
667 #define MPI2_MANPAGE7_PINOUT_TYPE_MASK (0x000000FF)
668 #define MPI2_MANPAGE7_PINOUT_TYPE_UNKNOWN (0x00)
669 #define MPI2_MANPAGE7_PINOUT_SATA_SINGLE (0x01)
670 #define MPI2_MANPAGE7_PINOUT_SFF_8482 (0x02)
671 #define MPI2_MANPAGE7_PINOUT_SFF_8486 (0x03)
672 #define MPI2_MANPAGE7_PINOUT_SFF_8484 (0x04)
673 #define MPI2_MANPAGE7_PINOUT_SFF_8087 (0x05)
674 #define MPI2_MANPAGE7_PINOUT_SFF_8643_4I (0x06)
675 #define MPI2_MANPAGE7_PINOUT_SFF_8643_8I (0x07)
676 #define MPI2_MANPAGE7_PINOUT_SFF_8470 (0x08)
677 #define MPI2_MANPAGE7_PINOUT_SFF_8088 (0x09)
678 #define MPI2_MANPAGE7_PINOUT_SFF_8644_4X (0x0A)
679 #define MPI2_MANPAGE7_PINOUT_SFF_8644_8X (0x0B)
680 #define MPI2_MANPAGE7_PINOUT_SFF_8644_16X (0x0C)
681 #define MPI2_MANPAGE7_PINOUT_SFF_8436 (0x0D)
683 /* defines for the Location field */
684 #define MPI2_MANPAGE7_LOCATION_UNKNOWN (0x01)
685 #define MPI2_MANPAGE7_LOCATION_INTERNAL (0x02)
686 #define MPI2_MANPAGE7_LOCATION_EXTERNAL (0x04)
687 #define MPI2_MANPAGE7_LOCATION_SWITCHABLE (0x08)
688 #define MPI2_MANPAGE7_LOCATION_AUTO (0x10)
689 #define MPI2_MANPAGE7_LOCATION_NOT_PRESENT (0x20)
690 #define MPI2_MANPAGE7_LOCATION_NOT_CONNECTED (0x80)
693 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
694 * one and check the value returned for NumPhys at runtime.
696 #ifndef MPI2_MANPAGE7_CONNECTOR_INFO_MAX
697 #define MPI2_MANPAGE7_CONNECTOR_INFO_MAX (1)
700 typedef struct _MPI2_CONFIG_PAGE_MAN_7
702 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
703 U32 Reserved1; /* 0x04 */
704 U32 Reserved2; /* 0x08 */
705 U32 Flags; /* 0x0C */
706 U8 EnclosureName[16]; /* 0x10 */
707 U8 NumPhys; /* 0x20 */
708 U8 Reserved3; /* 0x21 */
709 U16 Reserved4; /* 0x22 */
710 MPI2_MANPAGE7_CONNECTOR_INFO ConnectorInfo[MPI2_MANPAGE7_CONNECTOR_INFO_MAX]; /* 0x24 */
711 } MPI2_CONFIG_PAGE_MAN_7,
712 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_7,
713 Mpi2ManufacturingPage7_t, MPI2_POINTER pMpi2ManufacturingPage7_t;
715 #define MPI2_MANUFACTURING7_PAGEVERSION (0x01)
717 /* defines for the Flags field */
718 #define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001)
722 * Generic structure to use for product-specific manufacturing pages
723 * (currently Manufacturing Page 8 through Manufacturing Page 31).
726 typedef struct _MPI2_CONFIG_PAGE_MAN_PS
728 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
729 U32 ProductSpecificInfo;/* 0x04 */
730 } MPI2_CONFIG_PAGE_MAN_PS,
731 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_PS,
732 Mpi2ManufacturingPagePS_t, MPI2_POINTER pMpi2ManufacturingPagePS_t;
734 #define MPI2_MANUFACTURING8_PAGEVERSION (0x00)
735 #define MPI2_MANUFACTURING9_PAGEVERSION (0x00)
736 #define MPI2_MANUFACTURING10_PAGEVERSION (0x00)
737 #define MPI2_MANUFACTURING11_PAGEVERSION (0x00)
738 #define MPI2_MANUFACTURING12_PAGEVERSION (0x00)
739 #define MPI2_MANUFACTURING13_PAGEVERSION (0x00)
740 #define MPI2_MANUFACTURING14_PAGEVERSION (0x00)
741 #define MPI2_MANUFACTURING15_PAGEVERSION (0x00)
742 #define MPI2_MANUFACTURING16_PAGEVERSION (0x00)
743 #define MPI2_MANUFACTURING17_PAGEVERSION (0x00)
744 #define MPI2_MANUFACTURING18_PAGEVERSION (0x00)
745 #define MPI2_MANUFACTURING19_PAGEVERSION (0x00)
746 #define MPI2_MANUFACTURING20_PAGEVERSION (0x00)
747 #define MPI2_MANUFACTURING21_PAGEVERSION (0x00)
748 #define MPI2_MANUFACTURING22_PAGEVERSION (0x00)
749 #define MPI2_MANUFACTURING23_PAGEVERSION (0x00)
750 #define MPI2_MANUFACTURING24_PAGEVERSION (0x00)
751 #define MPI2_MANUFACTURING25_PAGEVERSION (0x00)
752 #define MPI2_MANUFACTURING26_PAGEVERSION (0x00)
753 #define MPI2_MANUFACTURING27_PAGEVERSION (0x00)
754 #define MPI2_MANUFACTURING28_PAGEVERSION (0x00)
755 #define MPI2_MANUFACTURING29_PAGEVERSION (0x00)
756 #define MPI2_MANUFACTURING30_PAGEVERSION (0x00)
757 #define MPI2_MANUFACTURING31_PAGEVERSION (0x00)
760 /****************************************************************************
761 * IO Unit Config Pages
762 ****************************************************************************/
766 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_0
768 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
769 U64 UniqueValue; /* 0x04 */
770 MPI2_VERSION_UNION NvdataVersionDefault; /* 0x08 */
771 MPI2_VERSION_UNION NvdataVersionPersistent; /* 0x0A */
772 } MPI2_CONFIG_PAGE_IO_UNIT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_0,
773 Mpi2IOUnitPage0_t, MPI2_POINTER pMpi2IOUnitPage0_t;
775 #define MPI2_IOUNITPAGE0_PAGEVERSION (0x02)
780 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1
782 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
783 U32 Flags; /* 0x04 */
784 } MPI2_CONFIG_PAGE_IO_UNIT_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_1,
785 Mpi2IOUnitPage1_t, MPI2_POINTER pMpi2IOUnitPage1_t;
787 #define MPI2_IOUNITPAGE1_PAGEVERSION (0x04)
789 /* IO Unit Page 1 Flags defines */
790 #define MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY (0x00000800)
791 #define MPI2_IOUNITPAGE1_MASK_SATA_WRITE_CACHE (0x00000600)
792 #define MPI2_IOUNITPAGE1_SATA_WRITE_CACHE_SHIFT (9)
793 #define MPI2_IOUNITPAGE1_ENABLE_SATA_WRITE_CACHE (0x00000000)
794 #define MPI2_IOUNITPAGE1_DISABLE_SATA_WRITE_CACHE (0x00000200)
795 #define MPI2_IOUNITPAGE1_UNCHANGED_SATA_WRITE_CACHE (0x00000400)
796 #define MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100)
797 #define MPI2_IOUNITPAGE1_DISABLE_IR (0x00000040)
798 #define MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING (0x00000020)
799 #define MPI2_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004)
805 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
806 * one and check the value returned for GPIOCount at runtime.
808 #ifndef MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX
809 #define MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1)
812 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_3
814 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
815 U8 GPIOCount; /* 0x04 */
816 U8 Reserved1; /* 0x05 */
817 U16 Reserved2; /* 0x06 */
818 U16 GPIOVal[MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX];/* 0x08 */
819 } MPI2_CONFIG_PAGE_IO_UNIT_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_3,
820 Mpi2IOUnitPage3_t, MPI2_POINTER pMpi2IOUnitPage3_t;
822 #define MPI2_IOUNITPAGE3_PAGEVERSION (0x01)
824 /* defines for IO Unit Page 3 GPIOVal field */
825 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFFFC)
826 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2)
827 #define MPI2_IOUNITPAGE3_GPIO_SETTING_OFF (0x0000)
828 #define MPI2_IOUNITPAGE3_GPIO_SETTING_ON (0x0001)
834 * Upper layer code (drivers, utilities, etc.) should leave this define set to
835 * one and check the value returned for NumDmaEngines at runtime.
837 #ifndef MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES
838 #define MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES (1)
841 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_5
843 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
844 U64 RaidAcceleratorBufferBaseAddress; /* 0x04 */
845 U64 RaidAcceleratorBufferSize; /* 0x0C */
846 U64 RaidAcceleratorControlBaseAddress; /* 0x14 */
847 U8 RAControlSize; /* 0x1C */
848 U8 NumDmaEngines; /* 0x1D */
849 U8 RAMinControlSize; /* 0x1E */
850 U8 RAMaxControlSize; /* 0x1F */
851 U32 Reserved1; /* 0x20 */
852 U32 Reserved2; /* 0x24 */
853 U32 Reserved3; /* 0x28 */
854 U32 DmaEngineCapabilities[MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES]; /* 0x2C */
855 } MPI2_CONFIG_PAGE_IO_UNIT_5, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_5,
856 Mpi2IOUnitPage5_t, MPI2_POINTER pMpi2IOUnitPage5_t;
858 #define MPI2_IOUNITPAGE5_PAGEVERSION (0x00)
860 /* defines for IO Unit Page 5 DmaEngineCapabilities field */
861 #define MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS (0xFF00)
862 #define MPI2_IOUNITPAGE5_DMA_CAP_SHIFT_MAX_REQUESTS (16)
864 #define MPI2_IOUNITPAGE5_DMA_CAP_EEDP (0x0008)
865 #define MPI2_IOUNITPAGE5_DMA_CAP_PARITY_GENERATION (0x0004)
866 #define MPI2_IOUNITPAGE5_DMA_CAP_HASHING (0x0002)
867 #define MPI2_IOUNITPAGE5_DMA_CAP_ENCRYPTION (0x0001)
872 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_6
874 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
875 U16 Flags; /* 0x04 */
876 U8 RAHostControlSize; /* 0x06 */
877 U8 Reserved0; /* 0x07 */
878 U64 RaidAcceleratorHostControlBaseAddress; /* 0x08 */
879 U32 Reserved1; /* 0x10 */
880 U32 Reserved2; /* 0x14 */
881 U32 Reserved3; /* 0x18 */
882 } MPI2_CONFIG_PAGE_IO_UNIT_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_6,
883 Mpi2IOUnitPage6_t, MPI2_POINTER pMpi2IOUnitPage6_t;
885 #define MPI2_IOUNITPAGE6_PAGEVERSION (0x00)
887 /* defines for IO Unit Page 6 Flags field */
888 #define MPI2_IOUNITPAGE6_FLAGS_ENABLE_RAID_ACCELERATOR (0x0001)
893 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_7
895 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
896 U16 Reserved1; /* 0x04 */
897 U8 PCIeWidth; /* 0x06 */
898 U8 PCIeSpeed; /* 0x07 */
899 U32 ProcessorState; /* 0x08 */
900 U32 PowerManagementCapabilities; /* 0x0C */
901 U16 IOCTemperature; /* 0x10 */
902 U8 IOCTemperatureUnits; /* 0x12 */
903 U8 IOCSpeed; /* 0x13 */
904 U16 BoardTemperature; /* 0x14 */
905 U8 BoardTemperatureUnits; /* 0x16 */
906 U8 Reserved3; /* 0x17 */
907 } MPI2_CONFIG_PAGE_IO_UNIT_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_7,
908 Mpi2IOUnitPage7_t, MPI2_POINTER pMpi2IOUnitPage7_t;
910 #define MPI2_IOUNITPAGE7_PAGEVERSION (0x02)
912 /* defines for IO Unit Page 7 PCIeWidth field */
913 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X1 (0x01)
914 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X2 (0x02)
915 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X4 (0x04)
916 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X8 (0x08)
918 /* defines for IO Unit Page 7 PCIeSpeed field */
919 #define MPI2_IOUNITPAGE7_PCIE_SPEED_2_5_GBPS (0x00)
920 #define MPI2_IOUNITPAGE7_PCIE_SPEED_5_0_GBPS (0x01)
921 #define MPI2_IOUNITPAGE7_PCIE_SPEED_8_0_GBPS (0x02)
923 /* defines for IO Unit Page 7 ProcessorState field */
924 #define MPI2_IOUNITPAGE7_PSTATE_MASK_SECOND (0x0000000F)
925 #define MPI2_IOUNITPAGE7_PSTATE_SHIFT_SECOND (0)
927 #define MPI2_IOUNITPAGE7_PSTATE_NOT_PRESENT (0x00)
928 #define MPI2_IOUNITPAGE7_PSTATE_DISABLED (0x01)
929 #define MPI2_IOUNITPAGE7_PSTATE_ENABLED (0x02)
931 /* defines for IO Unit Page 7 PowerManagementCapabilities field */
932 #define MPI2_IOUNITPAGE7_PMCAP_12_5_PCT_IOCSPEED (0x00000400)
933 #define MPI2_IOUNITPAGE7_PMCAP_25_0_PCT_IOCSPEED (0x00000200)
934 #define MPI2_IOUNITPAGE7_PMCAP_50_0_PCT_IOCSPEED (0x00000100)
935 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_WIDTH_CHANGE (0x00000008)
936 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_SPEED_CHANGE (0x00000004)
938 /* defines for IO Unit Page 7 IOCTemperatureUnits field */
939 #define MPI2_IOUNITPAGE7_IOC_TEMP_NOT_PRESENT (0x00)
940 #define MPI2_IOUNITPAGE7_IOC_TEMP_FAHRENHEIT (0x01)
941 #define MPI2_IOUNITPAGE7_IOC_TEMP_CELSIUS (0x02)
943 /* defines for IO Unit Page 7 IOCSpeed field */
944 #define MPI2_IOUNITPAGE7_IOC_SPEED_FULL (0x01)
945 #define MPI2_IOUNITPAGE7_IOC_SPEED_HALF (0x02)
946 #define MPI2_IOUNITPAGE7_IOC_SPEED_QUARTER (0x04)
947 #define MPI2_IOUNITPAGE7_IOC_SPEED_EIGHTH (0x08)
949 /* defines for IO Unit Page 7 BoardTemperatureUnits field */
950 #define MPI2_IOUNITPAGE7_BOARD_TEMP_NOT_PRESENT (0x00)
951 #define MPI2_IOUNITPAGE7_BOARD_TEMP_FAHRENHEIT (0x01)
952 #define MPI2_IOUNITPAGE7_BOARD_TEMP_CELSIUS (0x02)
956 /****************************************************************************
958 ****************************************************************************/
962 typedef struct _MPI2_CONFIG_PAGE_IOC_0
964 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
965 U32 Reserved1; /* 0x04 */
966 U32 Reserved2; /* 0x08 */
967 U16 VendorID; /* 0x0C */
968 U16 DeviceID; /* 0x0E */
969 U8 RevisionID; /* 0x10 */
970 U8 Reserved3; /* 0x11 */
971 U16 Reserved4; /* 0x12 */
972 U32 ClassCode; /* 0x14 */
973 U16 SubsystemVendorID; /* 0x18 */
974 U16 SubsystemID; /* 0x1A */
975 } MPI2_CONFIG_PAGE_IOC_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_0,
976 Mpi2IOCPage0_t, MPI2_POINTER pMpi2IOCPage0_t;
978 #define MPI2_IOCPAGE0_PAGEVERSION (0x02)
983 typedef struct _MPI2_CONFIG_PAGE_IOC_1
985 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
986 U32 Flags; /* 0x04 */
987 U32 CoalescingTimeout; /* 0x08 */
988 U8 CoalescingDepth; /* 0x0C */
989 U8 PCISlotNum; /* 0x0D */
990 U8 PCIBusNum; /* 0x0E */
991 U8 PCIDomainSegment; /* 0x0F */
992 U32 Reserved1; /* 0x10 */
993 U32 Reserved2; /* 0x14 */
994 } MPI2_CONFIG_PAGE_IOC_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_1,
995 Mpi2IOCPage1_t, MPI2_POINTER pMpi2IOCPage1_t;
997 #define MPI2_IOCPAGE1_PAGEVERSION (0x05)
999 /* defines for IOC Page 1 Flags field */
1000 #define MPI2_IOCPAGE1_REPLY_COALESCING (0x00000001)
1002 #define MPI2_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF)
1003 #define MPI2_IOCPAGE1_PCIBUSNUM_UNKNOWN (0xFF)
1004 #define MPI2_IOCPAGE1_PCIDOMAIN_UNKNOWN (0xFF)
1008 typedef struct _MPI2_CONFIG_PAGE_IOC_6
1010 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1011 U32 CapabilitiesFlags; /* 0x04 */
1012 U8 MaxDrivesRAID0; /* 0x08 */
1013 U8 MaxDrivesRAID1; /* 0x09 */
1014 U8 MaxDrivesRAID1E; /* 0x0A */
1015 U8 MaxDrivesRAID10; /* 0x0B */
1016 U8 MinDrivesRAID0; /* 0x0C */
1017 U8 MinDrivesRAID1; /* 0x0D */
1018 U8 MinDrivesRAID1E; /* 0x0E */
1019 U8 MinDrivesRAID10; /* 0x0F */
1020 U32 Reserved1; /* 0x10 */
1021 U8 MaxGlobalHotSpares; /* 0x14 */
1022 U8 MaxPhysDisks; /* 0x15 */
1023 U8 MaxVolumes; /* 0x16 */
1024 U8 MaxConfigs; /* 0x17 */
1025 U8 MaxOCEDisks; /* 0x18 */
1026 U8 Reserved2; /* 0x19 */
1027 U16 Reserved3; /* 0x1A */
1028 U32 SupportedStripeSizeMapRAID0; /* 0x1C */
1029 U32 SupportedStripeSizeMapRAID1E; /* 0x20 */
1030 U32 SupportedStripeSizeMapRAID10; /* 0x24 */
1031 U32 Reserved4; /* 0x28 */
1032 U32 Reserved5; /* 0x2C */
1033 U16 DefaultMetadataSize; /* 0x30 */
1034 U16 Reserved6; /* 0x32 */
1035 U16 MaxBadBlockTableEntries; /* 0x34 */
1036 U16 Reserved7; /* 0x36 */
1037 U32 IRNvsramVersion; /* 0x38 */
1038 } MPI2_CONFIG_PAGE_IOC_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_6,
1039 Mpi2IOCPage6_t, MPI2_POINTER pMpi2IOCPage6_t;
1041 #define MPI2_IOCPAGE6_PAGEVERSION (0x04)
1043 /* defines for IOC Page 6 CapabilitiesFlags */
1044 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID10_SUPPORT (0x00000010)
1045 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1_SUPPORT (0x00000008)
1046 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1E_SUPPORT (0x00000004)
1047 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID0_SUPPORT (0x00000002)
1048 #define MPI2_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE (0x00000001)
1053 #define MPI2_IOCPAGE7_EVENTMASK_WORDS (4)
1055 typedef struct _MPI2_CONFIG_PAGE_IOC_7
1057 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1058 U32 Reserved1; /* 0x04 */
1059 U32 EventMasks[MPI2_IOCPAGE7_EVENTMASK_WORDS];/* 0x08 */
1060 U16 SASBroadcastPrimitiveMasks; /* 0x18 */
1061 U16 Reserved2; /* 0x1A */
1062 U32 Reserved3; /* 0x1C */
1063 } MPI2_CONFIG_PAGE_IOC_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_7,
1064 Mpi2IOCPage7_t, MPI2_POINTER pMpi2IOCPage7_t;
1066 #define MPI2_IOCPAGE7_PAGEVERSION (0x01)
1071 typedef struct _MPI2_CONFIG_PAGE_IOC_8
1073 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1074 U8 NumDevsPerEnclosure; /* 0x04 */
1075 U8 Reserved1; /* 0x05 */
1076 U16 Reserved2; /* 0x06 */
1077 U16 MaxPersistentEntries; /* 0x08 */
1078 U16 MaxNumPhysicalMappedIDs; /* 0x0A */
1079 U16 Flags; /* 0x0C */
1080 U16 Reserved3; /* 0x0E */
1081 U16 IRVolumeMappingFlags; /* 0x10 */
1082 U16 Reserved4; /* 0x12 */
1083 U32 Reserved5; /* 0x14 */
1084 } MPI2_CONFIG_PAGE_IOC_8, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_8,
1085 Mpi2IOCPage8_t, MPI2_POINTER pMpi2IOCPage8_t;
1087 #define MPI2_IOCPAGE8_PAGEVERSION (0x00)
1089 /* defines for IOC Page 8 Flags field */
1090 #define MPI2_IOCPAGE8_FLAGS_DA_START_SLOT_1 (0x00000020)
1091 #define MPI2_IOCPAGE8_FLAGS_RESERVED_TARGETID_0 (0x00000010)
1093 #define MPI2_IOCPAGE8_FLAGS_MASK_MAPPING_MODE (0x0000000E)
1094 #define MPI2_IOCPAGE8_FLAGS_DEVICE_PERSISTENCE_MAPPING (0x00000000)
1095 #define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING (0x00000002)
1097 #define MPI2_IOCPAGE8_FLAGS_DISABLE_PERSISTENT_MAPPING (0x00000001)
1098 #define MPI2_IOCPAGE8_FLAGS_ENABLE_PERSISTENT_MAPPING (0x00000000)
1100 /* defines for IOC Page 8 IRVolumeMappingFlags */
1101 #define MPI2_IOCPAGE8_IRFLAGS_MASK_VOLUME_MAPPING_MODE (0x00000003)
1102 #define MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING (0x00000000)
1103 #define MPI2_IOCPAGE8_IRFLAGS_HIGH_VOLUME_MAPPING (0x00000001)
1106 /****************************************************************************
1108 ****************************************************************************/
1112 typedef struct _MPI2_CONFIG_PAGE_BIOS_1
1114 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1115 U32 BiosOptions; /* 0x04 */
1116 U32 IOCSettings; /* 0x08 */
1117 U32 Reserved1; /* 0x0C */
1118 U32 DeviceSettings; /* 0x10 */
1119 U16 NumberOfDevices; /* 0x14 */
1120 U16 Reserved2; /* 0x16 */
1121 U16 IOTimeoutBlockDevicesNonRM; /* 0x18 */
1122 U16 IOTimeoutSequential; /* 0x1A */
1123 U16 IOTimeoutOther; /* 0x1C */
1124 U16 IOTimeoutBlockDevicesRM; /* 0x1E */
1125 } MPI2_CONFIG_PAGE_BIOS_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_1,
1126 Mpi2BiosPage1_t, MPI2_POINTER pMpi2BiosPage1_t;
1128 #define MPI2_BIOSPAGE1_PAGEVERSION (0x04)
1130 /* values for BIOS Page 1 BiosOptions field */
1131 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001)
1133 /* values for BIOS Page 1 IOCSettings field */
1134 #define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000)
1135 #define MPI2_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000)
1136 #define MPI2_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000)
1138 #define MPI2_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0)
1139 #define MPI2_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000)
1140 #define MPI2_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040)
1141 #define MPI2_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080)
1143 #define MPI2_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030)
1144 #define MPI2_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000)
1145 #define MPI2_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010)
1146 #define MPI2_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020)
1147 #define MPI2_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030)
1149 #define MPI2_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008)
1151 /* values for BIOS Page 1 DeviceSettings field */
1152 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING (0x00000010)
1153 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008)
1154 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004)
1155 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002)
1156 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001)
1161 typedef struct _MPI2_BOOT_DEVICE_ADAPTER_ORDER
1163 U32 Reserved1; /* 0x00 */
1164 U32 Reserved2; /* 0x04 */
1165 U32 Reserved3; /* 0x08 */
1166 U32 Reserved4; /* 0x0C */
1167 U32 Reserved5; /* 0x10 */
1168 U32 Reserved6; /* 0x14 */
1169 } MPI2_BOOT_DEVICE_ADAPTER_ORDER,
1170 MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ADAPTER_ORDER,
1171 Mpi2BootDeviceAdapterOrder_t, MPI2_POINTER pMpi2BootDeviceAdapterOrder_t;
1173 typedef struct _MPI2_BOOT_DEVICE_SAS_WWID
1175 U64 SASAddress; /* 0x00 */
1176 U8 LUN[8]; /* 0x08 */
1177 U32 Reserved1; /* 0x10 */
1178 U32 Reserved2; /* 0x14 */
1179 } MPI2_BOOT_DEVICE_SAS_WWID, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_SAS_WWID,
1180 Mpi2BootDeviceSasWwid_t, MPI2_POINTER pMpi2BootDeviceSasWwid_t;
1182 typedef struct _MPI2_BOOT_DEVICE_ENCLOSURE_SLOT
1184 U64 EnclosureLogicalID; /* 0x00 */
1185 U32 Reserved1; /* 0x08 */
1186 U32 Reserved2; /* 0x0C */
1187 U16 SlotNumber; /* 0x10 */
1188 U16 Reserved3; /* 0x12 */
1189 U32 Reserved4; /* 0x14 */
1190 } MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
1191 MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
1192 Mpi2BootDeviceEnclosureSlot_t, MPI2_POINTER pMpi2BootDeviceEnclosureSlot_t;
1194 typedef struct _MPI2_BOOT_DEVICE_DEVICE_NAME
1196 U64 DeviceName; /* 0x00 */
1197 U8 LUN[8]; /* 0x08 */
1198 U32 Reserved1; /* 0x10 */
1199 U32 Reserved2; /* 0x14 */
1200 } MPI2_BOOT_DEVICE_DEVICE_NAME, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_DEVICE_NAME,
1201 Mpi2BootDeviceDeviceName_t, MPI2_POINTER pMpi2BootDeviceDeviceName_t;
1203 typedef union _MPI2_MPI2_BIOSPAGE2_BOOT_DEVICE
1205 MPI2_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder;
1206 MPI2_BOOT_DEVICE_SAS_WWID SasWwid;
1207 MPI2_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot;
1208 MPI2_BOOT_DEVICE_DEVICE_NAME DeviceName;
1209 } MPI2_BIOSPAGE2_BOOT_DEVICE, MPI2_POINTER PTR_MPI2_BIOSPAGE2_BOOT_DEVICE,
1210 Mpi2BiosPage2BootDevice_t, MPI2_POINTER pMpi2BiosPage2BootDevice_t;
1212 typedef struct _MPI2_CONFIG_PAGE_BIOS_2
1214 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1215 U32 Reserved1; /* 0x04 */
1216 U32 Reserved2; /* 0x08 */
1217 U32 Reserved3; /* 0x0C */
1218 U32 Reserved4; /* 0x10 */
1219 U32 Reserved5; /* 0x14 */
1220 U32 Reserved6; /* 0x18 */
1221 U8 ReqBootDeviceForm; /* 0x1C */
1222 U8 Reserved7; /* 0x1D */
1223 U16 Reserved8; /* 0x1E */
1224 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedBootDevice; /* 0x20 */
1225 U8 ReqAltBootDeviceForm; /* 0x38 */
1226 U8 Reserved9; /* 0x39 */
1227 U16 Reserved10; /* 0x3A */
1228 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedAltBootDevice; /* 0x3C */
1229 U8 CurrentBootDeviceForm; /* 0x58 */
1230 U8 Reserved11; /* 0x59 */
1231 U16 Reserved12; /* 0x5A */
1232 MPI2_BIOSPAGE2_BOOT_DEVICE CurrentBootDevice; /* 0x58 */
1233 } MPI2_CONFIG_PAGE_BIOS_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_2,
1234 Mpi2BiosPage2_t, MPI2_POINTER pMpi2BiosPage2_t;
1236 #define MPI2_BIOSPAGE2_PAGEVERSION (0x04)
1238 /* values for BIOS Page 2 BootDeviceForm fields */
1239 #define MPI2_BIOSPAGE2_FORM_MASK (0x0F)
1240 #define MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED (0x00)
1241 #define MPI2_BIOSPAGE2_FORM_SAS_WWID (0x05)
1242 #define MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06)
1243 #define MPI2_BIOSPAGE2_FORM_DEVICE_NAME (0x07)
1248 typedef struct _MPI2_ADAPTER_INFO
1250 U8 PciBusNumber; /* 0x00 */
1251 U8 PciDeviceAndFunctionNumber; /* 0x01 */
1252 U16 AdapterFlags; /* 0x02 */
1253 } MPI2_ADAPTER_INFO, MPI2_POINTER PTR_MPI2_ADAPTER_INFO,
1254 Mpi2AdapterInfo_t, MPI2_POINTER pMpi2AdapterInfo_t;
1256 #define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001)
1257 #define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002)
1259 typedef struct _MPI2_CONFIG_PAGE_BIOS_3
1261 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1262 U32 GlobalFlags; /* 0x04 */
1263 U32 BiosVersion; /* 0x08 */
1264 MPI2_ADAPTER_INFO AdapterOrder[4]; /* 0x0C */
1265 U32 Reserved1; /* 0x1C */
1266 } MPI2_CONFIG_PAGE_BIOS_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_3,
1267 Mpi2BiosPage3_t, MPI2_POINTER pMpi2BiosPage3_t;
1269 #define MPI2_BIOSPAGE3_PAGEVERSION (0x00)
1271 /* values for BIOS Page 3 GlobalFlags */
1272 #define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR (0x00000002)
1273 #define MPI2_BIOSPAGE3_FLAGS_VERBOSE_ENABLE (0x00000004)
1274 #define MPI2_BIOSPAGE3_FLAGS_HOOK_INT_40_DISABLE (0x00000010)
1276 #define MPI2_BIOSPAGE3_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0)
1277 #define MPI2_BIOSPAGE3_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000)
1278 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DISPLAY (0x00000020)
1279 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040)
1285 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1286 * one and check the value returned for NumPhys at runtime.
1288 #ifndef MPI2_BIOS_PAGE_4_PHY_ENTRIES
1289 #define MPI2_BIOS_PAGE_4_PHY_ENTRIES (1)
1292 typedef struct _MPI2_BIOS4_ENTRY
1294 U64 ReassignmentWWID; /* 0x00 */
1295 U64 ReassignmentDeviceName; /* 0x08 */
1296 } MPI2_BIOS4_ENTRY, MPI2_POINTER PTR_MPI2_BIOS4_ENTRY,
1297 Mpi2MBios4Entry_t, MPI2_POINTER pMpi2Bios4Entry_t;
1299 typedef struct _MPI2_CONFIG_PAGE_BIOS_4
1301 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1302 U8 NumPhys; /* 0x04 */
1303 U8 Reserved1; /* 0x05 */
1304 U16 Reserved2; /* 0x06 */
1305 MPI2_BIOS4_ENTRY Phy[MPI2_BIOS_PAGE_4_PHY_ENTRIES]; /* 0x08 */
1306 } MPI2_CONFIG_PAGE_BIOS_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_4,
1307 Mpi2BiosPage4_t, MPI2_POINTER pMpi2BiosPage4_t;
1309 #define MPI2_BIOSPAGE4_PAGEVERSION (0x01)
1312 /****************************************************************************
1313 * RAID Volume Config Pages
1314 ****************************************************************************/
1316 /* RAID Volume Page 0 */
1318 typedef struct _MPI2_RAIDVOL0_PHYS_DISK
1320 U8 RAIDSetNum; /* 0x00 */
1321 U8 PhysDiskMap; /* 0x01 */
1322 U8 PhysDiskNum; /* 0x02 */
1323 U8 Reserved; /* 0x03 */
1324 } MPI2_RAIDVOL0_PHYS_DISK, MPI2_POINTER PTR_MPI2_RAIDVOL0_PHYS_DISK,
1325 Mpi2RaidVol0PhysDisk_t, MPI2_POINTER pMpi2RaidVol0PhysDisk_t;
1327 /* defines for the PhysDiskMap field */
1328 #define MPI2_RAIDVOL0_PHYSDISK_PRIMARY (0x01)
1329 #define MPI2_RAIDVOL0_PHYSDISK_SECONDARY (0x02)
1331 typedef struct _MPI2_RAIDVOL0_SETTINGS
1333 U16 Settings; /* 0x00 */
1334 U8 HotSparePool; /* 0x01 */
1335 U8 Reserved; /* 0x02 */
1336 } MPI2_RAIDVOL0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDVOL0_SETTINGS,
1337 Mpi2RaidVol0Settings_t, MPI2_POINTER pMpi2RaidVol0Settings_t;
1339 /* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */
1340 #define MPI2_RAID_HOT_SPARE_POOL_0 (0x01)
1341 #define MPI2_RAID_HOT_SPARE_POOL_1 (0x02)
1342 #define MPI2_RAID_HOT_SPARE_POOL_2 (0x04)
1343 #define MPI2_RAID_HOT_SPARE_POOL_3 (0x08)
1344 #define MPI2_RAID_HOT_SPARE_POOL_4 (0x10)
1345 #define MPI2_RAID_HOT_SPARE_POOL_5 (0x20)
1346 #define MPI2_RAID_HOT_SPARE_POOL_6 (0x40)
1347 #define MPI2_RAID_HOT_SPARE_POOL_7 (0x80)
1349 /* RAID Volume Page 0 VolumeSettings defines */
1350 #define MPI2_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0008)
1351 #define MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE (0x0004)
1353 #define MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING (0x0003)
1354 #define MPI2_RAIDVOL0_SETTING_UNCHANGED (0x0000)
1355 #define MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING (0x0001)
1356 #define MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING (0x0002)
1359 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1360 * one and check the value returned for NumPhysDisks at runtime.
1362 #ifndef MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX
1363 #define MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX (1)
1366 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_0
1368 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1369 U16 DevHandle; /* 0x04 */
1370 U8 VolumeState; /* 0x06 */
1371 U8 VolumeType; /* 0x07 */
1372 U32 VolumeStatusFlags; /* 0x08 */
1373 MPI2_RAIDVOL0_SETTINGS VolumeSettings; /* 0x0C */
1374 U64 MaxLBA; /* 0x10 */
1375 U32 StripeSize; /* 0x18 */
1376 U16 BlockSize; /* 0x1C */
1377 U16 Reserved1; /* 0x1E */
1378 U8 SupportedPhysDisks; /* 0x20 */
1379 U8 ResyncRate; /* 0x21 */
1380 U16 DataScrubDuration; /* 0x22 */
1381 U8 NumPhysDisks; /* 0x24 */
1382 U8 Reserved2; /* 0x25 */
1383 U8 Reserved3; /* 0x26 */
1384 U8 InactiveStatus; /* 0x27 */
1385 MPI2_RAIDVOL0_PHYS_DISK PhysDisk[MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX]; /* 0x28 */
1386 } MPI2_CONFIG_PAGE_RAID_VOL_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_0,
1387 Mpi2RaidVolPage0_t, MPI2_POINTER pMpi2RaidVolPage0_t;
1389 #define MPI2_RAIDVOLPAGE0_PAGEVERSION (0x0A)
1391 /* values for RAID VolumeState */
1392 #define MPI2_RAID_VOL_STATE_MISSING (0x00)
1393 #define MPI2_RAID_VOL_STATE_FAILED (0x01)
1394 #define MPI2_RAID_VOL_STATE_INITIALIZING (0x02)
1395 #define MPI2_RAID_VOL_STATE_ONLINE (0x03)
1396 #define MPI2_RAID_VOL_STATE_DEGRADED (0x04)
1397 #define MPI2_RAID_VOL_STATE_OPTIMAL (0x05)
1399 /* values for RAID VolumeType */
1400 #define MPI2_RAID_VOL_TYPE_RAID0 (0x00)
1401 #define MPI2_RAID_VOL_TYPE_RAID1E (0x01)
1402 #define MPI2_RAID_VOL_TYPE_RAID1 (0x02)
1403 #define MPI2_RAID_VOL_TYPE_RAID10 (0x05)
1404 #define MPI2_RAID_VOL_TYPE_UNKNOWN (0xFF)
1406 /* values for RAID Volume Page 0 VolumeStatusFlags field */
1407 #define MPI2_RAIDVOL0_STATUS_FLAG_PENDING_RESYNC (0x02000000)
1408 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKG_INIT_PENDING (0x01000000)
1409 #define MPI2_RAIDVOL0_STATUS_FLAG_MDC_PENDING (0x00800000)
1410 #define MPI2_RAIDVOL0_STATUS_FLAG_USER_CONSIST_PENDING (0x00400000)
1411 #define MPI2_RAIDVOL0_STATUS_FLAG_MAKE_DATA_CONSISTENT (0x00200000)
1412 #define MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB (0x00100000)
1413 #define MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK (0x00080000)
1414 #define MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION (0x00040000)
1415 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT (0x00020000)
1416 #define MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x00010000)
1417 #define MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT (0x00000080)
1418 #define MPI2_RAIDVOL0_STATUS_FLAG_OCE_ALLOWED (0x00000040)
1419 #define MPI2_RAIDVOL0_STATUS_FLAG_BGI_COMPLETE (0x00000020)
1420 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_OFFSET_MIRROR (0x00000000)
1421 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_ADJACENT_MIRROR (0x00000010)
1422 #define MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x00000008)
1423 #define MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x00000004)
1424 #define MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED (0x00000002)
1425 #define MPI2_RAIDVOL0_STATUS_FLAG_ENABLED (0x00000001)
1427 /* values for RAID Volume Page 0 SupportedPhysDisks field */
1428 #define MPI2_RAIDVOL0_SUPPORT_SOLID_STATE_DISKS (0x08)
1429 #define MPI2_RAIDVOL0_SUPPORT_HARD_DISKS (0x04)
1430 #define MPI2_RAIDVOL0_SUPPORT_SAS_PROTOCOL (0x02)
1431 #define MPI2_RAIDVOL0_SUPPORT_SATA_PROTOCOL (0x01)
1433 /* values for RAID Volume Page 0 InactiveStatus field */
1434 #define MPI2_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00)
1435 #define MPI2_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01)
1436 #define MPI2_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02)
1437 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03)
1438 #define MPI2_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04)
1439 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05)
1440 #define MPI2_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06)
1443 /* RAID Volume Page 1 */
1445 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_1
1447 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1448 U16 DevHandle; /* 0x04 */
1449 U16 Reserved0; /* 0x06 */
1450 U8 GUID[24]; /* 0x08 */
1451 U8 Name[16]; /* 0x20 */
1452 U64 WWID; /* 0x30 */
1453 U32 Reserved1; /* 0x38 */
1454 U32 Reserved2; /* 0x3C */
1455 } MPI2_CONFIG_PAGE_RAID_VOL_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_1,
1456 Mpi2RaidVolPage1_t, MPI2_POINTER pMpi2RaidVolPage1_t;
1458 #define MPI2_RAIDVOLPAGE1_PAGEVERSION (0x03)
1461 /****************************************************************************
1462 * RAID Physical Disk Config Pages
1463 ****************************************************************************/
1465 /* RAID Physical Disk Page 0 */
1467 typedef struct _MPI2_RAIDPHYSDISK0_SETTINGS
1469 U16 Reserved1; /* 0x00 */
1470 U8 HotSparePool; /* 0x02 */
1471 U8 Reserved2; /* 0x03 */
1472 } MPI2_RAIDPHYSDISK0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_SETTINGS,
1473 Mpi2RaidPhysDisk0Settings_t, MPI2_POINTER pMpi2RaidPhysDisk0Settings_t;
1475 /* use MPI2_RAID_HOT_SPARE_POOL_ defines for the HotSparePool field */
1477 typedef struct _MPI2_RAIDPHYSDISK0_INQUIRY_DATA
1479 U8 VendorID[8]; /* 0x00 */
1480 U8 ProductID[16]; /* 0x08 */
1481 U8 ProductRevLevel[4]; /* 0x18 */
1482 U8 SerialNum[32]; /* 0x1C */
1483 } MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
1484 MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
1485 Mpi2RaidPhysDisk0InquiryData_t, MPI2_POINTER pMpi2RaidPhysDisk0InquiryData_t;
1487 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_0
1489 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1490 U16 DevHandle; /* 0x04 */
1491 U8 Reserved1; /* 0x06 */
1492 U8 PhysDiskNum; /* 0x07 */
1493 MPI2_RAIDPHYSDISK0_SETTINGS PhysDiskSettings; /* 0x08 */
1494 U32 Reserved2; /* 0x0C */
1495 MPI2_RAIDPHYSDISK0_INQUIRY_DATA InquiryData; /* 0x10 */
1496 U32 Reserved3; /* 0x4C */
1497 U8 PhysDiskState; /* 0x50 */
1498 U8 OfflineReason; /* 0x51 */
1499 U8 IncompatibleReason; /* 0x52 */
1500 U8 PhysDiskAttributes; /* 0x53 */
1501 U32 PhysDiskStatusFlags; /* 0x54 */
1502 U64 DeviceMaxLBA; /* 0x58 */
1503 U64 HostMaxLBA; /* 0x60 */
1504 U64 CoercedMaxLBA; /* 0x68 */
1505 U16 BlockSize; /* 0x70 */
1506 U16 Reserved5; /* 0x72 */
1507 U32 Reserved6; /* 0x74 */
1508 } MPI2_CONFIG_PAGE_RD_PDISK_0,
1509 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_0,
1510 Mpi2RaidPhysDiskPage0_t, MPI2_POINTER pMpi2RaidPhysDiskPage0_t;
1512 #define MPI2_RAIDPHYSDISKPAGE0_PAGEVERSION (0x05)
1514 /* PhysDiskState defines */
1515 #define MPI2_RAID_PD_STATE_NOT_CONFIGURED (0x00)
1516 #define MPI2_RAID_PD_STATE_NOT_COMPATIBLE (0x01)
1517 #define MPI2_RAID_PD_STATE_OFFLINE (0x02)
1518 #define MPI2_RAID_PD_STATE_ONLINE (0x03)
1519 #define MPI2_RAID_PD_STATE_HOT_SPARE (0x04)
1520 #define MPI2_RAID_PD_STATE_DEGRADED (0x05)
1521 #define MPI2_RAID_PD_STATE_REBUILDING (0x06)
1522 #define MPI2_RAID_PD_STATE_OPTIMAL (0x07)
1524 /* OfflineReason defines */
1525 #define MPI2_PHYSDISK0_ONLINE (0x00)
1526 #define MPI2_PHYSDISK0_OFFLINE_MISSING (0x01)
1527 #define MPI2_PHYSDISK0_OFFLINE_FAILED (0x03)
1528 #define MPI2_PHYSDISK0_OFFLINE_INITIALIZING (0x04)
1529 #define MPI2_PHYSDISK0_OFFLINE_REQUESTED (0x05)
1530 #define MPI2_PHYSDISK0_OFFLINE_FAILED_REQUESTED (0x06)
1531 #define MPI2_PHYSDISK0_OFFLINE_OTHER (0xFF)
1533 /* IncompatibleReason defines */
1534 #define MPI2_PHYSDISK0_COMPATIBLE (0x00)
1535 #define MPI2_PHYSDISK0_INCOMPATIBLE_PROTOCOL (0x01)
1536 #define MPI2_PHYSDISK0_INCOMPATIBLE_BLOCKSIZE (0x02)
1537 #define MPI2_PHYSDISK0_INCOMPATIBLE_MAX_LBA (0x03)
1538 #define MPI2_PHYSDISK0_INCOMPATIBLE_SATA_EXTENDED_CMD (0x04)
1539 #define MPI2_PHYSDISK0_INCOMPATIBLE_REMOVEABLE_MEDIA (0x05)
1540 #define MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE (0x06)
1541 #define MPI2_PHYSDISK0_INCOMPATIBLE_UNKNOWN (0xFF)
1543 /* PhysDiskAttributes defines */
1544 #define MPI2_PHYSDISK0_ATTRIB_MEDIA_MASK (0x0C)
1545 #define MPI2_PHYSDISK0_ATTRIB_SOLID_STATE_DRIVE (0x08)
1546 #define MPI2_PHYSDISK0_ATTRIB_HARD_DISK_DRIVE (0x04)
1548 #define MPI2_PHYSDISK0_ATTRIB_PROTOCOL_MASK (0x03)
1549 #define MPI2_PHYSDISK0_ATTRIB_SAS_PROTOCOL (0x02)
1550 #define MPI2_PHYSDISK0_ATTRIB_SATA_PROTOCOL (0x01)
1552 /* PhysDiskStatusFlags defines */
1553 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED (0x00000040)
1554 #define MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET (0x00000020)
1555 #define MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED (0x00000010)
1556 #define MPI2_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00000000)
1557 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x00000008)
1558 #define MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x00000004)
1559 #define MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED (0x00000002)
1560 #define MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x00000001)
1563 /* RAID Physical Disk Page 1 */
1566 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1567 * one and check the value returned for NumPhysDiskPaths at runtime.
1569 #ifndef MPI2_RAID_PHYS_DISK1_PATH_MAX
1570 #define MPI2_RAID_PHYS_DISK1_PATH_MAX (1)
1573 typedef struct _MPI2_RAIDPHYSDISK1_PATH
1575 U16 DevHandle; /* 0x00 */
1576 U16 Reserved1; /* 0x02 */
1577 U64 WWID; /* 0x04 */
1578 U64 OwnerWWID; /* 0x0C */
1579 U8 OwnerIdentifier; /* 0x14 */
1580 U8 Reserved2; /* 0x15 */
1581 U16 Flags; /* 0x16 */
1582 } MPI2_RAIDPHYSDISK1_PATH, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK1_PATH,
1583 Mpi2RaidPhysDisk1Path_t, MPI2_POINTER pMpi2RaidPhysDisk1Path_t;
1585 /* RAID Physical Disk Page 1 Physical Disk Path Flags field defines */
1586 #define MPI2_RAID_PHYSDISK1_FLAG_PRIMARY (0x0004)
1587 #define MPI2_RAID_PHYSDISK1_FLAG_BROKEN (0x0002)
1588 #define MPI2_RAID_PHYSDISK1_FLAG_INVALID (0x0001)
1590 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_1
1592 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1593 U8 NumPhysDiskPaths; /* 0x04 */
1594 U8 PhysDiskNum; /* 0x05 */
1595 U16 Reserved1; /* 0x06 */
1596 U32 Reserved2; /* 0x08 */
1597 MPI2_RAIDPHYSDISK1_PATH PhysicalDiskPath[MPI2_RAID_PHYS_DISK1_PATH_MAX];/* 0x0C */
1598 } MPI2_CONFIG_PAGE_RD_PDISK_1,
1599 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_1,
1600 Mpi2RaidPhysDiskPage1_t, MPI2_POINTER pMpi2RaidPhysDiskPage1_t;
1602 #define MPI2_RAIDPHYSDISKPAGE1_PAGEVERSION (0x02)
1605 /****************************************************************************
1606 * values for fields used by several types of SAS Config Pages
1607 ****************************************************************************/
1609 /* values for NegotiatedLinkRates fields */
1610 #define MPI2_SAS_NEG_LINK_RATE_MASK_LOGICAL (0xF0)
1611 #define MPI2_SAS_NEG_LINK_RATE_SHIFT_LOGICAL (4)
1612 #define MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL (0x0F)
1613 /* link rates used for Negotiated Physical and Logical Link Rate */
1614 #define MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00)
1615 #define MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01)
1616 #define MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02)
1617 #define MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE (0x03)
1618 #define MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR (0x04)
1619 #define MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS (0x05)
1620 #define MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY (0x06)
1621 #define MPI2_SAS_NEG_LINK_RATE_1_5 (0x08)
1622 #define MPI2_SAS_NEG_LINK_RATE_3_0 (0x09)
1623 #define MPI2_SAS_NEG_LINK_RATE_6_0 (0x0A)
1626 /* values for AttachedPhyInfo fields */
1627 #define MPI2_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT (0x00000040)
1628 #define MPI2_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS (0x00000020)
1629 #define MPI2_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010)
1631 #define MPI2_SAS_APHYINFO_REASON_MASK (0x0000000F)
1632 #define MPI2_SAS_APHYINFO_REASON_UNKNOWN (0x00000000)
1633 #define MPI2_SAS_APHYINFO_REASON_POWER_ON (0x00000001)
1634 #define MPI2_SAS_APHYINFO_REASON_HARD_RESET (0x00000002)
1635 #define MPI2_SAS_APHYINFO_REASON_SMP_PHY_CONTROL (0x00000003)
1636 #define MPI2_SAS_APHYINFO_REASON_LOSS_OF_SYNC (0x00000004)
1637 #define MPI2_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ (0x00000005)
1638 #define MPI2_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00000006)
1639 #define MPI2_SAS_APHYINFO_REASON_BREAK_TIMEOUT (0x00000007)
1640 #define MPI2_SAS_APHYINFO_REASON_PHY_TEST_STOPPED (0x00000008)
1643 /* values for PhyInfo fields */
1644 #define MPI2_SAS_PHYINFO_PHY_VACANT (0x80000000)
1646 #define MPI2_SAS_PHYINFO_PHY_POWER_CONDITION_MASK (0x18000000)
1647 #define MPI2_SAS_PHYINFO_SHIFT_PHY_POWER_CONDITION (27)
1648 #define MPI2_SAS_PHYINFO_PHY_POWER_ACTIVE (0x00000000)
1649 #define MPI2_SAS_PHYINFO_PHY_POWER_PARTIAL (0x08000000)
1650 #define MPI2_SAS_PHYINFO_PHY_POWER_SLUMBER (0x10000000)
1652 #define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS (0x04000000)
1653 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT (0x02000000)
1654 #define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS (0x01000000)
1655 #define MPI2_SAS_PHYINFO_ZONE_GROUP_PERSISTENT (0x00400000)
1656 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS (0x00200000)
1657 #define MPI2_SAS_PHYINFO_ZONING_ENABLED (0x00100000)
1659 #define MPI2_SAS_PHYINFO_REASON_MASK (0x000F0000)
1660 #define MPI2_SAS_PHYINFO_REASON_UNKNOWN (0x00000000)
1661 #define MPI2_SAS_PHYINFO_REASON_POWER_ON (0x00010000)
1662 #define MPI2_SAS_PHYINFO_REASON_HARD_RESET (0x00020000)
1663 #define MPI2_SAS_PHYINFO_REASON_SMP_PHY_CONTROL (0x00030000)
1664 #define MPI2_SAS_PHYINFO_REASON_LOSS_OF_SYNC (0x00040000)
1665 #define MPI2_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ (0x00050000)
1666 #define MPI2_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00060000)
1667 #define MPI2_SAS_PHYINFO_REASON_BREAK_TIMEOUT (0x00070000)
1668 #define MPI2_SAS_PHYINFO_REASON_PHY_TEST_STOPPED (0x00080000)
1670 #define MPI2_SAS_PHYINFO_MULTIPLEXING_SUPPORTED (0x00008000)
1671 #define MPI2_SAS_PHYINFO_SATA_PORT_ACTIVE (0x00004000)
1672 #define MPI2_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT (0x00002000)
1673 #define MPI2_SAS_PHYINFO_VIRTUAL_PHY (0x00001000)
1675 #define MPI2_SAS_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00)
1676 #define MPI2_SAS_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8)
1678 #define MPI2_SAS_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0)
1679 #define MPI2_SAS_PHYINFO_DIRECT_ROUTING (0x00000000)
1680 #define MPI2_SAS_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010)
1681 #define MPI2_SAS_PHYINFO_TABLE_ROUTING (0x00000020)
1684 /* values for SAS ProgrammedLinkRate fields */
1685 #define MPI2_SAS_PRATE_MAX_RATE_MASK (0xF0)
1686 #define MPI2_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00)
1687 #define MPI2_SAS_PRATE_MAX_RATE_1_5 (0x80)
1688 #define MPI2_SAS_PRATE_MAX_RATE_3_0 (0x90)
1689 #define MPI2_SAS_PRATE_MAX_RATE_6_0 (0xA0)
1690 #define MPI2_SAS_PRATE_MIN_RATE_MASK (0x0F)
1691 #define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00)
1692 #define MPI2_SAS_PRATE_MIN_RATE_1_5 (0x08)
1693 #define MPI2_SAS_PRATE_MIN_RATE_3_0 (0x09)
1694 #define MPI2_SAS_PRATE_MIN_RATE_6_0 (0x0A)
1697 /* values for SAS HwLinkRate fields */
1698 #define MPI2_SAS_HWRATE_MAX_RATE_MASK (0xF0)
1699 #define MPI2_SAS_HWRATE_MAX_RATE_1_5 (0x80)
1700 #define MPI2_SAS_HWRATE_MAX_RATE_3_0 (0x90)
1701 #define MPI2_SAS_HWRATE_MAX_RATE_6_0 (0xA0)
1702 #define MPI2_SAS_HWRATE_MIN_RATE_MASK (0x0F)
1703 #define MPI2_SAS_HWRATE_MIN_RATE_1_5 (0x08)
1704 #define MPI2_SAS_HWRATE_MIN_RATE_3_0 (0x09)
1705 #define MPI2_SAS_HWRATE_MIN_RATE_6_0 (0x0A)
1709 /****************************************************************************
1710 * SAS IO Unit Config Pages
1711 ****************************************************************************/
1713 /* SAS IO Unit Page 0 */
1715 typedef struct _MPI2_SAS_IO_UNIT0_PHY_DATA
1718 U8 PortFlags; /* 0x01 */
1719 U8 PhyFlags; /* 0x02 */
1720 U8 NegotiatedLinkRate; /* 0x03 */
1721 U32 ControllerPhyDeviceInfo;/* 0x04 */
1722 U16 AttachedDevHandle; /* 0x08 */
1723 U16 ControllerDevHandle; /* 0x0A */
1724 U32 DiscoveryStatus; /* 0x0C */
1725 U32 Reserved; /* 0x10 */
1726 } MPI2_SAS_IO_UNIT0_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT0_PHY_DATA,
1727 Mpi2SasIOUnit0PhyData_t, MPI2_POINTER pMpi2SasIOUnit0PhyData_t;
1730 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1731 * one and check the value returned for NumPhys at runtime.
1733 #ifndef MPI2_SAS_IOUNIT0_PHY_MAX
1734 #define MPI2_SAS_IOUNIT0_PHY_MAX (1)
1737 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_0
1739 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1740 U32 Reserved1; /* 0x08 */
1741 U8 NumPhys; /* 0x0C */
1742 U8 Reserved2; /* 0x0D */
1743 U16 Reserved3; /* 0x0E */
1744 MPI2_SAS_IO_UNIT0_PHY_DATA PhyData[MPI2_SAS_IOUNIT0_PHY_MAX]; /* 0x10 */
1745 } MPI2_CONFIG_PAGE_SASIOUNIT_0,
1746 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_0,
1747 Mpi2SasIOUnitPage0_t, MPI2_POINTER pMpi2SasIOUnitPage0_t;
1749 #define MPI2_SASIOUNITPAGE0_PAGEVERSION (0x05)
1751 /* values for SAS IO Unit Page 0 PortFlags */
1752 #define MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS (0x08)
1753 #define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG (0x01)
1755 /* values for SAS IO Unit Page 0 PhyFlags */
1756 #define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED (0x10)
1757 #define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08)
1759 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
1761 /* see mpi2_sas.h for values for SAS IO Unit Page 0 ControllerPhyDeviceInfo values */
1763 /* values for SAS IO Unit Page 0 DiscoveryStatus */
1764 #define MPI2_SASIOUNIT0_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
1765 #define MPI2_SASIOUNIT0_DS_MAX_EXPANDERS_EXCEED (0x40000000)
1766 #define MPI2_SASIOUNIT0_DS_MAX_DEVICES_EXCEED (0x20000000)
1767 #define MPI2_SASIOUNIT0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
1768 #define MPI2_SASIOUNIT0_DS_DOWNSTREAM_INITIATOR (0x08000000)
1769 #define MPI2_SASIOUNIT0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
1770 #define MPI2_SASIOUNIT0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
1771 #define MPI2_SASIOUNIT0_DS_MULTI_PORT_DOMAIN (0x00002000)
1772 #define MPI2_SASIOUNIT0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
1773 #define MPI2_SASIOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800)
1774 #define MPI2_SASIOUNIT0_DS_TABLE_LINK (0x00000400)
1775 #define MPI2_SASIOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200)
1776 #define MPI2_SASIOUNIT0_DS_SMP_CRC_ERROR (0x00000100)
1777 #define MPI2_SASIOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080)
1778 #define MPI2_SASIOUNIT0_DS_INDEX_NOT_EXIST (0x00000040)
1779 #define MPI2_SASIOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020)
1780 #define MPI2_SASIOUNIT0_DS_SMP_TIMEOUT (0x00000010)
1781 #define MPI2_SASIOUNIT0_DS_MULTIPLE_PORTS (0x00000004)
1782 #define MPI2_SASIOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002)
1783 #define MPI2_SASIOUNIT0_DS_LOOP_DETECTED (0x00000001)
1786 /* SAS IO Unit Page 1 */
1788 typedef struct _MPI2_SAS_IO_UNIT1_PHY_DATA
1791 U8 PortFlags; /* 0x01 */
1792 U8 PhyFlags; /* 0x02 */
1793 U8 MaxMinLinkRate; /* 0x03 */
1794 U32 ControllerPhyDeviceInfo; /* 0x04 */
1795 U16 MaxTargetPortConnectTime; /* 0x08 */
1796 U16 Reserved1; /* 0x0A */
1797 } MPI2_SAS_IO_UNIT1_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT1_PHY_DATA,
1798 Mpi2SasIOUnit1PhyData_t, MPI2_POINTER pMpi2SasIOUnit1PhyData_t;
1801 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1802 * one and check the value returned for NumPhys at runtime.
1804 #ifndef MPI2_SAS_IOUNIT1_PHY_MAX
1805 #define MPI2_SAS_IOUNIT1_PHY_MAX (1)
1808 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_1
1810 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1811 U16 ControlFlags; /* 0x08 */
1812 U16 SASNarrowMaxQueueDepth; /* 0x0A */
1813 U16 AdditionalControlFlags; /* 0x0C */
1814 U16 SASWideMaxQueueDepth; /* 0x0E */
1815 U8 NumPhys; /* 0x10 */
1816 U8 SATAMaxQDepth; /* 0x11 */
1817 U8 ReportDeviceMissingDelay; /* 0x12 */
1818 U8 IODeviceMissingDelay; /* 0x13 */
1819 MPI2_SAS_IO_UNIT1_PHY_DATA PhyData[MPI2_SAS_IOUNIT1_PHY_MAX]; /* 0x14 */
1820 } MPI2_CONFIG_PAGE_SASIOUNIT_1,
1821 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_1,
1822 Mpi2SasIOUnitPage1_t, MPI2_POINTER pMpi2SasIOUnitPage1_t;
1824 #define MPI2_SASIOUNITPAGE1_PAGEVERSION (0x09)
1826 /* values for SAS IO Unit Page 1 ControlFlags */
1827 #define MPI2_SASIOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000)
1828 #define MPI2_SASIOUNIT1_CONTROL_SATA_3_0_MAX (0x4000)
1829 #define MPI2_SASIOUNIT1_CONTROL_SATA_1_5_MAX (0x2000)
1830 #define MPI2_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000)
1832 #define MPI2_SASIOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600)
1833 #define MPI2_SASIOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9)
1834 #define MPI2_SASIOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x0)
1835 #define MPI2_SASIOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x1)
1836 #define MPI2_SASIOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x2)
1838 #define MPI2_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080)
1839 #define MPI2_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040)
1840 #define MPI2_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020)
1841 #define MPI2_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010)
1842 #define MPI2_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL (0x0008)
1843 #define MPI2_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004)
1844 #define MPI2_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002)
1845 #define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001)
1847 /* values for SAS IO Unit Page 1 AdditionalControlFlags */
1848 #define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080)
1849 #define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040)
1850 #define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION (0x0020)
1851 #define MPI2_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010)
1852 #define MPI2_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008)
1853 #define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004)
1854 #define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002)
1855 #define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001)
1857 /* defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */
1858 #define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F)
1859 #define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16 (0x80)
1861 /* values for SAS IO Unit Page 1 PortFlags */
1862 #define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01)
1864 /* values for SAS IO Unit Page 1 PhyFlags */
1865 #define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE (0x10)
1866 #define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08)
1868 /* values for SAS IO Unit Page 1 MaxMinLinkRate */
1869 #define MPI2_SASIOUNIT1_MAX_RATE_MASK (0xF0)
1870 #define MPI2_SASIOUNIT1_MAX_RATE_1_5 (0x80)
1871 #define MPI2_SASIOUNIT1_MAX_RATE_3_0 (0x90)
1872 #define MPI2_SASIOUNIT1_MAX_RATE_6_0 (0xA0)
1873 #define MPI2_SASIOUNIT1_MIN_RATE_MASK (0x0F)
1874 #define MPI2_SASIOUNIT1_MIN_RATE_1_5 (0x08)
1875 #define MPI2_SASIOUNIT1_MIN_RATE_3_0 (0x09)
1876 #define MPI2_SASIOUNIT1_MIN_RATE_6_0 (0x0A)
1878 /* see mpi2_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */
1881 /* SAS IO Unit Page 4 */
1883 typedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP
1885 U8 MaxTargetSpinup; /* 0x00 */
1886 U8 SpinupDelay; /* 0x01 */
1887 U16 Reserved1; /* 0x02 */
1888 } MPI2_SAS_IOUNIT4_SPINUP_GROUP, MPI2_POINTER PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP,
1889 Mpi2SasIOUnit4SpinupGroup_t, MPI2_POINTER pMpi2SasIOUnit4SpinupGroup_t;
1892 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1893 * one and check the value returned for NumPhys at runtime.
1895 #ifndef MPI2_SAS_IOUNIT4_PHY_MAX
1896 #define MPI2_SAS_IOUNIT4_PHY_MAX (4)
1899 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_4
1901 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1902 MPI2_SAS_IOUNIT4_SPINUP_GROUP SpinupGroupParameters[4]; /* 0x08 */
1903 U32 Reserved1; /* 0x18 */
1904 U32 Reserved2; /* 0x1C */
1905 U32 Reserved3; /* 0x20 */
1906 U8 BootDeviceWaitTime; /* 0x24 */
1907 U8 Reserved4; /* 0x25 */
1908 U16 Reserved5; /* 0x26 */
1909 U8 NumPhys; /* 0x28 */
1910 U8 PEInitialSpinupDelay; /* 0x29 */
1911 U8 PEReplyDelay; /* 0x2A */
1912 U8 Flags; /* 0x2B */
1913 U8 PHY[MPI2_SAS_IOUNIT4_PHY_MAX]; /* 0x2C */
1914 } MPI2_CONFIG_PAGE_SASIOUNIT_4,
1915 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4,
1916 Mpi2SasIOUnitPage4_t, MPI2_POINTER pMpi2SasIOUnitPage4_t;
1918 #define MPI2_SASIOUNITPAGE4_PAGEVERSION (0x02)
1920 /* defines for Flags field */
1921 #define MPI2_SASIOUNIT4_FLAGS_AUTO_PORTENABLE (0x01)
1923 /* defines for PHY field */
1924 #define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK (0x03)
1927 /* SAS IO Unit Page 5 */
1929 typedef struct _MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS
1931 U8 ControlFlags; /* 0x00 */
1932 U8 PortWidthModGroup; /* 0x01 */
1933 U16 InactivityTimerExponent; /* 0x02 */
1934 U8 SATAPartialTimeout; /* 0x04 */
1935 U8 Reserved2; /* 0x05 */
1936 U8 SATASlumberTimeout; /* 0x06 */
1937 U8 Reserved3; /* 0x07 */
1938 U8 SASPartialTimeout; /* 0x08 */
1939 U8 Reserved4; /* 0x09 */
1940 U8 SASSlumberTimeout; /* 0x0A */
1941 U8 Reserved5; /* 0x0B */
1942 } MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
1943 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
1944 Mpi2SasIOUnit5PhyPmSettings_t, MPI2_POINTER pMpi2SasIOUnit5PhyPmSettings_t;
1946 /* defines for ControlFlags field */
1947 #define MPI2_SASIOUNIT5_CONTROL_SAS_SLUMBER_ENABLE (0x08)
1948 #define MPI2_SASIOUNIT5_CONTROL_SAS_PARTIAL_ENABLE (0x04)
1949 #define MPI2_SASIOUNIT5_CONTROL_SATA_SLUMBER_ENABLE (0x02)
1950 #define MPI2_SASIOUNIT5_CONTROL_SATA_PARTIAL_ENABLE (0x01)
1952 /* defines for PortWidthModeGroup field */
1953 #define MPI2_SASIOUNIT5_PWMG_DISABLE (0xFF)
1955 /* defines for InactivityTimerExponent field */
1956 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_SLUMBER (0x7000)
1957 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_SLUMBER (12)
1958 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_PARTIAL (0x0700)
1959 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_PARTIAL (8)
1960 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_SLUMBER (0x0070)
1961 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_SLUMBER (4)
1962 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_PARTIAL (0x0007)
1963 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_PARTIAL (0)
1965 #define MPI2_SASIOUNIT5_ITE_TEN_SECONDS (7)
1966 #define MPI2_SASIOUNIT5_ITE_ONE_SECOND (6)
1967 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MILLISECONDS (5)
1968 #define MPI2_SASIOUNIT5_ITE_TEN_MILLISECONDS (4)
1969 #define MPI2_SASIOUNIT5_ITE_ONE_MILLISECOND (3)
1970 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MICROSECONDS (2)
1971 #define MPI2_SASIOUNIT5_ITE_TEN_MICROSECONDS (1)
1972 #define MPI2_SASIOUNIT5_ITE_ONE_MICROSECOND (0)
1975 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1976 * one and check the value returned for NumPhys at runtime.
1978 #ifndef MPI2_SAS_IOUNIT5_PHY_MAX
1979 #define MPI2_SAS_IOUNIT5_PHY_MAX (1)
1982 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_5
1984 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1985 U8 NumPhys; /* 0x08 */
1986 U8 Reserved1; /* 0x09 */
1987 U16 Reserved2; /* 0x0A */
1988 U32 Reserved3; /* 0x0C */
1989 MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS SASPhyPowerManagementSettings[MPI2_SAS_IOUNIT5_PHY_MAX]; /* 0x10 */
1990 } MPI2_CONFIG_PAGE_SASIOUNIT_5,
1991 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_5,
1992 Mpi2SasIOUnitPage5_t, MPI2_POINTER pMpi2SasIOUnitPage5_t;
1994 #define MPI2_SASIOUNITPAGE5_PAGEVERSION (0x01)
1997 /* SAS IO Unit Page 6 */
1999 typedef struct _MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS
2001 U8 CurrentStatus; /* 0x00 */
2002 U8 CurrentModulation; /* 0x01 */
2003 U8 CurrentUtilization; /* 0x02 */
2004 U8 Reserved1; /* 0x03 */
2005 U32 Reserved2; /* 0x04 */
2006 } MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS,
2007 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS,
2008 Mpi2SasIOUnit6PortWidthModGroupStatus_t,
2009 MPI2_POINTER pMpi2SasIOUnit6PortWidthModGroupStatus_t;
2011 /* defines for CurrentStatus field */
2012 #define MPI2_SASIOUNIT6_STATUS_UNAVAILABLE (0x00)
2013 #define MPI2_SASIOUNIT6_STATUS_UNCONFIGURED (0x01)
2014 #define MPI2_SASIOUNIT6_STATUS_INVALID_CONFIG (0x02)
2015 #define MPI2_SASIOUNIT6_STATUS_LINK_DOWN (0x03)
2016 #define MPI2_SASIOUNIT6_STATUS_OBSERVATION_ONLY (0x04)
2017 #define MPI2_SASIOUNIT6_STATUS_INACTIVE (0x05)
2018 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_IOUNIT (0x06)
2019 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_HOST (0x07)
2021 /* defines for CurrentModulation field */
2022 #define MPI2_SASIOUNIT6_MODULATION_25_PERCENT (0x00)
2023 #define MPI2_SASIOUNIT6_MODULATION_50_PERCENT (0x01)
2024 #define MPI2_SASIOUNIT6_MODULATION_75_PERCENT (0x02)
2025 #define MPI2_SASIOUNIT6_MODULATION_100_PERCENT (0x03)
2028 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2029 * one and check the value returned for NumGroups at runtime.
2031 #ifndef MPI2_SAS_IOUNIT6_GROUP_MAX
2032 #define MPI2_SAS_IOUNIT6_GROUP_MAX (1)
2035 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_6
2037 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2038 U32 Reserved1; /* 0x08 */
2039 U32 Reserved2; /* 0x0C */
2040 U8 NumGroups; /* 0x10 */
2041 U8 Reserved3; /* 0x11 */
2042 U16 Reserved4; /* 0x12 */
2043 MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS
2044 PortWidthModulationGroupStatus[MPI2_SAS_IOUNIT6_GROUP_MAX]; /* 0x14 */
2045 } MPI2_CONFIG_PAGE_SASIOUNIT_6,
2046 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_6,
2047 Mpi2SasIOUnitPage6_t, MPI2_POINTER pMpi2SasIOUnitPage6_t;
2049 #define MPI2_SASIOUNITPAGE6_PAGEVERSION (0x00)
2052 /* SAS IO Unit Page 7 */
2054 typedef struct _MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS
2056 U8 Flags; /* 0x00 */
2057 U8 Reserved1; /* 0x01 */
2058 U16 Reserved2; /* 0x02 */
2059 U8 Threshold75Pct; /* 0x04 */
2060 U8 Threshold50Pct; /* 0x05 */
2061 U8 Threshold25Pct; /* 0x06 */
2062 U8 Reserved3; /* 0x07 */
2063 } MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS,
2064 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS,
2065 Mpi2SasIOUnit7PortWidthModGroupSettings_t,
2066 MPI2_POINTER pMpi2SasIOUnit7PortWidthModGroupSettings_t;
2068 /* defines for Flags field */
2069 #define MPI2_SASIOUNIT7_FLAGS_ENABLE_PORT_WIDTH_MODULATION (0x01)
2073 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2074 * one and check the value returned for NumGroups at runtime.
2076 #ifndef MPI2_SAS_IOUNIT7_GROUP_MAX
2077 #define MPI2_SAS_IOUNIT7_GROUP_MAX (1)
2080 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_7
2082 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2083 U8 SamplingInterval; /* 0x08 */
2084 U8 WindowLength; /* 0x09 */
2085 U16 Reserved1; /* 0x0A */
2086 U32 Reserved2; /* 0x0C */
2087 U32 Reserved3; /* 0x10 */
2088 U8 NumGroups; /* 0x14 */
2089 U8 Reserved4; /* 0x15 */
2090 U16 Reserved5; /* 0x16 */
2091 MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS
2092 PortWidthModulationGroupSettings[MPI2_SAS_IOUNIT7_GROUP_MAX]; /* 0x18 */
2093 } MPI2_CONFIG_PAGE_SASIOUNIT_7,
2094 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_7,
2095 Mpi2SasIOUnitPage7_t, MPI2_POINTER pMpi2SasIOUnitPage7_t;
2097 #define MPI2_SASIOUNITPAGE7_PAGEVERSION (0x00)
2100 /* SAS IO Unit Page 8 */
2102 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_8
2104 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2105 U32 Reserved1; /* 0x08 */
2106 U32 PowerManagementCapabilities; /* 0x0C */
2107 U32 Reserved2; /* 0x10 */
2108 } MPI2_CONFIG_PAGE_SASIOUNIT_8,
2109 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_8,
2110 Mpi2SasIOUnitPage8_t, MPI2_POINTER pMpi2SasIOUnitPage8_t;
2112 #define MPI2_SASIOUNITPAGE8_PAGEVERSION (0x00)
2114 /* defines for PowerManagementCapabilities field */
2115 #define MPI2_SASIOUNIT8_PM_HOST_PORT_WIDTH_MOD (0x000001000)
2116 #define MPI2_SASIOUNIT8_PM_HOST_SAS_SLUMBER_MODE (0x000000800)
2117 #define MPI2_SASIOUNIT8_PM_HOST_SAS_PARTIAL_MODE (0x000000400)
2118 #define MPI2_SASIOUNIT8_PM_HOST_SATA_SLUMBER_MODE (0x000000200)
2119 #define MPI2_SASIOUNIT8_PM_HOST_SATA_PARTIAL_MODE (0x000000100)
2120 #define MPI2_SASIOUNIT8_PM_IOUNIT_PORT_WIDTH_MOD (0x000000010)
2121 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_SLUMBER_MODE (0x000000008)
2122 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_PARTIAL_MODE (0x000000004)
2123 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_SLUMBER_MODE (0x000000002)
2124 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_PARTIAL_MODE (0x000000001)
2129 /****************************************************************************
2130 * SAS Expander Config Pages
2131 ****************************************************************************/
2133 /* SAS Expander Page 0 */
2135 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_0
2137 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2138 U8 PhysicalPort; /* 0x08 */
2139 U8 ReportGenLength; /* 0x09 */
2140 U16 EnclosureHandle; /* 0x0A */
2141 U64 SASAddress; /* 0x0C */
2142 U32 DiscoveryStatus; /* 0x14 */
2143 U16 DevHandle; /* 0x18 */
2144 U16 ParentDevHandle; /* 0x1A */
2145 U16 ExpanderChangeCount; /* 0x1C */
2146 U16 ExpanderRouteIndexes; /* 0x1E */
2147 U8 NumPhys; /* 0x20 */
2148 U8 SASLevel; /* 0x21 */
2149 U16 Flags; /* 0x22 */
2150 U16 STPBusInactivityTimeLimit; /* 0x24 */
2151 U16 STPMaxConnectTimeLimit; /* 0x26 */
2152 U16 STP_SMP_NexusLossTime; /* 0x28 */
2153 U16 MaxNumRoutedSasAddresses; /* 0x2A */
2154 U64 ActiveZoneManagerSASAddress;/* 0x2C */
2155 U16 ZoneLockInactivityLimit; /* 0x34 */
2156 U16 Reserved1; /* 0x36 */
2157 U8 TimeToReducedFunc; /* 0x38 */
2158 U8 InitialTimeToReducedFunc; /* 0x39 */
2159 U8 MaxReducedFuncTime; /* 0x3A */
2160 U8 Reserved2; /* 0x3B */
2161 } MPI2_CONFIG_PAGE_EXPANDER_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_0,
2162 Mpi2ExpanderPage0_t, MPI2_POINTER pMpi2ExpanderPage0_t;
2164 #define MPI2_SASEXPANDER0_PAGEVERSION (0x06)
2166 /* values for SAS Expander Page 0 DiscoveryStatus field */
2167 #define MPI2_SAS_EXPANDER0_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
2168 #define MPI2_SAS_EXPANDER0_DS_MAX_EXPANDERS_EXCEED (0x40000000)
2169 #define MPI2_SAS_EXPANDER0_DS_MAX_DEVICES_EXCEED (0x20000000)
2170 #define MPI2_SAS_EXPANDER0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
2171 #define MPI2_SAS_EXPANDER0_DS_DOWNSTREAM_INITIATOR (0x08000000)
2172 #define MPI2_SAS_EXPANDER0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
2173 #define MPI2_SAS_EXPANDER0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
2174 #define MPI2_SAS_EXPANDER0_DS_MULTI_PORT_DOMAIN (0x00002000)
2175 #define MPI2_SAS_EXPANDER0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
2176 #define MPI2_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800)
2177 #define MPI2_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400)
2178 #define MPI2_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200)
2179 #define MPI2_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100)
2180 #define MPI2_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080)
2181 #define MPI2_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040)
2182 #define MPI2_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020)
2183 #define MPI2_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010)
2184 #define MPI2_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004)
2185 #define MPI2_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002)
2186 #define MPI2_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001)
2188 /* values for SAS Expander Page 0 Flags field */
2189 #define MPI2_SAS_EXPANDER0_FLAGS_REDUCED_FUNCTIONALITY (0x2000)
2190 #define MPI2_SAS_EXPANDER0_FLAGS_ZONE_LOCKED (0x1000)
2191 #define MPI2_SAS_EXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES (0x0800)
2192 #define MPI2_SAS_EXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES (0x0400)
2193 #define MPI2_SAS_EXPANDER0_FLAGS_ZONING_SUPPORT (0x0200)
2194 #define MPI2_SAS_EXPANDER0_FLAGS_ENABLED_ZONING (0x0100)
2195 #define MPI2_SAS_EXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT (0x0080)
2196 #define MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x0010)
2197 #define MPI2_SAS_EXPANDER0_FLAGS_OTHERS_CONFIG (0x0004)
2198 #define MPI2_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x0002)
2199 #define MPI2_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x0001)
2202 /* SAS Expander Page 1 */
2204 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_1
2206 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2207 U8 PhysicalPort; /* 0x08 */
2208 U8 Reserved1; /* 0x09 */
2209 U16 Reserved2; /* 0x0A */
2210 U8 NumPhys; /* 0x0C */
2212 U16 NumTableEntriesProgrammed; /* 0x0E */
2213 U8 ProgrammedLinkRate; /* 0x10 */
2214 U8 HwLinkRate; /* 0x11 */
2215 U16 AttachedDevHandle; /* 0x12 */
2216 U32 PhyInfo; /* 0x14 */
2217 U32 AttachedDeviceInfo; /* 0x18 */
2218 U16 ExpanderDevHandle; /* 0x1C */
2219 U8 ChangeCount; /* 0x1E */
2220 U8 NegotiatedLinkRate; /* 0x1F */
2221 U8 PhyIdentifier; /* 0x20 */
2222 U8 AttachedPhyIdentifier; /* 0x21 */
2223 U8 Reserved3; /* 0x22 */
2224 U8 DiscoveryInfo; /* 0x23 */
2225 U32 AttachedPhyInfo; /* 0x24 */
2226 U8 ZoneGroup; /* 0x28 */
2227 U8 SelfConfigStatus; /* 0x29 */
2228 U16 Reserved4; /* 0x2A */
2229 } MPI2_CONFIG_PAGE_EXPANDER_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_1,
2230 Mpi2ExpanderPage1_t, MPI2_POINTER pMpi2ExpanderPage1_t;
2232 #define MPI2_SASEXPANDER1_PAGEVERSION (0x02)
2234 /* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
2236 /* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
2238 /* use MPI2_SAS_PHYINFO_ for the PhyInfo field */
2240 /* see mpi2_sas.h for the MPI2_SAS_DEVICE_INFO_ defines used for the AttachedDeviceInfo field */
2242 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
2244 /* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
2246 /* values for SAS Expander Page 1 DiscoveryInfo field */
2247 #define MPI2_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04)
2248 #define MPI2_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02)
2249 #define MPI2_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01)
2252 /****************************************************************************
2253 * SAS Device Config Pages
2254 ****************************************************************************/
2256 /* SAS Device Page 0 */
2258 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_0
2260 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2261 U16 Slot; /* 0x08 */
2262 U16 EnclosureHandle; /* 0x0A */
2263 U64 SASAddress; /* 0x0C */
2264 U16 ParentDevHandle; /* 0x14 */
2265 U8 PhyNum; /* 0x16 */
2266 U8 AccessStatus; /* 0x17 */
2267 U16 DevHandle; /* 0x18 */
2268 U8 AttachedPhyIdentifier; /* 0x1A */
2269 U8 ZoneGroup; /* 0x1B */
2270 U32 DeviceInfo; /* 0x1C */
2271 U16 Flags; /* 0x20 */
2272 U8 PhysicalPort; /* 0x22 */
2273 U8 MaxPortConnections; /* 0x23 */
2274 U64 DeviceName; /* 0x24 */
2275 U8 PortGroups; /* 0x2C */
2276 U8 DmaGroup; /* 0x2D */
2277 U8 ControlGroup; /* 0x2E */
2278 U8 Reserved1; /* 0x2F */
2279 U32 Reserved2; /* 0x30 */
2280 U32 Reserved3; /* 0x34 */
2281 } MPI2_CONFIG_PAGE_SAS_DEV_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_0,
2282 Mpi2SasDevicePage0_t, MPI2_POINTER pMpi2SasDevicePage0_t;
2284 #define MPI2_SASDEVICE0_PAGEVERSION (0x08)
2286 /* values for SAS Device Page 0 AccessStatus field */
2287 #define MPI2_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00)
2288 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01)
2289 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02)
2290 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT (0x03)
2291 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION (0x04)
2292 #define MPI2_SAS_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE (0x05)
2293 #define MPI2_SAS_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE (0x06)
2294 #define MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED (0x07)
2295 /* specific values for SATA Init failures */
2296 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN (0x10)
2297 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x11)
2298 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_DIAG (0x12)
2299 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x13)
2300 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x14)
2301 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_PIO_SN (0x15)
2302 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN (0x16)
2303 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN (0x17)
2304 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x18)
2305 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x19)
2306 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MAX (0x1F)
2308 /* see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */
2310 /* values for SAS Device Page 0 Flags field */
2311 #define MPI2_SAS_DEVICE0_FLAGS_SLUMBER_PM_CAPABLE (0x1000)
2312 #define MPI2_SAS_DEVICE0_FLAGS_PARTIAL_PM_CAPABLE (0x0800)
2313 #define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400)
2314 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200)
2315 #define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100)
2316 #define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080)
2317 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040)
2318 #define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020)
2319 #define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010)
2320 #define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008)
2321 #define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001)
2324 /* SAS Device Page 1 */
2326 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1
2328 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2329 U32 Reserved1; /* 0x08 */
2330 U64 SASAddress; /* 0x0C */
2331 U32 Reserved2; /* 0x14 */
2332 U16 DevHandle; /* 0x18 */
2333 U16 Reserved3; /* 0x1A */
2334 U8 InitialRegDeviceFIS[20];/* 0x1C */
2335 } MPI2_CONFIG_PAGE_SAS_DEV_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_1,
2336 Mpi2SasDevicePage1_t, MPI2_POINTER pMpi2SasDevicePage1_t;
2338 #define MPI2_SASDEVICE1_PAGEVERSION (0x01)
2341 /****************************************************************************
2342 * SAS PHY Config Pages
2343 ****************************************************************************/
2345 /* SAS PHY Page 0 */
2347 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_0
2349 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2350 U16 OwnerDevHandle; /* 0x08 */
2351 U16 Reserved1; /* 0x0A */
2352 U16 AttachedDevHandle; /* 0x0C */
2353 U8 AttachedPhyIdentifier; /* 0x0E */
2354 U8 Reserved2; /* 0x0F */
2355 U32 AttachedPhyInfo; /* 0x10 */
2356 U8 ProgrammedLinkRate; /* 0x14 */
2357 U8 HwLinkRate; /* 0x15 */
2358 U8 ChangeCount; /* 0x16 */
2359 U8 Flags; /* 0x17 */
2360 U32 PhyInfo; /* 0x18 */
2361 U8 NegotiatedLinkRate; /* 0x1C */
2362 U8 Reserved3; /* 0x1D */
2363 U16 Reserved4; /* 0x1E */
2364 } MPI2_CONFIG_PAGE_SAS_PHY_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_0,
2365 Mpi2SasPhyPage0_t, MPI2_POINTER pMpi2SasPhyPage0_t;
2367 #define MPI2_SASPHY0_PAGEVERSION (0x03)
2369 /* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
2371 /* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
2373 /* values for SAS PHY Page 0 Flags field */
2374 #define MPI2_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01)
2376 /* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
2378 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
2380 /* use MPI2_SAS_PHYINFO_ for the PhyInfo field */
2383 /* SAS PHY Page 1 */
2385 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_1
2387 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2388 U32 Reserved1; /* 0x08 */
2389 U32 InvalidDwordCount; /* 0x0C */
2390 U32 RunningDisparityErrorCount; /* 0x10 */
2391 U32 LossDwordSynchCount; /* 0x14 */
2392 U32 PhyResetProblemCount; /* 0x18 */
2393 } MPI2_CONFIG_PAGE_SAS_PHY_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_1,
2394 Mpi2SasPhyPage1_t, MPI2_POINTER pMpi2SasPhyPage1_t;
2396 #define MPI2_SASPHY1_PAGEVERSION (0x01)
2399 /* SAS PHY Page 2 */
2401 typedef struct _MPI2_SASPHY2_PHY_EVENT
2403 U8 PhyEventCode; /* 0x00 */
2404 U8 Reserved1; /* 0x01 */
2405 U16 Reserved2; /* 0x02 */
2406 U32 PhyEventInfo; /* 0x04 */
2407 } MPI2_SASPHY2_PHY_EVENT, MPI2_POINTER PTR_MPI2_SASPHY2_PHY_EVENT,
2408 Mpi2SasPhy2PhyEvent_t, MPI2_POINTER pMpi2SasPhy2PhyEvent_t;
2410 /* use MPI2_SASPHY3_EVENT_CODE_ for the PhyEventCode field */
2414 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2415 * one and check the value returned for NumPhyEvents at runtime.
2417 #ifndef MPI2_SASPHY2_PHY_EVENT_MAX
2418 #define MPI2_SASPHY2_PHY_EVENT_MAX (1)
2421 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_2
2423 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2424 U32 Reserved1; /* 0x08 */
2425 U8 NumPhyEvents; /* 0x0C */
2426 U8 Reserved2; /* 0x0D */
2427 U16 Reserved3; /* 0x0E */
2428 MPI2_SASPHY2_PHY_EVENT PhyEvent[MPI2_SASPHY2_PHY_EVENT_MAX]; /* 0x10 */
2429 } MPI2_CONFIG_PAGE_SAS_PHY_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_2,
2430 Mpi2SasPhyPage2_t, MPI2_POINTER pMpi2SasPhyPage2_t;
2432 #define MPI2_SASPHY2_PAGEVERSION (0x00)
2435 /* SAS PHY Page 3 */
2437 typedef struct _MPI2_SASPHY3_PHY_EVENT_CONFIG
2439 U8 PhyEventCode; /* 0x00 */
2440 U8 Reserved1; /* 0x01 */
2441 U16 Reserved2; /* 0x02 */
2442 U8 CounterType; /* 0x04 */
2443 U8 ThresholdWindow; /* 0x05 */
2444 U8 TimeUnits; /* 0x06 */
2445 U8 Reserved3; /* 0x07 */
2446 U32 EventThreshold; /* 0x08 */
2447 U16 ThresholdFlags; /* 0x0C */
2448 U16 Reserved4; /* 0x0E */
2449 } MPI2_SASPHY3_PHY_EVENT_CONFIG, MPI2_POINTER PTR_MPI2_SASPHY3_PHY_EVENT_CONFIG,
2450 Mpi2SasPhy3PhyEventConfig_t, MPI2_POINTER pMpi2SasPhy3PhyEventConfig_t;
2452 /* values for PhyEventCode field */
2453 #define MPI2_SASPHY3_EVENT_CODE_NO_EVENT (0x00)
2454 #define MPI2_SASPHY3_EVENT_CODE_INVALID_DWORD (0x01)
2455 #define MPI2_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR (0x02)
2456 #define MPI2_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC (0x03)
2457 #define MPI2_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM (0x04)
2458 #define MPI2_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW (0x05)
2459 #define MPI2_SASPHY3_EVENT_CODE_RX_ERROR (0x06)
2460 #define MPI2_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR (0x20)
2461 #define MPI2_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT (0x21)
2462 #define MPI2_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT (0x22)
2463 #define MPI2_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT (0x23)
2464 #define MPI2_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT (0x24)
2465 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON (0x25)
2466 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON (0x26)
2467 #define MPI2_SASPHY3_EVENT_CODE_TX_BREAK (0x27)
2468 #define MPI2_SASPHY3_EVENT_CODE_RX_BREAK (0x28)
2469 #define MPI2_SASPHY3_EVENT_CODE_BREAK_TIMEOUT (0x29)
2470 #define MPI2_SASPHY3_EVENT_CODE_CONNECTION (0x2A)
2471 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED (0x2B)
2472 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME (0x2C)
2473 #define MPI2_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME (0x2D)
2474 #define MPI2_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME (0x2E)
2475 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_FRAMES (0x40)
2476 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_FRAMES (0x41)
2477 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES (0x42)
2478 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES (0x43)
2479 #define MPI2_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED (0x44)
2480 #define MPI2_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED (0x45)
2481 #define MPI2_SASPHY3_EVENT_CODE_TX_SATA_FRAMES (0x50)
2482 #define MPI2_SASPHY3_EVENT_CODE_RX_SATA_FRAMES (0x51)
2483 #define MPI2_SASPHY3_EVENT_CODE_SATA_OVERFLOW (0x52)
2484 #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_FRAMES (0x60)
2485 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_FRAMES (0x61)
2486 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES (0x63)
2487 #define MPI2_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT (0xD0)
2488 #define MPI2_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE (0xD1)
2489 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP (0xD2)
2491 /* values for the CounterType field */
2492 #define MPI2_SASPHY3_COUNTER_TYPE_WRAPPING (0x00)
2493 #define MPI2_SASPHY3_COUNTER_TYPE_SATURATING (0x01)
2494 #define MPI2_SASPHY3_COUNTER_TYPE_PEAK_VALUE (0x02)
2496 /* values for the TimeUnits field */
2497 #define MPI2_SASPHY3_TIME_UNITS_10_MICROSECONDS (0x00)
2498 #define MPI2_SASPHY3_TIME_UNITS_100_MICROSECONDS (0x01)
2499 #define MPI2_SASPHY3_TIME_UNITS_1_MILLISECOND (0x02)
2500 #define MPI2_SASPHY3_TIME_UNITS_10_MILLISECONDS (0x03)
2502 /* values for the ThresholdFlags field */
2503 #define MPI2_SASPHY3_TFLAGS_PHY_RESET (0x0002)
2504 #define MPI2_SASPHY3_TFLAGS_EVENT_NOTIFY (0x0001)
2507 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2508 * one and check the value returned for NumPhyEvents at runtime.
2510 #ifndef MPI2_SASPHY3_PHY_EVENT_MAX
2511 #define MPI2_SASPHY3_PHY_EVENT_MAX (1)
2514 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_3
2516 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2517 U32 Reserved1; /* 0x08 */
2518 U8 NumPhyEvents; /* 0x0C */
2519 U8 Reserved2; /* 0x0D */
2520 U16 Reserved3; /* 0x0E */
2521 MPI2_SASPHY3_PHY_EVENT_CONFIG PhyEventConfig[MPI2_SASPHY3_PHY_EVENT_MAX]; /* 0x10 */
2522 } MPI2_CONFIG_PAGE_SAS_PHY_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_3,
2523 Mpi2SasPhyPage3_t, MPI2_POINTER pMpi2SasPhyPage3_t;
2525 #define MPI2_SASPHY3_PAGEVERSION (0x00)
2528 /* SAS PHY Page 4 */
2530 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_4
2532 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2533 U16 Reserved1; /* 0x08 */
2534 U8 Reserved2; /* 0x0A */
2535 U8 Flags; /* 0x0B */
2536 U8 InitialFrame[28]; /* 0x0C */
2537 } MPI2_CONFIG_PAGE_SAS_PHY_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_4,
2538 Mpi2SasPhyPage4_t, MPI2_POINTER pMpi2SasPhyPage4_t;
2540 #define MPI2_SASPHY4_PAGEVERSION (0x00)
2542 /* values for the Flags field */
2543 #define MPI2_SASPHY4_FLAGS_FRAME_VALID (0x02)
2544 #define MPI2_SASPHY4_FLAGS_SATA_FRAME (0x01)
2549 /****************************************************************************
2550 * SAS Port Config Pages
2551 ****************************************************************************/
2553 /* SAS Port Page 0 */
2555 typedef struct _MPI2_CONFIG_PAGE_SAS_PORT_0
2557 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2558 U8 PortNumber; /* 0x08 */
2559 U8 PhysicalPort; /* 0x09 */
2560 U8 PortWidth; /* 0x0A */
2561 U8 PhysicalPortWidth; /* 0x0B */
2562 U8 ZoneGroup; /* 0x0C */
2563 U8 Reserved1; /* 0x0D */
2564 U16 Reserved2; /* 0x0E */
2565 U64 SASAddress; /* 0x10 */
2566 U32 DeviceInfo; /* 0x18 */
2567 U32 Reserved3; /* 0x1C */
2568 U32 Reserved4; /* 0x20 */
2569 } MPI2_CONFIG_PAGE_SAS_PORT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PORT_0,
2570 Mpi2SasPortPage0_t, MPI2_POINTER pMpi2SasPortPage0_t;
2572 #define MPI2_SASPORT0_PAGEVERSION (0x00)
2574 /* see mpi2_sas.h for values for SAS Port Page 0 DeviceInfo values */
2577 /****************************************************************************
2578 * SAS Enclosure Config Pages
2579 ****************************************************************************/
2581 /* SAS Enclosure Page 0 */
2583 typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0
2585 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2586 U32 Reserved1; /* 0x08 */
2587 U64 EnclosureLogicalID; /* 0x0C */
2588 U16 Flags; /* 0x14 */
2589 U16 EnclosureHandle; /* 0x16 */
2590 U16 NumSlots; /* 0x18 */
2591 U16 StartSlot; /* 0x1A */
2592 U16 Reserved2; /* 0x1C */
2593 U16 SEPDevHandle; /* 0x1E */
2594 U32 Reserved3; /* 0x20 */
2595 U32 Reserved4; /* 0x24 */
2596 } MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
2597 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
2598 Mpi2SasEnclosurePage0_t, MPI2_POINTER pMpi2SasEnclosurePage0_t;
2600 #define MPI2_SASENCLOSURE0_PAGEVERSION (0x03)
2602 /* values for SAS Enclosure Page 0 Flags field */
2603 #define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F)
2604 #define MPI2_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000)
2605 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001)
2606 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002)
2607 #define MPI2_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003)
2608 #define MPI2_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004)
2609 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005)
2612 /****************************************************************************
2614 ****************************************************************************/
2619 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2620 * one and check the value returned for NumLogEntries at runtime.
2622 #ifndef MPI2_LOG_0_NUM_LOG_ENTRIES
2623 #define MPI2_LOG_0_NUM_LOG_ENTRIES (1)
2626 #define MPI2_LOG_0_LOG_DATA_LENGTH (0x1C)
2628 typedef struct _MPI2_LOG_0_ENTRY
2630 U64 TimeStamp; /* 0x00 */
2631 U32 Reserved1; /* 0x08 */
2632 U16 LogSequence; /* 0x0C */
2633 U16 LogEntryQualifier; /* 0x0E */
2634 U8 VP_ID; /* 0x10 */
2635 U8 VF_ID; /* 0x11 */
2636 U16 Reserved2; /* 0x12 */
2637 U8 LogData[MPI2_LOG_0_LOG_DATA_LENGTH];/* 0x14 */
2638 } MPI2_LOG_0_ENTRY, MPI2_POINTER PTR_MPI2_LOG_0_ENTRY,
2639 Mpi2Log0Entry_t, MPI2_POINTER pMpi2Log0Entry_t;
2641 /* values for Log Page 0 LogEntry LogEntryQualifier field */
2642 #define MPI2_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000)
2643 #define MPI2_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001)
2644 #define MPI2_LOG_0_ENTRY_QUAL_TIMESTAMP_UPDATE (0x0002)
2645 #define MPI2_LOG_0_ENTRY_QUAL_MIN_IMPLEMENT_SPEC (0x8000)
2646 #define MPI2_LOG_0_ENTRY_QUAL_MAX_IMPLEMENT_SPEC (0xFFFF)
2648 typedef struct _MPI2_CONFIG_PAGE_LOG_0
2650 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2651 U32 Reserved1; /* 0x08 */
2652 U32 Reserved2; /* 0x0C */
2653 U16 NumLogEntries; /* 0x10 */
2654 U16 Reserved3; /* 0x12 */
2655 MPI2_LOG_0_ENTRY LogEntry[MPI2_LOG_0_NUM_LOG_ENTRIES]; /* 0x14 */
2656 } MPI2_CONFIG_PAGE_LOG_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_LOG_0,
2657 Mpi2LogPage0_t, MPI2_POINTER pMpi2LogPage0_t;
2659 #define MPI2_LOG_0_PAGEVERSION (0x02)
2662 /****************************************************************************
2664 ****************************************************************************/
2669 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2670 * one and check the value returned for NumElements at runtime.
2672 #ifndef MPI2_RAIDCONFIG0_MAX_ELEMENTS
2673 #define MPI2_RAIDCONFIG0_MAX_ELEMENTS (1)
2676 typedef struct _MPI2_RAIDCONFIG0_CONFIG_ELEMENT
2678 U16 ElementFlags; /* 0x00 */
2679 U16 VolDevHandle; /* 0x02 */
2680 U8 HotSparePool; /* 0x04 */
2681 U8 PhysDiskNum; /* 0x05 */
2682 U16 PhysDiskDevHandle; /* 0x06 */
2683 } MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
2684 MPI2_POINTER PTR_MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
2685 Mpi2RaidConfig0ConfigElement_t, MPI2_POINTER pMpi2RaidConfig0ConfigElement_t;
2687 /* values for the ElementFlags field */
2688 #define MPI2_RAIDCONFIG0_EFLAGS_MASK_ELEMENT_TYPE (0x000F)
2689 #define MPI2_RAIDCONFIG0_EFLAGS_VOLUME_ELEMENT (0x0000)
2690 #define MPI2_RAIDCONFIG0_EFLAGS_VOL_PHYS_DISK_ELEMENT (0x0001)
2691 #define MPI2_RAIDCONFIG0_EFLAGS_HOT_SPARE_ELEMENT (0x0002)
2692 #define MPI2_RAIDCONFIG0_EFLAGS_OCE_ELEMENT (0x0003)
2695 typedef struct _MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0
2697 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2698 U8 NumHotSpares; /* 0x08 */
2699 U8 NumPhysDisks; /* 0x09 */
2700 U8 NumVolumes; /* 0x0A */
2701 U8 ConfigNum; /* 0x0B */
2702 U32 Flags; /* 0x0C */
2703 U8 ConfigGUID[24]; /* 0x10 */
2704 U32 Reserved1; /* 0x28 */
2705 U8 NumElements; /* 0x2C */
2706 U8 Reserved2; /* 0x2D */
2707 U16 Reserved3; /* 0x2E */
2708 MPI2_RAIDCONFIG0_CONFIG_ELEMENT ConfigElement[MPI2_RAIDCONFIG0_MAX_ELEMENTS]; /* 0x30 */
2709 } MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
2710 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
2711 Mpi2RaidConfigurationPage0_t, MPI2_POINTER pMpi2RaidConfigurationPage0_t;
2713 #define MPI2_RAIDCONFIG0_PAGEVERSION (0x00)
2715 /* values for RAID Configuration Page 0 Flags field */
2716 #define MPI2_RAIDCONFIG0_FLAG_FOREIGN_CONFIG (0x00000001)
2719 /****************************************************************************
2720 * Driver Persistent Mapping Config Pages
2721 ****************************************************************************/
2723 /* Driver Persistent Mapping Page 0 */
2725 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY
2727 U64 PhysicalIdentifier; /* 0x00 */
2728 U16 MappingInformation; /* 0x08 */
2729 U16 DeviceIndex; /* 0x0A */
2730 U32 PhysicalBitsMapping; /* 0x0C */
2731 U32 Reserved1; /* 0x10 */
2732 } MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
2733 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
2734 Mpi2DriverMap0Entry_t, MPI2_POINTER pMpi2DriverMap0Entry_t;
2736 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAPPING_0
2738 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2739 MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY Entry; /* 0x08 */
2740 } MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
2741 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
2742 Mpi2DriverMappingPage0_t, MPI2_POINTER pMpi2DriverMappingPage0_t;
2744 #define MPI2_DRIVERMAPPING0_PAGEVERSION (0x00)
2746 /* values for Driver Persistent Mapping Page 0 MappingInformation field */
2747 #define MPI2_DRVMAP0_MAPINFO_SLOT_MASK (0x07F0)
2748 #define MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT (4)
2749 #define MPI2_DRVMAP0_MAPINFO_MISSING_MASK (0x000F)
2752 /****************************************************************************
2753 * Ethernet Config Pages
2754 ****************************************************************************/
2756 /* Ethernet Page 0 */
2758 /* IP address (union of IPv4 and IPv6) */
2759 typedef union _MPI2_ETHERNET_IP_ADDR
2763 } MPI2_ETHERNET_IP_ADDR, MPI2_POINTER PTR_MPI2_ETHERNET_IP_ADDR,
2764 Mpi2EthernetIpAddr_t, MPI2_POINTER pMpi2EthernetIpAddr_t;
2766 #define MPI2_ETHERNET_HOST_NAME_LENGTH (32)
2768 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_0
2770 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2771 U8 NumInterfaces; /* 0x08 */
2772 U8 Reserved0; /* 0x09 */
2773 U16 Reserved1; /* 0x0A */
2774 U32 Status; /* 0x0C */
2775 U8 MediaState; /* 0x10 */
2776 U8 Reserved2; /* 0x11 */
2777 U16 Reserved3; /* 0x12 */
2778 U8 MacAddress[6]; /* 0x14 */
2779 U8 Reserved4; /* 0x1A */
2780 U8 Reserved5; /* 0x1B */
2781 MPI2_ETHERNET_IP_ADDR IpAddress; /* 0x1C */
2782 MPI2_ETHERNET_IP_ADDR SubnetMask; /* 0x2C */
2783 MPI2_ETHERNET_IP_ADDR GatewayIpAddress; /* 0x3C */
2784 MPI2_ETHERNET_IP_ADDR DNS1IpAddress; /* 0x4C */
2785 MPI2_ETHERNET_IP_ADDR DNS2IpAddress; /* 0x5C */
2786 MPI2_ETHERNET_IP_ADDR DhcpIpAddress; /* 0x6C */
2787 U8 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */
2788 } MPI2_CONFIG_PAGE_ETHERNET_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_0,
2789 Mpi2EthernetPage0_t, MPI2_POINTER pMpi2EthernetPage0_t;
2791 #define MPI2_ETHERNETPAGE0_PAGEVERSION (0x00)
2793 /* values for Ethernet Page 0 Status field */
2794 #define MPI2_ETHPG0_STATUS_IPV6_CAPABLE (0x80000000)
2795 #define MPI2_ETHPG0_STATUS_IPV4_CAPABLE (0x40000000)
2796 #define MPI2_ETHPG0_STATUS_CONSOLE_CONNECTED (0x20000000)
2797 #define MPI2_ETHPG0_STATUS_DEFAULT_IF (0x00000100)
2798 #define MPI2_ETHPG0_STATUS_FW_DWNLD_ENABLED (0x00000080)
2799 #define MPI2_ETHPG0_STATUS_TELNET_ENABLED (0x00000040)
2800 #define MPI2_ETHPG0_STATUS_SSH2_ENABLED (0x00000020)
2801 #define MPI2_ETHPG0_STATUS_DHCP_CLIENT_ENABLED (0x00000010)
2802 #define MPI2_ETHPG0_STATUS_IPV6_ENABLED (0x00000008)
2803 #define MPI2_ETHPG0_STATUS_IPV4_ENABLED (0x00000004)
2804 #define MPI2_ETHPG0_STATUS_IPV6_ADDRESSES (0x00000002)
2805 #define MPI2_ETHPG0_STATUS_ETH_IF_ENABLED (0x00000001)
2807 /* values for Ethernet Page 0 MediaState field */
2808 #define MPI2_ETHPG0_MS_DUPLEX_MASK (0x80)
2809 #define MPI2_ETHPG0_MS_HALF_DUPLEX (0x00)
2810 #define MPI2_ETHPG0_MS_FULL_DUPLEX (0x80)
2812 #define MPI2_ETHPG0_MS_CONNECT_SPEED_MASK (0x07)
2813 #define MPI2_ETHPG0_MS_NOT_CONNECTED (0x00)
2814 #define MPI2_ETHPG0_MS_10MBIT (0x01)
2815 #define MPI2_ETHPG0_MS_100MBIT (0x02)
2816 #define MPI2_ETHPG0_MS_1GBIT (0x03)
2819 /* Ethernet Page 1 */
2821 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_1
2823 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2824 U32 Reserved0; /* 0x08 */
2825 U32 Flags; /* 0x0C */
2826 U8 MediaState; /* 0x10 */
2827 U8 Reserved1; /* 0x11 */
2828 U16 Reserved2; /* 0x12 */
2829 U8 MacAddress[6]; /* 0x14 */
2830 U8 Reserved3; /* 0x1A */
2831 U8 Reserved4; /* 0x1B */
2832 MPI2_ETHERNET_IP_ADDR StaticIpAddress; /* 0x1C */
2833 MPI2_ETHERNET_IP_ADDR StaticSubnetMask; /* 0x2C */
2834 MPI2_ETHERNET_IP_ADDR StaticGatewayIpAddress; /* 0x3C */
2835 MPI2_ETHERNET_IP_ADDR StaticDNS1IpAddress; /* 0x4C */
2836 MPI2_ETHERNET_IP_ADDR StaticDNS2IpAddress; /* 0x5C */
2837 U32 Reserved5; /* 0x6C */
2838 U32 Reserved6; /* 0x70 */
2839 U32 Reserved7; /* 0x74 */
2840 U32 Reserved8; /* 0x78 */
2841 U8 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */
2842 } MPI2_CONFIG_PAGE_ETHERNET_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_1,
2843 Mpi2EthernetPage1_t, MPI2_POINTER pMpi2EthernetPage1_t;
2845 #define MPI2_ETHERNETPAGE1_PAGEVERSION (0x00)
2847 /* values for Ethernet Page 1 Flags field */
2848 #define MPI2_ETHPG1_FLAG_SET_DEFAULT_IF (0x00000100)
2849 #define MPI2_ETHPG1_FLAG_ENABLE_FW_DOWNLOAD (0x00000080)
2850 #define MPI2_ETHPG1_FLAG_ENABLE_TELNET (0x00000040)
2851 #define MPI2_ETHPG1_FLAG_ENABLE_SSH2 (0x00000020)
2852 #define MPI2_ETHPG1_FLAG_ENABLE_DHCP_CLIENT (0x00000010)
2853 #define MPI2_ETHPG1_FLAG_ENABLE_IPV6 (0x00000008)
2854 #define MPI2_ETHPG1_FLAG_ENABLE_IPV4 (0x00000004)
2855 #define MPI2_ETHPG1_FLAG_USE_IPV6_ADDRESSES (0x00000002)
2856 #define MPI2_ETHPG1_FLAG_ENABLE_ETH_IF (0x00000001)
2858 /* values for Ethernet Page 1 MediaState field */
2859 #define MPI2_ETHPG1_MS_DUPLEX_MASK (0x80)
2860 #define MPI2_ETHPG1_MS_HALF_DUPLEX (0x00)
2861 #define MPI2_ETHPG1_MS_FULL_DUPLEX (0x80)
2863 #define MPI2_ETHPG1_MS_DATA_RATE_MASK (0x07)
2864 #define MPI2_ETHPG1_MS_DATA_RATE_AUTO (0x00)
2865 #define MPI2_ETHPG1_MS_DATA_RATE_10MBIT (0x01)
2866 #define MPI2_ETHPG1_MS_DATA_RATE_100MBIT (0x02)
2867 #define MPI2_ETHPG1_MS_DATA_RATE_1GBIT (0x03)
2870 /****************************************************************************
2871 * Extended Manufacturing Config Pages
2872 ****************************************************************************/
2875 * Generic structure to use for product-specific extended manufacturing pages
2876 * (currently Extended Manufacturing Page 40 through Extended Manufacturing
2880 typedef struct _MPI2_CONFIG_PAGE_EXT_MAN_PS
2882 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2883 U32 ProductSpecificInfo; /* 0x08 */
2884 } MPI2_CONFIG_PAGE_EXT_MAN_PS,
2885 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXT_MAN_PS,
2886 Mpi2ExtManufacturingPagePS_t, MPI2_POINTER pMpi2ExtManufacturingPagePS_t;
2888 /* PageVersion should be provided by product-specific code */