2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2006-2015 LSI Corp.
5 * Copyright (c) 2013-2015 Avago Technologies
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
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12 * notice, this list of conditions and the following disclaimer.
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29 * Avago Technologies (LSI) MPT-Fusion Host Adapter FreeBSD
35 * Copyright (c) 2006-2015 LSI Corporation.
36 * Copyright (c) 2013-2015 Avago Technologies
40 * Title: MPI IOC, Port, Event, FW Download, and FW Upload messages
41 * Creation Date: October 11, 2006
43 * mpi2_ioc.h Version: 02.00.16
48 * Date Version Description
49 * -------- -------- ------------------------------------------------------
50 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
51 * 06-04-07 02.00.01 In IOCFacts Reply structure, renamed MaxDevices to
53 * Added TotalImageSize field to FWDownload Request.
54 * Added reserved words to FWUpload Request.
55 * 06-26-07 02.00.02 Added IR Configuration Change List Event.
56 * 08-31-07 02.00.03 Removed SystemReplyQueueDepth field from the IOCInit
57 * request and replaced it with
58 * ReplyDescriptorPostQueueDepth and ReplyFreeQueueDepth.
59 * Replaced the MinReplyQueueDepth field of the IOCFacts
60 * reply with MaxReplyDescriptorPostQueueDepth.
61 * Added MPI2_RDPQ_DEPTH_MIN define to specify the minimum
62 * depth for the Reply Descriptor Post Queue.
63 * Added SASAddress field to Initiator Device Table
64 * Overflow Event data.
65 * 10-31-07 02.00.04 Added ReasonCode MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING
66 * for SAS Initiator Device Status Change Event data.
67 * Modified Reason Code defines for SAS Topology Change
68 * List Event data, including adding a bit for PHY Vacant
69 * status, and adding a mask for the Reason Code.
71 * MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING.
72 * Added define for MPI2_EXT_IMAGE_TYPE_MEGARAID.
73 * 12-18-07 02.00.05 Added Boot Status defines for the IOCExceptions field of
75 * Removed MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
76 * Moved MPI2_VERSION_UNION to mpi2.h.
77 * Changed MPI2_EVENT_NOTIFICATION_REQUEST to use masks
78 * instead of enables, and added SASBroadcastPrimitiveMasks
80 * Added Log Entry Added Event and related structure.
81 * 02-29-08 02.00.06 Added define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID.
82 * Removed define MPI2_IOCFACTS_PROTOCOL_SMP_TARGET.
83 * Added MaxVolumes and MaxPersistentEntries fields to
85 * Added ProtocalFlags and IOCCapabilities fields to
86 * MPI2_FW_IMAGE_HEADER.
87 * Removed MPI2_PORTENABLE_FLAGS_ENABLE_SINGLE_PORT.
88 * 03-03-08 02.00.07 Fixed MPI2_FW_IMAGE_HEADER by changing Reserved26 to
90 * Removed extra 's' from EventMasks name.
91 * 06-27-08 02.00.08 Fixed an offset in a comment.
92 * 10-02-08 02.00.09 Removed SystemReplyFrameSize from MPI2_IOC_INIT_REQUEST.
93 * Removed CurReplyFrameSize from MPI2_IOC_FACTS_REPLY and
94 * renamed MinReplyFrameSize to ReplyFrameSize.
95 * Added MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX.
96 * Added two new RAIDOperation values for Integrated RAID
97 * Operations Status Event data.
98 * Added four new IR Configuration Change List Event data
100 * Added two new ReasonCode defines for SAS Device Status
102 * Added three new DiscoveryStatus bits for the SAS
103 * Discovery event data.
104 * Added Multiplexing Status Change bit to the PhyStatus
105 * field of the SAS Topology Change List event data.
106 * Removed define for MPI2_INIT_IMAGE_BOOTFLAGS_XMEMCOPY.
107 * BootFlags are now product-specific.
108 * Added defines for the indivdual signature bytes
109 * for MPI2_INIT_IMAGE_FOOTER.
110 * 01-19-09 02.00.10 Added MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY define.
111 * Added MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR
113 * Added MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE
115 * Removed MPI2_EVENT_SAS_DISC_DS_SATA_INIT_FAILURE define.
116 * 05-06-09 02.00.11 Added MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR define.
117 * Added MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX define.
118 * Added two new reason codes for SAS Device Status Change
120 * Added new event: SAS PHY Counter.
121 * 07-30-09 02.00.12 Added GPIO Interrupt event define and structure.
122 * Added MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
123 * Added new product id family for 2208.
124 * 10-28-09 02.00.13 Added HostMSIxVectors field to MPI2_IOC_INIT_REQUEST.
125 * Added MaxMSIxVectors field to MPI2_IOC_FACTS_REPLY.
126 * Added MinDevHandle field to MPI2_IOC_FACTS_REPLY.
127 * Added MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY.
128 * Added MPI2_EVENT_HOST_BASED_DISCOVERY_PHY define.
129 * Added MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER define.
130 * Added Host Based Discovery Phy Event data.
131 * Added defines for ProductID Product field
132 * (MPI2_FW_HEADER_PID_).
133 * Modified values for SAS ProductID Family
134 * (MPI2_FW_HEADER_PID_FAMILY_).
135 * 02-10-10 02.00.14 Added SAS Quiesce Event structure and defines.
136 * Added PowerManagementControl Request structures and
138 * 05-12-10 02.00.15 Marked Task Set Full Event as obsolete.
139 * Added MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY define.
140 * 11-10-10 02.00.16 Added MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC.
141 * --------------------------------------------------------------------------
147 /*****************************************************************************
151 *****************************************************************************/
153 /****************************************************************************
155 ****************************************************************************/
157 /* IOCInit Request message */
158 typedef struct _MPI2_IOC_INIT_REQUEST
160 U8 WhoInit; /* 0x00 */
161 U8 Reserved1; /* 0x01 */
162 U8 ChainOffset; /* 0x02 */
163 U8 Function; /* 0x03 */
164 U16 Reserved2; /* 0x04 */
165 U8 Reserved3; /* 0x06 */
166 U8 MsgFlags; /* 0x07 */
169 U16 Reserved4; /* 0x0A */
170 U16 MsgVersion; /* 0x0C */
171 U16 HeaderVersion; /* 0x0E */
172 U32 Reserved5; /* 0x10 */
173 U16 Reserved6; /* 0x14 */
174 U8 Reserved7; /* 0x16 */
175 U8 HostMSIxVectors; /* 0x17 */
176 U16 Reserved8; /* 0x18 */
177 U16 SystemRequestFrameSize; /* 0x1A */
178 U16 ReplyDescriptorPostQueueDepth; /* 0x1C */
179 U16 ReplyFreeQueueDepth; /* 0x1E */
180 U32 SenseBufferAddressHigh; /* 0x20 */
181 U32 SystemReplyAddressHigh; /* 0x24 */
182 U64 SystemRequestFrameBaseAddress; /* 0x28 */
183 U64 ReplyDescriptorPostQueueAddress;/* 0x30 */
184 U64 ReplyFreeQueueAddress; /* 0x38 */
185 U64 TimeStamp; /* 0x40 */
186 } MPI2_IOC_INIT_REQUEST, MPI2_POINTER PTR_MPI2_IOC_INIT_REQUEST,
187 Mpi2IOCInitRequest_t, MPI2_POINTER pMpi2IOCInitRequest_t;
190 #define MPI2_WHOINIT_NOT_INITIALIZED (0x00)
191 #define MPI2_WHOINIT_SYSTEM_BIOS (0x01)
192 #define MPI2_WHOINIT_ROM_BIOS (0x02)
193 #define MPI2_WHOINIT_PCI_PEER (0x03)
194 #define MPI2_WHOINIT_HOST_DRIVER (0x04)
195 #define MPI2_WHOINIT_MANUFACTURER (0x05)
198 #define MPI2_IOCINIT_MSGVERSION_MAJOR_MASK (0xFF00)
199 #define MPI2_IOCINIT_MSGVERSION_MAJOR_SHIFT (8)
200 #define MPI2_IOCINIT_MSGVERSION_MINOR_MASK (0x00FF)
201 #define MPI2_IOCINIT_MSGVERSION_MINOR_SHIFT (0)
204 #define MPI2_IOCINIT_HDRVERSION_UNIT_MASK (0xFF00)
205 #define MPI2_IOCINIT_HDRVERSION_UNIT_SHIFT (8)
206 #define MPI2_IOCINIT_HDRVERSION_DEV_MASK (0x00FF)
207 #define MPI2_IOCINIT_HDRVERSION_DEV_SHIFT (0)
209 /* minimum depth for the Reply Descriptor Post Queue */
210 #define MPI2_RDPQ_DEPTH_MIN (16)
213 /* IOCInit Reply message */
214 typedef struct _MPI2_IOC_INIT_REPLY
216 U8 WhoInit; /* 0x00 */
217 U8 Reserved1; /* 0x01 */
218 U8 MsgLength; /* 0x02 */
219 U8 Function; /* 0x03 */
220 U16 Reserved2; /* 0x04 */
221 U8 Reserved3; /* 0x06 */
222 U8 MsgFlags; /* 0x07 */
225 U16 Reserved4; /* 0x0A */
226 U16 Reserved5; /* 0x0C */
227 U16 IOCStatus; /* 0x0E */
228 U32 IOCLogInfo; /* 0x10 */
229 } MPI2_IOC_INIT_REPLY, MPI2_POINTER PTR_MPI2_IOC_INIT_REPLY,
230 Mpi2IOCInitReply_t, MPI2_POINTER pMpi2IOCInitReply_t;
233 /****************************************************************************
235 ****************************************************************************/
237 /* IOCFacts Request message */
238 typedef struct _MPI2_IOC_FACTS_REQUEST
240 U16 Reserved1; /* 0x00 */
241 U8 ChainOffset; /* 0x02 */
242 U8 Function; /* 0x03 */
243 U16 Reserved2; /* 0x04 */
244 U8 Reserved3; /* 0x06 */
245 U8 MsgFlags; /* 0x07 */
248 U16 Reserved4; /* 0x0A */
249 } MPI2_IOC_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_IOC_FACTS_REQUEST,
250 Mpi2IOCFactsRequest_t, MPI2_POINTER pMpi2IOCFactsRequest_t;
253 /* IOCFacts Reply message */
254 typedef struct _MPI2_IOC_FACTS_REPLY
256 U16 MsgVersion; /* 0x00 */
257 U8 MsgLength; /* 0x02 */
258 U8 Function; /* 0x03 */
259 U16 HeaderVersion; /* 0x04 */
260 U8 IOCNumber; /* 0x06 */
261 U8 MsgFlags; /* 0x07 */
264 U16 Reserved1; /* 0x0A */
265 U16 IOCExceptions; /* 0x0C */
266 U16 IOCStatus; /* 0x0E */
267 U32 IOCLogInfo; /* 0x10 */
268 U8 MaxChainDepth; /* 0x14 */
269 U8 WhoInit; /* 0x15 */
270 U8 NumberOfPorts; /* 0x16 */
271 U8 MaxMSIxVectors; /* 0x17 */
272 U16 RequestCredit; /* 0x18 */
273 U16 ProductID; /* 0x1A */
274 U32 IOCCapabilities; /* 0x1C */
275 MPI2_VERSION_UNION FWVersion; /* 0x20 */
276 U16 IOCRequestFrameSize; /* 0x24 */
277 U16 Reserved3; /* 0x26 */
278 U16 MaxInitiators; /* 0x28 */
279 U16 MaxTargets; /* 0x2A */
280 U16 MaxSasExpanders; /* 0x2C */
281 U16 MaxEnclosures; /* 0x2E */
282 U16 ProtocolFlags; /* 0x30 */
283 U16 HighPriorityCredit; /* 0x32 */
284 U16 MaxReplyDescriptorPostQueueDepth; /* 0x34 */
285 U8 ReplyFrameSize; /* 0x36 */
286 U8 MaxVolumes; /* 0x37 */
287 U16 MaxDevHandle; /* 0x38 */
288 U16 MaxPersistentEntries; /* 0x3A */
289 U16 MinDevHandle; /* 0x3C */
290 U16 Reserved4; /* 0x3E */
291 } MPI2_IOC_FACTS_REPLY, MPI2_POINTER PTR_MPI2_IOC_FACTS_REPLY,
292 Mpi2IOCFactsReply_t, MPI2_POINTER pMpi2IOCFactsReply_t;
295 #define MPI2_IOCFACTS_MSGVERSION_MAJOR_MASK (0xFF00)
296 #define MPI2_IOCFACTS_MSGVERSION_MAJOR_SHIFT (8)
297 #define MPI2_IOCFACTS_MSGVERSION_MINOR_MASK (0x00FF)
298 #define MPI2_IOCFACTS_MSGVERSION_MINOR_SHIFT (0)
301 #define MPI2_IOCFACTS_HDRVERSION_UNIT_MASK (0xFF00)
302 #define MPI2_IOCFACTS_HDRVERSION_UNIT_SHIFT (8)
303 #define MPI2_IOCFACTS_HDRVERSION_DEV_MASK (0x00FF)
304 #define MPI2_IOCFACTS_HDRVERSION_DEV_SHIFT (0)
307 #define MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX (0x0100)
309 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_MASK (0x00E0)
310 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_GOOD (0x0000)
311 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_BACKUP (0x0020)
312 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_RESTORED (0x0040)
313 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_CORRUPT_BACKUP (0x0060)
315 #define MPI2_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED (0x0010)
316 #define MPI2_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL (0x0008)
317 #define MPI2_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL (0x0004)
318 #define MPI2_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID (0x0002)
319 #define MPI2_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (0x0001)
321 /* defines for WhoInit field are after the IOCInit Request */
323 /* ProductID field uses MPI2_FW_HEADER_PID_ */
325 /* IOCCapabilities */
326 #define MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY (0x00010000)
327 #define MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX (0x00008000)
328 #define MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR (0x00004000)
329 #define MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY (0x00002000)
330 #define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID (0x00001000)
331 #define MPI2_IOCFACTS_CAPABILITY_TLR (0x00000800)
332 #define MPI2_IOCFACTS_CAPABILITY_MULTICAST (0x00000100)
333 #define MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET (0x00000080)
334 #define MPI2_IOCFACTS_CAPABILITY_EEDP (0x00000040)
335 #define MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER (0x00000020)
336 #define MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER (0x00000010)
337 #define MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER (0x00000008)
338 #define MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING (0x00000004)
341 #define MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET (0x0001)
342 #define MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR (0x0002)
345 /****************************************************************************
347 ****************************************************************************/
349 /* PortFacts Request message */
350 typedef struct _MPI2_PORT_FACTS_REQUEST
352 U16 Reserved1; /* 0x00 */
353 U8 ChainOffset; /* 0x02 */
354 U8 Function; /* 0x03 */
355 U16 Reserved2; /* 0x04 */
356 U8 PortNumber; /* 0x06 */
357 U8 MsgFlags; /* 0x07 */
360 U16 Reserved3; /* 0x0A */
361 } MPI2_PORT_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_PORT_FACTS_REQUEST,
362 Mpi2PortFactsRequest_t, MPI2_POINTER pMpi2PortFactsRequest_t;
364 /* PortFacts Reply message */
365 typedef struct _MPI2_PORT_FACTS_REPLY
367 U16 Reserved1; /* 0x00 */
368 U8 MsgLength; /* 0x02 */
369 U8 Function; /* 0x03 */
370 U16 Reserved2; /* 0x04 */
371 U8 PortNumber; /* 0x06 */
372 U8 MsgFlags; /* 0x07 */
375 U16 Reserved3; /* 0x0A */
376 U16 Reserved4; /* 0x0C */
377 U16 IOCStatus; /* 0x0E */
378 U32 IOCLogInfo; /* 0x10 */
379 U8 Reserved5; /* 0x14 */
380 U8 PortType; /* 0x15 */
381 U16 Reserved6; /* 0x16 */
382 U16 MaxPostedCmdBuffers; /* 0x18 */
383 U16 Reserved7; /* 0x1A */
384 } MPI2_PORT_FACTS_REPLY, MPI2_POINTER PTR_MPI2_PORT_FACTS_REPLY,
385 Mpi2PortFactsReply_t, MPI2_POINTER pMpi2PortFactsReply_t;
387 /* PortType values */
388 #define MPI2_PORTFACTS_PORTTYPE_INACTIVE (0x00)
389 #define MPI2_PORTFACTS_PORTTYPE_FC (0x10)
390 #define MPI2_PORTFACTS_PORTTYPE_ISCSI (0x20)
391 #define MPI2_PORTFACTS_PORTTYPE_SAS_PHYSICAL (0x30)
392 #define MPI2_PORTFACTS_PORTTYPE_SAS_VIRTUAL (0x31)
395 /****************************************************************************
397 ****************************************************************************/
399 /* PortEnable Request message */
400 typedef struct _MPI2_PORT_ENABLE_REQUEST
402 U16 Reserved1; /* 0x00 */
403 U8 ChainOffset; /* 0x02 */
404 U8 Function; /* 0x03 */
405 U8 Reserved2; /* 0x04 */
406 U8 PortFlags; /* 0x05 */
407 U8 Reserved3; /* 0x06 */
408 U8 MsgFlags; /* 0x07 */
411 U16 Reserved4; /* 0x0A */
412 } MPI2_PORT_ENABLE_REQUEST, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REQUEST,
413 Mpi2PortEnableRequest_t, MPI2_POINTER pMpi2PortEnableRequest_t;
416 /* PortEnable Reply message */
417 typedef struct _MPI2_PORT_ENABLE_REPLY
419 U16 Reserved1; /* 0x00 */
420 U8 MsgLength; /* 0x02 */
421 U8 Function; /* 0x03 */
422 U8 Reserved2; /* 0x04 */
423 U8 PortFlags; /* 0x05 */
424 U8 Reserved3; /* 0x06 */
425 U8 MsgFlags; /* 0x07 */
428 U16 Reserved4; /* 0x0A */
429 U16 Reserved5; /* 0x0C */
430 U16 IOCStatus; /* 0x0E */
431 U32 IOCLogInfo; /* 0x10 */
432 } MPI2_PORT_ENABLE_REPLY, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REPLY,
433 Mpi2PortEnableReply_t, MPI2_POINTER pMpi2PortEnableReply_t;
436 /****************************************************************************
437 * EventNotification message
438 ****************************************************************************/
440 /* EventNotification Request message */
441 #define MPI2_EVENT_NOTIFY_EVENTMASK_WORDS (4)
443 typedef struct _MPI2_EVENT_NOTIFICATION_REQUEST
445 U16 Reserved1; /* 0x00 */
446 U8 ChainOffset; /* 0x02 */
447 U8 Function; /* 0x03 */
448 U16 Reserved2; /* 0x04 */
449 U8 Reserved3; /* 0x06 */
450 U8 MsgFlags; /* 0x07 */
453 U16 Reserved4; /* 0x0A */
454 U32 Reserved5; /* 0x0C */
455 U32 Reserved6; /* 0x10 */
456 U32 EventMasks[MPI2_EVENT_NOTIFY_EVENTMASK_WORDS];/* 0x14 */
457 U16 SASBroadcastPrimitiveMasks; /* 0x24 */
458 U16 Reserved7; /* 0x26 */
459 U32 Reserved8; /* 0x28 */
460 } MPI2_EVENT_NOTIFICATION_REQUEST,
461 MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REQUEST,
462 Mpi2EventNotificationRequest_t, MPI2_POINTER pMpi2EventNotificationRequest_t;
465 /* EventNotification Reply message */
466 typedef struct _MPI2_EVENT_NOTIFICATION_REPLY
468 U16 EventDataLength; /* 0x00 */
469 U8 MsgLength; /* 0x02 */
470 U8 Function; /* 0x03 */
471 U16 Reserved1; /* 0x04 */
472 U8 AckRequired; /* 0x06 */
473 U8 MsgFlags; /* 0x07 */
476 U16 Reserved2; /* 0x0A */
477 U16 Reserved3; /* 0x0C */
478 U16 IOCStatus; /* 0x0E */
479 U32 IOCLogInfo; /* 0x10 */
480 U16 Event; /* 0x14 */
481 U16 Reserved4; /* 0x16 */
482 U32 EventContext; /* 0x18 */
483 U32 EventData[1]; /* 0x1C */
484 } MPI2_EVENT_NOTIFICATION_REPLY, MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REPLY,
485 Mpi2EventNotificationReply_t, MPI2_POINTER pMpi2EventNotificationReply_t;
488 #define MPI2_EVENT_NOTIFICATION_ACK_NOT_REQUIRED (0x00)
489 #define MPI2_EVENT_NOTIFICATION_ACK_REQUIRED (0x01)
492 #define MPI2_EVENT_LOG_DATA (0x0001)
493 #define MPI2_EVENT_STATE_CHANGE (0x0002)
494 #define MPI2_EVENT_HARD_RESET_RECEIVED (0x0005)
495 #define MPI2_EVENT_EVENT_CHANGE (0x000A)
496 #define MPI2_EVENT_TASK_SET_FULL (0x000E) /* obsolete */
497 #define MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE (0x000F)
498 #define MPI2_EVENT_IR_OPERATION_STATUS (0x0014)
499 #define MPI2_EVENT_SAS_DISCOVERY (0x0016)
500 #define MPI2_EVENT_SAS_BROADCAST_PRIMITIVE (0x0017)
501 #define MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE (0x0018)
502 #define MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW (0x0019)
503 #define MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST (0x001C)
504 #define MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE (0x001D)
505 #define MPI2_EVENT_IR_VOLUME (0x001E)
506 #define MPI2_EVENT_IR_PHYSICAL_DISK (0x001F)
507 #define MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST (0x0020)
508 #define MPI2_EVENT_LOG_ENTRY_ADDED (0x0021)
509 #define MPI2_EVENT_SAS_PHY_COUNTER (0x0022)
510 #define MPI2_EVENT_GPIO_INTERRUPT (0x0023)
511 #define MPI2_EVENT_HOST_BASED_DISCOVERY_PHY (0x0024)
512 #define MPI2_EVENT_SAS_QUIESCE (0x0025)
515 /* Log Entry Added Event data */
517 /* the following structure matches MPI2_LOG_0_ENTRY in mpi2_cnfg.h */
518 #define MPI2_EVENT_DATA_LOG_DATA_LENGTH (0x1C)
520 typedef struct _MPI2_EVENT_DATA_LOG_ENTRY_ADDED
522 U64 TimeStamp; /* 0x00 */
523 U32 Reserved1; /* 0x08 */
524 U16 LogSequence; /* 0x0C */
525 U16 LogEntryQualifier; /* 0x0E */
528 U16 Reserved2; /* 0x12 */
529 U8 LogData[MPI2_EVENT_DATA_LOG_DATA_LENGTH];/* 0x14 */
530 } MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
531 MPI2_POINTER PTR_MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
532 Mpi2EventDataLogEntryAdded_t, MPI2_POINTER pMpi2EventDataLogEntryAdded_t;
534 /* GPIO Interrupt Event data */
536 typedef struct _MPI2_EVENT_DATA_GPIO_INTERRUPT
538 U8 GPIONum; /* 0x00 */
539 U8 Reserved1; /* 0x01 */
540 U16 Reserved2; /* 0x02 */
541 } MPI2_EVENT_DATA_GPIO_INTERRUPT,
542 MPI2_POINTER PTR_MPI2_EVENT_DATA_GPIO_INTERRUPT,
543 Mpi2EventDataGpioInterrupt_t, MPI2_POINTER pMpi2EventDataGpioInterrupt_t;
545 /* Hard Reset Received Event data */
547 typedef struct _MPI2_EVENT_DATA_HARD_RESET_RECEIVED
549 U8 Reserved1; /* 0x00 */
551 U16 Reserved2; /* 0x02 */
552 } MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
553 MPI2_POINTER PTR_MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
554 Mpi2EventDataHardResetReceived_t,
555 MPI2_POINTER pMpi2EventDataHardResetReceived_t;
557 /* Task Set Full Event data */
558 /* this event is obsolete */
560 typedef struct _MPI2_EVENT_DATA_TASK_SET_FULL
562 U16 DevHandle; /* 0x00 */
563 U16 CurrentDepth; /* 0x02 */
564 } MPI2_EVENT_DATA_TASK_SET_FULL, MPI2_POINTER PTR_MPI2_EVENT_DATA_TASK_SET_FULL,
565 Mpi2EventDataTaskSetFull_t, MPI2_POINTER pMpi2EventDataTaskSetFull_t;
568 /* SAS Device Status Change Event data */
570 typedef struct _MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE
572 U16 TaskTag; /* 0x00 */
573 U8 ReasonCode; /* 0x02 */
574 U8 Reserved1; /* 0x03 */
577 U16 DevHandle; /* 0x06 */
578 U32 Reserved2; /* 0x08 */
579 U64 SASAddress; /* 0x0C */
580 U8 LUN[8]; /* 0x14 */
581 } MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
582 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
583 Mpi2EventDataSasDeviceStatusChange_t,
584 MPI2_POINTER pMpi2EventDataSasDeviceStatusChange_t;
586 /* SAS Device Status Change Event data ReasonCode values */
587 #define MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA (0x05)
588 #define MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED (0x07)
589 #define MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET (0x08)
590 #define MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL (0x09)
591 #define MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL (0x0A)
592 #define MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL (0x0B)
593 #define MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL (0x0C)
594 #define MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION (0x0D)
595 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET (0x0E)
596 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL (0x0F)
597 #define MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE (0x10)
598 #define MPI2_EVENT_SAS_DEV_STAT_RC_EXPANDER_REDUCED_FUNCTIONALITY (0x11)
599 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_EXPANDER_REDUCED_FUNCTIONALITY (0x12)
602 /* Integrated RAID Operation Status Event data */
604 typedef struct _MPI2_EVENT_DATA_IR_OPERATION_STATUS
606 U16 VolDevHandle; /* 0x00 */
607 U16 Reserved1; /* 0x02 */
608 U8 RAIDOperation; /* 0x04 */
609 U8 PercentComplete; /* 0x05 */
610 U16 Reserved2; /* 0x06 */
611 U32 Resereved3; /* 0x08 */
612 } MPI2_EVENT_DATA_IR_OPERATION_STATUS,
613 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_OPERATION_STATUS,
614 Mpi2EventDataIrOperationStatus_t,
615 MPI2_POINTER pMpi2EventDataIrOperationStatus_t;
617 /* Integrated RAID Operation Status Event data RAIDOperation values */
618 #define MPI2_EVENT_IR_RAIDOP_RESYNC (0x00)
619 #define MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION (0x01)
620 #define MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK (0x02)
621 #define MPI2_EVENT_IR_RAIDOP_BACKGROUND_INIT (0x03)
622 #define MPI2_EVENT_IR_RAIDOP_MAKE_DATA_CONSISTENT (0x04)
625 /* Integrated RAID Volume Event data */
627 typedef struct _MPI2_EVENT_DATA_IR_VOLUME
629 U16 VolDevHandle; /* 0x00 */
630 U8 ReasonCode; /* 0x02 */
631 U8 Reserved1; /* 0x03 */
632 U32 NewValue; /* 0x04 */
633 U32 PreviousValue; /* 0x08 */
634 } MPI2_EVENT_DATA_IR_VOLUME, MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_VOLUME,
635 Mpi2EventDataIrVolume_t, MPI2_POINTER pMpi2EventDataIrVolume_t;
637 /* Integrated RAID Volume Event data ReasonCode values */
638 #define MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED (0x01)
639 #define MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED (0x02)
640 #define MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED (0x03)
643 /* Integrated RAID Physical Disk Event data */
645 typedef struct _MPI2_EVENT_DATA_IR_PHYSICAL_DISK
647 U16 Reserved1; /* 0x00 */
648 U8 ReasonCode; /* 0x02 */
649 U8 PhysDiskNum; /* 0x03 */
650 U16 PhysDiskDevHandle; /* 0x04 */
651 U16 Reserved2; /* 0x06 */
653 U16 EnclosureHandle; /* 0x0A */
654 U32 NewValue; /* 0x0C */
655 U32 PreviousValue; /* 0x10 */
656 } MPI2_EVENT_DATA_IR_PHYSICAL_DISK,
657 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_PHYSICAL_DISK,
658 Mpi2EventDataIrPhysicalDisk_t, MPI2_POINTER pMpi2EventDataIrPhysicalDisk_t;
660 /* Integrated RAID Physical Disk Event data ReasonCode values */
661 #define MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED (0x01)
662 #define MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED (0x02)
663 #define MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED (0x03)
666 /* Integrated RAID Configuration Change List Event data */
669 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
670 * one and check NumElements at runtime.
672 #ifndef MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT
673 #define MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT (1)
676 typedef struct _MPI2_EVENT_IR_CONFIG_ELEMENT
678 U16 ElementFlags; /* 0x00 */
679 U16 VolDevHandle; /* 0x02 */
680 U8 ReasonCode; /* 0x04 */
681 U8 PhysDiskNum; /* 0x05 */
682 U16 PhysDiskDevHandle; /* 0x06 */
683 } MPI2_EVENT_IR_CONFIG_ELEMENT, MPI2_POINTER PTR_MPI2_EVENT_IR_CONFIG_ELEMENT,
684 Mpi2EventIrConfigElement_t, MPI2_POINTER pMpi2EventIrConfigElement_t;
686 /* IR Configuration Change List Event data ElementFlags values */
687 #define MPI2_EVENT_IR_CHANGE_EFLAGS_ELEMENT_TYPE_MASK (0x000F)
688 #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLUME_ELEMENT (0x0000)
689 #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLPHYSDISK_ELEMENT (0x0001)
690 #define MPI2_EVENT_IR_CHANGE_EFLAGS_HOTSPARE_ELEMENT (0x0002)
692 /* IR Configuration Change List Event data ReasonCode values */
693 #define MPI2_EVENT_IR_CHANGE_RC_ADDED (0x01)
694 #define MPI2_EVENT_IR_CHANGE_RC_REMOVED (0x02)
695 #define MPI2_EVENT_IR_CHANGE_RC_NO_CHANGE (0x03)
696 #define MPI2_EVENT_IR_CHANGE_RC_HIDE (0x04)
697 #define MPI2_EVENT_IR_CHANGE_RC_UNHIDE (0x05)
698 #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED (0x06)
699 #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED (0x07)
700 #define MPI2_EVENT_IR_CHANGE_RC_PD_CREATED (0x08)
701 #define MPI2_EVENT_IR_CHANGE_RC_PD_DELETED (0x09)
703 typedef struct _MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST
705 U8 NumElements; /* 0x00 */
706 U8 Reserved1; /* 0x01 */
707 U8 Reserved2; /* 0x02 */
708 U8 ConfigNum; /* 0x03 */
709 U32 Flags; /* 0x04 */
710 MPI2_EVENT_IR_CONFIG_ELEMENT ConfigElement[MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT]; /* 0x08 */
711 } MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,
712 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,
713 Mpi2EventDataIrConfigChangeList_t,
714 MPI2_POINTER pMpi2EventDataIrConfigChangeList_t;
716 /* IR Configuration Change List Event data Flags values */
717 #define MPI2_EVENT_IR_CHANGE_FLAGS_FOREIGN_CONFIG (0x00000001)
720 /* SAS Discovery Event data */
722 typedef struct _MPI2_EVENT_DATA_SAS_DISCOVERY
725 U8 ReasonCode; /* 0x01 */
726 U8 PhysicalPort; /* 0x02 */
727 U8 Reserved1; /* 0x03 */
728 U32 DiscoveryStatus; /* 0x04 */
729 } MPI2_EVENT_DATA_SAS_DISCOVERY,
730 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DISCOVERY,
731 Mpi2EventDataSasDiscovery_t, MPI2_POINTER pMpi2EventDataSasDiscovery_t;
733 /* SAS Discovery Event data Flags values */
734 #define MPI2_EVENT_SAS_DISC_DEVICE_CHANGE (0x02)
735 #define MPI2_EVENT_SAS_DISC_IN_PROGRESS (0x01)
737 /* SAS Discovery Event data ReasonCode values */
738 #define MPI2_EVENT_SAS_DISC_RC_STARTED (0x01)
739 #define MPI2_EVENT_SAS_DISC_RC_COMPLETED (0x02)
741 /* SAS Discovery Event data DiscoveryStatus values */
742 #define MPI2_EVENT_SAS_DISC_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
743 #define MPI2_EVENT_SAS_DISC_DS_MAX_EXPANDERS_EXCEED (0x40000000)
744 #define MPI2_EVENT_SAS_DISC_DS_MAX_DEVICES_EXCEED (0x20000000)
745 #define MPI2_EVENT_SAS_DISC_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
746 #define MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR (0x08000000)
747 #define MPI2_EVENT_SAS_DISC_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
748 #define MPI2_EVENT_SAS_DISC_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
749 #define MPI2_EVENT_SAS_DISC_DS_MULTI_PORT_DOMAIN (0x00002000)
750 #define MPI2_EVENT_SAS_DISC_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
751 #define MPI2_EVENT_SAS_DISC_DS_UNSUPPORTED_DEVICE (0x00000800)
752 #define MPI2_EVENT_SAS_DISC_DS_TABLE_LINK (0x00000400)
753 #define MPI2_EVENT_SAS_DISC_DS_SUBTRACTIVE_LINK (0x00000200)
754 #define MPI2_EVENT_SAS_DISC_DS_SMP_CRC_ERROR (0x00000100)
755 #define MPI2_EVENT_SAS_DISC_DS_SMP_FUNCTION_FAILED (0x00000080)
756 #define MPI2_EVENT_SAS_DISC_DS_INDEX_NOT_EXIST (0x00000040)
757 #define MPI2_EVENT_SAS_DISC_DS_OUT_ROUTE_ENTRIES (0x00000020)
758 #define MPI2_EVENT_SAS_DISC_DS_SMP_TIMEOUT (0x00000010)
759 #define MPI2_EVENT_SAS_DISC_DS_MULTIPLE_PORTS (0x00000004)
760 #define MPI2_EVENT_SAS_DISC_DS_UNADDRESSABLE_DEVICE (0x00000002)
761 #define MPI2_EVENT_SAS_DISC_DS_LOOP_DETECTED (0x00000001)
764 /* SAS Broadcast Primitive Event data */
766 typedef struct _MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE
768 U8 PhyNum; /* 0x00 */
770 U8 PortWidth; /* 0x02 */
771 U8 Primitive; /* 0x03 */
772 } MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
773 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
774 Mpi2EventDataSasBroadcastPrimitive_t,
775 MPI2_POINTER pMpi2EventDataSasBroadcastPrimitive_t;
777 /* defines for the Primitive field */
778 #define MPI2_EVENT_PRIMITIVE_CHANGE (0x01)
779 #define MPI2_EVENT_PRIMITIVE_SES (0x02)
780 #define MPI2_EVENT_PRIMITIVE_EXPANDER (0x03)
781 #define MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT (0x04)
782 #define MPI2_EVENT_PRIMITIVE_RESERVED3 (0x05)
783 #define MPI2_EVENT_PRIMITIVE_RESERVED4 (0x06)
784 #define MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED (0x07)
785 #define MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED (0x08)
788 /* SAS Initiator Device Status Change Event data */
790 typedef struct _MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE
792 U8 ReasonCode; /* 0x00 */
793 U8 PhysicalPort; /* 0x01 */
794 U16 DevHandle; /* 0x02 */
795 U64 SASAddress; /* 0x04 */
796 } MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
797 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
798 Mpi2EventDataSasInitDevStatusChange_t,
799 MPI2_POINTER pMpi2EventDataSasInitDevStatusChange_t;
801 /* SAS Initiator Device Status Change event ReasonCode values */
802 #define MPI2_EVENT_SAS_INIT_RC_ADDED (0x01)
803 #define MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING (0x02)
806 /* SAS Initiator Device Table Overflow Event data */
808 typedef struct _MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW
810 U16 MaxInit; /* 0x00 */
811 U16 CurrentInit; /* 0x02 */
812 U64 SASAddress; /* 0x04 */
813 } MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
814 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
815 Mpi2EventDataSasInitTableOverflow_t,
816 MPI2_POINTER pMpi2EventDataSasInitTableOverflow_t;
819 /* SAS Topology Change List Event data */
822 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
823 * one and check NumEntries at runtime.
825 #ifndef MPI2_EVENT_SAS_TOPO_PHY_COUNT
826 #define MPI2_EVENT_SAS_TOPO_PHY_COUNT (1)
829 typedef struct _MPI2_EVENT_SAS_TOPO_PHY_ENTRY
831 U16 AttachedDevHandle; /* 0x00 */
832 U8 LinkRate; /* 0x02 */
833 U8 PhyStatus; /* 0x03 */
834 } MPI2_EVENT_SAS_TOPO_PHY_ENTRY, MPI2_POINTER PTR_MPI2_EVENT_SAS_TOPO_PHY_ENTRY,
835 Mpi2EventSasTopoPhyEntry_t, MPI2_POINTER pMpi2EventSasTopoPhyEntry_t;
837 typedef struct _MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST
839 U16 EnclosureHandle; /* 0x00 */
840 U16 ExpanderDevHandle; /* 0x02 */
841 U8 NumPhys; /* 0x04 */
842 U8 Reserved1; /* 0x05 */
843 U16 Reserved2; /* 0x06 */
844 U8 NumEntries; /* 0x08 */
845 U8 StartPhyNum; /* 0x09 */
846 U8 ExpStatus; /* 0x0A */
847 U8 PhysicalPort; /* 0x0B */
848 MPI2_EVENT_SAS_TOPO_PHY_ENTRY PHY[MPI2_EVENT_SAS_TOPO_PHY_COUNT]; /* 0x0C*/
849 } MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
850 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
851 Mpi2EventDataSasTopologyChangeList_t,
852 MPI2_POINTER pMpi2EventDataSasTopologyChangeList_t;
854 /* values for the ExpStatus field */
855 #define MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER (0x00)
856 #define MPI2_EVENT_SAS_TOPO_ES_ADDED (0x01)
857 #define MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING (0x02)
858 #define MPI2_EVENT_SAS_TOPO_ES_RESPONDING (0x03)
859 #define MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING (0x04)
861 /* defines for the LinkRate field */
862 #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK (0xF0)
863 #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT (4)
864 #define MPI2_EVENT_SAS_TOPO_LR_PREV_MASK (0x0F)
865 #define MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT (0)
867 #define MPI2_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE (0x00)
868 #define MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED (0x01)
869 #define MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED (0x02)
870 #define MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE (0x03)
871 #define MPI2_EVENT_SAS_TOPO_LR_PORT_SELECTOR (0x04)
872 #define MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS (0x05)
873 #define MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY (0x06)
874 #define MPI2_EVENT_SAS_TOPO_LR_RATE_1_5 (0x08)
875 #define MPI2_EVENT_SAS_TOPO_LR_RATE_3_0 (0x09)
876 #define MPI2_EVENT_SAS_TOPO_LR_RATE_6_0 (0x0A)
878 /* values for the PhyStatus field */
879 #define MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT (0x80)
880 #define MPI2_EVENT_SAS_TOPO_PS_MULTIPLEX_CHANGE (0x10)
881 /* values for the PhyStatus ReasonCode sub-field */
882 #define MPI2_EVENT_SAS_TOPO_RC_MASK (0x0F)
883 #define MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED (0x01)
884 #define MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING (0x02)
885 #define MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED (0x03)
886 #define MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE (0x04)
887 #define MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING (0x05)
890 /* SAS Enclosure Device Status Change Event data */
892 typedef struct _MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE
894 U16 EnclosureHandle; /* 0x00 */
895 U8 ReasonCode; /* 0x02 */
896 U8 PhysicalPort; /* 0x03 */
897 U64 EnclosureLogicalID; /* 0x04 */
898 U16 NumSlots; /* 0x0C */
899 U16 StartSlot; /* 0x0E */
900 U32 PhyBits; /* 0x10 */
901 } MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
902 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
903 Mpi2EventDataSasEnclDevStatusChange_t,
904 MPI2_POINTER pMpi2EventDataSasEnclDevStatusChange_t;
906 /* SAS Enclosure Device Status Change event ReasonCode values */
907 #define MPI2_EVENT_SAS_ENCL_RC_ADDED (0x01)
908 #define MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING (0x02)
911 /* SAS PHY Counter Event data */
913 typedef struct _MPI2_EVENT_DATA_SAS_PHY_COUNTER
915 U64 TimeStamp; /* 0x00 */
916 U32 Reserved1; /* 0x08 */
917 U8 PhyEventCode; /* 0x0C */
918 U8 PhyNum; /* 0x0D */
919 U16 Reserved2; /* 0x0E */
920 U32 PhyEventInfo; /* 0x10 */
921 U8 CounterType; /* 0x14 */
922 U8 ThresholdWindow; /* 0x15 */
923 U8 TimeUnits; /* 0x16 */
924 U8 Reserved3; /* 0x17 */
925 U32 EventThreshold; /* 0x18 */
926 U16 ThresholdFlags; /* 0x1C */
927 U16 Reserved4; /* 0x1E */
928 } MPI2_EVENT_DATA_SAS_PHY_COUNTER,
929 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_PHY_COUNTER,
930 Mpi2EventDataSasPhyCounter_t, MPI2_POINTER pMpi2EventDataSasPhyCounter_t;
932 /* use MPI2_SASPHY3_EVENT_CODE_ values from mpi2_cnfg.h for the PhyEventCode field */
934 /* use MPI2_SASPHY3_COUNTER_TYPE_ values from mpi2_cnfg.h for the CounterType field */
936 /* use MPI2_SASPHY3_TIME_UNITS_ values from mpi2_cnfg.h for the TimeUnits field */
938 /* use MPI2_SASPHY3_TFLAGS_ values from mpi2_cnfg.h for the ThresholdFlags field */
941 /* SAS Quiesce Event data */
943 typedef struct _MPI2_EVENT_DATA_SAS_QUIESCE
945 U8 ReasonCode; /* 0x00 */
946 U8 Reserved1; /* 0x01 */
947 U16 Reserved2; /* 0x02 */
948 U32 Reserved3; /* 0x04 */
949 } MPI2_EVENT_DATA_SAS_QUIESCE,
950 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_QUIESCE,
951 Mpi2EventDataSasQuiesce_t, MPI2_POINTER pMpi2EventDataSasQuiesce_t;
953 /* SAS Quiesce Event data ReasonCode values */
954 #define MPI2_EVENT_SAS_QUIESCE_RC_STARTED (0x01)
955 #define MPI2_EVENT_SAS_QUIESCE_RC_COMPLETED (0x02)
958 /* Host Based Discovery Phy Event data */
960 typedef struct _MPI2_EVENT_HBD_PHY_SAS
963 U8 NegotiatedLinkRate; /* 0x01 */
964 U8 PhyNum; /* 0x02 */
965 U8 PhysicalPort; /* 0x03 */
966 U32 Reserved1; /* 0x04 */
967 U8 InitialFrame[28]; /* 0x08 */
968 } MPI2_EVENT_HBD_PHY_SAS, MPI2_POINTER PTR_MPI2_EVENT_HBD_PHY_SAS,
969 Mpi2EventHbdPhySas_t, MPI2_POINTER pMpi2EventHbdPhySas_t;
971 /* values for the Flags field */
972 #define MPI2_EVENT_HBD_SAS_FLAGS_FRAME_VALID (0x02)
973 #define MPI2_EVENT_HBD_SAS_FLAGS_SATA_FRAME (0x01)
975 /* use MPI2_SAS_NEG_LINK_RATE_ defines from mpi2_cnfg.h for the NegotiatedLinkRate field */
977 typedef union _MPI2_EVENT_HBD_DESCRIPTOR
979 MPI2_EVENT_HBD_PHY_SAS Sas;
980 } MPI2_EVENT_HBD_DESCRIPTOR, MPI2_POINTER PTR_MPI2_EVENT_HBD_DESCRIPTOR,
981 Mpi2EventHbdDescriptor_t, MPI2_POINTER pMpi2EventHbdDescriptor_t;
983 typedef struct _MPI2_EVENT_DATA_HBD_PHY
985 U8 DescriptorType; /* 0x00 */
986 U8 Reserved1; /* 0x01 */
987 U16 Reserved2; /* 0x02 */
988 U32 Reserved3; /* 0x04 */
989 MPI2_EVENT_HBD_DESCRIPTOR Descriptor; /* 0x08 */
990 } MPI2_EVENT_DATA_HBD_PHY, MPI2_POINTER PTR_MPI2_EVENT_DATA_HBD_PHY,
991 Mpi2EventDataHbdPhy_t, MPI2_POINTER pMpi2EventDataMpi2EventDataHbdPhy_t;
993 /* values for the DescriptorType field */
994 #define MPI2_EVENT_HBD_DT_SAS (0x01)
998 /****************************************************************************
1000 ****************************************************************************/
1002 /* EventAck Request message */
1003 typedef struct _MPI2_EVENT_ACK_REQUEST
1005 U16 Reserved1; /* 0x00 */
1006 U8 ChainOffset; /* 0x02 */
1007 U8 Function; /* 0x03 */
1008 U16 Reserved2; /* 0x04 */
1009 U8 Reserved3; /* 0x06 */
1010 U8 MsgFlags; /* 0x07 */
1011 U8 VP_ID; /* 0x08 */
1012 U8 VF_ID; /* 0x09 */
1013 U16 Reserved4; /* 0x0A */
1014 U16 Event; /* 0x0C */
1015 U16 Reserved5; /* 0x0E */
1016 U32 EventContext; /* 0x10 */
1017 } MPI2_EVENT_ACK_REQUEST, MPI2_POINTER PTR_MPI2_EVENT_ACK_REQUEST,
1018 Mpi2EventAckRequest_t, MPI2_POINTER pMpi2EventAckRequest_t;
1021 /* EventAck Reply message */
1022 typedef struct _MPI2_EVENT_ACK_REPLY
1024 U16 Reserved1; /* 0x00 */
1025 U8 MsgLength; /* 0x02 */
1026 U8 Function; /* 0x03 */
1027 U16 Reserved2; /* 0x04 */
1028 U8 Reserved3; /* 0x06 */
1029 U8 MsgFlags; /* 0x07 */
1030 U8 VP_ID; /* 0x08 */
1031 U8 VF_ID; /* 0x09 */
1032 U16 Reserved4; /* 0x0A */
1033 U16 Reserved5; /* 0x0C */
1034 U16 IOCStatus; /* 0x0E */
1035 U32 IOCLogInfo; /* 0x10 */
1036 } MPI2_EVENT_ACK_REPLY, MPI2_POINTER PTR_MPI2_EVENT_ACK_REPLY,
1037 Mpi2EventAckReply_t, MPI2_POINTER pMpi2EventAckReply_t;
1040 /****************************************************************************
1041 * FWDownload message
1042 ****************************************************************************/
1044 /* FWDownload Request message */
1045 typedef struct _MPI2_FW_DOWNLOAD_REQUEST
1047 U8 ImageType; /* 0x00 */
1048 U8 Reserved1; /* 0x01 */
1049 U8 ChainOffset; /* 0x02 */
1050 U8 Function; /* 0x03 */
1051 U16 Reserved2; /* 0x04 */
1052 U8 Reserved3; /* 0x06 */
1053 U8 MsgFlags; /* 0x07 */
1054 U8 VP_ID; /* 0x08 */
1055 U8 VF_ID; /* 0x09 */
1056 U16 Reserved4; /* 0x0A */
1057 U32 TotalImageSize; /* 0x0C */
1058 U32 Reserved5; /* 0x10 */
1059 MPI2_MPI_SGE_UNION SGL; /* 0x14 */
1060 } MPI2_FW_DOWNLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REQUEST,
1061 Mpi2FWDownloadRequest, MPI2_POINTER pMpi2FWDownloadRequest;
1063 #define MPI2_FW_DOWNLOAD_MSGFLGS_LAST_SEGMENT (0x01)
1065 #define MPI2_FW_DOWNLOAD_ITYPE_FW (0x01)
1066 #define MPI2_FW_DOWNLOAD_ITYPE_BIOS (0x02)
1067 #define MPI2_FW_DOWNLOAD_ITYPE_MANUFACTURING (0x06)
1068 #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_1 (0x07)
1069 #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_2 (0x08)
1070 #define MPI2_FW_DOWNLOAD_ITYPE_MEGARAID (0x09)
1071 #define MPI2_FW_DOWNLOAD_ITYPE_COMPLETE (0x0A)
1072 #define MPI2_FW_DOWNLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B)
1073 #define MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC (0xF0)
1075 /* FWDownload TransactionContext Element */
1076 typedef struct _MPI2_FW_DOWNLOAD_TCSGE
1078 U8 Reserved1; /* 0x00 */
1079 U8 ContextSize; /* 0x01 */
1080 U8 DetailsLength; /* 0x02 */
1081 U8 Flags; /* 0x03 */
1082 U32 Reserved2; /* 0x04 */
1083 U32 ImageOffset; /* 0x08 */
1084 U32 ImageSize; /* 0x0C */
1085 } MPI2_FW_DOWNLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_TCSGE,
1086 Mpi2FWDownloadTCSGE_t, MPI2_POINTER pMpi2FWDownloadTCSGE_t;
1088 /* FWDownload Reply message */
1089 typedef struct _MPI2_FW_DOWNLOAD_REPLY
1091 U8 ImageType; /* 0x00 */
1092 U8 Reserved1; /* 0x01 */
1093 U8 MsgLength; /* 0x02 */
1094 U8 Function; /* 0x03 */
1095 U16 Reserved2; /* 0x04 */
1096 U8 Reserved3; /* 0x06 */
1097 U8 MsgFlags; /* 0x07 */
1098 U8 VP_ID; /* 0x08 */
1099 U8 VF_ID; /* 0x09 */
1100 U16 Reserved4; /* 0x0A */
1101 U16 Reserved5; /* 0x0C */
1102 U16 IOCStatus; /* 0x0E */
1103 U32 IOCLogInfo; /* 0x10 */
1104 } MPI2_FW_DOWNLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REPLY,
1105 Mpi2FWDownloadReply_t, MPI2_POINTER pMpi2FWDownloadReply_t;
1108 /****************************************************************************
1110 ****************************************************************************/
1112 /* FWUpload Request message */
1113 typedef struct _MPI2_FW_UPLOAD_REQUEST
1115 U8 ImageType; /* 0x00 */
1116 U8 Reserved1; /* 0x01 */
1117 U8 ChainOffset; /* 0x02 */
1118 U8 Function; /* 0x03 */
1119 U16 Reserved2; /* 0x04 */
1120 U8 Reserved3; /* 0x06 */
1121 U8 MsgFlags; /* 0x07 */
1122 U8 VP_ID; /* 0x08 */
1123 U8 VF_ID; /* 0x09 */
1124 U16 Reserved4; /* 0x0A */
1125 U32 Reserved5; /* 0x0C */
1126 U32 Reserved6; /* 0x10 */
1127 MPI2_MPI_SGE_UNION SGL; /* 0x14 */
1128 } MPI2_FW_UPLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REQUEST,
1129 Mpi2FWUploadRequest_t, MPI2_POINTER pMpi2FWUploadRequest_t;
1131 #define MPI2_FW_UPLOAD_ITYPE_FW_CURRENT (0x00)
1132 #define MPI2_FW_UPLOAD_ITYPE_FW_FLASH (0x01)
1133 #define MPI2_FW_UPLOAD_ITYPE_BIOS_FLASH (0x02)
1134 #define MPI2_FW_UPLOAD_ITYPE_FW_BACKUP (0x05)
1135 #define MPI2_FW_UPLOAD_ITYPE_MANUFACTURING (0x06)
1136 #define MPI2_FW_UPLOAD_ITYPE_CONFIG_1 (0x07)
1137 #define MPI2_FW_UPLOAD_ITYPE_CONFIG_2 (0x08)
1138 #define MPI2_FW_UPLOAD_ITYPE_MEGARAID (0x09)
1139 #define MPI2_FW_UPLOAD_ITYPE_COMPLETE (0x0A)
1140 #define MPI2_FW_UPLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B)
1142 typedef struct _MPI2_FW_UPLOAD_TCSGE
1144 U8 Reserved1; /* 0x00 */
1145 U8 ContextSize; /* 0x01 */
1146 U8 DetailsLength; /* 0x02 */
1147 U8 Flags; /* 0x03 */
1148 U32 Reserved2; /* 0x04 */
1149 U32 ImageOffset; /* 0x08 */
1150 U32 ImageSize; /* 0x0C */
1151 } MPI2_FW_UPLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_UPLOAD_TCSGE,
1152 Mpi2FWUploadTCSGE_t, MPI2_POINTER pMpi2FWUploadTCSGE_t;
1154 /* FWUpload Reply message */
1155 typedef struct _MPI2_FW_UPLOAD_REPLY
1157 U8 ImageType; /* 0x00 */
1158 U8 Reserved1; /* 0x01 */
1159 U8 MsgLength; /* 0x02 */
1160 U8 Function; /* 0x03 */
1161 U16 Reserved2; /* 0x04 */
1162 U8 Reserved3; /* 0x06 */
1163 U8 MsgFlags; /* 0x07 */
1164 U8 VP_ID; /* 0x08 */
1165 U8 VF_ID; /* 0x09 */
1166 U16 Reserved4; /* 0x0A */
1167 U16 Reserved5; /* 0x0C */
1168 U16 IOCStatus; /* 0x0E */
1169 U32 IOCLogInfo; /* 0x10 */
1170 U32 ActualImageSize; /* 0x14 */
1171 } MPI2_FW_UPLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REPLY,
1172 Mpi2FWUploadReply_t, MPI2_POINTER pMPi2FWUploadReply_t;
1175 /* FW Image Header */
1176 typedef struct _MPI2_FW_IMAGE_HEADER
1178 U32 Signature; /* 0x00 */
1179 U32 Signature0; /* 0x04 */
1180 U32 Signature1; /* 0x08 */
1181 U32 Signature2; /* 0x0C */
1182 MPI2_VERSION_UNION MPIVersion; /* 0x10 */
1183 MPI2_VERSION_UNION FWVersion; /* 0x14 */
1184 MPI2_VERSION_UNION NVDATAVersion; /* 0x18 */
1185 MPI2_VERSION_UNION PackageVersion; /* 0x1C */
1186 U16 VendorID; /* 0x20 */
1187 U16 ProductID; /* 0x22 */
1188 U16 ProtocolFlags; /* 0x24 */
1189 U16 Reserved26; /* 0x26 */
1190 U32 IOCCapabilities; /* 0x28 */
1191 U32 ImageSize; /* 0x2C */
1192 U32 NextImageHeaderOffset; /* 0x30 */
1193 U32 Checksum; /* 0x34 */
1194 U32 Reserved38; /* 0x38 */
1195 U32 Reserved3C; /* 0x3C */
1196 U32 Reserved40; /* 0x40 */
1197 U32 Reserved44; /* 0x44 */
1198 U32 Reserved48; /* 0x48 */
1199 U32 Reserved4C; /* 0x4C */
1200 U32 Reserved50; /* 0x50 */
1201 U32 Reserved54; /* 0x54 */
1202 U32 Reserved58; /* 0x58 */
1203 U32 Reserved5C; /* 0x5C */
1204 U32 Reserved60; /* 0x60 */
1205 U32 FirmwareVersionNameWhat; /* 0x64 */
1206 U8 FirmwareVersionName[32]; /* 0x68 */
1207 U32 VendorNameWhat; /* 0x88 */
1208 U8 VendorName[32]; /* 0x8C */
1209 U32 PackageNameWhat; /* 0x88 */
1210 U8 PackageName[32]; /* 0x8C */
1211 U32 ReservedD0; /* 0xD0 */
1212 U32 ReservedD4; /* 0xD4 */
1213 U32 ReservedD8; /* 0xD8 */
1214 U32 ReservedDC; /* 0xDC */
1215 U32 ReservedE0; /* 0xE0 */
1216 U32 ReservedE4; /* 0xE4 */
1217 U32 ReservedE8; /* 0xE8 */
1218 U32 ReservedEC; /* 0xEC */
1219 U32 ReservedF0; /* 0xF0 */
1220 U32 ReservedF4; /* 0xF4 */
1221 U32 ReservedF8; /* 0xF8 */
1222 U32 ReservedFC; /* 0xFC */
1223 } MPI2_FW_IMAGE_HEADER, MPI2_POINTER PTR_MPI2_FW_IMAGE_HEADER,
1224 Mpi2FWImageHeader_t, MPI2_POINTER pMpi2FWImageHeader_t;
1226 /* Signature field */
1227 #define MPI2_FW_HEADER_SIGNATURE_OFFSET (0x00)
1228 #define MPI2_FW_HEADER_SIGNATURE_MASK (0xFF000000)
1229 #define MPI2_FW_HEADER_SIGNATURE (0xEA000000)
1231 /* Signature0 field */
1232 #define MPI2_FW_HEADER_SIGNATURE0_OFFSET (0x04)
1233 #define MPI2_FW_HEADER_SIGNATURE0 (0x5AFAA55A)
1235 /* Signature1 field */
1236 #define MPI2_FW_HEADER_SIGNATURE1_OFFSET (0x08)
1237 #define MPI2_FW_HEADER_SIGNATURE1 (0xA55AFAA5)
1239 /* Signature2 field */
1240 #define MPI2_FW_HEADER_SIGNATURE2_OFFSET (0x0C)
1241 #define MPI2_FW_HEADER_SIGNATURE2 (0x5AA55AFA)
1244 /* defines for using the ProductID field */
1245 #define MPI2_FW_HEADER_PID_TYPE_MASK (0xF000)
1246 #define MPI2_FW_HEADER_PID_TYPE_SAS (0x2000)
1248 #define MPI2_FW_HEADER_PID_PROD_MASK (0x0F00)
1249 #define MPI2_FW_HEADER_PID_PROD_A (0x0000)
1250 #define MPI2_FW_HEADER_PID_PROD_TARGET_INITIATOR_SCSI (0x0200)
1251 #define MPI2_FW_HEADER_PID_PROD_IR_SCSI (0x0700)
1254 #define MPI2_FW_HEADER_PID_FAMILY_MASK (0x00FF)
1256 #define MPI2_FW_HEADER_PID_FAMILY_2108_SAS (0x0013)
1257 #define MPI2_FW_HEADER_PID_FAMILY_2208_SAS (0x0014)
1259 /* use MPI2_IOCFACTS_PROTOCOL_ defines for ProtocolFlags field */
1261 /* use MPI2_IOCFACTS_CAPABILITY_ defines for IOCCapabilities field */
1264 #define MPI2_FW_HEADER_IMAGESIZE_OFFSET (0x2C)
1265 #define MPI2_FW_HEADER_NEXTIMAGE_OFFSET (0x30)
1266 #define MPI2_FW_HEADER_VERNMHWAT_OFFSET (0x64)
1268 #define MPI2_FW_HEADER_WHAT_SIGNATURE (0x29232840)
1270 #define MPI2_FW_HEADER_SIZE (0x100)
1273 /* Extended Image Header */
1274 typedef struct _MPI2_EXT_IMAGE_HEADER
1277 U8 ImageType; /* 0x00 */
1278 U8 Reserved1; /* 0x01 */
1279 U16 Reserved2; /* 0x02 */
1280 U32 Checksum; /* 0x04 */
1281 U32 ImageSize; /* 0x08 */
1282 U32 NextImageHeaderOffset; /* 0x0C */
1283 U32 PackageVersion; /* 0x10 */
1284 U32 Reserved3; /* 0x14 */
1285 U32 Reserved4; /* 0x18 */
1286 U32 Reserved5; /* 0x1C */
1287 U8 IdentifyString[32]; /* 0x20 */
1288 } MPI2_EXT_IMAGE_HEADER, MPI2_POINTER PTR_MPI2_EXT_IMAGE_HEADER,
1289 Mpi2ExtImageHeader_t, MPI2_POINTER pMpi2ExtImageHeader_t;
1291 /* useful offsets */
1292 #define MPI2_EXT_IMAGE_IMAGETYPE_OFFSET (0x00)
1293 #define MPI2_EXT_IMAGE_IMAGESIZE_OFFSET (0x08)
1294 #define MPI2_EXT_IMAGE_NEXTIMAGE_OFFSET (0x0C)
1296 #define MPI2_EXT_IMAGE_HEADER_SIZE (0x40)
1298 /* defines for the ImageType field */
1299 #define MPI2_EXT_IMAGE_TYPE_UNSPECIFIED (0x00)
1300 #define MPI2_EXT_IMAGE_TYPE_FW (0x01)
1301 #define MPI2_EXT_IMAGE_TYPE_NVDATA (0x03)
1302 #define MPI2_EXT_IMAGE_TYPE_BOOTLOADER (0x04)
1303 #define MPI2_EXT_IMAGE_TYPE_INITIALIZATION (0x05)
1304 #define MPI2_EXT_IMAGE_TYPE_FLASH_LAYOUT (0x06)
1305 #define MPI2_EXT_IMAGE_TYPE_SUPPORTED_DEVICES (0x07)
1306 #define MPI2_EXT_IMAGE_TYPE_MEGARAID (0x08)
1308 #define MPI2_EXT_IMAGE_TYPE_MAX (MPI2_EXT_IMAGE_TYPE_MEGARAID)
1312 /* FLASH Layout Extended Image Data */
1315 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1316 * one and check RegionsPerLayout at runtime.
1318 #ifndef MPI2_FLASH_NUMBER_OF_REGIONS
1319 #define MPI2_FLASH_NUMBER_OF_REGIONS (1)
1323 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1324 * one and check NumberOfLayouts at runtime.
1326 #ifndef MPI2_FLASH_NUMBER_OF_LAYOUTS
1327 #define MPI2_FLASH_NUMBER_OF_LAYOUTS (1)
1330 typedef struct _MPI2_FLASH_REGION
1332 U8 RegionType; /* 0x00 */
1333 U8 Reserved1; /* 0x01 */
1334 U16 Reserved2; /* 0x02 */
1335 U32 RegionOffset; /* 0x04 */
1336 U32 RegionSize; /* 0x08 */
1337 U32 Reserved3; /* 0x0C */
1338 } MPI2_FLASH_REGION, MPI2_POINTER PTR_MPI2_FLASH_REGION,
1339 Mpi2FlashRegion_t, MPI2_POINTER pMpi2FlashRegion_t;
1341 typedef struct _MPI2_FLASH_LAYOUT
1343 U32 FlashSize; /* 0x00 */
1344 U32 Reserved1; /* 0x04 */
1345 U32 Reserved2; /* 0x08 */
1346 U32 Reserved3; /* 0x0C */
1347 MPI2_FLASH_REGION Region[MPI2_FLASH_NUMBER_OF_REGIONS];/* 0x10 */
1348 } MPI2_FLASH_LAYOUT, MPI2_POINTER PTR_MPI2_FLASH_LAYOUT,
1349 Mpi2FlashLayout_t, MPI2_POINTER pMpi2FlashLayout_t;
1351 typedef struct _MPI2_FLASH_LAYOUT_DATA
1353 U8 ImageRevision; /* 0x00 */
1354 U8 Reserved1; /* 0x01 */
1355 U8 SizeOfRegion; /* 0x02 */
1356 U8 Reserved2; /* 0x03 */
1357 U16 NumberOfLayouts; /* 0x04 */
1358 U16 RegionsPerLayout; /* 0x06 */
1359 U16 MinimumSectorAlignment; /* 0x08 */
1360 U16 Reserved3; /* 0x0A */
1361 U32 Reserved4; /* 0x0C */
1362 MPI2_FLASH_LAYOUT Layout[MPI2_FLASH_NUMBER_OF_LAYOUTS];/* 0x10 */
1363 } MPI2_FLASH_LAYOUT_DATA, MPI2_POINTER PTR_MPI2_FLASH_LAYOUT_DATA,
1364 Mpi2FlashLayoutData_t, MPI2_POINTER pMpi2FlashLayoutData_t;
1366 /* defines for the RegionType field */
1367 #define MPI2_FLASH_REGION_UNUSED (0x00)
1368 #define MPI2_FLASH_REGION_FIRMWARE (0x01)
1369 #define MPI2_FLASH_REGION_BIOS (0x02)
1370 #define MPI2_FLASH_REGION_NVDATA (0x03)
1371 #define MPI2_FLASH_REGION_FIRMWARE_BACKUP (0x05)
1372 #define MPI2_FLASH_REGION_MFG_INFORMATION (0x06)
1373 #define MPI2_FLASH_REGION_CONFIG_1 (0x07)
1374 #define MPI2_FLASH_REGION_CONFIG_2 (0x08)
1375 #define MPI2_FLASH_REGION_MEGARAID (0x09)
1376 #define MPI2_FLASH_REGION_INIT (0x0A)
1379 #define MPI2_FLASH_LAYOUT_IMAGE_REVISION (0x00)
1383 /* Supported Devices Extended Image Data */
1386 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1387 * one and check NumberOfDevices at runtime.
1389 #ifndef MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES
1390 #define MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES (1)
1393 typedef struct _MPI2_SUPPORTED_DEVICE
1395 U16 DeviceID; /* 0x00 */
1396 U16 VendorID; /* 0x02 */
1397 U16 DeviceIDMask; /* 0x04 */
1398 U16 Reserved1; /* 0x06 */
1399 U8 LowPCIRev; /* 0x08 */
1400 U8 HighPCIRev; /* 0x09 */
1401 U16 Reserved2; /* 0x0A */
1402 U32 Reserved3; /* 0x0C */
1403 } MPI2_SUPPORTED_DEVICE, MPI2_POINTER PTR_MPI2_SUPPORTED_DEVICE,
1404 Mpi2SupportedDevice_t, MPI2_POINTER pMpi2SupportedDevice_t;
1406 typedef struct _MPI2_SUPPORTED_DEVICES_DATA
1408 U8 ImageRevision; /* 0x00 */
1409 U8 Reserved1; /* 0x01 */
1410 U8 NumberOfDevices; /* 0x02 */
1411 U8 Reserved2; /* 0x03 */
1412 U32 Reserved3; /* 0x04 */
1413 MPI2_SUPPORTED_DEVICE SupportedDevice[MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES]; /* 0x08 */
1414 } MPI2_SUPPORTED_DEVICES_DATA, MPI2_POINTER PTR_MPI2_SUPPORTED_DEVICES_DATA,
1415 Mpi2SupportedDevicesData_t, MPI2_POINTER pMpi2SupportedDevicesData_t;
1418 #define MPI2_SUPPORTED_DEVICES_IMAGE_REVISION (0x00)
1421 /* Init Extended Image Data */
1423 typedef struct _MPI2_INIT_IMAGE_FOOTER
1426 U32 BootFlags; /* 0x00 */
1427 U32 ImageSize; /* 0x04 */
1428 U32 Signature0; /* 0x08 */
1429 U32 Signature1; /* 0x0C */
1430 U32 Signature2; /* 0x10 */
1431 U32 ResetVector; /* 0x14 */
1432 } MPI2_INIT_IMAGE_FOOTER, MPI2_POINTER PTR_MPI2_INIT_IMAGE_FOOTER,
1433 Mpi2InitImageFooter_t, MPI2_POINTER pMpi2InitImageFooter_t;
1435 /* defines for the BootFlags field */
1436 #define MPI2_INIT_IMAGE_BOOTFLAGS_OFFSET (0x00)
1438 /* defines for the ImageSize field */
1439 #define MPI2_INIT_IMAGE_IMAGESIZE_OFFSET (0x04)
1441 /* defines for the Signature0 field */
1442 #define MPI2_INIT_IMAGE_SIGNATURE0_OFFSET (0x08)
1443 #define MPI2_INIT_IMAGE_SIGNATURE0 (0x5AA55AEA)
1445 /* defines for the Signature1 field */
1446 #define MPI2_INIT_IMAGE_SIGNATURE1_OFFSET (0x0C)
1447 #define MPI2_INIT_IMAGE_SIGNATURE1 (0xA55AEAA5)
1449 /* defines for the Signature2 field */
1450 #define MPI2_INIT_IMAGE_SIGNATURE2_OFFSET (0x10)
1451 #define MPI2_INIT_IMAGE_SIGNATURE2 (0x5AEAA55A)
1453 /* Signature fields as individual bytes */
1454 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_0 (0xEA)
1455 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_1 (0x5A)
1456 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_2 (0xA5)
1457 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_3 (0x5A)
1459 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_4 (0xA5)
1460 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_5 (0xEA)
1461 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_6 (0x5A)
1462 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_7 (0xA5)
1464 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_8 (0x5A)
1465 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_9 (0xA5)
1466 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_A (0xEA)
1467 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_B (0x5A)
1469 /* defines for the ResetVector field */
1470 #define MPI2_INIT_IMAGE_RESETVECTOR_OFFSET (0x14)
1473 /****************************************************************************
1474 * PowerManagementControl message
1475 ****************************************************************************/
1477 /* PowerManagementControl Request message */
1478 typedef struct _MPI2_PWR_MGMT_CONTROL_REQUEST
1480 U8 Feature; /* 0x00 */
1481 U8 Reserved1; /* 0x01 */
1482 U8 ChainOffset; /* 0x02 */
1483 U8 Function; /* 0x03 */
1484 U16 Reserved2; /* 0x04 */
1485 U8 Reserved3; /* 0x06 */
1486 U8 MsgFlags; /* 0x07 */
1487 U8 VP_ID; /* 0x08 */
1488 U8 VF_ID; /* 0x09 */
1489 U16 Reserved4; /* 0x0A */
1490 U8 Parameter1; /* 0x0C */
1491 U8 Parameter2; /* 0x0D */
1492 U8 Parameter3; /* 0x0E */
1493 U8 Parameter4; /* 0x0F */
1494 U32 Reserved5; /* 0x10 */
1495 U32 Reserved6; /* 0x14 */
1496 } MPI2_PWR_MGMT_CONTROL_REQUEST, MPI2_POINTER PTR_MPI2_PWR_MGMT_CONTROL_REQUEST,
1497 Mpi2PwrMgmtControlRequest_t, MPI2_POINTER pMpi2PwrMgmtControlRequest_t;
1499 /* defines for the Feature field */
1500 #define MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND (0x01)
1501 #define MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION (0x02)
1502 #define MPI2_PM_CONTROL_FEATURE_PCIE_LINK (0x03)
1503 #define MPI2_PM_CONTROL_FEATURE_IOC_SPEED (0x04)
1504 #define MPI2_PM_CONTROL_FEATURE_MIN_PRODUCT_SPECIFIC (0x80)
1505 #define MPI2_PM_CONTROL_FEATURE_MAX_PRODUCT_SPECIFIC (0xFF)
1507 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND Feature */
1508 /* Parameter1 contains a PHY number */
1509 /* Parameter2 indicates power condition action using these defines */
1510 #define MPI2_PM_CONTROL_PARAM2_PARTIAL (0x01)
1511 #define MPI2_PM_CONTROL_PARAM2_SLUMBER (0x02)
1512 #define MPI2_PM_CONTROL_PARAM2_EXIT_PWR_MGMT (0x03)
1513 /* Parameter3 and Parameter4 are reserved */
1515 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION Feature */
1516 /* Parameter1 contains SAS port width modulation group number */
1517 /* Parameter2 indicates IOC action using these defines */
1518 #define MPI2_PM_CONTROL_PARAM2_REQUEST_OWNERSHIP (0x01)
1519 #define MPI2_PM_CONTROL_PARAM2_CHANGE_MODULATION (0x02)
1520 #define MPI2_PM_CONTROL_PARAM2_RELINQUISH_OWNERSHIP (0x03)
1521 /* Parameter3 indicates desired modulation level using these defines */
1522 #define MPI2_PM_CONTROL_PARAM3_25_PERCENT (0x00)
1523 #define MPI2_PM_CONTROL_PARAM3_50_PERCENT (0x01)
1524 #define MPI2_PM_CONTROL_PARAM3_75_PERCENT (0x02)
1525 #define MPI2_PM_CONTROL_PARAM3_100_PERCENT (0x03)
1526 /* Parameter4 is reserved */
1528 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_PCIE_LINK Feature */
1529 /* Parameter1 indicates desired PCIe link speed using these defines */
1530 #define MPI2_PM_CONTROL_PARAM1_PCIE_2_5_GBPS (0x00)
1531 #define MPI2_PM_CONTROL_PARAM1_PCIE_5_0_GBPS (0x01)
1532 #define MPI2_PM_CONTROL_PARAM1_PCIE_8_0_GBPS (0x02)
1533 /* Parameter2 indicates desired PCIe link width using these defines */
1534 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X1 (0x01)
1535 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X2 (0x02)
1536 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X4 (0x04)
1537 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X8 (0x08)
1538 /* Parameter3 and Parameter4 are reserved */
1540 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_IOC_SPEED Feature */
1541 /* Parameter1 indicates desired IOC hardware clock speed using these defines */
1542 #define MPI2_PM_CONTROL_PARAM1_FULL_IOC_SPEED (0x01)
1543 #define MPI2_PM_CONTROL_PARAM1_HALF_IOC_SPEED (0x02)
1544 #define MPI2_PM_CONTROL_PARAM1_QUARTER_IOC_SPEED (0x04)
1545 #define MPI2_PM_CONTROL_PARAM1_EIGHTH_IOC_SPEED (0x08)
1546 /* Parameter2, Parameter3, and Parameter4 are reserved */
1549 /* PowerManagementControl Reply message */
1550 typedef struct _MPI2_PWR_MGMT_CONTROL_REPLY
1552 U8 Feature; /* 0x00 */
1553 U8 Reserved1; /* 0x01 */
1554 U8 MsgLength; /* 0x02 */
1555 U8 Function; /* 0x03 */
1556 U16 Reserved2; /* 0x04 */
1557 U8 Reserved3; /* 0x06 */
1558 U8 MsgFlags; /* 0x07 */
1559 U8 VP_ID; /* 0x08 */
1560 U8 VF_ID; /* 0x09 */
1561 U16 Reserved4; /* 0x0A */
1562 U16 Reserved5; /* 0x0C */
1563 U16 IOCStatus; /* 0x0E */
1564 U32 IOCLogInfo; /* 0x10 */
1565 } MPI2_PWR_MGMT_CONTROL_REPLY, MPI2_POINTER PTR_MPI2_PWR_MGMT_CONTROL_REPLY,
1566 Mpi2PwrMgmtControlReply_t, MPI2_POINTER pMpi2PwrMgmtControlReply_t;