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33 * Title: MPI Config message, structures, and Pages
34 * Creation Date: July 27, 2000
36 * mpi_cnfg.h Version: 01.05.15
41 * Date Version Description
42 * -------- -------- ------------------------------------------------------
43 * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000.
44 * 06-06-00 01.00.01 Update version number for 1.0 release.
45 * 06-08-00 01.00.02 Added _PAGEVERSION definitions for all pages.
46 * Added FcPhLowestVersion, FcPhHighestVersion, Reserved2
47 * fields to FC_DEVICE_0 page, updated the page version.
48 * Changed _FREE_RUNNING_CLOCK to _PACING_TRANSFERS in
49 * SCSI_PORT_0, SCSI_DEVICE_0 and SCSI_DEVICE_1 pages
50 * and updated the page versions.
51 * Added _RESPONSE_ID_MASK definition to SCSI_PORT_1
52 * page and updated the page version.
53 * Added Information field and _INFO_PARAMS_NEGOTIATED
54 * definitionto SCSI_DEVICE_0 page.
55 * 06-22-00 01.00.03 Removed batch controls from LAN_0 page and updated the
57 * Added BucketsRemaining to LAN_1 page, redefined the
58 * state values, and updated the page version.
59 * Revised bus width definitions in SCSI_PORT_0,
60 * SCSI_DEVICE_0 and SCSI_DEVICE_1 pages.
61 * 06-30-00 01.00.04 Added MaxReplySize to LAN_1 page and updated the page
63 * Moved FC_DEVICE_0 PageAddress description to spec.
64 * 07-27-00 01.00.05 Corrected the SubsystemVendorID and SubsystemID field
65 * widths in IOC_0 page and updated the page version.
66 * 11-02-00 01.01.01 Original release for post 1.0 work
67 * Added Manufacturing pages, IO Unit Page 2, SCSI SPI
68 * Port Page 2, FC Port Page 4, FC Port Page 5
69 * 11-15-00 01.01.02 Interim changes to match proposals
70 * 12-04-00 01.01.03 Config page changes to match MPI rev 1.00.01.
71 * 12-05-00 01.01.04 Modified config page actions.
72 * 01-09-01 01.01.05 Added defines for page address formats.
73 * Data size for Manufacturing pages 2 and 3 no longer
75 * Io Unit Page 2 size is fixed at 4 adapters and some
77 * SCSI Port Page 2 Device Settings modified.
78 * New fields added to FC Port Page 0 and some flags
80 * Removed impedance flash from FC Port Page 1.
81 * Added FC Port pages 6 and 7.
82 * 01-25-01 01.01.06 Added MaxInitiators field to FcPortPage0.
83 * 01-29-01 01.01.07 Changed some defines to make them 32 character unique.
84 * Added some LinkType defines for FcPortPage0.
85 * 02-20-01 01.01.08 Started using MPI_POINTER.
86 * 02-27-01 01.01.09 Replaced MPI_CONFIG_PAGETYPE_SCSI_LUN with
87 * MPI_CONFIG_PAGETYPE_RAID_VOLUME.
88 * Added definitions and structures for IOC Page 2 and
90 * 03-27-01 01.01.10 Added CONFIG_PAGE_FC_PORT_8 and CONFIG_PAGE_FC_PORT_9.
91 * CONFIG_PAGE_FC_PORT_3 now supports persistent by DID.
92 * Added VendorId and ProductRevLevel fields to
93 * RAIDVOL2_IM_PHYS_ID struct.
94 * Modified values for MPI_FCPORTPAGE0_FLAGS_ATTACH_
95 * defines to make them compatible to MPI version 1.0.
96 * Added structure offset comments.
97 * 04-09-01 01.01.11 Added some new defines for the PageAddress field and
98 * removed some obsolete ones.
99 * Added IO Unit Page 3.
100 * Modified defines for Scsi Port Page 2.
101 * Modified RAID Volume Pages.
102 * 08-08-01 01.02.01 Original release for v1.2 work.
103 * Added SepID and SepBus to RVP2 IMPhysicalDisk struct.
104 * Added defines for the SEP bits in RVP2 VolumeSettings.
105 * Modified the DeviceSettings field in RVP2 to use the
107 * Added defines for SES, SAF-TE, and cross channel for
108 * IOCPage2 CapabilitiesFlags.
109 * Removed define for MPI_IOUNITPAGE2_FLAGS_RAID_DISABLE.
111 * MPI_SCSIPORTPAGE2_PORT_FLAGS_PARITY_ENABLE.
112 * Added define for MPI_CONFIG_PAGEATTR_RO_PERSISTENT.
113 * 08-29-01 01.02.02 Fixed value for MPI_MANUFACTPAGE_DEVID_53C1035.
114 * Added defines for MPI_FCPORTPAGE1_FLAGS_HARD_ALPA_ONLY
115 * and MPI_FCPORTPAGE1_FLAGS_IMMEDIATE_ERROR_REPLY.
116 * Removed MPI_SCSIPORTPAGE0_CAP_PACING_TRANSFERS,
117 * MPI_SCSIDEVPAGE0_NP_PACING_TRANSFERS, and
118 * MPI_SCSIDEVPAGE1_RP_PACING_TRANSFERS, and
119 * MPI_SCSIDEVPAGE1_CONF_PPR_ALLOWED.
120 * Added defines for MPI_SCSIDEVPAGE1_CONF_WDTR_DISALLOWED
121 * and MPI_SCSIDEVPAGE1_CONF_SDTR_DISALLOWED.
122 * Added OnBusTimerValue to CONFIG_PAGE_SCSI_PORT_1.
123 * Added rejected bits to SCSI Device Page 0 Information.
124 * Increased size of ALPA array in FC Port Page 2 by one
125 * and removed a one byte reserved field.
126 * 09-28-01 01.02.03 Swapped NegWireSpeedLow and NegWireSpeedLow in
127 * CONFIG_PAGE_LAN_1 to match preferred 64-bit ordering.
128 * Added structures for Manufacturing Page 4, IO Unit
129 * Page 3, IOC Page 3, IOC Page 4, RAID Volume Page 0, and
130 * RAID PhysDisk Page 0.
131 * 10-04-01 01.02.04 Added define for MPI_CONFIG_PAGETYPE_RAID_PHYSDISK.
132 * Modified some of the new defines to make them 32
134 * Modified how variable length pages (arrays) are defined.
135 * Added generic defines for hot spare pools and RAID
137 * 11-01-01 01.02.05 Added define for MPI_IOUNITPAGE1_DISABLE_IR.
138 * 03-14-02 01.02.06 Added PCISlotNum field to CONFIG_PAGE_IOC_1 along with
139 * related define, and bumped the page version define.
140 * 05-31-02 01.02.07 Added a Flags field to CONFIG_PAGE_IOC_2_RAID_VOL in a
141 * reserved byte and added a define.
143 * MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE.
144 * Added new config page: CONFIG_PAGE_IOC_5.
145 * Added MaxAliases, MaxHardAliases, and NumCurrentAliases
146 * fields to CONFIG_PAGE_FC_PORT_0.
147 * Added AltConnector and NumRequestedAliases fields to
148 * CONFIG_PAGE_FC_PORT_1.
149 * Added new config page: CONFIG_PAGE_FC_PORT_10.
150 * 07-12-02 01.02.08 Added more MPI_MANUFACTPAGE_DEVID_ defines.
151 * Added additional MPI_SCSIDEVPAGE0_NP_ defines.
152 * Added more MPI_SCSIDEVPAGE1_RP_ defines.
154 * MPI_SCSIDEVPAGE1_CONF_EXTENDED_PARAMS_ENABLE.
155 * Added new config page: CONFIG_PAGE_SCSI_DEVICE_3.
156 * Modified MPI_FCPORTPAGE5_FLAGS_ defines.
157 * 09-16-02 01.02.09 Added MPI_SCSIDEVPAGE1_CONF_FORCE_PPR_MSG define.
158 * 11-15-02 01.02.10 Added ConnectedID defines for CONFIG_PAGE_SCSI_PORT_0.
159 * Added more Flags defines for CONFIG_PAGE_FC_PORT_1.
160 * Added more Flags defines for CONFIG_PAGE_FC_DEVICE_0.
161 * 04-01-03 01.02.11 Added RR_TOV field and additional Flags defines for
162 * CONFIG_PAGE_FC_PORT_1.
163 * Added define MPI_FCPORTPAGE5_FLAGS_DISABLE to disable
165 * Added more device id defines.
166 * 06-26-03 01.02.12 Added MPI_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID define.
167 * Added TargetConfig and IDConfig fields to
168 * CONFIG_PAGE_SCSI_PORT_1.
169 * Added more PortFlags defines for CONFIG_PAGE_SCSI_PORT_2
171 * Added more Flags defines for CONFIG_PAGE_FC_PORT_1.
172 * In CONFIG_PAGE_FC_DEVICE_0, replaced Reserved1 field
173 * with ADISCHardALPA.
174 * Added MPI_FC_DEVICE_PAGE0_PROT_FCP_RETRY define.
175 * 01-16-04 01.02.13 Added InitiatorDeviceTimeout and InitiatorIoPendTimeout
176 * fields and related defines to CONFIG_PAGE_FC_PORT_1.
178 * MPI_FCPORTPAGE1_FLAGS_SOFT_ALPA_FALLBACK.
179 * Added new fields to the substructures of
180 * CONFIG_PAGE_FC_PORT_10.
181 * 04-29-04 01.02.14 Added define for IDP bit for CONFIG_PAGE_SCSI_PORT_0,
182 * CONFIG_PAGE_SCSI_DEVICE_0, and
183 * CONFIG_PAGE_SCSI_DEVICE_1. Also bumped Page Version for
185 * 05-11-04 01.03.01 Added structure for CONFIG_PAGE_INBAND_0.
186 * 08-19-04 01.05.01 Modified MSG_CONFIG request to support extended config
188 * Added a new structure for extended config page header.
189 * Added new extended config pages types and structures for
190 * SAS IO Unit, SAS Expander, SAS Device, and SAS PHY.
191 * Replaced a reserved byte in CONFIG_PAGE_MANUFACTURING_4
192 * to add a Flags field.
193 * Two new Manufacturing config pages (5 and 6).
194 * Two new bits defined for IO Unit Page 1 Flags field.
195 * Modified CONFIG_PAGE_IO_UNIT_2 to add three new fields
196 * to specify the BIOS boot device.
197 * Four new Flags bits defined for IO Unit Page 2.
198 * Added IO Unit Page 4.
199 * Added EEDP Flags settings to IOC Page 1.
200 * Added new BIOS Page 1 config page.
201 * 10-05-04 01.05.02 Added define for
202 * MPI_IOCPAGE1_INITIATOR_CONTEXT_REPLY_DISABLE.
203 * Added new Flags field to CONFIG_PAGE_MANUFACTURING_5 and
204 * associated defines.
205 * Added more defines for SAS IO Unit Page 0
206 * DiscoveryStatus field.
207 * Added define for MPI_SAS_IOUNIT0_DS_SUBTRACTIVE_LINK
208 * and MPI_SAS_IOUNIT0_DS_TABLE_LINK.
209 * Added defines for Physical Mapping Modes to SAS IO Unit
212 * MPI_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH.
213 * 10-27-04 01.05.03 Added defines for new SAS PHY page addressing mode.
214 * Added defines for MaxTargetSpinUp to BIOS Page 1.
215 * Added 5 new ControlFlags defines for SAS IO Unit
217 * Added MaxNumPhysicalMappedIDs field to SAS IO Unit
219 * Added AccessStatus field to SAS Device Page 0 and added
220 * new Flags bits for supported SATA features.
221 * 12-07-04 01.05.04 Added config page structures for BIOS Page 2, RAID
222 * Volume Page 1, and RAID Physical Disk Page 1.
223 * Replaced IO Unit Page 1 BootTargetID,BootBus, and
224 * BootAdapterNum with reserved field.
225 * Added DataScrubRate and ResyncRate to RAID Volume
227 * Added MPI_SAS_IOUNIT2_FLAGS_RESERVE_ID_0_FOR_BOOT
229 * 12-09-04 01.05.05 Added Target Mode Large CDB Enable to FC Port Page 1
231 * Added Auto Port Config flag define for SAS IOUNIT
232 * Page 1 ControlFlags.
233 * Added Disabled bad Phy define to Expander Page 1
234 * Discovery Info field.
235 * Added SAS/SATA device support to SAS IOUnit Page 1
237 * Added Unsupported device to SAS Dev Page 0 Flags field
238 * Added disable use SATA Hash Address for SAS IOUNIT
239 * page 1 in ControlFields.
240 * 01-15-05 01.05.06 Added defaults for data scrub rate and resync rate to
241 * Manufacturing Page 4.
242 * Added new defines for BIOS Page 1 IOCSettings field.
243 * Added ExtDiskIdentifier field to RAID Physical Disk
245 * Added new defines for SAS IO Unit Page 1 ControlFlags
246 * and to SAS Device Page 0 Flags to control SATA devices.
247 * Added defines and structures for the new Log Page 0, a
248 * new type of configuration page.
249 * 02-09-05 01.05.07 Added InactiveStatus field to RAID Volume Page 0.
250 * Added WWID field to RAID Volume Page 1.
251 * Added PhysicalPort field to SAS Expander pages 0 and 1.
252 * 03-11-05 01.05.08 Removed the EEDP flags from IOC Page 1.
253 * Added Enclosure/Slot boot device format to BIOS Page 2.
254 * New status value for RAID Volume Page 0 VolumeStatus
255 * (VolumeState subfield).
256 * New value for RAID Physical Page 0 InactiveStatus.
257 * Added Inactive Volume Member flag RAID Physical Disk
258 * Page 0 PhysDiskStatus field.
259 * New physical mapping mode in SAS IO Unit Page 2.
260 * Added CONFIG_PAGE_SAS_ENCLOSURE_0.
261 * Added Slot and Enclosure fields to SAS Device Page 0.
262 * 06-24-05 01.05.09 Added EEDP defines to IOC Page 1.
263 * Added more RAID type defines to IOC Page 2.
264 * Added Port Enable Delay settings to BIOS Page 1.
265 * Added Bad Block Table Full define to RAID Volume Page 0.
266 * Added Previous State defines to RAID Physical Disk
268 * Added Max Sata Targets define for DiscoveryStatus field
269 * of SAS IO Unit Page 0.
270 * Added Device Self Test to Control Flags of SAS IO Unit
272 * Added Direct Attach Starting Slot Number define for SAS
274 * Added new fields in SAS Device Page 2 for enclosure
276 * Added OwnerDevHandle and Flags field to SAS PHY Page 0.
277 * Added IOC GPIO Flags define to SAS Enclosure Page 0.
278 * Fixed the value for MPI_SAS_IOUNIT1_CONTROL_DEV_SATA_SUPPORT.
279 * 08-03-05 01.05.10 Removed ISDataScrubRate and ISResyncRate from
280 * Manufacturing Page 4.
281 * Added MPI_IOUNITPAGE1_SATA_WRITE_CACHE_DISABLE bit.
282 * Added NumDevsPerEnclosure field to SAS IO Unit page 2.
283 * Added MPI_SAS_IOUNIT2_FLAGS_HOST_ASSIGNED_PHYS_MAP
285 * Added EnclosureHandle field to SAS Expander page 0.
286 * Removed redundant NumTableEntriesProg field from SAS
288 * 08-30-05 01.05.11 Added DeviceID for FC949E and changed the DeviceID for
290 * Added more defines for Manufacturing Page 4 Flags field.
291 * Added more defines for IOCSettings and added
292 * ExpanderSpinup field to Bios Page 1.
293 * Added postpone SATA Init bit to SAS IO Unit Page 1
295 * Changed LogEntry format for Log Page 0.
296 * 03-27-06 01.05.12 Added two new Flags defines for Manufacturing Page 4.
297 * Added Manufacturing Page 7.
298 * Added MPI_IOCPAGE2_CAP_FLAGS_RAID_64_BIT_ADDRESSING.
300 * Added PrevBootDeviceForm field to CONFIG_PAGE_BIOS_2.
301 * Added MaxLBAHigh field to RAID Volume Page 0.
302 * Added Nvdata version fields to SAS IO Unit Page 0.
303 * Added AdditionalControlFlags, MaxTargetPortConnectTime,
304 * ReportDeviceMissingDelay, and IODeviceMissingDelay
305 * fields to SAS IO Unit Page 1.
306 * 10-11-06 01.05.13 Added NumForceWWID field and ForceWWID array to
307 * Manufacturing Page 5.
308 * Added Manufacturing pages 8 through 10.
309 * Added defines for supported metadata size bits in
310 * CapabilitiesFlags field of IOC Page 6.
311 * Added defines for metadata size bits in VolumeSettings
312 * field of RAID Volume Page 0.
313 * Added SATA Link Reset settings, Enable SATA Asynchronous
314 * Notification bit, and HideNonZeroAttachedPhyIdentifiers
315 * bit to AdditionalControlFlags field of SAS IO Unit
317 * Added defines for Enclosure Devices Unmapped and
318 * Device Limit Exceeded bits in Status field of SAS IO
320 * Added more AccessStatus values for SAS Device Page 0.
321 * Added bit for SATA Asynchronous Notification Support in
322 * Flags field of SAS Device Page 0.
323 * 02-28-07 01.05.14 Added ExtFlags field to Manufacturing Page 4.
324 * Added Disable SMART Polling for CapabilitiesFlags of
326 * Added Disable SMART Polling to DeviceSettings of BIOS
328 * Added Multi-Port Domain bit for DiscoveryStatus field
329 * of SAS IO Unit Page.
330 * Added Multi-Port Domain Illegal flag for SAS IO Unit
331 * Page 1 AdditionalControlFlags field.
332 * 05-24-07 01.05.15 Added Hide Physical Disks with Non-Integrated RAID
333 * Metadata bit to Manufacturing Page 4 ExtFlags field.
334 * Added Internal Connector to End Device Present bit to
335 * Expander Page 0 Flags field.
337 * MPI_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED.
338 * --------------------------------------------------------------------------
345 /*****************************************************************************
347 * C o n f i g M e s s a g e a n d S t r u c t u r e s
349 *****************************************************************************/
351 typedef struct _CONFIG_PAGE_HEADER
353 U8 PageVersion; /* 00h */
354 U8 PageLength; /* 01h */
355 U8 PageNumber; /* 02h */
356 U8 PageType; /* 03h */
357 } CONFIG_PAGE_HEADER, MPI_POINTER PTR_CONFIG_PAGE_HEADER,
358 ConfigPageHeader_t, MPI_POINTER pConfigPageHeader_t;
360 typedef union _CONFIG_PAGE_HEADER_UNION
362 ConfigPageHeader_t Struct;
366 } ConfigPageHeaderUnion, MPI_POINTER pConfigPageHeaderUnion,
367 CONFIG_PAGE_HEADER_UNION, MPI_POINTER PTR_CONFIG_PAGE_HEADER_UNION;
369 typedef struct _CONFIG_EXTENDED_PAGE_HEADER
371 U8 PageVersion; /* 00h */
372 U8 Reserved1; /* 01h */
373 U8 PageNumber; /* 02h */
374 U8 PageType; /* 03h */
375 U16 ExtPageLength; /* 04h */
376 U8 ExtPageType; /* 06h */
377 U8 Reserved2; /* 07h */
378 } CONFIG_EXTENDED_PAGE_HEADER, MPI_POINTER PTR_CONFIG_EXTENDED_PAGE_HEADER,
379 ConfigExtendedPageHeader_t, MPI_POINTER pConfigExtendedPageHeader_t;
383 /****************************************************************************
384 * PageType field values
385 ****************************************************************************/
386 #define MPI_CONFIG_PAGEATTR_READ_ONLY (0x00)
387 #define MPI_CONFIG_PAGEATTR_CHANGEABLE (0x10)
388 #define MPI_CONFIG_PAGEATTR_PERSISTENT (0x20)
389 #define MPI_CONFIG_PAGEATTR_RO_PERSISTENT (0x30)
390 #define MPI_CONFIG_PAGEATTR_MASK (0xF0)
392 #define MPI_CONFIG_PAGETYPE_IO_UNIT (0x00)
393 #define MPI_CONFIG_PAGETYPE_IOC (0x01)
394 #define MPI_CONFIG_PAGETYPE_BIOS (0x02)
395 #define MPI_CONFIG_PAGETYPE_SCSI_PORT (0x03)
396 #define MPI_CONFIG_PAGETYPE_SCSI_DEVICE (0x04)
397 #define MPI_CONFIG_PAGETYPE_FC_PORT (0x05)
398 #define MPI_CONFIG_PAGETYPE_FC_DEVICE (0x06)
399 #define MPI_CONFIG_PAGETYPE_LAN (0x07)
400 #define MPI_CONFIG_PAGETYPE_RAID_VOLUME (0x08)
401 #define MPI_CONFIG_PAGETYPE_MANUFACTURING (0x09)
402 #define MPI_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A)
403 #define MPI_CONFIG_PAGETYPE_INBAND (0x0B)
404 #define MPI_CONFIG_PAGETYPE_EXTENDED (0x0F)
405 #define MPI_CONFIG_PAGETYPE_MASK (0x0F)
407 #define MPI_CONFIG_TYPENUM_MASK (0x0FFF)
410 /****************************************************************************
411 * ExtPageType field values
412 ****************************************************************************/
413 #define MPI_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10)
414 #define MPI_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11)
415 #define MPI_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12)
416 #define MPI_CONFIG_EXTPAGETYPE_SAS_PHY (0x13)
417 #define MPI_CONFIG_EXTPAGETYPE_LOG (0x14)
418 #define MPI_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15)
421 /****************************************************************************
422 * PageAddress field values
423 ****************************************************************************/
424 #define MPI_SCSI_PORT_PGAD_PORT_MASK (0x000000FF)
426 #define MPI_SCSI_DEVICE_FORM_MASK (0xF0000000)
427 #define MPI_SCSI_DEVICE_FORM_BUS_TID (0x00000000)
428 #define MPI_SCSI_DEVICE_TARGET_ID_MASK (0x000000FF)
429 #define MPI_SCSI_DEVICE_TARGET_ID_SHIFT (0)
430 #define MPI_SCSI_DEVICE_BUS_MASK (0x0000FF00)
431 #define MPI_SCSI_DEVICE_BUS_SHIFT (8)
432 #define MPI_SCSI_DEVICE_FORM_TARGET_MODE (0x10000000)
433 #define MPI_SCSI_DEVICE_TM_RESPOND_ID_MASK (0x000000FF)
434 #define MPI_SCSI_DEVICE_TM_RESPOND_ID_SHIFT (0)
435 #define MPI_SCSI_DEVICE_TM_BUS_MASK (0x0000FF00)
436 #define MPI_SCSI_DEVICE_TM_BUS_SHIFT (8)
437 #define MPI_SCSI_DEVICE_TM_INIT_ID_MASK (0x00FF0000)
438 #define MPI_SCSI_DEVICE_TM_INIT_ID_SHIFT (16)
440 #define MPI_FC_PORT_PGAD_PORT_MASK (0xF0000000)
441 #define MPI_FC_PORT_PGAD_PORT_SHIFT (28)
442 #define MPI_FC_PORT_PGAD_FORM_MASK (0x0F000000)
443 #define MPI_FC_PORT_PGAD_FORM_INDEX (0x01000000)
444 #define MPI_FC_PORT_PGAD_INDEX_MASK (0x0000FFFF)
445 #define MPI_FC_PORT_PGAD_INDEX_SHIFT (0)
447 #define MPI_FC_DEVICE_PGAD_PORT_MASK (0xF0000000)
448 #define MPI_FC_DEVICE_PGAD_PORT_SHIFT (28)
449 #define MPI_FC_DEVICE_PGAD_FORM_MASK (0x0F000000)
450 #define MPI_FC_DEVICE_PGAD_FORM_NEXT_DID (0x00000000)
451 #define MPI_FC_DEVICE_PGAD_ND_PORT_MASK (0xF0000000)
452 #define MPI_FC_DEVICE_PGAD_ND_PORT_SHIFT (28)
453 #define MPI_FC_DEVICE_PGAD_ND_DID_MASK (0x00FFFFFF)
454 #define MPI_FC_DEVICE_PGAD_ND_DID_SHIFT (0)
455 #define MPI_FC_DEVICE_PGAD_FORM_BUS_TID (0x01000000)
456 #define MPI_FC_DEVICE_PGAD_BT_BUS_MASK (0x0000FF00)
457 #define MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT (8)
458 #define MPI_FC_DEVICE_PGAD_BT_TID_MASK (0x000000FF)
459 #define MPI_FC_DEVICE_PGAD_BT_TID_SHIFT (0)
461 #define MPI_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF)
462 #define MPI_PHYSDISK_PGAD_PHYSDISKNUM_SHIFT (0)
464 #define MPI_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000)
465 #define MPI_SAS_EXPAND_PGAD_FORM_SHIFT (28)
466 #define MPI_SAS_EXPAND_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
467 #define MPI_SAS_EXPAND_PGAD_FORM_HANDLE_PHY_NUM (0x00000001)
468 #define MPI_SAS_EXPAND_PGAD_FORM_HANDLE (0x00000002)
469 #define MPI_SAS_EXPAND_PGAD_GNH_MASK_HANDLE (0x0000FFFF)
470 #define MPI_SAS_EXPAND_PGAD_GNH_SHIFT_HANDLE (0)
471 #define MPI_SAS_EXPAND_PGAD_HPN_MASK_PHY (0x00FF0000)
472 #define MPI_SAS_EXPAND_PGAD_HPN_SHIFT_PHY (16)
473 #define MPI_SAS_EXPAND_PGAD_HPN_MASK_HANDLE (0x0000FFFF)
474 #define MPI_SAS_EXPAND_PGAD_HPN_SHIFT_HANDLE (0)
475 #define MPI_SAS_EXPAND_PGAD_H_MASK_HANDLE (0x0000FFFF)
476 #define MPI_SAS_EXPAND_PGAD_H_SHIFT_HANDLE (0)
478 #define MPI_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000)
479 #define MPI_SAS_DEVICE_PGAD_FORM_SHIFT (28)
480 #define MPI_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
481 #define MPI_SAS_DEVICE_PGAD_FORM_BUS_TARGET_ID (0x00000001)
482 #define MPI_SAS_DEVICE_PGAD_FORM_HANDLE (0x00000002)
483 #define MPI_SAS_DEVICE_PGAD_GNH_HANDLE_MASK (0x0000FFFF)
484 #define MPI_SAS_DEVICE_PGAD_GNH_HANDLE_SHIFT (0)
485 #define MPI_SAS_DEVICE_PGAD_BT_BUS_MASK (0x0000FF00)
486 #define MPI_SAS_DEVICE_PGAD_BT_BUS_SHIFT (8)
487 #define MPI_SAS_DEVICE_PGAD_BT_TID_MASK (0x000000FF)
488 #define MPI_SAS_DEVICE_PGAD_BT_TID_SHIFT (0)
489 #define MPI_SAS_DEVICE_PGAD_H_HANDLE_MASK (0x0000FFFF)
490 #define MPI_SAS_DEVICE_PGAD_H_HANDLE_SHIFT (0)
492 #define MPI_SAS_PHY_PGAD_FORM_MASK (0xF0000000)
493 #define MPI_SAS_PHY_PGAD_FORM_SHIFT (28)
494 #define MPI_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x0)
495 #define MPI_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x1)
496 #define MPI_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF)
497 #define MPI_SAS_PHY_PGAD_PHY_NUMBER_SHIFT (0)
498 #define MPI_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF)
499 #define MPI_SAS_PHY_PGAD_PHY_TBL_INDEX_SHIFT (0)
501 #define MPI_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000)
502 #define MPI_SAS_ENCLOS_PGAD_FORM_SHIFT (28)
503 #define MPI_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
504 #define MPI_SAS_ENCLOS_PGAD_FORM_HANDLE (0x00000001)
505 #define MPI_SAS_ENCLOS_PGAD_GNH_HANDLE_MASK (0x0000FFFF)
506 #define MPI_SAS_ENCLOS_PGAD_GNH_HANDLE_SHIFT (0)
507 #define MPI_SAS_ENCLOS_PGAD_H_HANDLE_MASK (0x0000FFFF)
508 #define MPI_SAS_ENCLOS_PGAD_H_HANDLE_SHIFT (0)
512 /****************************************************************************
513 * Config Request Message
514 ****************************************************************************/
515 typedef struct _MSG_CONFIG
518 U8 Reserved; /* 01h */
519 U8 ChainOffset; /* 02h */
520 U8 Function; /* 03h */
521 U16 ExtPageLength; /* 04h */
522 U8 ExtPageType; /* 06h */
523 U8 MsgFlags; /* 07h */
524 U32 MsgContext; /* 08h */
525 U8 Reserved2[8]; /* 0Ch */
526 CONFIG_PAGE_HEADER Header; /* 14h */
527 U32 PageAddress; /* 18h */
528 SGE_IO_UNION PageBufferSGE; /* 1Ch */
529 } MSG_CONFIG, MPI_POINTER PTR_MSG_CONFIG,
530 Config_t, MPI_POINTER pConfig_t;
533 /****************************************************************************
534 * Action field values
535 ****************************************************************************/
536 #define MPI_CONFIG_ACTION_PAGE_HEADER (0x00)
537 #define MPI_CONFIG_ACTION_PAGE_READ_CURRENT (0x01)
538 #define MPI_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02)
539 #define MPI_CONFIG_ACTION_PAGE_DEFAULT (0x03)
540 #define MPI_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04)
541 #define MPI_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05)
542 #define MPI_CONFIG_ACTION_PAGE_READ_NVRAM (0x06)
545 /* Config Reply Message */
546 typedef struct _MSG_CONFIG_REPLY
549 U8 Reserved; /* 01h */
550 U8 MsgLength; /* 02h */
551 U8 Function; /* 03h */
552 U16 ExtPageLength; /* 04h */
553 U8 ExtPageType; /* 06h */
554 U8 MsgFlags; /* 07h */
555 U32 MsgContext; /* 08h */
556 U8 Reserved2[2]; /* 0Ch */
557 U16 IOCStatus; /* 0Eh */
558 U32 IOCLogInfo; /* 10h */
559 CONFIG_PAGE_HEADER Header; /* 14h */
560 } MSG_CONFIG_REPLY, MPI_POINTER PTR_MSG_CONFIG_REPLY,
561 ConfigReply_t, MPI_POINTER pConfigReply_t;
565 /*****************************************************************************
567 * C o n f i g u r a t i o n P a g e s
569 *****************************************************************************/
571 /****************************************************************************
572 * Manufacturing Config pages
573 ****************************************************************************/
574 #define MPI_MANUFACTPAGE_VENDORID_LSILOGIC (0x1000)
576 #define MPI_MANUFACTPAGE_DEVICEID_FC909 (0x0621)
577 #define MPI_MANUFACTPAGE_DEVICEID_FC919 (0x0624)
578 #define MPI_MANUFACTPAGE_DEVICEID_FC929 (0x0622)
579 #define MPI_MANUFACTPAGE_DEVICEID_FC919X (0x0628)
580 #define MPI_MANUFACTPAGE_DEVICEID_FC929X (0x0626)
581 #define MPI_MANUFACTPAGE_DEVICEID_FC939X (0x0642)
582 #define MPI_MANUFACTPAGE_DEVICEID_FC949X (0x0640)
583 #define MPI_MANUFACTPAGE_DEVICEID_FC949E (0x0646)
585 #define MPI_MANUFACTPAGE_DEVID_53C1030 (0x0030)
586 #define MPI_MANUFACTPAGE_DEVID_53C1030ZC (0x0031)
587 #define MPI_MANUFACTPAGE_DEVID_1030_53C1035 (0x0032)
588 #define MPI_MANUFACTPAGE_DEVID_1030ZC_53C1035 (0x0033)
589 #define MPI_MANUFACTPAGE_DEVID_53C1035 (0x0040)
590 #define MPI_MANUFACTPAGE_DEVID_53C1035ZC (0x0041)
592 #define MPI_MANUFACTPAGE_DEVID_SAS1064 (0x0050)
593 #define MPI_MANUFACTPAGE_DEVID_SAS1064A (0x005C)
594 #define MPI_MANUFACTPAGE_DEVID_SAS1064E (0x0056)
595 #define MPI_MANUFACTPAGE_DEVID_SAS1066 (0x005E)
596 #define MPI_MANUFACTPAGE_DEVID_SAS1066E (0x005A)
597 #define MPI_MANUFACTPAGE_DEVID_SAS1068 (0x0054)
598 #define MPI_MANUFACTPAGE_DEVID_SAS1068E (0x0058)
599 #define MPI_MANUFACTPAGE_DEVID_SAS1078 (0x0062)
602 typedef struct _CONFIG_PAGE_MANUFACTURING_0
604 CONFIG_PAGE_HEADER Header; /* 00h */
605 U8 ChipName[16]; /* 04h */
606 U8 ChipRevision[8]; /* 14h */
607 U8 BoardName[16]; /* 1Ch */
608 U8 BoardAssembly[16]; /* 2Ch */
609 U8 BoardTracerNumber[16]; /* 3Ch */
611 } CONFIG_PAGE_MANUFACTURING_0, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_0,
612 ManufacturingPage0_t, MPI_POINTER pManufacturingPage0_t;
614 #define MPI_MANUFACTURING0_PAGEVERSION (0x00)
617 typedef struct _CONFIG_PAGE_MANUFACTURING_1
619 CONFIG_PAGE_HEADER Header; /* 00h */
620 U8 VPD[256]; /* 04h */
621 } CONFIG_PAGE_MANUFACTURING_1, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_1,
622 ManufacturingPage1_t, MPI_POINTER pManufacturingPage1_t;
624 #define MPI_MANUFACTURING1_PAGEVERSION (0x00)
627 typedef struct _MPI_CHIP_REVISION_ID
629 U16 DeviceID; /* 00h */
630 U8 PCIRevisionID; /* 02h */
631 U8 Reserved; /* 03h */
632 } MPI_CHIP_REVISION_ID, MPI_POINTER PTR_MPI_CHIP_REVISION_ID,
633 MpiChipRevisionId_t, MPI_POINTER pMpiChipRevisionId_t;
637 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
638 * one and check Header.PageLength at runtime.
640 #ifndef MPI_MAN_PAGE_2_HW_SETTINGS_WORDS
641 #define MPI_MAN_PAGE_2_HW_SETTINGS_WORDS (1)
644 typedef struct _CONFIG_PAGE_MANUFACTURING_2
646 CONFIG_PAGE_HEADER Header; /* 00h */
647 MPI_CHIP_REVISION_ID ChipId; /* 04h */
648 U32 HwSettings[MPI_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 08h */
649 } CONFIG_PAGE_MANUFACTURING_2, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_2,
650 ManufacturingPage2_t, MPI_POINTER pManufacturingPage2_t;
652 #define MPI_MANUFACTURING2_PAGEVERSION (0x00)
656 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
657 * one and check Header.PageLength at runtime.
659 #ifndef MPI_MAN_PAGE_3_INFO_WORDS
660 #define MPI_MAN_PAGE_3_INFO_WORDS (1)
663 typedef struct _CONFIG_PAGE_MANUFACTURING_3
665 CONFIG_PAGE_HEADER Header; /* 00h */
666 MPI_CHIP_REVISION_ID ChipId; /* 04h */
667 U32 Info[MPI_MAN_PAGE_3_INFO_WORDS];/* 08h */
668 } CONFIG_PAGE_MANUFACTURING_3, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_3,
669 ManufacturingPage3_t, MPI_POINTER pManufacturingPage3_t;
671 #define MPI_MANUFACTURING3_PAGEVERSION (0x00)
674 typedef struct _CONFIG_PAGE_MANUFACTURING_4
676 CONFIG_PAGE_HEADER Header; /* 00h */
677 U32 Reserved1; /* 04h */
678 U8 InfoOffset0; /* 08h */
679 U8 InfoSize0; /* 09h */
680 U8 InfoOffset1; /* 0Ah */
681 U8 InfoSize1; /* 0Bh */
682 U8 InquirySize; /* 0Ch */
684 U16 ExtFlags; /* 0Eh */
685 U8 InquiryData[56]; /* 10h */
686 U32 ISVolumeSettings; /* 48h */
687 U32 IMEVolumeSettings; /* 4Ch */
688 U32 IMVolumeSettings; /* 50h */
689 U32 Reserved3; /* 54h */
690 U32 Reserved4; /* 58h */
691 U32 Reserved5; /* 5Ch */
692 U8 IMEDataScrubRate; /* 60h */
693 U8 IMEResyncRate; /* 61h */
694 U16 Reserved6; /* 62h */
695 U8 IMDataScrubRate; /* 64h */
696 U8 IMResyncRate; /* 65h */
697 U16 Reserved7; /* 66h */
698 U32 Reserved8; /* 68h */
699 U32 Reserved9; /* 6Ch */
700 } CONFIG_PAGE_MANUFACTURING_4, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_4,
701 ManufacturingPage4_t, MPI_POINTER pManufacturingPage4_t;
703 #define MPI_MANUFACTURING4_PAGEVERSION (0x05)
705 /* defines for the Flags field */
706 #define MPI_MANPAGE4_FORCE_BAD_BLOCK_TABLE (0x80)
707 #define MPI_MANPAGE4_FORCE_OFFLINE_FAILOVER (0x40)
708 #define MPI_MANPAGE4_IME_DISABLE (0x20)
709 #define MPI_MANPAGE4_IM_DISABLE (0x10)
710 #define MPI_MANPAGE4_IS_DISABLE (0x08)
711 #define MPI_MANPAGE4_IR_MODEPAGE8_DISABLE (0x04)
712 #define MPI_MANPAGE4_IM_RESYNC_CACHE_ENABLE (0x02)
713 #define MPI_MANPAGE4_IR_NO_MIX_SAS_SATA (0x01)
715 /* defines for the ExtFlags field */
716 #define MPI_MANPAGE4_EXTFLAGS_HIDE_NON_IR_METADATA (0x0008)
717 #define MPI_MANPAGE4_EXTFLAGS_SAS_CACHE_DISABLE (0x0004)
718 #define MPI_MANPAGE4_EXTFLAGS_SATA_CACHE_DISABLE (0x0002)
719 #define MPI_MANPAGE4_EXTFLAGS_LEGACY_MODE (0x0001)
722 #ifndef MPI_MANPAGE5_NUM_FORCEWWID
723 #define MPI_MANPAGE5_NUM_FORCEWWID (1)
726 typedef struct _CONFIG_PAGE_MANUFACTURING_5
728 CONFIG_PAGE_HEADER Header; /* 00h */
729 U64 BaseWWID; /* 04h */
731 U8 NumForceWWID; /* 0Dh */
732 U16 Reserved2; /* 0Eh */
733 U32 Reserved3; /* 10h */
734 U32 Reserved4; /* 14h */
735 U64 ForceWWID[MPI_MANPAGE5_NUM_FORCEWWID]; /* 18h */
736 } CONFIG_PAGE_MANUFACTURING_5, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_5,
737 ManufacturingPage5_t, MPI_POINTER pManufacturingPage5_t;
739 #define MPI_MANUFACTURING5_PAGEVERSION (0x02)
741 /* defines for the Flags field */
742 #define MPI_MANPAGE5_TWO_WWID_PER_PHY (0x01)
745 typedef struct _CONFIG_PAGE_MANUFACTURING_6
747 CONFIG_PAGE_HEADER Header; /* 00h */
748 U32 ProductSpecificInfo;/* 04h */
749 } CONFIG_PAGE_MANUFACTURING_6, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_6,
750 ManufacturingPage6_t, MPI_POINTER pManufacturingPage6_t;
752 #define MPI_MANUFACTURING6_PAGEVERSION (0x00)
755 typedef struct _MPI_MANPAGE7_CONNECTOR_INFO
757 U32 Pinout; /* 00h */
758 U8 Connector[16]; /* 04h */
759 U8 Location; /* 14h */
760 U8 Reserved1; /* 15h */
762 U32 Reserved2; /* 18h */
763 } MPI_MANPAGE7_CONNECTOR_INFO, MPI_POINTER PTR_MPI_MANPAGE7_CONNECTOR_INFO,
764 MpiManPage7ConnectorInfo_t, MPI_POINTER pMpiManPage7ConnectorInfo_t;
766 /* defines for the Pinout field */
767 #define MPI_MANPAGE7_PINOUT_SFF_8484_L4 (0x00080000)
768 #define MPI_MANPAGE7_PINOUT_SFF_8484_L3 (0x00040000)
769 #define MPI_MANPAGE7_PINOUT_SFF_8484_L2 (0x00020000)
770 #define MPI_MANPAGE7_PINOUT_SFF_8484_L1 (0x00010000)
771 #define MPI_MANPAGE7_PINOUT_SFF_8470_L4 (0x00000800)
772 #define MPI_MANPAGE7_PINOUT_SFF_8470_L3 (0x00000400)
773 #define MPI_MANPAGE7_PINOUT_SFF_8470_L2 (0x00000200)
774 #define MPI_MANPAGE7_PINOUT_SFF_8470_L1 (0x00000100)
775 #define MPI_MANPAGE7_PINOUT_SFF_8482 (0x00000002)
776 #define MPI_MANPAGE7_PINOUT_CONNECTION_UNKNOWN (0x00000001)
778 /* defines for the Location field */
779 #define MPI_MANPAGE7_LOCATION_UNKNOWN (0x01)
780 #define MPI_MANPAGE7_LOCATION_INTERNAL (0x02)
781 #define MPI_MANPAGE7_LOCATION_EXTERNAL (0x04)
782 #define MPI_MANPAGE7_LOCATION_SWITCHABLE (0x08)
783 #define MPI_MANPAGE7_LOCATION_AUTO (0x10)
784 #define MPI_MANPAGE7_LOCATION_NOT_PRESENT (0x20)
785 #define MPI_MANPAGE7_LOCATION_NOT_CONNECTED (0x80)
788 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
789 * one and check NumPhys at runtime.
791 #ifndef MPI_MANPAGE7_CONNECTOR_INFO_MAX
792 #define MPI_MANPAGE7_CONNECTOR_INFO_MAX (1)
795 typedef struct _CONFIG_PAGE_MANUFACTURING_7
797 CONFIG_PAGE_HEADER Header; /* 00h */
798 U32 Reserved1; /* 04h */
799 U32 Reserved2; /* 08h */
801 U8 EnclosureName[16]; /* 10h */
802 U8 NumPhys; /* 20h */
803 U8 Reserved3; /* 21h */
804 U16 Reserved4; /* 22h */
805 MPI_MANPAGE7_CONNECTOR_INFO ConnectorInfo[MPI_MANPAGE7_CONNECTOR_INFO_MAX]; /* 24h */
806 } CONFIG_PAGE_MANUFACTURING_7, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_7,
807 ManufacturingPage7_t, MPI_POINTER pManufacturingPage7_t;
809 #define MPI_MANUFACTURING7_PAGEVERSION (0x00)
811 /* defines for the Flags field */
812 #define MPI_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001)
815 typedef struct _CONFIG_PAGE_MANUFACTURING_8
817 CONFIG_PAGE_HEADER Header; /* 00h */
818 U32 ProductSpecificInfo;/* 04h */
819 } CONFIG_PAGE_MANUFACTURING_8, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_8,
820 ManufacturingPage8_t, MPI_POINTER pManufacturingPage8_t;
822 #define MPI_MANUFACTURING8_PAGEVERSION (0x00)
825 typedef struct _CONFIG_PAGE_MANUFACTURING_9
827 CONFIG_PAGE_HEADER Header; /* 00h */
828 U32 ProductSpecificInfo;/* 04h */
829 } CONFIG_PAGE_MANUFACTURING_9, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_9,
830 ManufacturingPage9_t, MPI_POINTER pManufacturingPage9_t;
832 #define MPI_MANUFACTURING9_PAGEVERSION (0x00)
835 typedef struct _CONFIG_PAGE_MANUFACTURING_10
837 CONFIG_PAGE_HEADER Header; /* 00h */
838 U32 ProductSpecificInfo;/* 04h */
839 } CONFIG_PAGE_MANUFACTURING_10, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_10,
840 ManufacturingPage10_t, MPI_POINTER pManufacturingPage10_t;
842 #define MPI_MANUFACTURING10_PAGEVERSION (0x00)
845 /****************************************************************************
846 * IO Unit Config Pages
847 ****************************************************************************/
849 typedef struct _CONFIG_PAGE_IO_UNIT_0
851 CONFIG_PAGE_HEADER Header; /* 00h */
852 U64 UniqueValue; /* 04h */
853 } CONFIG_PAGE_IO_UNIT_0, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_0,
854 IOUnitPage0_t, MPI_POINTER pIOUnitPage0_t;
856 #define MPI_IOUNITPAGE0_PAGEVERSION (0x00)
859 typedef struct _CONFIG_PAGE_IO_UNIT_1
861 CONFIG_PAGE_HEADER Header; /* 00h */
863 } CONFIG_PAGE_IO_UNIT_1, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_1,
864 IOUnitPage1_t, MPI_POINTER pIOUnitPage1_t;
866 #define MPI_IOUNITPAGE1_PAGEVERSION (0x02)
868 /* IO Unit Page 1 Flags defines */
869 #define MPI_IOUNITPAGE1_MULTI_FUNCTION (0x00000000)
870 #define MPI_IOUNITPAGE1_SINGLE_FUNCTION (0x00000001)
871 #define MPI_IOUNITPAGE1_MULTI_PATHING (0x00000002)
872 #define MPI_IOUNITPAGE1_SINGLE_PATHING (0x00000000)
873 #define MPI_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004)
874 #define MPI_IOUNITPAGE1_DISABLE_QUEUE_FULL_HANDLING (0x00000020)
875 #define MPI_IOUNITPAGE1_DISABLE_IR (0x00000040)
876 #define MPI_IOUNITPAGE1_FORCE_32 (0x00000080)
877 #define MPI_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100)
878 #define MPI_IOUNITPAGE1_SATA_WRITE_CACHE_DISABLE (0x00000200)
880 typedef struct _MPI_ADAPTER_INFO
882 U8 PciBusNumber; /* 00h */
883 U8 PciDeviceAndFunctionNumber; /* 01h */
884 U16 AdapterFlags; /* 02h */
885 } MPI_ADAPTER_INFO, MPI_POINTER PTR_MPI_ADAPTER_INFO,
886 MpiAdapterInfo_t, MPI_POINTER pMpiAdapterInfo_t;
888 #define MPI_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001)
889 #define MPI_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002)
891 typedef struct _CONFIG_PAGE_IO_UNIT_2
893 CONFIG_PAGE_HEADER Header; /* 00h */
895 U32 BiosVersion; /* 08h */
896 MPI_ADAPTER_INFO AdapterOrder[4]; /* 0Ch */
897 U32 Reserved1; /* 1Ch */
898 } CONFIG_PAGE_IO_UNIT_2, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_2,
899 IOUnitPage2_t, MPI_POINTER pIOUnitPage2_t;
901 #define MPI_IOUNITPAGE2_PAGEVERSION (0x02)
903 #define MPI_IOUNITPAGE2_FLAGS_PAUSE_ON_ERROR (0x00000002)
904 #define MPI_IOUNITPAGE2_FLAGS_VERBOSE_ENABLE (0x00000004)
905 #define MPI_IOUNITPAGE2_FLAGS_COLOR_VIDEO_DISABLE (0x00000008)
906 #define MPI_IOUNITPAGE2_FLAGS_DONT_HOOK_INT_40 (0x00000010)
908 #define MPI_IOUNITPAGE2_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0)
909 #define MPI_IOUNITPAGE2_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000)
910 #define MPI_IOUNITPAGE2_FLAGS_ADAPTER_DISPLAY (0x00000020)
911 #define MPI_IOUNITPAGE2_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040)
915 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
916 * one and check Header.PageLength at runtime.
918 #ifndef MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX
919 #define MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1)
922 typedef struct _CONFIG_PAGE_IO_UNIT_3
924 CONFIG_PAGE_HEADER Header; /* 00h */
925 U8 GPIOCount; /* 04h */
926 U8 Reserved1; /* 05h */
927 U16 Reserved2; /* 06h */
928 U16 GPIOVal[MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX]; /* 08h */
929 } CONFIG_PAGE_IO_UNIT_3, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_3,
930 IOUnitPage3_t, MPI_POINTER pIOUnitPage3_t;
932 #define MPI_IOUNITPAGE3_PAGEVERSION (0x01)
934 #define MPI_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFC)
935 #define MPI_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2)
936 #define MPI_IOUNITPAGE3_GPIO_SETTING_OFF (0x00)
937 #define MPI_IOUNITPAGE3_GPIO_SETTING_ON (0x01)
940 typedef struct _CONFIG_PAGE_IO_UNIT_4
942 CONFIG_PAGE_HEADER Header; /* 00h */
943 U32 Reserved1; /* 04h */
944 SGE_SIMPLE_UNION FWImageSGE; /* 08h */
945 } CONFIG_PAGE_IO_UNIT_4, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_4,
946 IOUnitPage4_t, MPI_POINTER pIOUnitPage4_t;
948 #define MPI_IOUNITPAGE4_PAGEVERSION (0x00)
951 /****************************************************************************
953 ****************************************************************************/
955 typedef struct _CONFIG_PAGE_IOC_0
957 CONFIG_PAGE_HEADER Header; /* 00h */
958 U32 TotalNVStore; /* 04h */
959 U32 FreeNVStore; /* 08h */
960 U16 VendorID; /* 0Ch */
961 U16 DeviceID; /* 0Eh */
962 U8 RevisionID; /* 10h */
963 U8 Reserved[3]; /* 11h */
964 U32 ClassCode; /* 14h */
965 U16 SubsystemVendorID; /* 18h */
966 U16 SubsystemID; /* 1Ah */
967 } CONFIG_PAGE_IOC_0, MPI_POINTER PTR_CONFIG_PAGE_IOC_0,
968 IOCPage0_t, MPI_POINTER pIOCPage0_t;
970 #define MPI_IOCPAGE0_PAGEVERSION (0x01)
973 typedef struct _CONFIG_PAGE_IOC_1
975 CONFIG_PAGE_HEADER Header; /* 00h */
977 U32 CoalescingTimeout; /* 08h */
978 U8 CoalescingDepth; /* 0Ch */
979 U8 PCISlotNum; /* 0Dh */
980 U8 Reserved[2]; /* 0Eh */
981 } CONFIG_PAGE_IOC_1, MPI_POINTER PTR_CONFIG_PAGE_IOC_1,
982 IOCPage1_t, MPI_POINTER pIOCPage1_t;
984 #define MPI_IOCPAGE1_PAGEVERSION (0x03)
986 /* defines for the Flags field */
987 #define MPI_IOCPAGE1_EEDP_MODE_MASK (0x07000000)
988 #define MPI_IOCPAGE1_EEDP_MODE_OFF (0x00000000)
989 #define MPI_IOCPAGE1_EEDP_MODE_T10 (0x01000000)
990 #define MPI_IOCPAGE1_EEDP_MODE_LSI_1 (0x02000000)
991 #define MPI_IOCPAGE1_INITIATOR_CONTEXT_REPLY_DISABLE (0x00000010)
992 #define MPI_IOCPAGE1_REPLY_COALESCING (0x00000001)
994 #define MPI_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF)
997 typedef struct _CONFIG_PAGE_IOC_2_RAID_VOL
999 U8 VolumeID; /* 00h */
1000 U8 VolumeBus; /* 01h */
1001 U8 VolumeIOC; /* 02h */
1002 U8 VolumePageNumber; /* 03h */
1003 U8 VolumeType; /* 04h */
1005 U16 Reserved3; /* 06h */
1006 } CONFIG_PAGE_IOC_2_RAID_VOL, MPI_POINTER PTR_CONFIG_PAGE_IOC_2_RAID_VOL,
1007 ConfigPageIoc2RaidVol_t, MPI_POINTER pConfigPageIoc2RaidVol_t;
1009 /* IOC Page 2 Volume RAID Type values, also used in RAID Volume pages */
1011 #define MPI_RAID_VOL_TYPE_IS (0x00)
1012 #define MPI_RAID_VOL_TYPE_IME (0x01)
1013 #define MPI_RAID_VOL_TYPE_IM (0x02)
1014 #define MPI_RAID_VOL_TYPE_RAID_5 (0x03)
1015 #define MPI_RAID_VOL_TYPE_RAID_6 (0x04)
1016 #define MPI_RAID_VOL_TYPE_RAID_10 (0x05)
1017 #define MPI_RAID_VOL_TYPE_RAID_50 (0x06)
1018 #define MPI_RAID_VOL_TYPE_UNKNOWN (0xFF)
1020 /* IOC Page 2 Volume Flags values */
1022 #define MPI_IOCPAGE2_FLAG_VOLUME_INACTIVE (0x08)
1025 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1026 * one and check Header.PageLength at runtime.
1028 #ifndef MPI_IOC_PAGE_2_RAID_VOLUME_MAX
1029 #define MPI_IOC_PAGE_2_RAID_VOLUME_MAX (1)
1032 typedef struct _CONFIG_PAGE_IOC_2
1034 CONFIG_PAGE_HEADER Header; /* 00h */
1035 U32 CapabilitiesFlags; /* 04h */
1036 U8 NumActiveVolumes; /* 08h */
1037 U8 MaxVolumes; /* 09h */
1038 U8 NumActivePhysDisks; /* 0Ah */
1039 U8 MaxPhysDisks; /* 0Bh */
1040 CONFIG_PAGE_IOC_2_RAID_VOL RaidVolume[MPI_IOC_PAGE_2_RAID_VOLUME_MAX];/* 0Ch */
1041 } CONFIG_PAGE_IOC_2, MPI_POINTER PTR_CONFIG_PAGE_IOC_2,
1042 IOCPage2_t, MPI_POINTER pIOCPage2_t;
1044 #define MPI_IOCPAGE2_PAGEVERSION (0x04)
1046 /* IOC Page 2 Capabilities flags */
1048 #define MPI_IOCPAGE2_CAP_FLAGS_IS_SUPPORT (0x00000001)
1049 #define MPI_IOCPAGE2_CAP_FLAGS_IME_SUPPORT (0x00000002)
1050 #define MPI_IOCPAGE2_CAP_FLAGS_IM_SUPPORT (0x00000004)
1051 #define MPI_IOCPAGE2_CAP_FLAGS_RAID_5_SUPPORT (0x00000008)
1052 #define MPI_IOCPAGE2_CAP_FLAGS_RAID_6_SUPPORT (0x00000010)
1053 #define MPI_IOCPAGE2_CAP_FLAGS_RAID_10_SUPPORT (0x00000020)
1054 #define MPI_IOCPAGE2_CAP_FLAGS_RAID_50_SUPPORT (0x00000040)
1055 #define MPI_IOCPAGE2_CAP_FLAGS_RAID_64_BIT_ADDRESSING (0x10000000)
1056 #define MPI_IOCPAGE2_CAP_FLAGS_SES_SUPPORT (0x20000000)
1057 #define MPI_IOCPAGE2_CAP_FLAGS_SAFTE_SUPPORT (0x40000000)
1058 #define MPI_IOCPAGE2_CAP_FLAGS_CROSS_CHANNEL_SUPPORT (0x80000000)
1061 typedef struct _IOC_3_PHYS_DISK
1063 U8 PhysDiskID; /* 00h */
1064 U8 PhysDiskBus; /* 01h */
1065 U8 PhysDiskIOC; /* 02h */
1066 U8 PhysDiskNum; /* 03h */
1067 } IOC_3_PHYS_DISK, MPI_POINTER PTR_IOC_3_PHYS_DISK,
1068 Ioc3PhysDisk_t, MPI_POINTER pIoc3PhysDisk_t;
1071 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1072 * one and check Header.PageLength at runtime.
1074 #ifndef MPI_IOC_PAGE_3_PHYSDISK_MAX
1075 #define MPI_IOC_PAGE_3_PHYSDISK_MAX (1)
1078 typedef struct _CONFIG_PAGE_IOC_3
1080 CONFIG_PAGE_HEADER Header; /* 00h */
1081 U8 NumPhysDisks; /* 04h */
1082 U8 Reserved1; /* 05h */
1083 U16 Reserved2; /* 06h */
1084 IOC_3_PHYS_DISK PhysDisk[MPI_IOC_PAGE_3_PHYSDISK_MAX]; /* 08h */
1085 } CONFIG_PAGE_IOC_3, MPI_POINTER PTR_CONFIG_PAGE_IOC_3,
1086 IOCPage3_t, MPI_POINTER pIOCPage3_t;
1088 #define MPI_IOCPAGE3_PAGEVERSION (0x00)
1091 typedef struct _IOC_4_SEP
1093 U8 SEPTargetID; /* 00h */
1094 U8 SEPBus; /* 01h */
1095 U16 Reserved; /* 02h */
1096 } IOC_4_SEP, MPI_POINTER PTR_IOC_4_SEP,
1097 Ioc4Sep_t, MPI_POINTER pIoc4Sep_t;
1100 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1101 * one and check Header.PageLength at runtime.
1103 #ifndef MPI_IOC_PAGE_4_SEP_MAX
1104 #define MPI_IOC_PAGE_4_SEP_MAX (1)
1107 typedef struct _CONFIG_PAGE_IOC_4
1109 CONFIG_PAGE_HEADER Header; /* 00h */
1110 U8 ActiveSEP; /* 04h */
1111 U8 MaxSEP; /* 05h */
1112 U16 Reserved1; /* 06h */
1113 IOC_4_SEP SEP[MPI_IOC_PAGE_4_SEP_MAX]; /* 08h */
1114 } CONFIG_PAGE_IOC_4, MPI_POINTER PTR_CONFIG_PAGE_IOC_4,
1115 IOCPage4_t, MPI_POINTER pIOCPage4_t;
1117 #define MPI_IOCPAGE4_PAGEVERSION (0x00)
1120 typedef struct _IOC_5_HOT_SPARE
1122 U8 PhysDiskNum; /* 00h */
1123 U8 Reserved; /* 01h */
1124 U8 HotSparePool; /* 02h */
1126 } IOC_5_HOT_SPARE, MPI_POINTER PTR_IOC_5_HOT_SPARE,
1127 Ioc5HotSpare_t, MPI_POINTER pIoc5HotSpare_t;
1129 /* IOC Page 5 HotSpare Flags */
1130 #define MPI_IOC_PAGE_5_HOT_SPARE_ACTIVE (0x01)
1133 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1134 * one and check Header.PageLength at runtime.
1136 #ifndef MPI_IOC_PAGE_5_HOT_SPARE_MAX
1137 #define MPI_IOC_PAGE_5_HOT_SPARE_MAX (1)
1140 typedef struct _CONFIG_PAGE_IOC_5
1142 CONFIG_PAGE_HEADER Header; /* 00h */
1143 U32 Reserved1; /* 04h */
1144 U8 NumHotSpares; /* 08h */
1145 U8 Reserved2; /* 09h */
1146 U16 Reserved3; /* 0Ah */
1147 IOC_5_HOT_SPARE HotSpare[MPI_IOC_PAGE_5_HOT_SPARE_MAX]; /* 0Ch */
1148 } CONFIG_PAGE_IOC_5, MPI_POINTER PTR_CONFIG_PAGE_IOC_5,
1149 IOCPage5_t, MPI_POINTER pIOCPage5_t;
1151 #define MPI_IOCPAGE5_PAGEVERSION (0x00)
1153 typedef struct _CONFIG_PAGE_IOC_6
1155 CONFIG_PAGE_HEADER Header; /* 00h */
1156 U32 CapabilitiesFlags; /* 04h */
1157 U8 MaxDrivesIS; /* 08h */
1158 U8 MaxDrivesIM; /* 09h */
1159 U8 MaxDrivesIME; /* 0Ah */
1160 U8 Reserved1; /* 0Bh */
1161 U8 MinDrivesIS; /* 0Ch */
1162 U8 MinDrivesIM; /* 0Dh */
1163 U8 MinDrivesIME; /* 0Eh */
1164 U8 Reserved2; /* 0Fh */
1165 U8 MaxGlobalHotSpares; /* 10h */
1166 U8 Reserved3; /* 11h */
1167 U16 Reserved4; /* 12h */
1168 U32 Reserved5; /* 14h */
1169 U32 SupportedStripeSizeMapIS; /* 18h */
1170 U32 SupportedStripeSizeMapIME; /* 1Ch */
1171 U32 Reserved6; /* 20h */
1172 U8 MetadataSize; /* 24h */
1173 U8 Reserved7; /* 25h */
1174 U16 Reserved8; /* 26h */
1175 U16 MaxBadBlockTableEntries; /* 28h */
1176 U16 Reserved9; /* 2Ah */
1177 U16 IRNvsramUsage; /* 2Ch */
1178 U16 Reserved10; /* 2Eh */
1179 U32 IRNvsramVersion; /* 30h */
1180 U32 Reserved11; /* 34h */
1181 U32 Reserved12; /* 38h */
1182 } CONFIG_PAGE_IOC_6, MPI_POINTER PTR_CONFIG_PAGE_IOC_6,
1183 IOCPage6_t, MPI_POINTER pIOCPage6_t;
1185 #define MPI_IOCPAGE6_PAGEVERSION (0x01)
1187 /* IOC Page 6 Capabilities Flags */
1189 #define MPI_IOCPAGE6_CAP_FLAGS_DISABLE_SMART_POLLING (0x00000008)
1191 #define MPI_IOCPAGE6_CAP_FLAGS_MASK_METADATA_SIZE (0x00000006)
1192 #define MPI_IOCPAGE6_CAP_FLAGS_64MB_METADATA_SIZE (0x00000000)
1193 #define MPI_IOCPAGE6_CAP_FLAGS_512MB_METADATA_SIZE (0x00000002)
1195 #define MPI_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE (0x00000001)
1198 /****************************************************************************
1200 ****************************************************************************/
1202 typedef struct _CONFIG_PAGE_BIOS_1
1204 CONFIG_PAGE_HEADER Header; /* 00h */
1205 U32 BiosOptions; /* 04h */
1206 U32 IOCSettings; /* 08h */
1207 U32 Reserved1; /* 0Ch */
1208 U32 DeviceSettings; /* 10h */
1209 U16 NumberOfDevices; /* 14h */
1210 U8 ExpanderSpinup; /* 16h */
1211 U8 Reserved2; /* 17h */
1212 U16 IOTimeoutBlockDevicesNonRM; /* 18h */
1213 U16 IOTimeoutSequential; /* 1Ah */
1214 U16 IOTimeoutOther; /* 1Ch */
1215 U16 IOTimeoutBlockDevicesRM; /* 1Eh */
1216 } CONFIG_PAGE_BIOS_1, MPI_POINTER PTR_CONFIG_PAGE_BIOS_1,
1217 BIOSPage1_t, MPI_POINTER pBIOSPage1_t;
1219 #define MPI_BIOSPAGE1_PAGEVERSION (0x03)
1221 /* values for the BiosOptions field */
1222 #define MPI_BIOSPAGE1_OPTIONS_SPI_ENABLE (0x00000400)
1223 #define MPI_BIOSPAGE1_OPTIONS_FC_ENABLE (0x00000200)
1224 #define MPI_BIOSPAGE1_OPTIONS_SAS_ENABLE (0x00000100)
1225 #define MPI_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001)
1227 /* values for the IOCSettings field */
1228 #define MPI_BIOSPAGE1_IOCSET_MASK_INITIAL_SPINUP_DELAY (0x0F000000)
1229 #define MPI_BIOSPAGE1_IOCSET_SHIFT_INITIAL_SPINUP_DELAY (24)
1231 #define MPI_BIOSPAGE1_IOCSET_MASK_PORT_ENABLE_DELAY (0x00F00000)
1232 #define MPI_BIOSPAGE1_IOCSET_SHIFT_PORT_ENABLE_DELAY (20)
1234 #define MPI_BIOSPAGE1_IOCSET_AUTO_PORT_ENABLE (0x00080000)
1235 #define MPI_BIOSPAGE1_IOCSET_DIRECT_ATTACH_SPINUP_MODE (0x00040000)
1237 #define MPI_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000)
1238 #define MPI_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000)
1239 #define MPI_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000)
1241 #define MPI_BIOSPAGE1_IOCSET_MASK_MAX_TARGET_SPIN_UP (0x0000F000)
1242 #define MPI_BIOSPAGE1_IOCSET_SHIFT_MAX_TARGET_SPIN_UP (12)
1244 #define MPI_BIOSPAGE1_IOCSET_MASK_SPINUP_DELAY (0x00000F00)
1245 #define MPI_BIOSPAGE1_IOCSET_SHIFT_SPINUP_DELAY (8)
1247 #define MPI_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0)
1248 #define MPI_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000)
1249 #define MPI_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040)
1250 #define MPI_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080)
1252 #define MPI_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030)
1253 #define MPI_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000)
1254 #define MPI_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010)
1255 #define MPI_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020)
1256 #define MPI_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030)
1258 #define MPI_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008)
1260 /* values for the DeviceSettings field */
1261 #define MPI_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING (0x00000010)
1262 #define MPI_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008)
1263 #define MPI_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004)
1264 #define MPI_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002)
1265 #define MPI_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001)
1267 /* defines for the ExpanderSpinup field */
1268 #define MPI_BIOSPAGE1_EXPSPINUP_MASK_MAX_TARGET (0xF0)
1269 #define MPI_BIOSPAGE1_EXPSPINUP_SHIFT_MAX_TARGET (4)
1270 #define MPI_BIOSPAGE1_EXPSPINUP_MASK_DELAY (0x0F)
1272 typedef struct _MPI_BOOT_DEVICE_ADAPTER_ORDER
1274 U32 Reserved1; /* 00h */
1275 U32 Reserved2; /* 04h */
1276 U32 Reserved3; /* 08h */
1277 U32 Reserved4; /* 0Ch */
1278 U32 Reserved5; /* 10h */
1279 U32 Reserved6; /* 14h */
1280 U32 Reserved7; /* 18h */
1281 U32 Reserved8; /* 1Ch */
1282 U32 Reserved9; /* 20h */
1283 U32 Reserved10; /* 24h */
1284 U32 Reserved11; /* 28h */
1285 U32 Reserved12; /* 2Ch */
1286 U32 Reserved13; /* 30h */
1287 U32 Reserved14; /* 34h */
1288 U32 Reserved15; /* 38h */
1289 U32 Reserved16; /* 3Ch */
1290 U32 Reserved17; /* 40h */
1291 } MPI_BOOT_DEVICE_ADAPTER_ORDER, MPI_POINTER PTR_MPI_BOOT_DEVICE_ADAPTER_ORDER;
1293 typedef struct _MPI_BOOT_DEVICE_ADAPTER_NUMBER
1295 U8 TargetID; /* 00h */
1297 U8 AdapterNumber; /* 02h */
1298 U8 Reserved1; /* 03h */
1299 U32 Reserved2; /* 04h */
1300 U32 Reserved3; /* 08h */
1301 U32 Reserved4; /* 0Ch */
1302 U8 LUN[8]; /* 10h */
1303 U32 Reserved5; /* 18h */
1304 U32 Reserved6; /* 1Ch */
1305 U32 Reserved7; /* 20h */
1306 U32 Reserved8; /* 24h */
1307 U32 Reserved9; /* 28h */
1308 U32 Reserved10; /* 2Ch */
1309 U32 Reserved11; /* 30h */
1310 U32 Reserved12; /* 34h */
1311 U32 Reserved13; /* 38h */
1312 U32 Reserved14; /* 3Ch */
1313 U32 Reserved15; /* 40h */
1314 } MPI_BOOT_DEVICE_ADAPTER_NUMBER, MPI_POINTER PTR_MPI_BOOT_DEVICE_ADAPTER_NUMBER;
1316 typedef struct _MPI_BOOT_DEVICE_PCI_ADDRESS
1318 U8 TargetID; /* 00h */
1320 U16 PCIAddress; /* 02h */
1321 U32 Reserved1; /* 04h */
1322 U32 Reserved2; /* 08h */
1323 U32 Reserved3; /* 0Ch */
1324 U8 LUN[8]; /* 10h */
1325 U32 Reserved4; /* 18h */
1326 U32 Reserved5; /* 1Ch */
1327 U32 Reserved6; /* 20h */
1328 U32 Reserved7; /* 24h */
1329 U32 Reserved8; /* 28h */
1330 U32 Reserved9; /* 2Ch */
1331 U32 Reserved10; /* 30h */
1332 U32 Reserved11; /* 34h */
1333 U32 Reserved12; /* 38h */
1334 U32 Reserved13; /* 3Ch */
1335 U32 Reserved14; /* 40h */
1336 } MPI_BOOT_DEVICE_PCI_ADDRESS, MPI_POINTER PTR_MPI_BOOT_DEVICE_PCI_ADDRESS;
1338 typedef struct _MPI_BOOT_DEVICE_SLOT_NUMBER
1340 U8 TargetID; /* 00h */
1342 U8 PCISlotNumber; /* 02h */
1343 U8 Reserved1; /* 03h */
1344 U32 Reserved2; /* 04h */
1345 U32 Reserved3; /* 08h */
1346 U32 Reserved4; /* 0Ch */
1347 U8 LUN[8]; /* 10h */
1348 U32 Reserved5; /* 18h */
1349 U32 Reserved6; /* 1Ch */
1350 U32 Reserved7; /* 20h */
1351 U32 Reserved8; /* 24h */
1352 U32 Reserved9; /* 28h */
1353 U32 Reserved10; /* 2Ch */
1354 U32 Reserved11; /* 30h */
1355 U32 Reserved12; /* 34h */
1356 U32 Reserved13; /* 38h */
1357 U32 Reserved14; /* 3Ch */
1358 U32 Reserved15; /* 40h */
1359 } MPI_BOOT_DEVICE_PCI_SLOT_NUMBER, MPI_POINTER PTR_MPI_BOOT_DEVICE_PCI_SLOT_NUMBER;
1361 typedef struct _MPI_BOOT_DEVICE_FC_WWN
1364 U32 Reserved1; /* 08h */
1365 U32 Reserved2; /* 0Ch */
1366 U8 LUN[8]; /* 10h */
1367 U32 Reserved3; /* 18h */
1368 U32 Reserved4; /* 1Ch */
1369 U32 Reserved5; /* 20h */
1370 U32 Reserved6; /* 24h */
1371 U32 Reserved7; /* 28h */
1372 U32 Reserved8; /* 2Ch */
1373 U32 Reserved9; /* 30h */
1374 U32 Reserved10; /* 34h */
1375 U32 Reserved11; /* 38h */
1376 U32 Reserved12; /* 3Ch */
1377 U32 Reserved13; /* 40h */
1378 } MPI_BOOT_DEVICE_FC_WWN, MPI_POINTER PTR_MPI_BOOT_DEVICE_FC_WWN;
1380 typedef struct _MPI_BOOT_DEVICE_SAS_WWN
1382 U64 SASAddress; /* 00h */
1383 U32 Reserved1; /* 08h */
1384 U32 Reserved2; /* 0Ch */
1385 U8 LUN[8]; /* 10h */
1386 U32 Reserved3; /* 18h */
1387 U32 Reserved4; /* 1Ch */
1388 U32 Reserved5; /* 20h */
1389 U32 Reserved6; /* 24h */
1390 U32 Reserved7; /* 28h */
1391 U32 Reserved8; /* 2Ch */
1392 U32 Reserved9; /* 30h */
1393 U32 Reserved10; /* 34h */
1394 U32 Reserved11; /* 38h */
1395 U32 Reserved12; /* 3Ch */
1396 U32 Reserved13; /* 40h */
1397 } MPI_BOOT_DEVICE_SAS_WWN, MPI_POINTER PTR_MPI_BOOT_DEVICE_SAS_WWN;
1399 typedef struct _MPI_BOOT_DEVICE_ENCLOSURE_SLOT
1401 U64 EnclosureLogicalID; /* 00h */
1402 U32 Reserved1; /* 08h */
1403 U32 Reserved2; /* 0Ch */
1404 U8 LUN[8]; /* 10h */
1405 U16 SlotNumber; /* 18h */
1406 U16 Reserved3; /* 1Ah */
1407 U32 Reserved4; /* 1Ch */
1408 U32 Reserved5; /* 20h */
1409 U32 Reserved6; /* 24h */
1410 U32 Reserved7; /* 28h */
1411 U32 Reserved8; /* 2Ch */
1412 U32 Reserved9; /* 30h */
1413 U32 Reserved10; /* 34h */
1414 U32 Reserved11; /* 38h */
1415 U32 Reserved12; /* 3Ch */
1416 U32 Reserved13; /* 40h */
1417 } MPI_BOOT_DEVICE_ENCLOSURE_SLOT,
1418 MPI_POINTER PTR_MPI_BOOT_DEVICE_ENCLOSURE_SLOT;
1420 typedef union _MPI_BIOSPAGE2_BOOT_DEVICE
1422 MPI_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder;
1423 MPI_BOOT_DEVICE_ADAPTER_NUMBER AdapterNumber;
1424 MPI_BOOT_DEVICE_PCI_ADDRESS PCIAddress;
1425 MPI_BOOT_DEVICE_PCI_SLOT_NUMBER PCISlotNumber;
1426 MPI_BOOT_DEVICE_FC_WWN FcWwn;
1427 MPI_BOOT_DEVICE_SAS_WWN SasWwn;
1428 MPI_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot;
1429 } MPI_BIOSPAGE2_BOOT_DEVICE, MPI_POINTER PTR_MPI_BIOSPAGE2_BOOT_DEVICE;
1431 typedef struct _CONFIG_PAGE_BIOS_2
1433 CONFIG_PAGE_HEADER Header; /* 00h */
1434 U32 Reserved1; /* 04h */
1435 U32 Reserved2; /* 08h */
1436 U32 Reserved3; /* 0Ch */
1437 U32 Reserved4; /* 10h */
1438 U32 Reserved5; /* 14h */
1439 U32 Reserved6; /* 18h */
1440 U8 BootDeviceForm; /* 1Ch */
1441 U8 PrevBootDeviceForm; /* 1Ch */
1442 U16 Reserved8; /* 1Eh */
1443 MPI_BIOSPAGE2_BOOT_DEVICE BootDevice; /* 20h */
1444 } CONFIG_PAGE_BIOS_2, MPI_POINTER PTR_CONFIG_PAGE_BIOS_2,
1445 BIOSPage2_t, MPI_POINTER pBIOSPage2_t;
1447 #define MPI_BIOSPAGE2_PAGEVERSION (0x02)
1449 #define MPI_BIOSPAGE2_FORM_MASK (0x0F)
1450 #define MPI_BIOSPAGE2_FORM_ADAPTER_ORDER (0x00)
1451 #define MPI_BIOSPAGE2_FORM_ADAPTER_NUMBER (0x01)
1452 #define MPI_BIOSPAGE2_FORM_PCI_ADDRESS (0x02)
1453 #define MPI_BIOSPAGE2_FORM_PCI_SLOT_NUMBER (0x03)
1454 #define MPI_BIOSPAGE2_FORM_FC_WWN (0x04)
1455 #define MPI_BIOSPAGE2_FORM_SAS_WWN (0x05)
1456 #define MPI_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06)
1459 /****************************************************************************
1460 * SCSI Port Config Pages
1461 ****************************************************************************/
1463 typedef struct _CONFIG_PAGE_SCSI_PORT_0
1465 CONFIG_PAGE_HEADER Header; /* 00h */
1466 U32 Capabilities; /* 04h */
1467 U32 PhysicalInterface; /* 08h */
1468 } CONFIG_PAGE_SCSI_PORT_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_0,
1469 SCSIPortPage0_t, MPI_POINTER pSCSIPortPage0_t;
1471 #define MPI_SCSIPORTPAGE0_PAGEVERSION (0x02)
1473 #define MPI_SCSIPORTPAGE0_CAP_IU (0x00000001)
1474 #define MPI_SCSIPORTPAGE0_CAP_DT (0x00000002)
1475 #define MPI_SCSIPORTPAGE0_CAP_QAS (0x00000004)
1476 #define MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK (0x0000FF00)
1477 #define MPI_SCSIPORTPAGE0_SYNC_ASYNC (0x00)
1478 #define MPI_SCSIPORTPAGE0_SYNC_5 (0x32)
1479 #define MPI_SCSIPORTPAGE0_SYNC_10 (0x19)
1480 #define MPI_SCSIPORTPAGE0_SYNC_20 (0x0C)
1481 #define MPI_SCSIPORTPAGE0_SYNC_33_33 (0x0B)
1482 #define MPI_SCSIPORTPAGE0_SYNC_40 (0x0A)
1483 #define MPI_SCSIPORTPAGE0_SYNC_80 (0x09)
1484 #define MPI_SCSIPORTPAGE0_SYNC_160 (0x08)
1485 #define MPI_SCSIPORTPAGE0_SYNC_UNKNOWN (0xFF)
1487 #define MPI_SCSIPORTPAGE0_CAP_SHIFT_MIN_SYNC_PERIOD (8)
1488 #define MPI_SCSIPORTPAGE0_CAP_GET_MIN_SYNC_PERIOD(Cap) \
1489 ( ((Cap) & MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK) \
1490 >> MPI_SCSIPORTPAGE0_CAP_SHIFT_MIN_SYNC_PERIOD \
1492 #define MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK (0x00FF0000)
1493 #define MPI_SCSIPORTPAGE0_CAP_SHIFT_MAX_SYNC_OFFSET (16)
1494 #define MPI_SCSIPORTPAGE0_CAP_GET_MAX_SYNC_OFFSET(Cap) \
1495 ( ((Cap) & MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK) \
1496 >> MPI_SCSIPORTPAGE0_CAP_SHIFT_MAX_SYNC_OFFSET \
1498 #define MPI_SCSIPORTPAGE0_CAP_IDP (0x08000000)
1499 #define MPI_SCSIPORTPAGE0_CAP_WIDE (0x20000000)
1500 #define MPI_SCSIPORTPAGE0_CAP_AIP (0x80000000)
1502 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_TYPE_MASK (0x00000003)
1503 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_HVD (0x01)
1504 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_SE (0x02)
1505 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_LVD (0x03)
1506 #define MPI_SCSIPORTPAGE0_PHY_MASK_CONNECTED_ID (0xFF000000)
1507 #define MPI_SCSIPORTPAGE0_PHY_SHIFT_CONNECTED_ID (24)
1508 #define MPI_SCSIPORTPAGE0_PHY_BUS_FREE_CONNECTED_ID (0xFE)
1509 #define MPI_SCSIPORTPAGE0_PHY_UNKNOWN_CONNECTED_ID (0xFF)
1512 typedef struct _CONFIG_PAGE_SCSI_PORT_1
1514 CONFIG_PAGE_HEADER Header; /* 00h */
1515 U32 Configuration; /* 04h */
1516 U32 OnBusTimerValue; /* 08h */
1517 U8 TargetConfig; /* 0Ch */
1518 U8 Reserved1; /* 0Dh */
1519 U16 IDConfig; /* 0Eh */
1520 } CONFIG_PAGE_SCSI_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_1,
1521 SCSIPortPage1_t, MPI_POINTER pSCSIPortPage1_t;
1523 #define MPI_SCSIPORTPAGE1_PAGEVERSION (0x03)
1525 /* Configuration values */
1526 #define MPI_SCSIPORTPAGE1_CFG_PORT_SCSI_ID_MASK (0x000000FF)
1527 #define MPI_SCSIPORTPAGE1_CFG_PORT_RESPONSE_ID_MASK (0xFFFF0000)
1528 #define MPI_SCSIPORTPAGE1_CFG_SHIFT_PORT_RESPONSE_ID (16)
1530 /* TargetConfig values */
1531 #define MPI_SCSIPORTPAGE1_TARGCONFIG_TARG_ONLY (0x01)
1532 #define MPI_SCSIPORTPAGE1_TARGCONFIG_INIT_TARG (0x02)
1535 typedef struct _MPI_DEVICE_INFO
1537 U8 Timeout; /* 00h */
1538 U8 SyncFactor; /* 01h */
1539 U16 DeviceFlags; /* 02h */
1540 } MPI_DEVICE_INFO, MPI_POINTER PTR_MPI_DEVICE_INFO,
1541 MpiDeviceInfo_t, MPI_POINTER pMpiDeviceInfo_t;
1543 typedef struct _CONFIG_PAGE_SCSI_PORT_2
1545 CONFIG_PAGE_HEADER Header; /* 00h */
1546 U32 PortFlags; /* 04h */
1547 U32 PortSettings; /* 08h */
1548 MPI_DEVICE_INFO DeviceSettings[16]; /* 0Ch */
1549 } CONFIG_PAGE_SCSI_PORT_2, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_2,
1550 SCSIPortPage2_t, MPI_POINTER pSCSIPortPage2_t;
1552 #define MPI_SCSIPORTPAGE2_PAGEVERSION (0x02)
1554 /* PortFlags values */
1555 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_SCAN_HIGH_TO_LOW (0x00000001)
1556 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_AVOID_SCSI_RESET (0x00000004)
1557 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_ALTERNATE_CHS (0x00000008)
1558 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_TERMINATION_DISABLE (0x00000010)
1560 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_DV_MASK (0x00000060)
1561 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_FULL_DV (0x00000000)
1562 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_BASIC_DV_ONLY (0x00000020)
1563 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_OFF_DV (0x00000060)
1566 /* PortSettings values */
1567 #define MPI_SCSIPORTPAGE2_PORT_HOST_ID_MASK (0x0000000F)
1568 #define MPI_SCSIPORTPAGE2_PORT_MASK_INIT_HBA (0x00000030)
1569 #define MPI_SCSIPORTPAGE2_PORT_DISABLE_INIT_HBA (0x00000000)
1570 #define MPI_SCSIPORTPAGE2_PORT_BIOS_INIT_HBA (0x00000010)
1571 #define MPI_SCSIPORTPAGE2_PORT_OS_INIT_HBA (0x00000020)
1572 #define MPI_SCSIPORTPAGE2_PORT_BIOS_OS_INIT_HBA (0x00000030)
1573 #define MPI_SCSIPORTPAGE2_PORT_REMOVABLE_MEDIA (0x000000C0)
1574 #define MPI_SCSIPORTPAGE2_PORT_RM_NONE (0x00000000)
1575 #define MPI_SCSIPORTPAGE2_PORT_RM_BOOT_ONLY (0x00000040)
1576 #define MPI_SCSIPORTPAGE2_PORT_RM_WITH_MEDIA (0x00000080)
1577 #define MPI_SCSIPORTPAGE2_PORT_SPINUP_DELAY_MASK (0x00000F00)
1578 #define MPI_SCSIPORTPAGE2_PORT_SHIFT_SPINUP_DELAY (8)
1579 #define MPI_SCSIPORTPAGE2_PORT_MASK_NEGO_MASTER_SETTINGS (0x00003000)
1580 #define MPI_SCSIPORTPAGE2_PORT_NEGO_MASTER_SETTINGS (0x00000000)
1581 #define MPI_SCSIPORTPAGE2_PORT_NONE_MASTER_SETTINGS (0x00001000)
1582 #define MPI_SCSIPORTPAGE2_PORT_ALL_MASTER_SETTINGS (0x00003000)
1584 #define MPI_SCSIPORTPAGE2_DEVICE_DISCONNECT_ENABLE (0x0001)
1585 #define MPI_SCSIPORTPAGE2_DEVICE_ID_SCAN_ENABLE (0x0002)
1586 #define MPI_SCSIPORTPAGE2_DEVICE_LUN_SCAN_ENABLE (0x0004)
1587 #define MPI_SCSIPORTPAGE2_DEVICE_TAG_QUEUE_ENABLE (0x0008)
1588 #define MPI_SCSIPORTPAGE2_DEVICE_WIDE_DISABLE (0x0010)
1589 #define MPI_SCSIPORTPAGE2_DEVICE_BOOT_CHOICE (0x0020)
1592 /****************************************************************************
1593 * SCSI Target Device Config Pages
1594 ****************************************************************************/
1596 typedef struct _CONFIG_PAGE_SCSI_DEVICE_0
1598 CONFIG_PAGE_HEADER Header; /* 00h */
1599 U32 NegotiatedParameters; /* 04h */
1600 U32 Information; /* 08h */
1601 } CONFIG_PAGE_SCSI_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_0,
1602 SCSIDevicePage0_t, MPI_POINTER pSCSIDevicePage0_t;
1604 #define MPI_SCSIDEVPAGE0_PAGEVERSION (0x04)
1606 #define MPI_SCSIDEVPAGE0_NP_IU (0x00000001)
1607 #define MPI_SCSIDEVPAGE0_NP_DT (0x00000002)
1608 #define MPI_SCSIDEVPAGE0_NP_QAS (0x00000004)
1609 #define MPI_SCSIDEVPAGE0_NP_HOLD_MCS (0x00000008)
1610 #define MPI_SCSIDEVPAGE0_NP_WR_FLOW (0x00000010)
1611 #define MPI_SCSIDEVPAGE0_NP_RD_STRM (0x00000020)
1612 #define MPI_SCSIDEVPAGE0_NP_RTI (0x00000040)
1613 #define MPI_SCSIDEVPAGE0_NP_PCOMP_EN (0x00000080)
1614 #define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_PERIOD_MASK (0x0000FF00)
1615 #define MPI_SCSIDEVPAGE0_NP_SHIFT_SYNC_PERIOD (8)
1616 #define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_OFFSET_MASK (0x00FF0000)
1617 #define MPI_SCSIDEVPAGE0_NP_SHIFT_SYNC_OFFSET (16)
1618 #define MPI_SCSIDEVPAGE0_NP_IDP (0x08000000)
1619 #define MPI_SCSIDEVPAGE0_NP_WIDE (0x20000000)
1620 #define MPI_SCSIDEVPAGE0_NP_AIP (0x80000000)
1622 #define MPI_SCSIDEVPAGE0_INFO_PARAMS_NEGOTIATED (0x00000001)
1623 #define MPI_SCSIDEVPAGE0_INFO_SDTR_REJECTED (0x00000002)
1624 #define MPI_SCSIDEVPAGE0_INFO_WDTR_REJECTED (0x00000004)
1625 #define MPI_SCSIDEVPAGE0_INFO_PPR_REJECTED (0x00000008)
1628 typedef struct _CONFIG_PAGE_SCSI_DEVICE_1
1630 CONFIG_PAGE_HEADER Header; /* 00h */
1631 U32 RequestedParameters; /* 04h */
1632 U32 Reserved; /* 08h */
1633 U32 Configuration; /* 0Ch */
1634 } CONFIG_PAGE_SCSI_DEVICE_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_1,
1635 SCSIDevicePage1_t, MPI_POINTER pSCSIDevicePage1_t;
1637 #define MPI_SCSIDEVPAGE1_PAGEVERSION (0x05)
1639 #define MPI_SCSIDEVPAGE1_RP_IU (0x00000001)
1640 #define MPI_SCSIDEVPAGE1_RP_DT (0x00000002)
1641 #define MPI_SCSIDEVPAGE1_RP_QAS (0x00000004)
1642 #define MPI_SCSIDEVPAGE1_RP_HOLD_MCS (0x00000008)
1643 #define MPI_SCSIDEVPAGE1_RP_WR_FLOW (0x00000010)
1644 #define MPI_SCSIDEVPAGE1_RP_RD_STRM (0x00000020)
1645 #define MPI_SCSIDEVPAGE1_RP_RTI (0x00000040)
1646 #define MPI_SCSIDEVPAGE1_RP_PCOMP_EN (0x00000080)
1647 #define MPI_SCSIDEVPAGE1_RP_MIN_SYNC_PERIOD_MASK (0x0000FF00)
1648 #define MPI_SCSIDEVPAGE1_RP_SHIFT_MIN_SYNC_PERIOD (8)
1649 #define MPI_SCSIDEVPAGE1_RP_MAX_SYNC_OFFSET_MASK (0x00FF0000)
1650 #define MPI_SCSIDEVPAGE1_RP_SHIFT_MAX_SYNC_OFFSET (16)
1651 #define MPI_SCSIDEVPAGE1_RP_IDP (0x08000000)
1652 #define MPI_SCSIDEVPAGE1_RP_WIDE (0x20000000)
1653 #define MPI_SCSIDEVPAGE1_RP_AIP (0x80000000)
1655 #define MPI_SCSIDEVPAGE1_CONF_WDTR_DISALLOWED (0x00000002)
1656 #define MPI_SCSIDEVPAGE1_CONF_SDTR_DISALLOWED (0x00000004)
1657 #define MPI_SCSIDEVPAGE1_CONF_EXTENDED_PARAMS_ENABLE (0x00000008)
1658 #define MPI_SCSIDEVPAGE1_CONF_FORCE_PPR_MSG (0x00000010)
1661 typedef struct _CONFIG_PAGE_SCSI_DEVICE_2
1663 CONFIG_PAGE_HEADER Header; /* 00h */
1664 U32 DomainValidation; /* 04h */
1665 U32 ParityPipeSelect; /* 08h */
1666 U32 DataPipeSelect; /* 0Ch */
1667 } CONFIG_PAGE_SCSI_DEVICE_2, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_2,
1668 SCSIDevicePage2_t, MPI_POINTER pSCSIDevicePage2_t;
1670 #define MPI_SCSIDEVPAGE2_PAGEVERSION (0x01)
1672 #define MPI_SCSIDEVPAGE2_DV_ISI_ENABLE (0x00000010)
1673 #define MPI_SCSIDEVPAGE2_DV_SECONDARY_DRIVER_ENABLE (0x00000020)
1674 #define MPI_SCSIDEVPAGE2_DV_SLEW_RATE_CTRL (0x00000380)
1675 #define MPI_SCSIDEVPAGE2_DV_PRIM_DRIVE_STR_CTRL (0x00001C00)
1676 #define MPI_SCSIDEVPAGE2_DV_SECOND_DRIVE_STR_CTRL (0x0000E000)
1677 #define MPI_SCSIDEVPAGE2_DV_XCLKH_ST (0x10000000)
1678 #define MPI_SCSIDEVPAGE2_DV_XCLKS_ST (0x20000000)
1679 #define MPI_SCSIDEVPAGE2_DV_XCLKH_DT (0x40000000)
1680 #define MPI_SCSIDEVPAGE2_DV_XCLKS_DT (0x80000000)
1682 #define MPI_SCSIDEVPAGE2_PPS_PPS_MASK (0x00000003)
1684 #define MPI_SCSIDEVPAGE2_DPS_BIT_0_PL_SELECT_MASK (0x00000003)
1685 #define MPI_SCSIDEVPAGE2_DPS_BIT_1_PL_SELECT_MASK (0x0000000C)
1686 #define MPI_SCSIDEVPAGE2_DPS_BIT_2_PL_SELECT_MASK (0x00000030)
1687 #define MPI_SCSIDEVPAGE2_DPS_BIT_3_PL_SELECT_MASK (0x000000C0)
1688 #define MPI_SCSIDEVPAGE2_DPS_BIT_4_PL_SELECT_MASK (0x00000300)
1689 #define MPI_SCSIDEVPAGE2_DPS_BIT_5_PL_SELECT_MASK (0x00000C00)
1690 #define MPI_SCSIDEVPAGE2_DPS_BIT_6_PL_SELECT_MASK (0x00003000)
1691 #define MPI_SCSIDEVPAGE2_DPS_BIT_7_PL_SELECT_MASK (0x0000C000)
1692 #define MPI_SCSIDEVPAGE2_DPS_BIT_8_PL_SELECT_MASK (0x00030000)
1693 #define MPI_SCSIDEVPAGE2_DPS_BIT_9_PL_SELECT_MASK (0x000C0000)
1694 #define MPI_SCSIDEVPAGE2_DPS_BIT_10_PL_SELECT_MASK (0x00300000)
1695 #define MPI_SCSIDEVPAGE2_DPS_BIT_11_PL_SELECT_MASK (0x00C00000)
1696 #define MPI_SCSIDEVPAGE2_DPS_BIT_12_PL_SELECT_MASK (0x03000000)
1697 #define MPI_SCSIDEVPAGE2_DPS_BIT_13_PL_SELECT_MASK (0x0C000000)
1698 #define MPI_SCSIDEVPAGE2_DPS_BIT_14_PL_SELECT_MASK (0x30000000)
1699 #define MPI_SCSIDEVPAGE2_DPS_BIT_15_PL_SELECT_MASK (0xC0000000)
1702 typedef struct _CONFIG_PAGE_SCSI_DEVICE_3
1704 CONFIG_PAGE_HEADER Header; /* 00h */
1705 U16 MsgRejectCount; /* 04h */
1706 U16 PhaseErrorCount; /* 06h */
1707 U16 ParityErrorCount; /* 08h */
1708 U16 Reserved; /* 0Ah */
1709 } CONFIG_PAGE_SCSI_DEVICE_3, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_3,
1710 SCSIDevicePage3_t, MPI_POINTER pSCSIDevicePage3_t;
1712 #define MPI_SCSIDEVPAGE3_PAGEVERSION (0x00)
1714 #define MPI_SCSIDEVPAGE3_MAX_COUNTER (0xFFFE)
1715 #define MPI_SCSIDEVPAGE3_UNSUPPORTED_COUNTER (0xFFFF)
1718 /****************************************************************************
1719 * FC Port Config Pages
1720 ****************************************************************************/
1722 typedef struct _CONFIG_PAGE_FC_PORT_0
1724 CONFIG_PAGE_HEADER Header; /* 00h */
1725 U32 Flags; /* 04h */
1726 U8 MPIPortNumber; /* 08h */
1727 U8 LinkType; /* 09h */
1728 U8 PortState; /* 0Ah */
1729 U8 Reserved; /* 0Bh */
1730 U32 PortIdentifier; /* 0Ch */
1733 U32 SupportedServiceClass; /* 20h */
1734 U32 SupportedSpeeds; /* 24h */
1735 U32 CurrentSpeed; /* 28h */
1736 U32 MaxFrameSize; /* 2Ch */
1737 U64 FabricWWNN; /* 30h */
1738 U64 FabricWWPN; /* 38h */
1739 U32 DiscoveredPortsCount; /* 40h */
1740 U32 MaxInitiators; /* 44h */
1741 U8 MaxAliasesSupported; /* 48h */
1742 U8 MaxHardAliasesSupported; /* 49h */
1743 U8 NumCurrentAliases; /* 4Ah */
1744 U8 Reserved1; /* 4Bh */
1745 } CONFIG_PAGE_FC_PORT_0, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_0,
1746 FCPortPage0_t, MPI_POINTER pFCPortPage0_t;
1748 #define MPI_FCPORTPAGE0_PAGEVERSION (0x02)
1750 #define MPI_FCPORTPAGE0_FLAGS_PROT_MASK (0x0000000F)
1751 #define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_INIT (MPI_PORTFACTS_PROTOCOL_INITIATOR)
1752 #define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_TARG (MPI_PORTFACTS_PROTOCOL_TARGET)
1753 #define MPI_FCPORTPAGE0_FLAGS_PROT_LAN (MPI_PORTFACTS_PROTOCOL_LAN)
1754 #define MPI_FCPORTPAGE0_FLAGS_PROT_LOGBUSADDR (MPI_PORTFACTS_PROTOCOL_LOGBUSADDR)
1756 #define MPI_FCPORTPAGE0_FLAGS_ALIAS_ALPA_SUPPORTED (0x00000010)
1757 #define MPI_FCPORTPAGE0_FLAGS_ALIAS_WWN_SUPPORTED (0x00000020)
1758 #define MPI_FCPORTPAGE0_FLAGS_FABRIC_WWN_VALID (0x00000040)
1760 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_TYPE_MASK (0x00000F00)
1761 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_NO_INIT (0x00000000)
1762 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_POINT_TO_POINT (0x00000100)
1763 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_PRIVATE_LOOP (0x00000200)
1764 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_FABRIC_DIRECT (0x00000400)
1765 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_PUBLIC_LOOP (0x00000800)
1767 #define MPI_FCPORTPAGE0_LTYPE_RESERVED (0x00)
1768 #define MPI_FCPORTPAGE0_LTYPE_OTHER (0x01)
1769 #define MPI_FCPORTPAGE0_LTYPE_UNKNOWN (0x02)
1770 #define MPI_FCPORTPAGE0_LTYPE_COPPER (0x03)
1771 #define MPI_FCPORTPAGE0_LTYPE_SINGLE_1300 (0x04)
1772 #define MPI_FCPORTPAGE0_LTYPE_SINGLE_1500 (0x05)
1773 #define MPI_FCPORTPAGE0_LTYPE_50_LASER_MULTI (0x06)
1774 #define MPI_FCPORTPAGE0_LTYPE_50_LED_MULTI (0x07)
1775 #define MPI_FCPORTPAGE0_LTYPE_62_LASER_MULTI (0x08)
1776 #define MPI_FCPORTPAGE0_LTYPE_62_LED_MULTI (0x09)
1777 #define MPI_FCPORTPAGE0_LTYPE_MULTI_LONG_WAVE (0x0A)
1778 #define MPI_FCPORTPAGE0_LTYPE_MULTI_SHORT_WAVE (0x0B)
1779 #define MPI_FCPORTPAGE0_LTYPE_LASER_SHORT_WAVE (0x0C)
1780 #define MPI_FCPORTPAGE0_LTYPE_LED_SHORT_WAVE (0x0D)
1781 #define MPI_FCPORTPAGE0_LTYPE_1300_LONG_WAVE (0x0E)
1782 #define MPI_FCPORTPAGE0_LTYPE_1500_LONG_WAVE (0x0F)
1784 #define MPI_FCPORTPAGE0_PORTSTATE_UNKNOWN (0x01) /*(SNIA)HBA_PORTSTATE_UNKNOWN 1 Unknown */
1785 #define MPI_FCPORTPAGE0_PORTSTATE_ONLINE (0x02) /*(SNIA)HBA_PORTSTATE_ONLINE 2 Operational */
1786 #define MPI_FCPORTPAGE0_PORTSTATE_OFFLINE (0x03) /*(SNIA)HBA_PORTSTATE_OFFLINE 3 User Offline */
1787 #define MPI_FCPORTPAGE0_PORTSTATE_BYPASSED (0x04) /*(SNIA)HBA_PORTSTATE_BYPASSED 4 Bypassed */
1788 #define MPI_FCPORTPAGE0_PORTSTATE_DIAGNOST (0x05) /*(SNIA)HBA_PORTSTATE_DIAGNOSTICS 5 In diagnostics mode */
1789 #define MPI_FCPORTPAGE0_PORTSTATE_LINKDOWN (0x06) /*(SNIA)HBA_PORTSTATE_LINKDOWN 6 Link Down */
1790 #define MPI_FCPORTPAGE0_PORTSTATE_ERROR (0x07) /*(SNIA)HBA_PORTSTATE_ERROR 7 Port Error */
1791 #define MPI_FCPORTPAGE0_PORTSTATE_LOOPBACK (0x08) /*(SNIA)HBA_PORTSTATE_LOOPBACK 8 Loopback */
1793 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_1 (0x00000001)
1794 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_2 (0x00000002)
1795 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_3 (0x00000004)
1797 #define MPI_FCPORTPAGE0_SUPPORT_SPEED_UKNOWN (0x00000000) /* (SNIA)HBA_PORTSPEED_UNKNOWN 0 Unknown - transceiver incapable of reporting */
1798 #define MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED (0x00000001) /* (SNIA)HBA_PORTSPEED_1GBIT 1 1 GBit/sec */
1799 #define MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED (0x00000002) /* (SNIA)HBA_PORTSPEED_2GBIT 2 2 GBit/sec */
1800 #define MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED (0x00000004) /* (SNIA)HBA_PORTSPEED_10GBIT 4 10 GBit/sec */
1801 #define MPI_FCPORTPAGE0_SUPPORT_4GBIT_SPEED (0x00000008) /* (SNIA)HBA_PORTSPEED_4GBIT 8 4 GBit/sec */
1803 #define MPI_FCPORTPAGE0_CURRENT_SPEED_UKNOWN MPI_FCPORTPAGE0_SUPPORT_SPEED_UKNOWN
1804 #define MPI_FCPORTPAGE0_CURRENT_SPEED_1GBIT MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED
1805 #define MPI_FCPORTPAGE0_CURRENT_SPEED_2GBIT MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED
1806 #define MPI_FCPORTPAGE0_CURRENT_SPEED_10GBIT MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED
1807 #define MPI_FCPORTPAGE0_CURRENT_SPEED_4GBIT MPI_FCPORTPAGE0_SUPPORT_4GBIT_SPEED
1808 #define MPI_FCPORTPAGE0_CURRENT_SPEED_NOT_NEGOTIATED (0x00008000) /* (SNIA)HBA_PORTSPEED_NOT_NEGOTIATED (1<<15) Speed not established */
1811 typedef struct _CONFIG_PAGE_FC_PORT_1
1813 CONFIG_PAGE_HEADER Header; /* 00h */
1814 U32 Flags; /* 04h */
1815 U64 NoSEEPROMWWNN; /* 08h */
1816 U64 NoSEEPROMWWPN; /* 10h */
1817 U8 HardALPA; /* 18h */
1818 U8 LinkConfig; /* 19h */
1819 U8 TopologyConfig; /* 1Ah */
1820 U8 AltConnector; /* 1Bh */
1821 U8 NumRequestedAliases; /* 1Ch */
1822 U8 RR_TOV; /* 1Dh */
1823 U8 InitiatorDeviceTimeout; /* 1Eh */
1824 U8 InitiatorIoPendTimeout; /* 1Fh */
1825 } CONFIG_PAGE_FC_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_1,
1826 FCPortPage1_t, MPI_POINTER pFCPortPage1_t;
1828 #define MPI_FCPORTPAGE1_PAGEVERSION (0x06)
1830 #define MPI_FCPORTPAGE1_FLAGS_EXT_FCP_STATUS_EN (0x08000000)
1831 #define MPI_FCPORTPAGE1_FLAGS_IMMEDIATE_ERROR_REPLY (0x04000000)
1832 #define MPI_FCPORTPAGE1_FLAGS_FORCE_USE_NOSEEPROM_WWNS (0x02000000)
1833 #define MPI_FCPORTPAGE1_FLAGS_VERBOSE_RESCAN_EVENTS (0x01000000)
1834 #define MPI_FCPORTPAGE1_FLAGS_TARGET_MODE_OXID (0x00800000)
1835 #define MPI_FCPORTPAGE1_FLAGS_PORT_OFFLINE (0x00400000)
1836 #define MPI_FCPORTPAGE1_FLAGS_SOFT_ALPA_FALLBACK (0x00200000)
1837 #define MPI_FCPORTPAGE1_FLAGS_TARGET_LARGE_CDB_ENABLE (0x00000080)
1838 #define MPI_FCPORTPAGE1_FLAGS_MASK_RR_TOV_UNITS (0x00000070)
1839 #define MPI_FCPORTPAGE1_FLAGS_SUPPRESS_PROT_REG (0x00000008)
1840 #define MPI_FCPORTPAGE1_FLAGS_PLOGI_ON_LOGO (0x00000004)
1841 #define MPI_FCPORTPAGE1_FLAGS_MAINTAIN_LOGINS (0x00000002)
1842 #define MPI_FCPORTPAGE1_FLAGS_SORT_BY_DID (0x00000001)
1843 #define MPI_FCPORTPAGE1_FLAGS_SORT_BY_WWN (0x00000000)
1845 #define MPI_FCPORTPAGE1_FLAGS_PROT_MASK (0xF0000000)
1846 #define MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT (28)
1847 #define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_INIT ((U32)MPI_PORTFACTS_PROTOCOL_INITIATOR << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
1848 #define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_TARG ((U32)MPI_PORTFACTS_PROTOCOL_TARGET << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
1849 #define MPI_FCPORTPAGE1_FLAGS_PROT_LAN ((U32)MPI_PORTFACTS_PROTOCOL_LAN << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
1850 #define MPI_FCPORTPAGE1_FLAGS_PROT_LOGBUSADDR ((U32)MPI_PORTFACTS_PROTOCOL_LOGBUSADDR << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
1852 #define MPI_FCPORTPAGE1_FLAGS_NONE_RR_TOV_UNITS (0x00000000)
1853 #define MPI_FCPORTPAGE1_FLAGS_THOUSANDTH_RR_TOV_UNITS (0x00000010)
1854 #define MPI_FCPORTPAGE1_FLAGS_TENTH_RR_TOV_UNITS (0x00000030)
1855 #define MPI_FCPORTPAGE1_FLAGS_TEN_RR_TOV_UNITS (0x00000050)
1857 #define MPI_FCPORTPAGE1_HARD_ALPA_NOT_USED (0xFF)
1859 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_MASK (0x0F)
1860 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_1GIG (0x00)
1861 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_2GIG (0x01)
1862 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_4GIG (0x02)
1863 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_10GIG (0x03)
1864 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_AUTO (0x0F)
1866 #define MPI_FCPORTPAGE1_TOPOLOGY_MASK (0x0F)
1867 #define MPI_FCPORTPAGE1_TOPOLOGY_NLPORT (0x01)
1868 #define MPI_FCPORTPAGE1_TOPOLOGY_NPORT (0x02)
1869 #define MPI_FCPORTPAGE1_TOPOLOGY_AUTO (0x0F)
1871 #define MPI_FCPORTPAGE1_ALT_CONN_UNKNOWN (0x00)
1873 #define MPI_FCPORTPAGE1_INITIATOR_DEV_TIMEOUT_MASK (0x7F)
1874 #define MPI_FCPORTPAGE1_INITIATOR_DEV_UNIT_16 (0x80)
1877 typedef struct _CONFIG_PAGE_FC_PORT_2
1879 CONFIG_PAGE_HEADER Header; /* 00h */
1880 U8 NumberActive; /* 04h */
1881 U8 ALPA[127]; /* 05h */
1882 } CONFIG_PAGE_FC_PORT_2, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_2,
1883 FCPortPage2_t, MPI_POINTER pFCPortPage2_t;
1885 #define MPI_FCPORTPAGE2_PAGEVERSION (0x01)
1888 typedef struct _WWN_FORMAT
1892 } WWN_FORMAT, MPI_POINTER PTR_WWN_FORMAT,
1893 WWNFormat, MPI_POINTER pWWNFormat;
1895 typedef union _FC_PORT_PERSISTENT_PHYSICAL_ID
1899 } FC_PORT_PERSISTENT_PHYSICAL_ID, MPI_POINTER PTR_FC_PORT_PERSISTENT_PHYSICAL_ID,
1900 PersistentPhysicalId_t, MPI_POINTER pPersistentPhysicalId_t;
1902 typedef struct _FC_PORT_PERSISTENT
1904 FC_PORT_PERSISTENT_PHYSICAL_ID PhysicalIdentifier; /* 00h */
1905 U8 TargetID; /* 10h */
1907 U16 Flags; /* 12h */
1908 } FC_PORT_PERSISTENT, MPI_POINTER PTR_FC_PORT_PERSISTENT,
1909 PersistentData_t, MPI_POINTER pPersistentData_t;
1911 #define MPI_PERSISTENT_FLAGS_SHIFT (16)
1912 #define MPI_PERSISTENT_FLAGS_ENTRY_VALID (0x0001)
1913 #define MPI_PERSISTENT_FLAGS_SCAN_ID (0x0002)
1914 #define MPI_PERSISTENT_FLAGS_SCAN_LUNS (0x0004)
1915 #define MPI_PERSISTENT_FLAGS_BOOT_DEVICE (0x0008)
1916 #define MPI_PERSISTENT_FLAGS_BY_DID (0x0080)
1919 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1920 * one and check Header.PageLength at runtime.
1922 #ifndef MPI_FC_PORT_PAGE_3_ENTRY_MAX
1923 #define MPI_FC_PORT_PAGE_3_ENTRY_MAX (1)
1926 typedef struct _CONFIG_PAGE_FC_PORT_3
1928 CONFIG_PAGE_HEADER Header; /* 00h */
1929 FC_PORT_PERSISTENT Entry[MPI_FC_PORT_PAGE_3_ENTRY_MAX]; /* 04h */
1930 } CONFIG_PAGE_FC_PORT_3, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_3,
1931 FCPortPage3_t, MPI_POINTER pFCPortPage3_t;
1933 #define MPI_FCPORTPAGE3_PAGEVERSION (0x01)
1936 typedef struct _CONFIG_PAGE_FC_PORT_4
1938 CONFIG_PAGE_HEADER Header; /* 00h */
1939 U32 PortFlags; /* 04h */
1940 U32 PortSettings; /* 08h */
1941 } CONFIG_PAGE_FC_PORT_4, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_4,
1942 FCPortPage4_t, MPI_POINTER pFCPortPage4_t;
1944 #define MPI_FCPORTPAGE4_PAGEVERSION (0x00)
1946 #define MPI_FCPORTPAGE4_PORT_FLAGS_ALTERNATE_CHS (0x00000008)
1948 #define MPI_FCPORTPAGE4_PORT_MASK_INIT_HBA (0x00000030)
1949 #define MPI_FCPORTPAGE4_PORT_DISABLE_INIT_HBA (0x00000000)
1950 #define MPI_FCPORTPAGE4_PORT_BIOS_INIT_HBA (0x00000010)
1951 #define MPI_FCPORTPAGE4_PORT_OS_INIT_HBA (0x00000020)
1952 #define MPI_FCPORTPAGE4_PORT_BIOS_OS_INIT_HBA (0x00000030)
1953 #define MPI_FCPORTPAGE4_PORT_REMOVABLE_MEDIA (0x000000C0)
1954 #define MPI_FCPORTPAGE4_PORT_SPINUP_DELAY_MASK (0x00000F00)
1957 typedef struct _CONFIG_PAGE_FC_PORT_5_ALIAS_INFO
1960 U8 AliasAlpa; /* 01h */
1961 U16 Reserved; /* 02h */
1962 U64 AliasWWNN; /* 04h */
1963 U64 AliasWWPN; /* 0Ch */
1964 } CONFIG_PAGE_FC_PORT_5_ALIAS_INFO,
1965 MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_5_ALIAS_INFO,
1966 FcPortPage5AliasInfo_t, MPI_POINTER pFcPortPage5AliasInfo_t;
1968 typedef struct _CONFIG_PAGE_FC_PORT_5
1970 CONFIG_PAGE_HEADER Header; /* 00h */
1971 CONFIG_PAGE_FC_PORT_5_ALIAS_INFO AliasInfo; /* 04h */
1972 } CONFIG_PAGE_FC_PORT_5, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_5,
1973 FCPortPage5_t, MPI_POINTER pFCPortPage5_t;
1975 #define MPI_FCPORTPAGE5_PAGEVERSION (0x02)
1977 #define MPI_FCPORTPAGE5_FLAGS_ALPA_ACQUIRED (0x01)
1978 #define MPI_FCPORTPAGE5_FLAGS_HARD_ALPA (0x02)
1979 #define MPI_FCPORTPAGE5_FLAGS_HARD_WWNN (0x04)
1980 #define MPI_FCPORTPAGE5_FLAGS_HARD_WWPN (0x08)
1981 #define MPI_FCPORTPAGE5_FLAGS_DISABLE (0x10)
1983 typedef struct _CONFIG_PAGE_FC_PORT_6
1985 CONFIG_PAGE_HEADER Header; /* 00h */
1986 U32 Reserved; /* 04h */
1987 U64 TimeSinceReset; /* 08h */
1988 U64 TxFrames; /* 10h */
1989 U64 RxFrames; /* 18h */
1990 U64 TxWords; /* 20h */
1991 U64 RxWords; /* 28h */
1992 U64 LipCount; /* 30h */
1993 U64 NosCount; /* 38h */
1994 U64 ErrorFrames; /* 40h */
1995 U64 DumpedFrames; /* 48h */
1996 U64 LinkFailureCount; /* 50h */
1997 U64 LossOfSyncCount; /* 58h */
1998 U64 LossOfSignalCount; /* 60h */
1999 U64 PrimativeSeqErrCount; /* 68h */
2000 U64 InvalidTxWordCount; /* 70h */
2001 U64 InvalidCrcCount; /* 78h */
2002 U64 FcpInitiatorIoCount; /* 80h */
2003 } CONFIG_PAGE_FC_PORT_6, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_6,
2004 FCPortPage6_t, MPI_POINTER pFCPortPage6_t;
2006 #define MPI_FCPORTPAGE6_PAGEVERSION (0x00)
2009 typedef struct _CONFIG_PAGE_FC_PORT_7
2011 CONFIG_PAGE_HEADER Header; /* 00h */
2012 U32 Reserved; /* 04h */
2013 U8 PortSymbolicName[256]; /* 08h */
2014 } CONFIG_PAGE_FC_PORT_7, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_7,
2015 FCPortPage7_t, MPI_POINTER pFCPortPage7_t;
2017 #define MPI_FCPORTPAGE7_PAGEVERSION (0x00)
2020 typedef struct _CONFIG_PAGE_FC_PORT_8
2022 CONFIG_PAGE_HEADER Header; /* 00h */
2023 U32 BitVector[8]; /* 04h */
2024 } CONFIG_PAGE_FC_PORT_8, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_8,
2025 FCPortPage8_t, MPI_POINTER pFCPortPage8_t;
2027 #define MPI_FCPORTPAGE8_PAGEVERSION (0x00)
2030 typedef struct _CONFIG_PAGE_FC_PORT_9
2032 CONFIG_PAGE_HEADER Header; /* 00h */
2033 U32 Reserved; /* 04h */
2034 U64 GlobalWWPN; /* 08h */
2035 U64 GlobalWWNN; /* 10h */
2036 U32 UnitType; /* 18h */
2037 U32 PhysicalPortNumber; /* 1Ch */
2038 U32 NumAttachedNodes; /* 20h */
2039 U16 IPVersion; /* 24h */
2040 U16 UDPPortNumber; /* 26h */
2041 U8 IPAddress[16]; /* 28h */
2042 U16 Reserved1; /* 38h */
2043 U16 TopologyDiscoveryFlags; /* 3Ah */
2044 } CONFIG_PAGE_FC_PORT_9, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_9,
2045 FCPortPage9_t, MPI_POINTER pFCPortPage9_t;
2047 #define MPI_FCPORTPAGE9_PAGEVERSION (0x00)
2050 typedef struct _CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA
2054 U8 Connector; /* 12h */
2055 U8 Transceiver[8]; /* 13h */
2056 U8 Encoding; /* 1Bh */
2057 U8 BitRate_100mbs; /* 1Ch */
2058 U8 Reserved1; /* 1Dh */
2059 U8 Length9u_km; /* 1Eh */
2060 U8 Length9u_100m; /* 1Fh */
2061 U8 Length50u_10m; /* 20h */
2062 U8 Length62p5u_10m; /* 21h */
2063 U8 LengthCopper_m; /* 22h */
2064 U8 Reseverved2; /* 22h */
2065 U8 VendorName[16]; /* 24h */
2066 U8 Reserved3; /* 34h */
2067 U8 VendorOUI[3]; /* 35h */
2068 U8 VendorPN[16]; /* 38h */
2069 U8 VendorRev[4]; /* 48h */
2070 U16 Wavelength; /* 4Ch */
2071 U8 Reserved4; /* 4Eh */
2072 U8 CC_BASE; /* 4Fh */
2073 } CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA,
2074 MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA,
2075 FCPortPage10BaseSfpData_t, MPI_POINTER pFCPortPage10BaseSfpData_t;
2077 #define MPI_FCPORT10_BASE_ID_UNKNOWN (0x00)
2078 #define MPI_FCPORT10_BASE_ID_GBIC (0x01)
2079 #define MPI_FCPORT10_BASE_ID_FIXED (0x02)
2080 #define MPI_FCPORT10_BASE_ID_SFP (0x03)
2081 #define MPI_FCPORT10_BASE_ID_SFP_MIN (0x04)
2082 #define MPI_FCPORT10_BASE_ID_SFP_MAX (0x7F)
2083 #define MPI_FCPORT10_BASE_ID_VEND_SPEC_MASK (0x80)
2085 #define MPI_FCPORT10_BASE_EXTID_UNKNOWN (0x00)
2086 #define MPI_FCPORT10_BASE_EXTID_MODDEF1 (0x01)
2087 #define MPI_FCPORT10_BASE_EXTID_MODDEF2 (0x02)
2088 #define MPI_FCPORT10_BASE_EXTID_MODDEF3 (0x03)
2089 #define MPI_FCPORT10_BASE_EXTID_SEEPROM (0x04)
2090 #define MPI_FCPORT10_BASE_EXTID_MODDEF5 (0x05)
2091 #define MPI_FCPORT10_BASE_EXTID_MODDEF6 (0x06)
2092 #define MPI_FCPORT10_BASE_EXTID_MODDEF7 (0x07)
2093 #define MPI_FCPORT10_BASE_EXTID_VNDSPC_MASK (0x80)
2095 #define MPI_FCPORT10_BASE_CONN_UNKNOWN (0x00)
2096 #define MPI_FCPORT10_BASE_CONN_SC (0x01)
2097 #define MPI_FCPORT10_BASE_CONN_COPPER1 (0x02)
2098 #define MPI_FCPORT10_BASE_CONN_COPPER2 (0x03)
2099 #define MPI_FCPORT10_BASE_CONN_BNC_TNC (0x04)
2100 #define MPI_FCPORT10_BASE_CONN_COAXIAL (0x05)
2101 #define MPI_FCPORT10_BASE_CONN_FIBERJACK (0x06)
2102 #define MPI_FCPORT10_BASE_CONN_LC (0x07)
2103 #define MPI_FCPORT10_BASE_CONN_MT_RJ (0x08)
2104 #define MPI_FCPORT10_BASE_CONN_MU (0x09)
2105 #define MPI_FCPORT10_BASE_CONN_SG (0x0A)
2106 #define MPI_FCPORT10_BASE_CONN_OPT_PIGT (0x0B)
2107 #define MPI_FCPORT10_BASE_CONN_RSV1_MIN (0x0C)
2108 #define MPI_FCPORT10_BASE_CONN_RSV1_MAX (0x1F)
2109 #define MPI_FCPORT10_BASE_CONN_HSSDC_II (0x20)
2110 #define MPI_FCPORT10_BASE_CONN_CPR_PIGT (0x21)
2111 #define MPI_FCPORT10_BASE_CONN_RSV2_MIN (0x22)
2112 #define MPI_FCPORT10_BASE_CONN_RSV2_MAX (0x7F)
2113 #define MPI_FCPORT10_BASE_CONN_VNDSPC_MASK (0x80)
2115 #define MPI_FCPORT10_BASE_ENCODE_UNSPEC (0x00)
2116 #define MPI_FCPORT10_BASE_ENCODE_8B10B (0x01)
2117 #define MPI_FCPORT10_BASE_ENCODE_4B5B (0x02)
2118 #define MPI_FCPORT10_BASE_ENCODE_NRZ (0x03)
2119 #define MPI_FCPORT10_BASE_ENCODE_MANCHESTER (0x04)
2122 typedef struct _CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA
2124 U8 Options[2]; /* 50h */
2125 U8 BitRateMax; /* 52h */
2126 U8 BitRateMin; /* 53h */
2127 U8 VendorSN[16]; /* 54h */
2128 U8 DateCode[8]; /* 64h */
2129 U8 DiagMonitoringType; /* 6Ch */
2130 U8 EnhancedOptions; /* 6Dh */
2131 U8 SFF8472Compliance; /* 6Eh */
2132 U8 CC_EXT; /* 6Fh */
2133 } CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA,
2134 MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA,
2135 FCPortPage10ExtendedSfpData_t, MPI_POINTER pFCPortPage10ExtendedSfpData_t;
2137 #define MPI_FCPORT10_EXT_OPTION1_RATESEL (0x20)
2138 #define MPI_FCPORT10_EXT_OPTION1_TX_DISABLE (0x10)
2139 #define MPI_FCPORT10_EXT_OPTION1_TX_FAULT (0x08)
2140 #define MPI_FCPORT10_EXT_OPTION1_LOS_INVERT (0x04)
2141 #define MPI_FCPORT10_EXT_OPTION1_LOS (0x02)
2144 typedef struct _CONFIG_PAGE_FC_PORT_10
2146 CONFIG_PAGE_HEADER Header; /* 00h */
2148 U8 Reserved1; /* 05h */
2149 U16 Reserved2; /* 06h */
2150 U32 HwConfig1; /* 08h */
2151 U32 HwConfig2; /* 0Ch */
2152 CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA Base; /* 10h */
2153 CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA Extended; /* 50h */
2154 U8 VendorSpecific[32]; /* 70h */
2155 } CONFIG_PAGE_FC_PORT_10, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10,
2156 FCPortPage10_t, MPI_POINTER pFCPortPage10_t;
2158 #define MPI_FCPORTPAGE10_PAGEVERSION (0x01)
2160 /* standard MODDEF pin definitions (from GBIC spec.) */
2161 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_MASK (0x00000007)
2162 #define MPI_FCPORTPAGE10_FLAGS_MODDEF2 (0x00000001)
2163 #define MPI_FCPORTPAGE10_FLAGS_MODDEF1 (0x00000002)
2164 #define MPI_FCPORTPAGE10_FLAGS_MODDEF0 (0x00000004)
2165 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_NOGBIC (0x00000007)
2166 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_CPR_IEEE_CX (0x00000006)
2167 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_COPPER (0x00000005)
2168 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_OPTICAL_LW (0x00000004)
2169 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_SEEPROM (0x00000003)
2170 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_SW_OPTICAL (0x00000002)
2171 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_LX_IEEE_OPT_LW (0x00000001)
2172 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_SX_IEEE_OPT_SW (0x00000000)
2174 #define MPI_FCPORTPAGE10_FLAGS_CC_BASE_OK (0x00000010)
2175 #define MPI_FCPORTPAGE10_FLAGS_CC_EXT_OK (0x00000020)
2178 /****************************************************************************
2179 * FC Device Config Pages
2180 ****************************************************************************/
2182 typedef struct _CONFIG_PAGE_FC_DEVICE_0
2184 CONFIG_PAGE_HEADER Header; /* 00h */
2187 U32 PortIdentifier; /* 14h */
2188 U8 Protocol; /* 18h */
2190 U16 BBCredit; /* 1Ah */
2191 U16 MaxRxFrameSize; /* 1Ch */
2192 U8 ADISCHardALPA; /* 1Eh */
2193 U8 PortNumber; /* 1Fh */
2194 U8 FcPhLowestVersion; /* 20h */
2195 U8 FcPhHighestVersion; /* 21h */
2196 U8 CurrentTargetID; /* 22h */
2197 U8 CurrentBus; /* 23h */
2198 } CONFIG_PAGE_FC_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_FC_DEVICE_0,
2199 FCDevicePage0_t, MPI_POINTER pFCDevicePage0_t;
2201 #define MPI_FC_DEVICE_PAGE0_PAGEVERSION (0x03)
2203 #define MPI_FC_DEVICE_PAGE0_FLAGS_TARGETID_BUS_VALID (0x01)
2204 #define MPI_FC_DEVICE_PAGE0_FLAGS_PLOGI_INVALID (0x02)
2205 #define MPI_FC_DEVICE_PAGE0_FLAGS_PRLI_INVALID (0x04)
2207 #define MPI_FC_DEVICE_PAGE0_PROT_IP (0x01)
2208 #define MPI_FC_DEVICE_PAGE0_PROT_FCP_TARGET (0x02)
2209 #define MPI_FC_DEVICE_PAGE0_PROT_FCP_INITIATOR (0x04)
2210 #define MPI_FC_DEVICE_PAGE0_PROT_FCP_RETRY (0x08)
2212 #define MPI_FC_DEVICE_PAGE0_PGAD_PORT_MASK (MPI_FC_DEVICE_PGAD_PORT_MASK)
2213 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_MASK (MPI_FC_DEVICE_PGAD_FORM_MASK)
2214 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_NEXT_DID (MPI_FC_DEVICE_PGAD_FORM_NEXT_DID)
2215 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_BUS_TID (MPI_FC_DEVICE_PGAD_FORM_BUS_TID)
2216 #define MPI_FC_DEVICE_PAGE0_PGAD_DID_MASK (MPI_FC_DEVICE_PGAD_ND_DID_MASK)
2217 #define MPI_FC_DEVICE_PAGE0_PGAD_BUS_MASK (MPI_FC_DEVICE_PGAD_BT_BUS_MASK)
2218 #define MPI_FC_DEVICE_PAGE0_PGAD_BUS_SHIFT (MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT)
2219 #define MPI_FC_DEVICE_PAGE0_PGAD_TID_MASK (MPI_FC_DEVICE_PGAD_BT_TID_MASK)
2221 #define MPI_FC_DEVICE_PAGE0_HARD_ALPA_UNKNOWN (0xFF)
2223 /****************************************************************************
2224 * RAID Volume Config Pages
2225 ****************************************************************************/
2227 typedef struct _RAID_VOL0_PHYS_DISK
2229 U16 Reserved; /* 00h */
2230 U8 PhysDiskMap; /* 02h */
2231 U8 PhysDiskNum; /* 03h */
2232 } RAID_VOL0_PHYS_DISK, MPI_POINTER PTR_RAID_VOL0_PHYS_DISK,
2233 RaidVol0PhysDisk_t, MPI_POINTER pRaidVol0PhysDisk_t;
2235 #define MPI_RAIDVOL0_PHYSDISK_PRIMARY (0x01)
2236 #define MPI_RAIDVOL0_PHYSDISK_SECONDARY (0x02)
2238 typedef struct _RAID_VOL0_STATUS
2242 U16 Reserved; /* 02h */
2243 } RAID_VOL0_STATUS, MPI_POINTER PTR_RAID_VOL0_STATUS,
2244 RaidVol0Status_t, MPI_POINTER pRaidVol0Status_t;
2246 /* RAID Volume Page 0 VolumeStatus defines */
2247 #define MPI_RAIDVOL0_STATUS_FLAG_ENABLED (0x01)
2248 #define MPI_RAIDVOL0_STATUS_FLAG_QUIESCED (0x02)
2249 #define MPI_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x04)
2250 #define MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x08)
2251 #define MPI_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x10)
2253 #define MPI_RAIDVOL0_STATUS_STATE_OPTIMAL (0x00)
2254 #define MPI_RAIDVOL0_STATUS_STATE_DEGRADED (0x01)
2255 #define MPI_RAIDVOL0_STATUS_STATE_FAILED (0x02)
2256 #define MPI_RAIDVOL0_STATUS_STATE_MISSING (0x03)
2258 typedef struct _RAID_VOL0_SETTINGS
2260 U16 Settings; /* 00h */
2261 U8 HotSparePool; /* 01h */ /* MPI_RAID_HOT_SPARE_POOL_ */
2262 U8 Reserved; /* 02h */
2263 } RAID_VOL0_SETTINGS, MPI_POINTER PTR_RAID_VOL0_SETTINGS,
2264 RaidVol0Settings, MPI_POINTER pRaidVol0Settings;
2266 /* RAID Volume Page 0 VolumeSettings defines */
2267 #define MPI_RAIDVOL0_SETTING_WRITE_CACHING_ENABLE (0x0001)
2268 #define MPI_RAIDVOL0_SETTING_OFFLINE_ON_SMART (0x0002)
2269 #define MPI_RAIDVOL0_SETTING_AUTO_CONFIGURE (0x0004)
2270 #define MPI_RAIDVOL0_SETTING_PRIORITY_RESYNC (0x0008)
2271 #define MPI_RAIDVOL0_SETTING_FAST_DATA_SCRUBBING_0102 (0x0020) /* obsolete */
2273 #define MPI_RAIDVOL0_SETTING_MASK_METADATA_SIZE (0x00C0)
2274 #define MPI_RAIDVOL0_SETTING_64MB_METADATA_SIZE (0x0000)
2275 #define MPI_RAIDVOL0_SETTING_512MB_METADATA_SIZE (0x0040)
2277 #define MPI_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0010)
2278 #define MPI_RAIDVOL0_SETTING_USE_DEFAULTS (0x8000)
2280 /* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */
2281 #define MPI_RAID_HOT_SPARE_POOL_0 (0x01)
2282 #define MPI_RAID_HOT_SPARE_POOL_1 (0x02)
2283 #define MPI_RAID_HOT_SPARE_POOL_2 (0x04)
2284 #define MPI_RAID_HOT_SPARE_POOL_3 (0x08)
2285 #define MPI_RAID_HOT_SPARE_POOL_4 (0x10)
2286 #define MPI_RAID_HOT_SPARE_POOL_5 (0x20)
2287 #define MPI_RAID_HOT_SPARE_POOL_6 (0x40)
2288 #define MPI_RAID_HOT_SPARE_POOL_7 (0x80)
2291 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2292 * one and check Header.PageLength at runtime.
2294 #ifndef MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX
2295 #define MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX (1)
2298 typedef struct _CONFIG_PAGE_RAID_VOL_0
2300 CONFIG_PAGE_HEADER Header; /* 00h */
2301 U8 VolumeID; /* 04h */
2302 U8 VolumeBus; /* 05h */
2303 U8 VolumeIOC; /* 06h */
2304 U8 VolumeType; /* 07h */ /* MPI_RAID_VOL_TYPE_ */
2305 RAID_VOL0_STATUS VolumeStatus; /* 08h */
2306 RAID_VOL0_SETTINGS VolumeSettings; /* 0Ch */
2307 U32 MaxLBA; /* 10h */
2308 U32 MaxLBAHigh; /* 14h */
2309 U32 StripeSize; /* 18h */
2310 U32 Reserved2; /* 1Ch */
2311 U32 Reserved3; /* 20h */
2312 U8 NumPhysDisks; /* 24h */
2313 U8 DataScrubRate; /* 25h */
2314 U8 ResyncRate; /* 26h */
2315 U8 InactiveStatus; /* 27h */
2316 RAID_VOL0_PHYS_DISK PhysDisk[MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX];/* 28h */
2317 } CONFIG_PAGE_RAID_VOL_0, MPI_POINTER PTR_CONFIG_PAGE_RAID_VOL_0,
2318 RaidVolumePage0_t, MPI_POINTER pRaidVolumePage0_t;
2320 #define MPI_RAIDVOLPAGE0_PAGEVERSION (0x07)
2322 /* values for RAID Volume Page 0 InactiveStatus field */
2323 #define MPI_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00)
2324 #define MPI_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01)
2325 #define MPI_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02)
2326 #define MPI_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03)
2327 #define MPI_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04)
2328 #define MPI_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05)
2329 #define MPI_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06)
2332 typedef struct _CONFIG_PAGE_RAID_VOL_1
2334 CONFIG_PAGE_HEADER Header; /* 00h */
2335 U8 VolumeID; /* 04h */
2336 U8 VolumeBus; /* 05h */
2337 U8 VolumeIOC; /* 06h */
2338 U8 Reserved0; /* 07h */
2339 U8 GUID[24]; /* 08h */
2340 U8 Name[32]; /* 20h */
2342 U32 Reserved1; /* 48h */
2343 U32 Reserved2; /* 4Ch */
2344 } CONFIG_PAGE_RAID_VOL_1, MPI_POINTER PTR_CONFIG_PAGE_RAID_VOL_1,
2345 RaidVolumePage1_t, MPI_POINTER pRaidVolumePage1_t;
2347 #define MPI_RAIDVOLPAGE1_PAGEVERSION (0x01)
2350 /****************************************************************************
2351 * RAID Physical Disk Config Pages
2352 ****************************************************************************/
2354 typedef struct _RAID_PHYS_DISK0_ERROR_DATA
2356 U8 ErrorCdbByte; /* 00h */
2357 U8 ErrorSenseKey; /* 01h */
2358 U16 Reserved; /* 02h */
2359 U16 ErrorCount; /* 04h */
2360 U8 ErrorASC; /* 06h */
2361 U8 ErrorASCQ; /* 07h */
2362 U16 SmartCount; /* 08h */
2363 U8 SmartASC; /* 0Ah */
2364 U8 SmartASCQ; /* 0Bh */
2365 } RAID_PHYS_DISK0_ERROR_DATA, MPI_POINTER PTR_RAID_PHYS_DISK0_ERROR_DATA,
2366 RaidPhysDisk0ErrorData_t, MPI_POINTER pRaidPhysDisk0ErrorData_t;
2368 typedef struct _RAID_PHYS_DISK_INQUIRY_DATA
2370 U8 VendorID[8]; /* 00h */
2371 U8 ProductID[16]; /* 08h */
2372 U8 ProductRevLevel[4]; /* 18h */
2373 U8 Info[32]; /* 1Ch */
2374 } RAID_PHYS_DISK0_INQUIRY_DATA, MPI_POINTER PTR_RAID_PHYS_DISK0_INQUIRY_DATA,
2375 RaidPhysDisk0InquiryData, MPI_POINTER pRaidPhysDisk0InquiryData;
2377 typedef struct _RAID_PHYS_DISK0_SETTINGS
2380 U8 SepBus; /* 01h */
2381 U8 HotSparePool; /* 02h */ /* MPI_RAID_HOT_SPARE_POOL_ */
2382 U8 PhysDiskSettings; /* 03h */
2383 } RAID_PHYS_DISK0_SETTINGS, MPI_POINTER PTR_RAID_PHYS_DISK0_SETTINGS,
2384 RaidPhysDiskSettings_t, MPI_POINTER pRaidPhysDiskSettings_t;
2386 typedef struct _RAID_PHYS_DISK0_STATUS
2390 U16 Reserved; /* 02h */
2391 } RAID_PHYS_DISK0_STATUS, MPI_POINTER PTR_RAID_PHYS_DISK0_STATUS,
2392 RaidPhysDiskStatus_t, MPI_POINTER pRaidPhysDiskStatus_t;
2394 /* RAID Physical Disk PhysDiskStatus flags */
2396 #define MPI_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x01)
2397 #define MPI_PHYSDISK0_STATUS_FLAG_QUIESCED (0x02)
2398 #define MPI_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x04)
2399 #define MPI_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00)
2400 #define MPI_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x08)
2402 #define MPI_PHYSDISK0_STATUS_ONLINE (0x00)
2403 #define MPI_PHYSDISK0_STATUS_MISSING (0x01)
2404 #define MPI_PHYSDISK0_STATUS_NOT_COMPATIBLE (0x02)
2405 #define MPI_PHYSDISK0_STATUS_FAILED (0x03)
2406 #define MPI_PHYSDISK0_STATUS_INITIALIZING (0x04)
2407 #define MPI_PHYSDISK0_STATUS_OFFLINE_REQUESTED (0x05)
2408 #define MPI_PHYSDISK0_STATUS_FAILED_REQUESTED (0x06)
2409 #define MPI_PHYSDISK0_STATUS_OTHER_OFFLINE (0xFF)
2411 typedef struct _CONFIG_PAGE_RAID_PHYS_DISK_0
2413 CONFIG_PAGE_HEADER Header; /* 00h */
2414 U8 PhysDiskID; /* 04h */
2415 U8 PhysDiskBus; /* 05h */
2416 U8 PhysDiskIOC; /* 06h */
2417 U8 PhysDiskNum; /* 07h */
2418 RAID_PHYS_DISK0_SETTINGS PhysDiskSettings; /* 08h */
2419 U32 Reserved1; /* 0Ch */
2420 U8 ExtDiskIdentifier[8]; /* 10h */
2421 U8 DiskIdentifier[16]; /* 18h */
2422 RAID_PHYS_DISK0_INQUIRY_DATA InquiryData; /* 28h */
2423 RAID_PHYS_DISK0_STATUS PhysDiskStatus; /* 64h */
2424 U32 MaxLBA; /* 68h */
2425 RAID_PHYS_DISK0_ERROR_DATA ErrorData; /* 6Ch */
2426 } CONFIG_PAGE_RAID_PHYS_DISK_0, MPI_POINTER PTR_CONFIG_PAGE_RAID_PHYS_DISK_0,
2427 RaidPhysDiskPage0_t, MPI_POINTER pRaidPhysDiskPage0_t;
2429 #define MPI_RAIDPHYSDISKPAGE0_PAGEVERSION (0x02)
2432 typedef struct _RAID_PHYS_DISK1_PATH
2434 U8 PhysDiskID; /* 00h */
2435 U8 PhysDiskBus; /* 01h */
2436 U16 Reserved1; /* 02h */
2438 U64 OwnerWWID; /* 0Ch */
2439 U8 OwnerIdentifier; /* 14h */
2440 U8 Reserved2; /* 15h */
2441 U16 Flags; /* 16h */
2442 } RAID_PHYS_DISK1_PATH, MPI_POINTER PTR_RAID_PHYS_DISK1_PATH,
2443 RaidPhysDisk1Path_t, MPI_POINTER pRaidPhysDisk1Path_t;
2445 /* RAID Physical Disk Page 1 Flags field defines */
2446 #define MPI_RAID_PHYSDISK1_FLAG_BROKEN (0x0002)
2447 #define MPI_RAID_PHYSDISK1_FLAG_INVALID (0x0001)
2449 typedef struct _CONFIG_PAGE_RAID_PHYS_DISK_1
2451 CONFIG_PAGE_HEADER Header; /* 00h */
2452 U8 NumPhysDiskPaths; /* 04h */
2453 U8 PhysDiskNum; /* 05h */
2454 U16 Reserved2; /* 06h */
2455 U32 Reserved1; /* 08h */
2456 RAID_PHYS_DISK1_PATH Path[1]; /* 0Ch */
2457 } CONFIG_PAGE_RAID_PHYS_DISK_1, MPI_POINTER PTR_CONFIG_PAGE_RAID_PHYS_DISK_1,
2458 RaidPhysDiskPage1_t, MPI_POINTER pRaidPhysDiskPage1_t;
2460 #define MPI_RAIDPHYSDISKPAGE1_PAGEVERSION (0x00)
2463 /****************************************************************************
2465 ****************************************************************************/
2467 typedef struct _CONFIG_PAGE_LAN_0
2469 ConfigPageHeader_t Header; /* 00h */
2470 U16 TxRxModes; /* 04h */
2471 U16 Reserved; /* 06h */
2472 U32 PacketPrePad; /* 08h */
2473 } CONFIG_PAGE_LAN_0, MPI_POINTER PTR_CONFIG_PAGE_LAN_0,
2474 LANPage0_t, MPI_POINTER pLANPage0_t;
2476 #define MPI_LAN_PAGE0_PAGEVERSION (0x01)
2478 #define MPI_LAN_PAGE0_RETURN_LOOPBACK (0x0000)
2479 #define MPI_LAN_PAGE0_SUPPRESS_LOOPBACK (0x0001)
2480 #define MPI_LAN_PAGE0_LOOPBACK_MASK (0x0001)
2482 typedef struct _CONFIG_PAGE_LAN_1
2484 ConfigPageHeader_t Header; /* 00h */
2485 U16 Reserved; /* 04h */
2486 U8 CurrentDeviceState; /* 06h */
2487 U8 Reserved1; /* 07h */
2488 U32 MinPacketSize; /* 08h */
2489 U32 MaxPacketSize; /* 0Ch */
2490 U32 HardwareAddressLow; /* 10h */
2491 U32 HardwareAddressHigh; /* 14h */
2492 U32 MaxWireSpeedLow; /* 18h */
2493 U32 MaxWireSpeedHigh; /* 1Ch */
2494 U32 BucketsRemaining; /* 20h */
2495 U32 MaxReplySize; /* 24h */
2496 U32 NegWireSpeedLow; /* 28h */
2497 U32 NegWireSpeedHigh; /* 2Ch */
2498 } CONFIG_PAGE_LAN_1, MPI_POINTER PTR_CONFIG_PAGE_LAN_1,
2499 LANPage1_t, MPI_POINTER pLANPage1_t;
2501 #define MPI_LAN_PAGE1_PAGEVERSION (0x03)
2503 #define MPI_LAN_PAGE1_DEV_STATE_RESET (0x00)
2504 #define MPI_LAN_PAGE1_DEV_STATE_OPERATIONAL (0x01)
2507 /****************************************************************************
2508 * Inband Config Pages
2509 ****************************************************************************/
2511 typedef struct _CONFIG_PAGE_INBAND_0
2513 CONFIG_PAGE_HEADER Header; /* 00h */
2514 MPI_VERSION_FORMAT InbandVersion; /* 04h */
2515 U16 MaximumBuffers; /* 08h */
2516 U16 Reserved1; /* 0Ah */
2517 } CONFIG_PAGE_INBAND_0, MPI_POINTER PTR_CONFIG_PAGE_INBAND_0,
2518 InbandPage0_t, MPI_POINTER pInbandPage0_t;
2520 #define MPI_INBAND_PAGEVERSION (0x00)
2524 /****************************************************************************
2525 * SAS IO Unit Config Pages
2526 ****************************************************************************/
2528 typedef struct _MPI_SAS_IO_UNIT0_PHY_DATA
2531 U8 PortFlags; /* 01h */
2532 U8 PhyFlags; /* 02h */
2533 U8 NegotiatedLinkRate; /* 03h */
2534 U32 ControllerPhyDeviceInfo;/* 04h */
2535 U16 AttachedDeviceHandle; /* 08h */
2536 U16 ControllerDevHandle; /* 0Ah */
2537 U32 DiscoveryStatus; /* 0Ch */
2538 } MPI_SAS_IO_UNIT0_PHY_DATA, MPI_POINTER PTR_MPI_SAS_IO_UNIT0_PHY_DATA,
2539 SasIOUnit0PhyData, MPI_POINTER pSasIOUnit0PhyData;
2542 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2543 * one and check Header.PageLength at runtime.
2545 #ifndef MPI_SAS_IOUNIT0_PHY_MAX
2546 #define MPI_SAS_IOUNIT0_PHY_MAX (1)
2549 typedef struct _CONFIG_PAGE_SAS_IO_UNIT_0
2551 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2552 U16 NvdataVersionDefault; /* 08h */
2553 U16 NvdataVersionPersistent; /* 0Ah */
2554 U8 NumPhys; /* 0Ch */
2555 U8 Reserved2; /* 0Dh */
2556 U16 Reserved3; /* 0Eh */
2557 MPI_SAS_IO_UNIT0_PHY_DATA PhyData[MPI_SAS_IOUNIT0_PHY_MAX]; /* 10h */
2558 } CONFIG_PAGE_SAS_IO_UNIT_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_0,
2559 SasIOUnitPage0_t, MPI_POINTER pSasIOUnitPage0_t;
2561 #define MPI_SASIOUNITPAGE0_PAGEVERSION (0x04)
2563 /* values for SAS IO Unit Page 0 PortFlags */
2564 #define MPI_SAS_IOUNIT0_PORT_FLAGS_DISCOVERY_IN_PROGRESS (0x08)
2565 #define MPI_SAS_IOUNIT0_PORT_FLAGS_0_TARGET_IOC_NUM (0x00)
2566 #define MPI_SAS_IOUNIT0_PORT_FLAGS_1_TARGET_IOC_NUM (0x04)
2567 #define MPI_SAS_IOUNIT0_PORT_FLAGS_AUTO_PORT_CONFIG (0x01)
2569 /* values for SAS IO Unit Page 0 PhyFlags */
2570 #define MPI_SAS_IOUNIT0_PHY_FLAGS_PHY_DISABLED (0x04)
2571 #define MPI_SAS_IOUNIT0_PHY_FLAGS_TX_INVERT (0x02)
2572 #define MPI_SAS_IOUNIT0_PHY_FLAGS_RX_INVERT (0x01)
2574 /* values for SAS IO Unit Page 0 NegotiatedLinkRate */
2575 #define MPI_SAS_IOUNIT0_RATE_UNKNOWN (0x00)
2576 #define MPI_SAS_IOUNIT0_RATE_PHY_DISABLED (0x01)
2577 #define MPI_SAS_IOUNIT0_RATE_FAILED_SPEED_NEGOTIATION (0x02)
2578 #define MPI_SAS_IOUNIT0_RATE_SATA_OOB_COMPLETE (0x03)
2579 #define MPI_SAS_IOUNIT0_RATE_1_5 (0x08)
2580 #define MPI_SAS_IOUNIT0_RATE_3_0 (0x09)
2582 /* see mpi_sas.h for values for SAS IO Unit Page 0 ControllerPhyDeviceInfo values */
2584 /* values for SAS IO Unit Page 0 DiscoveryStatus */
2585 #define MPI_SAS_IOUNIT0_DS_LOOP_DETECTED (0x00000001)
2586 #define MPI_SAS_IOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002)
2587 #define MPI_SAS_IOUNIT0_DS_MULTIPLE_PORTS (0x00000004)
2588 #define MPI_SAS_IOUNIT0_DS_EXPANDER_ERR (0x00000008)
2589 #define MPI_SAS_IOUNIT0_DS_SMP_TIMEOUT (0x00000010)
2590 #define MPI_SAS_IOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020)
2591 #define MPI_SAS_IOUNIT0_DS_INDEX_NOT_EXIST (0x00000040)
2592 #define MPI_SAS_IOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080)
2593 #define MPI_SAS_IOUNIT0_DS_SMP_CRC_ERROR (0x00000100)
2594 #define MPI_SAS_IOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200)
2595 #define MPI_SAS_IOUNIT0_DS_TABLE_LINK (0x00000400)
2596 #define MPI_SAS_IOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800)
2597 #define MPI_SAS_IOUNIT0_DS_MAX_SATA_TARGETS (0x00001000)
2598 #define MPI_SAS_IOUNIT0_DS_MULTI_PORT_DOMAIN (0x00002000)
2601 typedef struct _MPI_SAS_IO_UNIT1_PHY_DATA
2604 U8 PortFlags; /* 01h */
2605 U8 PhyFlags; /* 02h */
2606 U8 MaxMinLinkRate; /* 03h */
2607 U32 ControllerPhyDeviceInfo; /* 04h */
2608 U16 MaxTargetPortConnectTime; /* 08h */
2609 U16 Reserved1; /* 0Ah */
2610 } MPI_SAS_IO_UNIT1_PHY_DATA, MPI_POINTER PTR_MPI_SAS_IO_UNIT1_PHY_DATA,
2611 SasIOUnit1PhyData, MPI_POINTER pSasIOUnit1PhyData;
2614 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2615 * one and check Header.PageLength at runtime.
2617 #ifndef MPI_SAS_IOUNIT1_PHY_MAX
2618 #define MPI_SAS_IOUNIT1_PHY_MAX (1)
2621 typedef struct _CONFIG_PAGE_SAS_IO_UNIT_1
2623 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2624 U16 ControlFlags; /* 08h */
2625 U16 MaxNumSATATargets; /* 0Ah */
2626 U16 AdditionalControlFlags; /* 0Ch */
2627 U16 Reserved1; /* 0Eh */
2628 U8 NumPhys; /* 10h */
2629 U8 SATAMaxQDepth; /* 11h */
2630 U8 ReportDeviceMissingDelay; /* 12h */
2631 U8 IODeviceMissingDelay; /* 13h */
2632 MPI_SAS_IO_UNIT1_PHY_DATA PhyData[MPI_SAS_IOUNIT1_PHY_MAX]; /* 14h */
2633 } CONFIG_PAGE_SAS_IO_UNIT_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_1,
2634 SasIOUnitPage1_t, MPI_POINTER pSasIOUnitPage1_t;
2636 #define MPI_SASIOUNITPAGE1_PAGEVERSION (0x07)
2638 /* values for SAS IO Unit Page 1 ControlFlags */
2639 #define MPI_SAS_IOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000)
2640 #define MPI_SAS_IOUNIT1_CONTROL_SATA_3_0_MAX (0x4000)
2641 #define MPI_SAS_IOUNIT1_CONTROL_SATA_1_5_MAX (0x2000)
2642 #define MPI_SAS_IOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000)
2643 #define MPI_SAS_IOUNIT1_CONTROL_DISABLE_SAS_HASH (0x0800)
2645 #define MPI_SAS_IOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600)
2646 #define MPI_SAS_IOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9)
2647 #define MPI_SAS_IOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x00)
2648 #define MPI_SAS_IOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x01)
2649 #define MPI_SAS_IOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x02)
2651 #define MPI_SAS_IOUNIT1_CONTROL_POSTPONE_SATA_INIT (0x0100)
2652 #define MPI_SAS_IOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080)
2653 #define MPI_SAS_IOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040)
2654 #define MPI_SAS_IOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020)
2655 #define MPI_SAS_IOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010)
2656 #define MPI_SAS_IOUNIT1_CONTROL_PHY_ENABLE_ORDER_HIGH (0x0008)
2657 #define MPI_SAS_IOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004)
2658 #define MPI_SAS_IOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002)
2659 #define MPI_SAS_IOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001)
2661 /* values for SAS IO Unit Page 1 AdditionalControlFlags */
2662 #define MPI_SAS_IOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080)
2663 #define MPI_SAS_IOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040)
2664 #define MPI_SAS_IOUNIT1_ACONTROL_HIDE_NONZERO_ATTACHED_PHY_IDENT (0x0020)
2665 #define MPI_SAS_IOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010)
2666 #define MPI_SAS_IOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008)
2667 #define MPI_SAS_IOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004)
2668 #define MPI_SAS_IOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002)
2669 #define MPI_SAS_IOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001)
2671 /* defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */
2672 #define MPI_SAS_IOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F)
2673 #define MPI_SAS_IOUNIT1_REPORT_MISSING_UNIT_16 (0x80)
2675 /* values for SAS IO Unit Page 1 PortFlags */
2676 #define MPI_SAS_IOUNIT1_PORT_FLAGS_0_TARGET_IOC_NUM (0x00)
2677 #define MPI_SAS_IOUNIT1_PORT_FLAGS_1_TARGET_IOC_NUM (0x04)
2678 #define MPI_SAS_IOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01)
2680 /* values for SAS IO Unit Page 0 PhyFlags */
2681 #define MPI_SAS_IOUNIT1_PHY_FLAGS_PHY_DISABLE (0x04)
2682 #define MPI_SAS_IOUNIT1_PHY_FLAGS_TX_INVERT (0x02)
2683 #define MPI_SAS_IOUNIT1_PHY_FLAGS_RX_INVERT (0x01)
2685 /* values for SAS IO Unit Page 0 MaxMinLinkRate */
2686 #define MPI_SAS_IOUNIT1_MAX_RATE_MASK (0xF0)
2687 #define MPI_SAS_IOUNIT1_MAX_RATE_1_5 (0x80)
2688 #define MPI_SAS_IOUNIT1_MAX_RATE_3_0 (0x90)
2689 #define MPI_SAS_IOUNIT1_MIN_RATE_MASK (0x0F)
2690 #define MPI_SAS_IOUNIT1_MIN_RATE_1_5 (0x08)
2691 #define MPI_SAS_IOUNIT1_MIN_RATE_3_0 (0x09)
2693 /* see mpi_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */
2696 typedef struct _CONFIG_PAGE_SAS_IO_UNIT_2
2698 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2699 U8 NumDevsPerEnclosure; /* 08h */
2700 U8 Reserved1; /* 09h */
2701 U16 Reserved2; /* 0Ah */
2702 U16 MaxPersistentIDs; /* 0Ch */
2703 U16 NumPersistentIDsUsed; /* 0Eh */
2704 U8 Status; /* 10h */
2706 U16 MaxNumPhysicalMappedIDs;/* 12h */
2707 } CONFIG_PAGE_SAS_IO_UNIT_2, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_2,
2708 SasIOUnitPage2_t, MPI_POINTER pSasIOUnitPage2_t;
2710 #define MPI_SASIOUNITPAGE2_PAGEVERSION (0x06)
2712 /* values for SAS IO Unit Page 2 Status field */
2713 #define MPI_SAS_IOUNIT2_STATUS_DEVICE_LIMIT_EXCEEDED (0x08)
2714 #define MPI_SAS_IOUNIT2_STATUS_ENCLOSURE_DEVICES_UNMAPPED (0x04)
2715 #define MPI_SAS_IOUNIT2_STATUS_DISABLED_PERSISTENT_MAPPINGS (0x02)
2716 #define MPI_SAS_IOUNIT2_STATUS_FULL_PERSISTENT_MAPPINGS (0x01)
2718 /* values for SAS IO Unit Page 2 Flags field */
2719 #define MPI_SAS_IOUNIT2_FLAGS_DISABLE_PERSISTENT_MAPPINGS (0x01)
2720 /* Physical Mapping Modes */
2721 #define MPI_SAS_IOUNIT2_FLAGS_MASK_PHYS_MAP_MODE (0x0E)
2722 #define MPI_SAS_IOUNIT2_FLAGS_SHIFT_PHYS_MAP_MODE (1)
2723 #define MPI_SAS_IOUNIT2_FLAGS_NO_PHYS_MAP (0x00)
2724 #define MPI_SAS_IOUNIT2_FLAGS_DIRECT_ATTACH_PHYS_MAP (0x01)
2725 #define MPI_SAS_IOUNIT2_FLAGS_ENCLOSURE_SLOT_PHYS_MAP (0x02)
2726 #define MPI_SAS_IOUNIT2_FLAGS_HOST_ASSIGNED_PHYS_MAP (0x07)
2728 #define MPI_SAS_IOUNIT2_FLAGS_RESERVE_ID_0_FOR_BOOT (0x10)
2729 #define MPI_SAS_IOUNIT2_FLAGS_DA_STARTING_SLOT (0x20)
2732 typedef struct _CONFIG_PAGE_SAS_IO_UNIT_3
2734 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2735 U32 Reserved1; /* 08h */
2736 U32 MaxInvalidDwordCount; /* 0Ch */
2737 U32 InvalidDwordCountTime; /* 10h */
2738 U32 MaxRunningDisparityErrorCount; /* 14h */
2739 U32 RunningDisparityErrorTime; /* 18h */
2740 U32 MaxLossDwordSynchCount; /* 1Ch */
2741 U32 LossDwordSynchCountTime; /* 20h */
2742 U32 MaxPhyResetProblemCount; /* 24h */
2743 U32 PhyResetProblemTime; /* 28h */
2744 } CONFIG_PAGE_SAS_IO_UNIT_3, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_3,
2745 SasIOUnitPage3_t, MPI_POINTER pSasIOUnitPage3_t;
2747 #define MPI_SASIOUNITPAGE3_PAGEVERSION (0x00)
2750 /****************************************************************************
2751 * SAS Expander Config Pages
2752 ****************************************************************************/
2754 typedef struct _CONFIG_PAGE_SAS_EXPANDER_0
2756 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2757 U8 PhysicalPort; /* 08h */
2758 U8 Reserved1; /* 09h */
2759 U16 EnclosureHandle; /* 0Ah */
2760 U64 SASAddress; /* 0Ch */
2761 U32 DiscoveryStatus; /* 14h */
2762 U16 DevHandle; /* 18h */
2763 U16 ParentDevHandle; /* 1Ah */
2764 U16 ExpanderChangeCount; /* 1Ch */
2765 U16 ExpanderRouteIndexes; /* 1Eh */
2766 U8 NumPhys; /* 20h */
2767 U8 SASLevel; /* 21h */
2769 U8 Reserved3; /* 23h */
2770 } CONFIG_PAGE_SAS_EXPANDER_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_EXPANDER_0,
2771 SasExpanderPage0_t, MPI_POINTER pSasExpanderPage0_t;
2773 #define MPI_SASEXPANDER0_PAGEVERSION (0x03)
2775 /* values for SAS Expander Page 0 DiscoveryStatus field */
2776 #define MPI_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001)
2777 #define MPI_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002)
2778 #define MPI_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004)
2779 #define MPI_SAS_EXPANDER0_DS_EXPANDER_ERR (0x00000008)
2780 #define MPI_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010)
2781 #define MPI_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020)
2782 #define MPI_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040)
2783 #define MPI_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080)
2784 #define MPI_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100)
2785 #define MPI_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200)
2786 #define MPI_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400)
2787 #define MPI_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800)
2789 /* values for SAS Expander Page 0 Flags field */
2790 #define MPI_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x04)
2791 #define MPI_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x02)
2792 #define MPI_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x01)
2795 typedef struct _CONFIG_PAGE_SAS_EXPANDER_1
2797 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2798 U8 PhysicalPort; /* 08h */
2799 U8 Reserved1; /* 09h */
2800 U16 Reserved2; /* 0Ah */
2801 U8 NumPhys; /* 0Ch */
2803 U16 NumTableEntriesProgrammed; /* 0Eh */
2804 U8 ProgrammedLinkRate; /* 10h */
2805 U8 HwLinkRate; /* 11h */
2806 U16 AttachedDevHandle; /* 12h */
2807 U32 PhyInfo; /* 14h */
2808 U32 AttachedDeviceInfo; /* 18h */
2809 U16 OwnerDevHandle; /* 1Ch */
2810 U8 ChangeCount; /* 1Eh */
2811 U8 NegotiatedLinkRate; /* 1Fh */
2812 U8 PhyIdentifier; /* 20h */
2813 U8 AttachedPhyIdentifier; /* 21h */
2814 U8 Reserved3; /* 22h */
2815 U8 DiscoveryInfo; /* 23h */
2816 U32 Reserved4; /* 24h */
2817 } CONFIG_PAGE_SAS_EXPANDER_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_EXPANDER_1,
2818 SasExpanderPage1_t, MPI_POINTER pSasExpanderPage1_t;
2820 #define MPI_SASEXPANDER1_PAGEVERSION (0x01)
2822 /* use MPI_SAS_PHY0_PRATE_ defines for ProgrammedLinkRate */
2824 /* use MPI_SAS_PHY0_HWRATE_ defines for HwLinkRate */
2826 /* use MPI_SAS_PHY0_PHYINFO_ defines for PhyInfo */
2828 /* see mpi_sas.h for values for SAS Expander Page 1 AttachedDeviceInfo values */
2830 /* values for SAS Expander Page 1 DiscoveryInfo field */
2831 #define MPI_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04)
2832 #define MPI_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02)
2833 #define MPI_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01)
2835 /* values for SAS Expander Page 1 NegotiatedLinkRate field */
2836 #define MPI_SAS_EXPANDER1_NEG_RATE_UNKNOWN (0x00)
2837 #define MPI_SAS_EXPANDER1_NEG_RATE_PHY_DISABLED (0x01)
2838 #define MPI_SAS_EXPANDER1_NEG_RATE_FAILED_NEGOTIATION (0x02)
2839 #define MPI_SAS_EXPANDER1_NEG_RATE_SATA_OOB_COMPLETE (0x03)
2840 #define MPI_SAS_EXPANDER1_NEG_RATE_1_5 (0x08)
2841 #define MPI_SAS_EXPANDER1_NEG_RATE_3_0 (0x09)
2844 /****************************************************************************
2845 * SAS Device Config Pages
2846 ****************************************************************************/
2848 typedef struct _CONFIG_PAGE_SAS_DEVICE_0
2850 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2852 U16 EnclosureHandle; /* 0Ah */
2853 U64 SASAddress; /* 0Ch */
2854 U16 ParentDevHandle; /* 14h */
2855 U8 PhyNum; /* 16h */
2856 U8 AccessStatus; /* 17h */
2857 U16 DevHandle; /* 18h */
2858 U8 TargetID; /* 1Ah */
2860 U32 DeviceInfo; /* 1Ch */
2861 U16 Flags; /* 20h */
2862 U8 PhysicalPort; /* 22h */
2863 U8 Reserved2; /* 23h */
2864 } CONFIG_PAGE_SAS_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_DEVICE_0,
2865 SasDevicePage0_t, MPI_POINTER pSasDevicePage0_t;
2867 #define MPI_SASDEVICE0_PAGEVERSION (0x05)
2869 /* values for SAS Device Page 0 AccessStatus field */
2870 #define MPI_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00)
2871 #define MPI_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01)
2872 #define MPI_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02)
2873 #define MPI_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT (0x03)
2874 /* specific values for SATA Init failures */
2875 #define MPI_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN (0x10)
2876 #define MPI_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x11)
2877 #define MPI_SAS_DEVICE0_ASTATUS_SIF_DIAG (0x12)
2878 #define MPI_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x13)
2879 #define MPI_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x14)
2880 #define MPI_SAS_DEVICE0_ASTATUS_SIF_PIO_SN (0x15)
2881 #define MPI_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN (0x16)
2882 #define MPI_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN (0x17)
2883 #define MPI_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x18)
2884 #define MPI_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x19)
2885 #define MPI_SAS_DEVICE0_ASTATUS_SIF_MAX (0x1F)
2887 /* values for SAS Device Page 0 Flags field */
2888 #define MPI_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400)
2889 #define MPI_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200)
2890 #define MPI_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100)
2891 #define MPI_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080)
2892 #define MPI_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040)
2893 #define MPI_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020)
2894 #define MPI_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010)
2895 #define MPI_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008)
2896 #define MPI_SAS_DEVICE0_FLAGS_MAPPING_PERSISTENT (0x0004)
2897 #define MPI_SAS_DEVICE0_FLAGS_DEVICE_MAPPED (0x0002)
2898 #define MPI_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001)
2900 /* see mpi_sas.h for values for SAS Device Page 0 DeviceInfo values */
2903 typedef struct _CONFIG_PAGE_SAS_DEVICE_1
2905 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2906 U32 Reserved1; /* 08h */
2907 U64 SASAddress; /* 0Ch */
2908 U32 Reserved2; /* 14h */
2909 U16 DevHandle; /* 18h */
2910 U8 TargetID; /* 1Ah */
2912 U8 InitialRegDeviceFIS[20];/* 1Ch */
2913 } CONFIG_PAGE_SAS_DEVICE_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_DEVICE_1,
2914 SasDevicePage1_t, MPI_POINTER pSasDevicePage1_t;
2916 #define MPI_SASDEVICE1_PAGEVERSION (0x00)
2919 typedef struct _CONFIG_PAGE_SAS_DEVICE_2
2921 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2922 U64 PhysicalIdentifier; /* 08h */
2923 U32 EnclosureMapping; /* 10h */
2924 } CONFIG_PAGE_SAS_DEVICE_2, MPI_POINTER PTR_CONFIG_PAGE_SAS_DEVICE_2,
2925 SasDevicePage2_t, MPI_POINTER pSasDevicePage2_t;
2927 #define MPI_SASDEVICE2_PAGEVERSION (0x01)
2929 /* defines for SAS Device Page 2 EnclosureMapping field */
2930 #define MPI_SASDEVICE2_ENC_MAP_MASK_MISSING_COUNT (0x0000000F)
2931 #define MPI_SASDEVICE2_ENC_MAP_SHIFT_MISSING_COUNT (0)
2932 #define MPI_SASDEVICE2_ENC_MAP_MASK_NUM_SLOTS (0x000007F0)
2933 #define MPI_SASDEVICE2_ENC_MAP_SHIFT_NUM_SLOTS (4)
2934 #define MPI_SASDEVICE2_ENC_MAP_MASK_START_INDEX (0x001FF800)
2935 #define MPI_SASDEVICE2_ENC_MAP_SHIFT_START_INDEX (11)
2938 /****************************************************************************
2939 * SAS PHY Config Pages
2940 ****************************************************************************/
2942 typedef struct _CONFIG_PAGE_SAS_PHY_0
2944 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2945 U16 OwnerDevHandle; /* 08h */
2946 U16 Reserved1; /* 0Ah */
2947 U64 SASAddress; /* 0Ch */
2948 U16 AttachedDevHandle; /* 14h */
2949 U8 AttachedPhyIdentifier; /* 16h */
2950 U8 Reserved2; /* 17h */
2951 U32 AttachedDeviceInfo; /* 18h */
2952 U8 ProgrammedLinkRate; /* 1Ch */
2953 U8 HwLinkRate; /* 1Dh */
2954 U8 ChangeCount; /* 1Eh */
2956 U32 PhyInfo; /* 20h */
2957 } CONFIG_PAGE_SAS_PHY_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_PHY_0,
2958 SasPhyPage0_t, MPI_POINTER pSasPhyPage0_t;
2960 #define MPI_SASPHY0_PAGEVERSION (0x01)
2962 /* values for SAS PHY Page 0 ProgrammedLinkRate field */
2963 #define MPI_SAS_PHY0_PRATE_MAX_RATE_MASK (0xF0)
2964 #define MPI_SAS_PHY0_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00)
2965 #define MPI_SAS_PHY0_PRATE_MAX_RATE_1_5 (0x80)
2966 #define MPI_SAS_PHY0_PRATE_MAX_RATE_3_0 (0x90)
2967 #define MPI_SAS_PHY0_PRATE_MIN_RATE_MASK (0x0F)
2968 #define MPI_SAS_PHY0_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00)
2969 #define MPI_SAS_PHY0_PRATE_MIN_RATE_1_5 (0x08)
2970 #define MPI_SAS_PHY0_PRATE_MIN_RATE_3_0 (0x09)
2972 /* values for SAS PHY Page 0 HwLinkRate field */
2973 #define MPI_SAS_PHY0_HWRATE_MAX_RATE_MASK (0xF0)
2974 #define MPI_SAS_PHY0_HWRATE_MAX_RATE_1_5 (0x80)
2975 #define MPI_SAS_PHY0_HWRATE_MAX_RATE_3_0 (0x90)
2976 #define MPI_SAS_PHY0_HWRATE_MIN_RATE_MASK (0x0F)
2977 #define MPI_SAS_PHY0_HWRATE_MIN_RATE_1_5 (0x08)
2978 #define MPI_SAS_PHY0_HWRATE_MIN_RATE_3_0 (0x09)
2980 /* values for SAS PHY Page 0 Flags field */
2981 #define MPI_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01)
2983 /* values for SAS PHY Page 0 PhyInfo field */
2984 #define MPI_SAS_PHY0_PHYINFO_SATA_PORT_ACTIVE (0x00004000)
2985 #define MPI_SAS_PHY0_PHYINFO_SATA_PORT_SELECTOR (0x00002000)
2986 #define MPI_SAS_PHY0_PHYINFO_VIRTUAL_PHY (0x00001000)
2988 #define MPI_SAS_PHY0_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00)
2989 #define MPI_SAS_PHY0_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8)
2991 #define MPI_SAS_PHY0_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0)
2992 #define MPI_SAS_PHY0_PHYINFO_DIRECT_ROUTING (0x00000000)
2993 #define MPI_SAS_PHY0_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010)
2994 #define MPI_SAS_PHY0_PHYINFO_TABLE_ROUTING (0x00000020)
2996 #define MPI_SAS_PHY0_PHYINFO_MASK_LINK_RATE (0x0000000F)
2997 #define MPI_SAS_PHY0_PHYINFO_UNKNOWN_LINK_RATE (0x00000000)
2998 #define MPI_SAS_PHY0_PHYINFO_PHY_DISABLED (0x00000001)
2999 #define MPI_SAS_PHY0_PHYINFO_NEGOTIATION_FAILED (0x00000002)
3000 #define MPI_SAS_PHY0_PHYINFO_SATA_OOB_COMPLETE (0x00000003)
3001 #define MPI_SAS_PHY0_PHYINFO_RATE_1_5 (0x00000008)
3002 #define MPI_SAS_PHY0_PHYINFO_RATE_3_0 (0x00000009)
3005 typedef struct _CONFIG_PAGE_SAS_PHY_1
3007 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
3008 U32 Reserved1; /* 08h */
3009 U32 InvalidDwordCount; /* 0Ch */
3010 U32 RunningDisparityErrorCount; /* 10h */
3011 U32 LossDwordSynchCount; /* 14h */
3012 U32 PhyResetProblemCount; /* 18h */
3013 } CONFIG_PAGE_SAS_PHY_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_PHY_1,
3014 SasPhyPage1_t, MPI_POINTER pSasPhyPage1_t;
3016 #define MPI_SASPHY1_PAGEVERSION (0x00)
3019 /****************************************************************************
3020 * SAS Enclosure Config Pages
3021 ****************************************************************************/
3023 typedef struct _CONFIG_PAGE_SAS_ENCLOSURE_0
3025 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
3026 U32 Reserved1; /* 08h */
3027 U64 EnclosureLogicalID; /* 0Ch */
3028 U16 Flags; /* 14h */
3029 U16 EnclosureHandle; /* 16h */
3030 U16 NumSlots; /* 18h */
3031 U16 StartSlot; /* 1Ah */
3032 U8 StartTargetID; /* 1Ch */
3033 U8 StartBus; /* 1Dh */
3034 U8 SEPTargetID; /* 1Eh */
3035 U8 SEPBus; /* 1Fh */
3036 U32 Reserved2; /* 20h */
3037 U32 Reserved3; /* 24h */
3038 } CONFIG_PAGE_SAS_ENCLOSURE_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_ENCLOSURE_0,
3039 SasEnclosurePage0_t, MPI_POINTER pSasEnclosurePage0_t;
3041 #define MPI_SASENCLOSURE0_PAGEVERSION (0x01)
3043 /* values for SAS Enclosure Page 0 Flags field */
3044 #define MPI_SAS_ENCLS0_FLAGS_SEP_BUS_ID_VALID (0x0020)
3045 #define MPI_SAS_ENCLS0_FLAGS_START_BUS_ID_VALID (0x0010)
3047 #define MPI_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F)
3048 #define MPI_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000)
3049 #define MPI_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001)
3050 #define MPI_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002)
3051 #define MPI_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003)
3052 #define MPI_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004)
3053 #define MPI_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005)
3056 /****************************************************************************
3058 ****************************************************************************/
3060 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
3061 * one and check NumLogEntries at runtime.
3063 #ifndef MPI_LOG_0_NUM_LOG_ENTRIES
3064 #define MPI_LOG_0_NUM_LOG_ENTRIES (1)
3067 #define MPI_LOG_0_LOG_DATA_LENGTH (0x1C)
3069 typedef struct _MPI_LOG_0_ENTRY
3071 U32 TimeStamp; /* 00h */
3072 U32 Reserved1; /* 04h */
3073 U16 LogSequence; /* 08h */
3074 U16 LogEntryQualifier; /* 0Ah */
3075 U8 LogData[MPI_LOG_0_LOG_DATA_LENGTH]; /* 0Ch */
3076 } MPI_LOG_0_ENTRY, MPI_POINTER PTR_MPI_LOG_0_ENTRY,
3077 MpiLog0Entry_t, MPI_POINTER pMpiLog0Entry_t;
3079 /* values for Log Page 0 LogEntry LogEntryQualifier field */
3080 #define MPI_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000)
3081 #define MPI_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001)
3083 typedef struct _CONFIG_PAGE_LOG_0
3085 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
3086 U32 Reserved1; /* 08h */
3087 U32 Reserved2; /* 0Ch */
3088 U16 NumLogEntries; /* 10h */
3089 U16 Reserved3; /* 12h */
3090 MPI_LOG_0_ENTRY LogEntry[MPI_LOG_0_NUM_LOG_ENTRIES]; /* 14h */
3091 } CONFIG_PAGE_LOG_0, MPI_POINTER PTR_CONFIG_PAGE_LOG_0,
3092 LogPage0_t, MPI_POINTER pLogPage0_t;
3094 #define MPI_LOG_0_PAGEVERSION (0x01)