sys/dev/mrsas/mrsas.h

   1 /*
   2  * Copyright (c) 2015, AVAGO Tech. All rights reserved. Authors: Marian Choy
   3  * Copyright (c) 2014, LSI Corp. All rights reserved. Authors: Marian Choy
   4  * Support: freebsdraid@avagotech.com
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are
   8  * met:
   9  *
  10  * 1. Redistributions of source code must retain the above copyright notice,
  11  * this list of conditions and the following disclaimer. 2. Redistributions
  12  * in binary form must reproduce the above copyright notice, this list of
  13  * conditions and the following disclaimer in the documentation and/or other
  14  * materials provided with the distribution. 3. Neither the name of the
  15  * <ORGANIZATION> nor the names of its contributors may be used to endorse or
  16  * promote products derived from this software without specific prior written
  17  * permission.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  *
  31  * The views and conclusions contained in the software and documentation are
  32  * those of the authors and should not be interpreted as representing
  33  * official policies,either expressed or implied, of the FreeBSD Project.
  34  *
  35  * Send feedback to: <megaraidfbsd@avagotech.com> Mail to: AVAGO TECHNOLOGIES, 1621
  36  * Barber Lane, Milpitas, CA 95035 ATTN: MegaRaid FreeBSD
  37  *
  38  */
  39
  40 #include <sys/cdefs.h>
  41 __FBSDID("$FreeBSD$");
  42
  43 #ifndef MRSAS_H
  44 #define MRSAS_H
  45
  46 #include <sys/param.h>                  /* defines used in kernel.h */
  47 #include <sys/module.h>
  48 #include <sys/systm.h>
  49 #include <sys/proc.h>
  50 #include <sys/errno.h>
  51 #include <sys/kernel.h>                 /* types used in module initialization */
  52 #include <sys/conf.h>                   /* cdevsw struct */
  53 #include <sys/uio.h>                    /* uio struct */
  54 #include <sys/malloc.h>
  55 #include <sys/bus.h>                    /* structs, prototypes for pci bus
  56                                          * stuff */
  57 #include <sys/rman.h>
  58 #include <sys/types.h>
  59 #include <sys/lock.h>
  60 #include <sys/mutex.h>
  61 #include <sys/sema.h>
  62 #include <sys/sysctl.h>
  63 #include <sys/stat.h>
  64 #include <sys/taskqueue.h>
  65 #include <sys/poll.h>
  66 #include <sys/selinfo.h>
  67
  68 #include <machine/bus.h>
  69 #include <machine/resource.h>
  70 #include <machine/atomic.h>
  71
  72 #include <dev/pci/pcivar.h>             /* For pci_get macros! */
  73 #include <dev/pci/pcireg.h>
  74
  75
  76 #define IOCTL_SEMA_DESCRIPTION  "mrsas semaphore for MFI pool"
  77
  78 /*
  79  * Device IDs and PCI
  80  */
  81 #define MRSAS_TBOLT                     0x005b
  82 #define MRSAS_INVADER           0x005d
  83 #define MRSAS_FURY                      0x005f
  84 #define MRSAS_INTRUDER          0x00ce
  85 #define MRSAS_INTRUDER_24       0x00cf
  86 #define MRSAS_CUTLASS_52        0x0052
  87 #define MRSAS_CUTLASS_53        0x0053
  88 /* Gen3.5 Conroller */
  89 #define MRSAS_VENTURA               0x0014
  90 #define MRSAS_CRUSADER              0x0015
  91 #define MRSAS_HARPOON               0x0016
  92 #define MRSAS_TOMCAT                0x0017
  93 #define MRSAS_VENTURA_4PORT         0x001B
  94 #define MRSAS_CRUSADER_4PORT        0x001C
  95 #define MRSAS_AERO_10E0             0x10E0
  96 #define MRSAS_AERO_10E1             0x10E1
  97 #define MRSAS_AERO_10E2             0x10E2
  98 #define MRSAS_AERO_10E3             0x10E3
  99 #define MRSAS_AERO_10E4             0x10E4
 100 #define MRSAS_AERO_10E5             0x10E5
 101 #define MRSAS_AERO_10E6             0x10E6
 102 #define MRSAS_AERO_10E7             0x10E7
 103
 104
 105 /*
 106  * Firmware State Defines
 107  */
 108 #define MRSAS_FWSTATE_MAXCMD_MASK               0x0000FFFF
 109 #define MRSAS_FWSTATE_SGE_MASK                  0x00FF0000
 110 #define MRSAS_FW_STATE_CHNG_INTERRUPT   1
 111
 112 /*
 113  * Message Frame Defines
 114  */
 115 #define MRSAS_SENSE_LEN                                 96
 116 #define MRSAS_FUSION_MAX_RESET_TRIES    3
 117
 118 /*
 119  * Miscellaneous Defines
 120  */
 121 #define BYTE_ALIGNMENT                                  1
 122 #define MRSAS_MAX_NAME_LENGTH                   32
 123 #define MRSAS_VERSION                                   "07.709.04.00-fbsd"
 124 #define MRSAS_ULONG_MAX                                 0xFFFFFFFFFFFFFFFF
 125 #define MRSAS_DEFAULT_TIMEOUT                   0x14    /* Temporarily set */
 126 #define DONE                                                    0
 127 #define MRSAS_PAGE_SIZE                                 4096
 128 #define MRSAS_RESET_NOTICE_INTERVAL             5
 129 #define MRSAS_IO_TIMEOUT                                180000  /* 180 second timeout */
 130 #define MRSAS_LDIO_QUEUE_DEPTH                  70      /* 70 percent as default */
 131 #define THRESHOLD_REPLY_COUNT                   50
 132 #define MAX_MSIX_COUNT                                  128
 133
 134 #define MAX_STREAMS_TRACKED                             8
 135 #define MR_STREAM_BITMAP                                0x76543210
 136 #define BITS_PER_INDEX_STREAM                   4       /* number of bits per index in U32 TrackStream */
 137 #define STREAM_MASK                                             ((1 << BITS_PER_INDEX_STREAM) - 1)
 138 #define ZERO_LAST_STREAM                                0x0fffffff
 139
 140 /*
 141  * Boolean types
 142  */
 143 #if (__FreeBSD_version < 901000)
 144 typedef enum _boolean {
 145         false, true
 146 }       boolean;
 147
 148 #endif
 149 enum err {
 150         SUCCESS, FAIL
 151 };
 152
 153 MALLOC_DECLARE(M_MRSAS);
 154 SYSCTL_DECL(_hw_mrsas);
 155
 156 #define MRSAS_INFO              (1 << 0)
 157 #define MRSAS_TRACE             (1 << 1)
 158 #define MRSAS_FAULT             (1 << 2)
 159 #define MRSAS_OCR               (1 << 3)
 160 #define MRSAS_TOUT              MRSAS_OCR
 161 #define MRSAS_AEN               (1 << 4)
 162 #define MRSAS_PRL11             (1 << 5)
 163
 164 #define mrsas_dprint(sc, level, msg, args...)       \
 165 do {                                                \
 166     if (sc->mrsas_debug & level)                    \
 167         device_printf(sc->mrsas_dev, msg, ##args);  \
 168 } while (0)
 169
 170
 171 /****************************************************************************
 172  * Raid Context structure which describes MegaRAID specific IO Paramenters
 173  * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames
 174  ****************************************************************************/
 175
 176 typedef struct _RAID_CONTEXT {
 177         u_int8_t Type:4;
 178         u_int8_t nseg:4;
 179         u_int8_t resvd0;
 180         u_int16_t timeoutValue;
 181         u_int8_t regLockFlags;
 182         u_int8_t resvd1;
 183         u_int16_t VirtualDiskTgtId;
 184         u_int64_t regLockRowLBA;
 185         u_int32_t regLockLength;
 186         u_int16_t nextLMId;
 187         u_int8_t exStatus;
 188         u_int8_t status;
 189         u_int8_t RAIDFlags;
 190         u_int8_t numSGE;
 191         u_int16_t configSeqNum;
 192         u_int8_t spanArm;
 193         u_int8_t priority;              /* 0x1D MR_PRIORITY_RANGE */
 194         u_int8_t numSGEExt;             /* 0x1E 1M IO support */
 195         u_int8_t resvd2;                /* 0x1F */
 196 }       RAID_CONTEXT;
 197
 198 /*
 199  * Raid Context structure which describes ventura MegaRAID specific IO Paramenters
 200  * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames
 201  */
 202 typedef struct _RAID_CONTEXT_G35 {
 203         u_int16_t Type:4;
 204         u_int16_t nseg:4;
 205         u_int16_t resvd0:8;
 206         u_int16_t timeoutValue;
 207         union {
 208                 struct {
 209                         u_int16_t reserved:1;
 210                         u_int16_t sld:1;
 211                         u_int16_t c2f:1;
 212                         u_int16_t fwn:1;
 213                         u_int16_t sqn:1;
 214                         u_int16_t sbs:1;
 215                         u_int16_t rw:1;
 216                         u_int16_t log:1;
 217                         u_int16_t cpuSel:4;
 218                         u_int16_t setDivert:4;
 219                 }       bits;
 220                 u_int16_t s;
 221         }       routingFlags;
 222         u_int16_t VirtualDiskTgtId;
 223         u_int64_t regLockRowLBA;
 224         u_int32_t regLockLength;
 225         union {
 226                 u_int16_t nextLMId;
 227                 u_int16_t peerSMID;
 228         }       smid;
 229         u_int8_t exStatus;
 230         u_int8_t status;
 231         u_int8_t RAIDFlags;
 232         u_int8_t spanArm;
 233         u_int16_t configSeqNum;
 234         u_int16_t numSGE:12;
 235         u_int16_t reserved:3;
 236         u_int16_t streamDetected:1;
 237         u_int8_t resvd2[2];
 238 }       RAID_CONTEXT_G35;
 239
 240 typedef union _RAID_CONTEXT_UNION {
 241         RAID_CONTEXT raid_context;
 242         RAID_CONTEXT_G35 raid_context_g35;
 243 }       RAID_CONTEXT_UNION, *PRAID_CONTEXT_UNION;
 244
 245
 246 /*************************************************************************
 247  * MPI2 Defines
 248  ************************************************************************/
 249
 250 #define MPI2_FUNCTION_IOC_INIT                                  (0x02)  /* IOC Init */
 251 #define MPI2_WHOINIT_HOST_DRIVER                                (0x04)
 252 #define MPI2_VERSION_MAJOR                                              (0x02)
 253 #define MPI2_VERSION_MINOR                                              (0x00)
 254 #define MPI2_VERSION_MAJOR_MASK                                 (0xFF00)
 255 #define MPI2_VERSION_MAJOR_SHIFT                                (8)
 256 #define MPI2_VERSION_MINOR_MASK                                 (0x00FF)
 257 #define MPI2_VERSION_MINOR_SHIFT                                (0)
 258 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
 259                       MPI2_VERSION_MINOR)
 260 #define MPI2_HEADER_VERSION_UNIT                                (0x10)
 261 #define MPI2_HEADER_VERSION_DEV                                 (0x00)
 262 #define MPI2_HEADER_VERSION_UNIT_MASK                   (0xFF00)
 263 #define MPI2_HEADER_VERSION_UNIT_SHIFT                  (8)
 264 #define MPI2_HEADER_VERSION_DEV_MASK                    (0x00FF)
 265 #define MPI2_HEADER_VERSION_DEV_SHIFT                   (0)
 266 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | MPI2_HEADER_VERSION_DEV)
 267 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR              (0x03)
 268 #define MPI2_SCSIIO_EEDPFLAGS_INC_PRI_REFTAG    (0x8000)
 269 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REFTAG              (0x0400)
 270 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REMOVE_OP   (0x0003)
 271 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_APPTAG              (0x0200)
 272 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_GUARD               (0x0100)
 273 #define MPI2_SCSIIO_EEDPFLAGS_INSERT_OP                 (0x0004)
 274 #define MPI2_FUNCTION_SCSI_IO_REQUEST                   (0x00)  /* SCSI IO */
 275 #define MPI2_FUNCTION_SCSI_TASK_MGMT                    (0x01)
 276 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY   (0x03)
 277 #define MPI2_REQ_DESCRIPT_FLAGS_FP_IO                   (0x06)
 278 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO                 (0x00)
 279 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING                (0x02)
 280 #define MPI2_SCSIIO_CONTROL_WRITE                               (0x01000000)
 281 #define MPI2_SCSIIO_CONTROL_READ                                (0x02000000)
 282 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK               (0x0E)
 283 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED                  (0x0F)
 284 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00)
 285 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK               (0x0F)
 286 #define MPI2_WRSEQ_FLUSH_KEY_VALUE                              (0x0)
 287 #define MPI2_WRITE_SEQUENCE_OFFSET                              (0x00000004)
 288 #define MPI2_WRSEQ_1ST_KEY_VALUE                                (0xF)
 289 #define MPI2_WRSEQ_2ND_KEY_VALUE                                (0x4)
 290 #define MPI2_WRSEQ_3RD_KEY_VALUE                                (0xB)
 291 #define MPI2_WRSEQ_4TH_KEY_VALUE                                (0x2)
 292 #define MPI2_WRSEQ_5TH_KEY_VALUE                                (0x7)
 293 #define MPI2_WRSEQ_6TH_KEY_VALUE                                (0xD)
 294
 295 #ifndef MPI2_POINTER
 296 #define MPI2_POINTER    *
 297 #endif
 298
 299
 300 /***************************************
 301  * MPI2 Structures
 302  ***************************************/
 303
 304 typedef struct _MPI25_IEEE_SGE_CHAIN64 {
 305         u_int64_t Address;
 306         u_int32_t Length;
 307         u_int16_t Reserved1;
 308         u_int8_t NextChainOffset;
 309         u_int8_t Flags;
 310 }       MPI25_IEEE_SGE_CHAIN64, MPI2_POINTER PTR_MPI25_IEEE_SGE_CHAIN64,
 311 Mpi25IeeeSgeChain64_t, MPI2_POINTER pMpi25IeeeSgeChain64_t;
 312
 313 typedef struct _MPI2_SGE_SIMPLE_UNION {
 314         u_int32_t FlagsLength;
 315         union {
 316                 u_int32_t Address32;
 317                 u_int64_t Address64;
 318         }       u;
 319 }       MPI2_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_SIMPLE_UNION,
 320 Mpi2SGESimpleUnion_t, MPI2_POINTER pMpi2SGESimpleUnion_t;
 321
 322 typedef struct {
 323         u_int8_t CDB[20];               /* 0x00 */
 324         u_int32_t PrimaryReferenceTag;  /* 0x14 */
 325         u_int16_t PrimaryApplicationTag;/* 0x18 */
 326         u_int16_t PrimaryApplicationTagMask;    /* 0x1A */
 327         u_int32_t TransferLength;       /* 0x1C */
 328 }       MPI2_SCSI_IO_CDB_EEDP32, MPI2_POINTER PTR_MPI2_SCSI_IO_CDB_EEDP32,
 329 Mpi2ScsiIoCdbEedp32_t, MPI2_POINTER pMpi2ScsiIoCdbEedp32_t;
 330
 331 typedef struct _MPI2_SGE_CHAIN_UNION {
 332         u_int16_t Length;
 333         u_int8_t NextChainOffset;
 334         u_int8_t Flags;
 335         union {
 336                 u_int32_t Address32;
 337                 u_int64_t Address64;
 338         }       u;
 339 }       MPI2_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_SGE_CHAIN_UNION,
 340 Mpi2SGEChainUnion_t, MPI2_POINTER pMpi2SGEChainUnion_t;
 341
 342 typedef struct _MPI2_IEEE_SGE_SIMPLE32 {
 343         u_int32_t Address;
 344         u_int32_t FlagsLength;
 345 }       MPI2_IEEE_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE32,
 346 Mpi2IeeeSgeSimple32_t, MPI2_POINTER pMpi2IeeeSgeSimple32_t;
 347 typedef struct _MPI2_IEEE_SGE_SIMPLE64 {
 348         u_int64_t Address;
 349         u_int32_t Length;
 350         u_int16_t Reserved1;
 351         u_int8_t Reserved2;
 352         u_int8_t Flags;
 353 }       MPI2_IEEE_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE64,
 354 Mpi2IeeeSgeSimple64_t, MPI2_POINTER pMpi2IeeeSgeSimple64_t;
 355
 356 typedef union _MPI2_IEEE_SGE_SIMPLE_UNION {
 357         MPI2_IEEE_SGE_SIMPLE32 Simple32;
 358         MPI2_IEEE_SGE_SIMPLE64 Simple64;
 359 }       MPI2_IEEE_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE_UNION,
 360 Mpi2IeeeSgeSimpleUnion_t, MPI2_POINTER pMpi2IeeeSgeSimpleUnion_t;
 361
 362 typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32;
 363 typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64;
 364
 365 typedef union _MPI2_IEEE_SGE_CHAIN_UNION {
 366         MPI2_IEEE_SGE_CHAIN32 Chain32;
 367         MPI2_IEEE_SGE_CHAIN64 Chain64;
 368 }       MPI2_IEEE_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_CHAIN_UNION,
 369 Mpi2IeeeSgeChainUnion_t, MPI2_POINTER pMpi2IeeeSgeChainUnion_t;
 370
 371 typedef union _MPI2_SGE_IO_UNION {
 372         MPI2_SGE_SIMPLE_UNION MpiSimple;
 373         MPI2_SGE_CHAIN_UNION MpiChain;
 374         MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
 375         MPI2_IEEE_SGE_CHAIN_UNION IeeeChain;
 376 }       MPI2_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_SGE_IO_UNION,
 377 Mpi2SGEIOUnion_t, MPI2_POINTER pMpi2SGEIOUnion_t;
 378
 379 typedef union {
 380         u_int8_t CDB32[32];
 381         MPI2_SCSI_IO_CDB_EEDP32 EEDP32;
 382         MPI2_SGE_SIMPLE_UNION SGE;
 383 }       MPI2_SCSI_IO_CDB_UNION, MPI2_POINTER PTR_MPI2_SCSI_IO_CDB_UNION,
 384 Mpi2ScsiIoCdb_t, MPI2_POINTER pMpi2ScsiIoCdb_t;
 385
 386 /****************************************************************************
 387  *  *  SCSI Task Management messages
 388  *   ****************************************************************************/
 389
 390 /*SCSI Task Management Request Message */
 391 typedef struct _MPI2_SCSI_TASK_MANAGE_REQUEST {
 392         u_int16_t DevHandle;        /*0x00 */
 393         u_int8_t ChainOffset;       /*0x02 */
 394         u_int8_t Function;      /*0x03 */
 395         u_int8_t Reserved1;     /*0x04 */
 396         u_int8_t TaskType;      /*0x05 */
 397         u_int8_t Reserved2;     /*0x06 */
 398         u_int8_t MsgFlags;      /*0x07 */
 399         u_int8_t VP_ID;     /*0x08 */
 400         u_int8_t VF_ID;     /*0x09 */
 401         u_int16_t Reserved3;        /*0x0A */
 402         u_int8_t LUN[8];        /*0x0C */
 403         u_int32_t Reserved4[7]; /*0x14 */
 404         u_int16_t TaskMID;      /*0x30 */
 405         u_int16_t Reserved5;        /*0x32 */
 406 } MPI2_SCSI_TASK_MANAGE_REQUEST;
 407
 408 /*SCSI Task Management Reply Message */
 409 typedef struct _MPI2_SCSI_TASK_MANAGE_REPLY {
 410         u_int16_t DevHandle;        /*0x00 */
 411         u_int8_t MsgLength;     /*0x02 */
 412         u_int8_t Function;      /*0x03 */
 413         u_int8_t ResponseCode;  /*0x04 */
 414         u_int8_t TaskType;      /*0x05 */
 415         u_int8_t Reserved1;     /*0x06 */
 416         u_int8_t MsgFlags;      /*0x07 */
 417         u_int8_t VP_ID;     /*0x08 */
 418         u_int8_t VF_ID;     /*0x09 */
 419         u_int16_t Reserved2;        /*0x0A */
 420         u_int16_t Reserved3;        /*0x0C */
 421         u_int16_t IOCStatus;        /*0x0E */
 422         u_int32_t IOCLogInfo;       /*0x10 */
 423         u_int32_t TerminationCount; /*0x14 */
 424         u_int32_t ResponseInfo; /*0x18 */
 425 } MPI2_SCSI_TASK_MANAGE_REPLY;
 426
 427 typedef struct _MR_TM_REQUEST {
 428         char request[128];
 429 } MR_TM_REQUEST;
 430
 431 typedef struct _MR_TM_REPLY {
 432         char reply[128];
 433 } MR_TM_REPLY;
 434
 435 /* SCSI Task Management Request Message */
 436 typedef struct _MR_TASK_MANAGE_REQUEST {
 437         /*To be type casted to struct MPI2_SCSI_TASK_MANAGE_REQUEST */
 438         MR_TM_REQUEST        TmRequest;
 439         union {
 440                 struct {
 441                         u_int32_t isTMForLD:1;
 442                         u_int32_t isTMForPD:1;
 443                         u_int32_t reserved1:30;
 444                         u_int32_t reserved2;
 445                 } tmReqFlags;
 446                 MR_TM_REPLY   TMReply;
 447         } uTmReqReply;
 448 } MR_TASK_MANAGE_REQUEST;
 449
 450 /* TaskType values */
 451 #define MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK           (0x01)
 452 #define MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET        (0x02)
 453 #define MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET         (0x03)
 454 #define MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET   (0x05)
 455 #define MPI2_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET       (0x06)
 456 #define MPI2_SCSITASKMGMT_TASKTYPE_QUERY_TASK           (0x07)
 457 #define MPI2_SCSITASKMGMT_TASKTYPE_CLR_ACA              (0x08)
 458 #define MPI2_SCSITASKMGMT_TASKTYPE_QRY_TASK_SET         (0x09)
 459 #define MPI2_SCSITASKMGMT_TASKTYPE_QRY_ASYNC_EVENT      (0x0A)
 460
 461 /* ResponseCode values */
 462 #define MPI2_SCSITASKMGMT_RSP_TM_COMPLETE               (0x00)
 463 #define MPI2_SCSITASKMGMT_RSP_INVALID_FRAME             (0x02)
 464 #define MPI2_SCSITASKMGMT_RSP_TM_NOT_SUPPORTED          (0x04)
 465 #define MPI2_SCSITASKMGMT_RSP_TM_FAILED                 (0x05)
 466 #define MPI2_SCSITASKMGMT_RSP_TM_SUCCEEDED              (0x08)
 467 #define MPI2_SCSITASKMGMT_RSP_TM_INVALID_LUN            (0x09)
 468 #define MPI2_SCSITASKMGMT_RSP_TM_OVERLAPPED_TAG         (0x0A)
 469 #define MPI2_SCSITASKMGMT_RSP_IO_QUEUED_ON_IOC          (0x80)
 470
 471 /*
 472  * RAID SCSI IO Request Message Total SGE count will be one less than
 473  * _MPI2_SCSI_IO_REQUEST
 474  */
 475 typedef struct _MPI2_RAID_SCSI_IO_REQUEST {
 476         u_int16_t DevHandle;            /* 0x00 */
 477         u_int8_t ChainOffset;           /* 0x02 */
 478         u_int8_t Function;              /* 0x03 */
 479         u_int16_t Reserved1;            /* 0x04 */
 480         u_int8_t Reserved2;             /* 0x06 */
 481         u_int8_t MsgFlags;              /* 0x07 */
 482         u_int8_t VP_ID;                 /* 0x08 */
 483         u_int8_t VF_ID;                 /* 0x09 */
 484         u_int16_t Reserved3;            /* 0x0A */
 485         u_int32_t SenseBufferLowAddress;/* 0x0C */
 486         u_int16_t SGLFlags;             /* 0x10 */
 487         u_int8_t SenseBufferLength;     /* 0x12 */
 488         u_int8_t Reserved4;             /* 0x13 */
 489         u_int8_t SGLOffset0;            /* 0x14 */
 490         u_int8_t SGLOffset1;            /* 0x15 */
 491         u_int8_t SGLOffset2;            /* 0x16 */
 492         u_int8_t SGLOffset3;            /* 0x17 */
 493         u_int32_t SkipCount;            /* 0x18 */
 494         u_int32_t DataLength;           /* 0x1C */
 495         u_int32_t BidirectionalDataLength;      /* 0x20 */
 496         u_int16_t IoFlags;              /* 0x24 */
 497         u_int16_t EEDPFlags;            /* 0x26 */
 498         u_int32_t EEDPBlockSize;        /* 0x28 */
 499         u_int32_t SecondaryReferenceTag;/* 0x2C */
 500         u_int16_t SecondaryApplicationTag;      /* 0x30 */
 501         u_int16_t ApplicationTagTranslationMask;        /* 0x32 */
 502         u_int8_t LUN[8];                /* 0x34 */
 503         u_int32_t Control;              /* 0x3C */
 504         MPI2_SCSI_IO_CDB_UNION CDB;     /* 0x40 */
 505         RAID_CONTEXT_UNION RaidContext; /* 0x60 */
 506         MPI2_SGE_IO_UNION SGL;          /* 0x80 */
 507 }       MRSAS_RAID_SCSI_IO_REQUEST, MPI2_POINTER PTR_MRSAS_RAID_SCSI_IO_REQUEST,
 508 MRSASRaidSCSIIORequest_t, MPI2_POINTER pMRSASRaidSCSIIORequest_t;
 509
 510 /*
 511  * MPT RAID MFA IO Descriptor.
 512  */
 513 typedef struct _MRSAS_RAID_MFA_IO_DESCRIPTOR {
 514         u_int32_t RequestFlags:8;
 515         u_int32_t MessageAddress1:24;   /* bits 31:8 */
 516         u_int32_t MessageAddress2;      /* bits 61:32 */
 517 }       MRSAS_RAID_MFA_IO_REQUEST_DESCRIPTOR, *PMRSAS_RAID_MFA_IO_REQUEST_DESCRIPTOR;
 518
 519 /* Default Request Descriptor */
 520 typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR {
 521         u_int8_t RequestFlags;          /* 0x00 */
 522         u_int8_t MSIxIndex;             /* 0x01 */
 523         u_int16_t SMID;                 /* 0x02 */
 524         u_int16_t LMID;                 /* 0x04 */
 525         u_int16_t DescriptorTypeDependent;      /* 0x06 */
 526 }       MPI2_DEFAULT_REQUEST_DESCRIPTOR,
 527
 528         MPI2_POINTER PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR,
 529 Mpi2DefaultRequestDescriptor_t, MPI2_POINTER pMpi2DefaultRequestDescriptor_t;
 530
 531 /* High Priority Request Descriptor */
 532 typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR {
 533         u_int8_t RequestFlags;          /* 0x00 */
 534         u_int8_t MSIxIndex;             /* 0x01 */
 535         u_int16_t SMID;                 /* 0x02 */
 536         u_int16_t LMID;                 /* 0x04 */
 537         u_int16_t Reserved1;            /* 0x06 */
 538 }       MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
 539
 540         MPI2_POINTER PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
 541 Mpi2HighPriorityRequestDescriptor_t, MPI2_POINTER pMpi2HighPriorityRequestDescriptor_t;
 542
 543 /* SCSI IO Request Descriptor */
 544 typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR {
 545         u_int8_t RequestFlags;          /* 0x00 */
 546         u_int8_t MSIxIndex;             /* 0x01 */
 547         u_int16_t SMID;                 /* 0x02 */
 548         u_int16_t LMID;                 /* 0x04 */
 549         u_int16_t DevHandle;            /* 0x06 */
 550 }       MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
 551
 552         MPI2_POINTER PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
 553 Mpi2SCSIIORequestDescriptor_t, MPI2_POINTER pMpi2SCSIIORequestDescriptor_t;
 554
 555 /* SCSI Target Request Descriptor */
 556 typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR {
 557         u_int8_t RequestFlags;          /* 0x00 */
 558         u_int8_t MSIxIndex;             /* 0x01 */
 559         u_int16_t SMID;                 /* 0x02 */
 560         u_int16_t LMID;                 /* 0x04 */
 561         u_int16_t IoIndex;              /* 0x06 */
 562 }       MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
 563
 564         MPI2_POINTER PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
 565 Mpi2SCSITargetRequestDescriptor_t, MPI2_POINTER pMpi2SCSITargetRequestDescriptor_t;
 566
 567 /* RAID Accelerator Request Descriptor */
 568 typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR {
 569         u_int8_t RequestFlags;          /* 0x00 */
 570         u_int8_t MSIxIndex;             /* 0x01 */
 571         u_int16_t SMID;                 /* 0x02 */
 572         u_int16_t LMID;                 /* 0x04 */
 573         u_int16_t Reserved;             /* 0x06 */
 574 }       MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
 575
 576         MPI2_POINTER PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
 577 Mpi2RAIDAcceleratorRequestDescriptor_t, MPI2_POINTER pMpi2RAIDAcceleratorRequestDescriptor_t;
 578
 579 /* union of Request Descriptors */
 580 typedef union _MRSAS_REQUEST_DESCRIPTOR_UNION {
 581         MPI2_DEFAULT_REQUEST_DESCRIPTOR Default;
 582         MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority;
 583         MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO;
 584         MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget;
 585         MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator;
 586         MRSAS_RAID_MFA_IO_REQUEST_DESCRIPTOR MFAIo;
 587         union {
 588                 struct {
 589                         u_int32_t low;
 590                         u_int32_t high;
 591                 }       u;
 592                 u_int64_t Words;
 593         }       addr;
 594 }       MRSAS_REQUEST_DESCRIPTOR_UNION;
 595
 596 /* Default Reply Descriptor */
 597 typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR {
 598         u_int8_t ReplyFlags;            /* 0x00 */
 599         u_int8_t MSIxIndex;             /* 0x01 */
 600         u_int16_t DescriptorTypeDependent1;     /* 0x02 */
 601         u_int32_t DescriptorTypeDependent2;     /* 0x04 */
 602 }       MPI2_DEFAULT_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR,
 603 Mpi2DefaultReplyDescriptor_t, MPI2_POINTER pMpi2DefaultReplyDescriptor_t;
 604
 605 /* Address Reply Descriptor */
 606 typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR {
 607         u_int8_t ReplyFlags;            /* 0x00 */
 608         u_int8_t MSIxIndex;             /* 0x01 */
 609         u_int16_t SMID;                 /* 0x02 */
 610         u_int32_t ReplyFrameAddress;    /* 0x04 */
 611 }       MPI2_ADDRESS_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR,
 612 Mpi2AddressReplyDescriptor_t, MPI2_POINTER pMpi2AddressReplyDescriptor_t;
 613
 614 /* SCSI IO Success Reply Descriptor */
 615 typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR {
 616         u_int8_t ReplyFlags;            /* 0x00 */
 617         u_int8_t MSIxIndex;             /* 0x01 */
 618         u_int16_t SMID;                 /* 0x02 */
 619         u_int16_t TaskTag;              /* 0x04 */
 620         u_int16_t Reserved1;            /* 0x06 */
 621 }       MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
 622
 623         MPI2_POINTER PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
 624 Mpi2SCSIIOSuccessReplyDescriptor_t, MPI2_POINTER pMpi2SCSIIOSuccessReplyDescriptor_t;
 625
 626 /* TargetAssist Success Reply Descriptor */
 627 typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR {
 628         u_int8_t ReplyFlags;            /* 0x00 */
 629         u_int8_t MSIxIndex;             /* 0x01 */
 630         u_int16_t SMID;                 /* 0x02 */
 631         u_int8_t SequenceNumber;        /* 0x04 */
 632         u_int8_t Reserved1;             /* 0x05 */
 633         u_int16_t IoIndex;              /* 0x06 */
 634 }       MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
 635
 636         MPI2_POINTER PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
 637 Mpi2TargetAssistSuccessReplyDescriptor_t, MPI2_POINTER pMpi2TargetAssistSuccessReplyDescriptor_t;
 638
 639 /* Target Command Buffer Reply Descriptor */
 640 typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR {
 641         u_int8_t ReplyFlags;            /* 0x00 */
 642         u_int8_t MSIxIndex;             /* 0x01 */
 643         u_int8_t VP_ID;                 /* 0x02 */
 644         u_int8_t Flags;                 /* 0x03 */
 645         u_int16_t InitiatorDevHandle;   /* 0x04 */
 646         u_int16_t IoIndex;              /* 0x06 */
 647 }       MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
 648
 649         MPI2_POINTER PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
 650 Mpi2TargetCommandBufferReplyDescriptor_t, MPI2_POINTER pMpi2TargetCommandBufferReplyDescriptor_t;
 651
 652 /* RAID Accelerator Success Reply Descriptor */
 653 typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR {
 654         u_int8_t ReplyFlags;            /* 0x00 */
 655         u_int8_t MSIxIndex;             /* 0x01 */
 656         u_int16_t SMID;                 /* 0x02 */
 657         u_int32_t Reserved;             /* 0x04 */
 658 }       MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
 659
 660         MPI2_POINTER PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
 661 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t, MPI2_POINTER pMpi2RAIDAcceleratorSuccessReplyDescriptor_t;
 662
 663 /* union of Reply Descriptors */
 664 typedef union _MPI2_REPLY_DESCRIPTORS_UNION {
 665         MPI2_DEFAULT_REPLY_DESCRIPTOR Default;
 666         MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply;
 667         MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess;
 668         MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess;
 669         MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer;
 670         MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess;
 671         u_int64_t Words;
 672 }       MPI2_REPLY_DESCRIPTORS_UNION, MPI2_POINTER PTR_MPI2_REPLY_DESCRIPTORS_UNION,
 673 Mpi2ReplyDescriptorsUnion_t, MPI2_POINTER pMpi2ReplyDescriptorsUnion_t;
 674
 675 typedef union {
 676         volatile unsigned int val;
 677         unsigned int val_rdonly;
 678 } mrsas_atomic_t;
 679
 680 #define mrsas_atomic_read(v)    atomic_load_acq_int(&(v)->val)
 681 #define mrsas_atomic_set(v,i)   atomic_store_rel_int(&(v)->val, i)
 682 #define mrsas_atomic_dec(v)     atomic_subtract_int(&(v)->val, 1)
 683 #define mrsas_atomic_inc(v)     atomic_add_int(&(v)->val, 1)
 684
 685 static inline int
 686 mrsas_atomic_inc_return(mrsas_atomic_t *v)
 687 {
 688         return 1 + atomic_fetchadd_int(&(v)->val, 1);
 689 }
 690
 691 /* IOCInit Request message */
 692 typedef struct _MPI2_IOC_INIT_REQUEST {
 693         u_int8_t WhoInit;               /* 0x00 */
 694         u_int8_t Reserved1;             /* 0x01 */
 695         u_int8_t ChainOffset;           /* 0x02 */
 696         u_int8_t Function;              /* 0x03 */
 697         u_int16_t Reserved2;            /* 0x04 */
 698         u_int8_t Reserved3;             /* 0x06 */
 699         u_int8_t MsgFlags;              /* 0x07 */
 700         u_int8_t VP_ID;                 /* 0x08 */
 701         u_int8_t VF_ID;                 /* 0x09 */
 702         u_int16_t Reserved4;            /* 0x0A */
 703         u_int16_t MsgVersion;           /* 0x0C */
 704         u_int16_t HeaderVersion;        /* 0x0E */
 705         u_int32_t Reserved5;            /* 0x10 */
 706         u_int16_t Reserved6;            /* 0x14 */
 707         u_int8_t HostPageSize;          /* 0x16 */
 708         u_int8_t HostMSIxVectors;       /* 0x17 */
 709         u_int16_t Reserved8;            /* 0x18 */
 710         u_int16_t SystemRequestFrameSize;       /* 0x1A */
 711         u_int16_t ReplyDescriptorPostQueueDepth;        /* 0x1C */
 712         u_int16_t ReplyFreeQueueDepth;  /* 0x1E */
 713         u_int32_t SenseBufferAddressHigh;       /* 0x20 */
 714         u_int32_t SystemReplyAddressHigh;       /* 0x24 */
 715         u_int64_t SystemRequestFrameBaseAddress;        /* 0x28 */
 716         u_int64_t ReplyDescriptorPostQueueAddress;      /* 0x30 */
 717         u_int64_t ReplyFreeQueueAddress;/* 0x38 */
 718         u_int64_t TimeStamp;            /* 0x40 */
 719 }       MPI2_IOC_INIT_REQUEST, MPI2_POINTER PTR_MPI2_IOC_INIT_REQUEST,
 720 Mpi2IOCInitRequest_t, MPI2_POINTER pMpi2IOCInitRequest_t;
 721
 722 /*
 723  * MR private defines
 724  */
 725 #define MR_PD_INVALID                   0xFFFF
 726 #define MR_DEVHANDLE_INVALID    0xFFFF
 727 #define MAX_SPAN_DEPTH                  8
 728 #define MAX_QUAD_DEPTH                  MAX_SPAN_DEPTH
 729 #define MAX_RAIDMAP_SPAN_DEPTH  (MAX_SPAN_DEPTH)
 730 #define MAX_ROW_SIZE                    32
 731 #define MAX_RAIDMAP_ROW_SIZE    (MAX_ROW_SIZE)
 732 #define MAX_LOGICAL_DRIVES              64
 733 #define MAX_LOGICAL_DRIVES_EXT  256
 734 #define MAX_LOGICAL_DRIVES_DYN  512
 735
 736 #define MAX_RAIDMAP_LOGICAL_DRIVES      (MAX_LOGICAL_DRIVES)
 737 #define MAX_RAIDMAP_VIEWS                       (MAX_LOGICAL_DRIVES)
 738
 739 #define MAX_ARRAYS                              128
 740 #define MAX_RAIDMAP_ARRAYS              (MAX_ARRAYS)
 741
 742 #define MAX_ARRAYS_EXT                  256
 743 #define MAX_API_ARRAYS_EXT              MAX_ARRAYS_EXT
 744 #define MAX_API_ARRAYS_DYN              512
 745
 746 #define MAX_PHYSICAL_DEVICES    256
 747 #define MAX_RAIDMAP_PHYSICAL_DEVICES    (MAX_PHYSICAL_DEVICES)
 748 #define MAX_RAIDMAP_PHYSICAL_DEVICES_DYN        512
 749 #define MR_DCMD_LD_MAP_GET_INFO 0x0300e101
 750 #define MR_DCMD_SYSTEM_PD_MAP_GET_INFO  0x0200e102
 751 #define MR_DCMD_PD_MFI_TASK_MGMT        0x0200e100
 752
 753 #define MR_DCMD_PD_GET_INFO             0x02020000
 754 #define MRSAS_MAX_PD_CHANNELS           1
 755 #define MRSAS_MAX_LD_CHANNELS           1
 756 #define MRSAS_MAX_DEV_PER_CHANNEL       256
 757 #define MRSAS_DEFAULT_INIT_ID           -1
 758 #define MRSAS_MAX_LUN                           8
 759 #define MRSAS_DEFAULT_CMD_PER_LUN       256
 760 #define MRSAS_MAX_PD                            (MRSAS_MAX_PD_CHANNELS * \
 761                         MRSAS_MAX_DEV_PER_CHANNEL)
 762 #define MRSAS_MAX_LD_IDS                        (MRSAS_MAX_LD_CHANNELS * \
 763                         MRSAS_MAX_DEV_PER_CHANNEL)
 764
 765
 766 #define VD_EXT_DEBUG    0
 767 #define TM_DEBUG                1
 768
 769 /*******************************************************************
 770  * RAID map related structures
 771  ********************************************************************/
 772 #pragma pack(1)
 773 typedef struct _MR_DEV_HANDLE_INFO {
 774         u_int16_t curDevHdl;
 775         u_int8_t validHandles;
 776         u_int8_t interfaceType;
 777         u_int16_t devHandle[2];
 778 }       MR_DEV_HANDLE_INFO;
 779
 780 #pragma pack()
 781
 782 typedef struct _MR_ARRAY_INFO {
 783         u_int16_t pd[MAX_RAIDMAP_ROW_SIZE];
 784 }       MR_ARRAY_INFO;
 785
 786 typedef struct _MR_QUAD_ELEMENT {
 787         u_int64_t logStart;
 788         u_int64_t logEnd;
 789         u_int64_t offsetInSpan;
 790         u_int32_t diff;
 791         u_int32_t reserved1;
 792 }       MR_QUAD_ELEMENT;
 793
 794 typedef struct _MR_SPAN_INFO {
 795         u_int32_t noElements;
 796         u_int32_t reserved1;
 797         MR_QUAD_ELEMENT quad[MAX_RAIDMAP_SPAN_DEPTH];
 798 }       MR_SPAN_INFO;
 799
 800 typedef struct _MR_LD_SPAN_ {
 801         u_int64_t startBlk;
 802         u_int64_t numBlks;
 803         u_int16_t arrayRef;
 804         u_int8_t spanRowSize;
 805         u_int8_t spanRowDataSize;
 806         u_int8_t reserved[4];
 807 }       MR_LD_SPAN;
 808
 809 typedef struct _MR_SPAN_BLOCK_INFO {
 810         u_int64_t num_rows;
 811         MR_LD_SPAN span;
 812         MR_SPAN_INFO block_span_info;
 813 }       MR_SPAN_BLOCK_INFO;
 814
 815 typedef struct _MR_LD_RAID {
 816         struct {
 817                 u_int32_t fpCapable:1;
 818                 u_int32_t raCapable:1;
 819                 u_int32_t reserved5:2;
 820                 u_int32_t ldPiMode:4;
 821                 u_int32_t pdPiMode:4;
 822                 u_int32_t encryptionType:8;
 823                 u_int32_t fpWriteCapable:1;
 824                 u_int32_t fpReadCapable:1;
 825                 u_int32_t fpWriteAcrossStripe:1;
 826                 u_int32_t fpReadAcrossStripe:1;
 827                 u_int32_t fpNonRWCapable:1;
 828                 u_int32_t tmCapable:1;
 829                 u_int32_t fpCacheBypassCapable:1;
 830                 u_int32_t reserved4:5;
 831         }       capability;
 832         u_int32_t reserved6;
 833         u_int64_t size;
 834
 835         u_int8_t spanDepth;
 836         u_int8_t level;
 837         u_int8_t stripeShift;
 838         u_int8_t rowSize;
 839
 840         u_int8_t rowDataSize;
 841         u_int8_t writeMode;
 842         u_int8_t PRL;
 843         u_int8_t SRL;
 844
 845         u_int16_t targetId;
 846         u_int8_t ldState;
 847         u_int8_t regTypeReqOnWrite;
 848         u_int8_t modFactor;
 849         u_int8_t regTypeReqOnRead;
 850         u_int16_t seqNum;
 851
 852         struct {
 853                 u_int32_t ldSyncRequired:1;
 854                 u_int32_t regTypeReqOnReadLsValid:1;
 855                 u_int32_t reserved:30;
 856         }       flags;
 857
 858         u_int8_t LUN[8];
 859         u_int8_t fpIoTimeoutForLd;
 860         u_int8_t reserved2[3];
 861         u_int32_t logicalBlockLength;
 862         struct {
 863                 u_int32_t LdPiExp:4;
 864                 u_int32_t LdLogicalBlockExp:4;
 865                 u_int32_t reserved1:24;
 866         }       exponent;
 867         u_int8_t reserved3[0x80 - 0x38];
 868 }       MR_LD_RAID;
 869
 870 typedef struct _MR_LD_SPAN_MAP {
 871         MR_LD_RAID ldRaid;
 872         u_int8_t dataArmMap[MAX_RAIDMAP_ROW_SIZE];
 873         MR_SPAN_BLOCK_INFO spanBlock[MAX_RAIDMAP_SPAN_DEPTH];
 874 }       MR_LD_SPAN_MAP;
 875
 876 typedef struct _MR_FW_RAID_MAP {
 877         u_int32_t totalSize;
 878         union {
 879                 struct {
 880                         u_int32_t maxLd;
 881                         u_int32_t maxSpanDepth;
 882                         u_int32_t maxRowSize;
 883                         u_int32_t maxPdCount;
 884                         u_int32_t maxArrays;
 885                 }       validationInfo;
 886                 u_int32_t version[5];
 887                 u_int32_t reserved1[5];
 888         }       raid_desc;
 889         u_int32_t ldCount;
 890         u_int32_t Reserved1;
 891
 892         /*
 893          * This doesn't correspond to FW Ld Tgt Id to LD, but will purge. For
 894          * example: if tgt Id is 4 and FW LD is 2, and there is only one LD,
 895          * FW will populate the array like this. [0xFF, 0xFF, 0xFF, 0xFF,
 896          * 0x0,.....]. This is to help reduce the entire strcture size if
 897          * there are few LDs or driver is looking info for 1 LD only.
 898          */
 899         u_int8_t ldTgtIdToLd[MAX_RAIDMAP_LOGICAL_DRIVES + MAX_RAIDMAP_VIEWS];
 900         u_int8_t fpPdIoTimeoutSec;
 901         u_int8_t reserved2[7];
 902         MR_ARRAY_INFO arMapInfo[MAX_RAIDMAP_ARRAYS];
 903         MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES];
 904         MR_LD_SPAN_MAP ldSpanMap[1];
 905 }       MR_FW_RAID_MAP;
 906
 907
 908 typedef struct _MR_FW_RAID_MAP_EXT {
 909         /* Not used in new map */
 910         u_int32_t reserved;
 911
 912         union {
 913                 struct {
 914                         u_int32_t maxLd;
 915                         u_int32_t maxSpanDepth;
 916                         u_int32_t maxRowSize;
 917                         u_int32_t maxPdCount;
 918                         u_int32_t maxArrays;
 919                 }       validationInfo;
 920                 u_int32_t version[5];
 921                 u_int32_t reserved1[5];
 922         }       fw_raid_desc;
 923
 924         u_int8_t fpPdIoTimeoutSec;
 925         u_int8_t reserved2[7];
 926
 927         u_int16_t ldCount;
 928         u_int16_t arCount;
 929         u_int16_t spanCount;
 930         u_int16_t reserve3;
 931
 932         MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES];
 933         u_int8_t ldTgtIdToLd[MAX_LOGICAL_DRIVES_EXT];
 934         MR_ARRAY_INFO arMapInfo[MAX_API_ARRAYS_EXT];
 935         MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES_EXT];
 936 }       MR_FW_RAID_MAP_EXT;
 937
 938
 939 typedef struct _MR_DRV_RAID_MAP {
 940         /*
 941          * Total size of this structure, including this field. This feild
 942          * will be manupulated by driver for ext raid map, else pick the
 943          * value from firmware raid map.
 944          */
 945         u_int32_t totalSize;
 946
 947         union {
 948                 struct {
 949                         u_int32_t maxLd;
 950                         u_int32_t maxSpanDepth;
 951                         u_int32_t maxRowSize;
 952                         u_int32_t maxPdCount;
 953                         u_int32_t maxArrays;
 954                 }       validationInfo;
 955                 u_int32_t version[5];
 956                 u_int32_t reserved1[5];
 957         }       drv_raid_desc;
 958
 959         /* timeout value used by driver in FP IOs */
 960         u_int8_t fpPdIoTimeoutSec;
 961         u_int8_t reserved2[7];
 962
 963         u_int16_t ldCount;
 964         u_int16_t arCount;
 965         u_int16_t spanCount;
 966         u_int16_t reserve3;
 967
 968         MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES_DYN];
 969         u_int16_t ldTgtIdToLd[MAX_LOGICAL_DRIVES_DYN];
 970         MR_ARRAY_INFO arMapInfo[MAX_API_ARRAYS_DYN];
 971         MR_LD_SPAN_MAP ldSpanMap[1];
 972
 973 }       MR_DRV_RAID_MAP;
 974
 975 /*
 976  * Driver raid map size is same as raid map ext MR_DRV_RAID_MAP_ALL is
 977  * created to sync with old raid. And it is mainly for code re-use purpose.
 978  */
 979
 980 #pragma pack(1)
 981 typedef struct _MR_DRV_RAID_MAP_ALL {
 982
 983         MR_DRV_RAID_MAP raidMap;
 984         MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES_DYN - 1];
 985 }       MR_DRV_RAID_MAP_ALL;
 986
 987 #pragma pack()
 988
 989 typedef struct _LD_LOAD_BALANCE_INFO {
 990         u_int8_t loadBalanceFlag;
 991         u_int8_t reserved1;
 992         mrsas_atomic_t scsi_pending_cmds[MAX_PHYSICAL_DEVICES];
 993         u_int64_t last_accessed_block[MAX_PHYSICAL_DEVICES];
 994 }       LD_LOAD_BALANCE_INFO, *PLD_LOAD_BALANCE_INFO;
 995
 996 /* SPAN_SET is info caclulated from span info from Raid map per ld */
 997 typedef struct _LD_SPAN_SET {
 998         u_int64_t log_start_lba;
 999         u_int64_t log_end_lba;
1000         u_int64_t span_row_start;
1001         u_int64_t span_row_end;
1002         u_int64_t data_strip_start;
1003         u_int64_t data_strip_end;
1004         u_int64_t data_row_start;
1005         u_int64_t data_row_end;
1006         u_int8_t strip_offset[MAX_SPAN_DEPTH];
1007         u_int32_t span_row_data_width;
1008         u_int32_t diff;
1009         u_int32_t reserved[2];
1010 }       LD_SPAN_SET, *PLD_SPAN_SET;
1011
1012 typedef struct LOG_BLOCK_SPAN_INFO {
1013         LD_SPAN_SET span_set[MAX_SPAN_DEPTH];
1014 }       LD_SPAN_INFO, *PLD_SPAN_INFO;
1015
1016 #pragma pack(1)
1017 typedef struct _MR_FW_RAID_MAP_ALL {
1018         MR_FW_RAID_MAP raidMap;
1019         MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES - 1];
1020 }       MR_FW_RAID_MAP_ALL;
1021
1022 #pragma pack()
1023
1024 struct IO_REQUEST_INFO {
1025         u_int64_t ldStartBlock;
1026         u_int32_t numBlocks;
1027         u_int16_t ldTgtId;
1028         u_int8_t isRead;
1029         u_int16_t devHandle;
1030         u_int8_t pdInterface;
1031         u_int64_t pdBlock;
1032         u_int8_t fpOkForIo;
1033         u_int8_t IoforUnevenSpan;
1034         u_int8_t start_span;
1035         u_int8_t reserved;
1036         u_int64_t start_row;
1037         /* span[7:5], arm[4:0] */
1038         u_int8_t span_arm;
1039         u_int8_t pd_after_lb;
1040         boolean_t raCapable;
1041         u_int16_t r1_alt_dev_handle;
1042 };
1043
1044 /*
1045  * define MR_PD_CFG_SEQ structure for system PDs
1046  */
1047 struct MR_PD_CFG_SEQ {
1048         u_int16_t seqNum;
1049         u_int16_t devHandle;
1050         struct {
1051                 u_int8_t tmCapable:1;
1052                 u_int8_t reserved:7;
1053         } capability;
1054         u_int8_t reserved;
1055         u_int16_t pdTargetId;
1056 } __packed;
1057
1058 struct MR_PD_CFG_SEQ_NUM_SYNC {
1059         u_int32_t size;
1060         u_int32_t count;
1061         struct MR_PD_CFG_SEQ seq[1];
1062 } __packed;
1063
1064 typedef struct _STREAM_DETECT {
1065         u_int64_t nextSeqLBA;
1066         struct megasas_cmd_fusion *first_cmd_fusion;
1067         struct megasas_cmd_fusion *last_cmd_fusion;
1068         u_int32_t countCmdsInStream;
1069         u_int16_t numSGEsInGroup;
1070         u_int8_t isRead;
1071         u_int8_t groupDepth;
1072         boolean_t groupFlush;
1073         u_int8_t reserved[7];
1074 } STREAM_DETECT, *PTR_STREAM_DETECT;
1075
1076 typedef struct _LD_STREAM_DETECT {
1077         boolean_t writeBack;
1078         boolean_t FPWriteEnabled;
1079         boolean_t membersSSDs;
1080         boolean_t fpCacheBypassCapable;
1081         u_int32_t mruBitMap;
1082         volatile long iosToFware;
1083         volatile long writeBytesOutstanding;
1084         STREAM_DETECT streamTrack[MAX_STREAMS_TRACKED];
1085 } LD_STREAM_DETECT, *PTR_LD_STREAM_DETECT;
1086
1087
1088 typedef struct _MR_LD_TARGET_SYNC {
1089         u_int8_t targetId;
1090         u_int8_t reserved;
1091         u_int16_t seqNum;
1092 }       MR_LD_TARGET_SYNC;
1093
1094
1095 /*
1096  * RAID Map descriptor Types.
1097  * Each element should uniquely idetify one data structure in the RAID map
1098  */
1099 typedef enum _MR_RAID_MAP_DESC_TYPE {
1100         RAID_MAP_DESC_TYPE_DEVHDL_INFO = 0,     /* MR_DEV_HANDLE_INFO data */
1101         RAID_MAP_DESC_TYPE_TGTID_INFO = 1,      /* target to Ld num Index map */
1102         RAID_MAP_DESC_TYPE_ARRAY_INFO = 2,      /* MR_ARRAY_INFO data */
1103         RAID_MAP_DESC_TYPE_SPAN_INFO = 3,       /* MR_LD_SPAN_MAP data */
1104         RAID_MAP_DESC_TYPE_COUNT,
1105 }       MR_RAID_MAP_DESC_TYPE;
1106
1107 /*
1108  * This table defines the offset, size and num elements  of each descriptor
1109  * type in the RAID Map buffer
1110  */
1111 typedef struct _MR_RAID_MAP_DESC_TABLE {
1112         /* Raid map descriptor type */
1113         u_int32_t       raidMapDescType;
1114         /* Offset into the RAID map buffer where descriptor data is saved */
1115         u_int32_t       raidMapDescOffset;
1116         /* total size of the descriptor buffer */
1117         u_int32_t       raidMapDescBufferSize;
1118         /* Number of elements contained in the descriptor buffer */
1119         u_int32_t       raidMapDescElements;
1120 }       MR_RAID_MAP_DESC_TABLE;
1121
1122 /*
1123  * Dynamic Raid Map Structure.
1124  */
1125 typedef struct _MR_FW_RAID_MAP_DYNAMIC {
1126         u_int32_t       raidMapSize;
1127         u_int32_t       descTableOffset;
1128         u_int32_t       descTableSize;
1129         u_int32_t       descTableNumElements;
1130         u_int64_t       PCIThresholdBandwidth;
1131         u_int32_t       reserved2[3];
1132
1133         u_int8_t        fpPdIoTimeoutSec;
1134         u_int8_t        reserved3[3];
1135         u_int32_t       rmwFPSeqNum;
1136         u_int16_t       ldCount;
1137         u_int16_t       arCount;
1138         u_int16_t       spanCount;
1139         u_int16_t       reserved4[3];
1140
1141         /*
1142         * The below structure of pointers is only to be used by the driver.
1143         * This is added in the API to reduce the amount of code changes needed in
1144         * the driver to support dynamic RAID map.
1145         * Firmware should not update these pointers while preparing the raid map
1146         */
1147         union {
1148                 struct {
1149                         MR_DEV_HANDLE_INFO      *devHndlInfo;
1150                         u_int16_t                       *ldTgtIdToLd;
1151                         MR_ARRAY_INFO           *arMapInfo;
1152                         MR_LD_SPAN_MAP          *ldSpanMap;
1153                 } ptrStruct;
1154                 u_int64_t ptrStructureSize[RAID_MAP_DESC_TYPE_COUNT];
1155         } RaidMapDescPtrs;
1156
1157         /*
1158         * RAID Map descriptor table defines the layout of data in the RAID Map.
1159         * The size of the descriptor table itself could change.
1160         */
1161
1162         /* Variable Size descriptor Table. */
1163         MR_RAID_MAP_DESC_TABLE raidMapDescTable[RAID_MAP_DESC_TYPE_COUNT];
1164         /* Variable Size buffer containing all data */
1165         u_int32_t raidMapDescData[1];
1166
1167 }       MR_FW_RAID_MAP_DYNAMIC;
1168
1169
1170 #define IEEE_SGE_FLAGS_ADDR_MASK                (0x03)
1171 #define IEEE_SGE_FLAGS_SYSTEM_ADDR              (0x00)
1172 #define IEEE_SGE_FLAGS_IOCDDR_ADDR              (0x01)
1173 #define IEEE_SGE_FLAGS_IOCPLB_ADDR              (0x02)
1174 #define IEEE_SGE_FLAGS_IOCPLBNTA_ADDR   (0x03)
1175 #define IEEE_SGE_FLAGS_CHAIN_ELEMENT    (0x80)
1176 #define IEEE_SGE_FLAGS_END_OF_LIST              (0x40)
1177
1178 /* Few NVME flags defines*/
1179 #define MPI2_SGE_FLAGS_SHIFT                (0x02)
1180 #define IEEE_SGE_FLAGS_FORMAT_MASK          (0xC0)
1181 #define IEEE_SGE_FLAGS_FORMAT_IEEE          (0x00)
1182 #define IEEE_SGE_FLAGS_FORMAT_PQI           (0x01)
1183 #define IEEE_SGE_FLAGS_FORMAT_NVME          (0x02)
1184 #define IEEE_SGE_FLAGS_FORMAT_AHCI          (0x03)
1185
1186
1187 #define MPI26_IEEE_SGE_FLAGS_NSF_MASK           (0x1C)
1188 #define MPI26_IEEE_SGE_FLAGS_NSF_MPI_IEEE       (0x00)
1189 #define MPI26_IEEE_SGE_FLAGS_NSF_PQI            (0x04)
1190 #define MPI26_IEEE_SGE_FLAGS_NSF_NVME_PRP       (0x08)
1191 #define MPI26_IEEE_SGE_FLAGS_NSF_AHCI_PRDT      (0x0C)
1192 #define MPI26_IEEE_SGE_FLAGS_NSF_NVME_SGL       (0x10)
1193
1194 union desc_value {
1195         u_int64_t word;
1196         struct {
1197                 u_int32_t low;
1198                 u_int32_t high;
1199         }       u;
1200 };
1201
1202 /*******************************************************************
1203  * Temporary command
1204  ********************************************************************/
1205 struct mrsas_tmp_dcmd {
1206         bus_dma_tag_t tmp_dcmd_tag;
1207         bus_dmamap_t tmp_dcmd_dmamap;
1208         void   *tmp_dcmd_mem;
1209         bus_addr_t tmp_dcmd_phys_addr;
1210 };
1211
1212 #define MR_MAX_RAID_MAP_SIZE_OFFSET_SHIFT  16
1213 #define MR_MAX_RAID_MAP_SIZE_MASK      0x1FF
1214 #define MR_MIN_MAP_SIZE                0x10000
1215
1216
1217 /*******************************************************************
1218  * Register set, included legacy controllers 1068 and 1078,
1219  * structure extended for 1078 registers
1220  *******************************************************************/
1221 #pragma pack(1)
1222 typedef struct _mrsas_register_set {
1223         u_int32_t doorbell;             /* 0000h */
1224         u_int32_t fusion_seq_offset;    /* 0004h */
1225         u_int32_t fusion_host_diag;     /* 0008h */
1226         u_int32_t reserved_01;          /* 000Ch */
1227
1228         u_int32_t inbound_msg_0;        /* 0010h */
1229         u_int32_t inbound_msg_1;        /* 0014h */
1230         u_int32_t outbound_msg_0;       /* 0018h */
1231         u_int32_t outbound_msg_1;       /* 001Ch */
1232
1233         u_int32_t inbound_doorbell;     /* 0020h */
1234         u_int32_t inbound_intr_status;  /* 0024h */
1235         u_int32_t inbound_intr_mask;    /* 0028h */
1236
1237         u_int32_t outbound_doorbell;    /* 002Ch */
1238         u_int32_t outbound_intr_status; /* 0030h */
1239         u_int32_t outbound_intr_mask;   /* 0034h */
1240
1241         u_int32_t reserved_1[2];        /* 0038h */
1242
1243         u_int32_t inbound_queue_port;   /* 0040h */
1244         u_int32_t outbound_queue_port;  /* 0044h */
1245
1246         u_int32_t reserved_2[9];        /* 0048h */
1247         u_int32_t reply_post_host_index;/* 006Ch */
1248         u_int32_t reserved_2_2[12];     /* 0070h */
1249
1250         u_int32_t outbound_doorbell_clear;      /* 00A0h */
1251
1252         u_int32_t reserved_3[3];        /* 00A4h */
1253
1254         u_int32_t outbound_scratch_pad; /* 00B0h */
1255         u_int32_t outbound_scratch_pad_2;       /* 00B4h */
1256         u_int32_t outbound_scratch_pad_3;       /* 00B8h */
1257         u_int32_t outbound_scratch_pad_4;       /* 00BCh */
1258
1259         u_int32_t inbound_low_queue_port;       /* 00C0h */
1260
1261         u_int32_t inbound_high_queue_port;      /* 00C4h */
1262
1263         u_int32_t inbound_single_queue_port;    /* 00C8h */
1264         u_int32_t res_6[11];            /* CCh */
1265         u_int32_t host_diag;
1266         u_int32_t seq_offset;
1267         u_int32_t index_registers[807]; /* 00CCh */
1268 }       mrsas_reg_set;
1269
1270 #pragma pack()
1271
1272 /*******************************************************************
1273  * Firmware Interface Defines
1274  *******************************************************************
1275  * MFI stands for MegaRAID SAS FW Interface. This is just a moniker
1276  * for protocol between the software and firmware. Commands are
1277  * issued using "message frames".
1278  ******************************************************************/
1279 /*
1280  * FW posts its state in upper 4 bits of outbound_msg_0 register
1281  */
1282 #define MFI_STATE_MASK                                  0xF0000000
1283 #define MFI_STATE_UNDEFINED                             0x00000000
1284 #define MFI_STATE_BB_INIT                               0x10000000
1285 #define MFI_STATE_FW_INIT                               0x40000000
1286 #define MFI_STATE_WAIT_HANDSHAKE                0x60000000
1287 #define MFI_STATE_FW_INIT_2                             0x70000000
1288 #define MFI_STATE_DEVICE_SCAN                   0x80000000
1289 #define MFI_STATE_BOOT_MESSAGE_PENDING  0x90000000
1290 #define MFI_STATE_FLUSH_CACHE                   0xA0000000
1291 #define MFI_STATE_READY                                 0xB0000000
1292 #define MFI_STATE_OPERATIONAL                   0xC0000000
1293 #define MFI_STATE_FAULT                                 0xF0000000
1294 #define MFI_RESET_REQUIRED                              0x00000001
1295 #define MFI_RESET_ADAPTER                               0x00000002
1296 #define MEGAMFI_FRAME_SIZE                              64
1297 #define MRSAS_MFI_FRAME_SIZE                    1024
1298 #define MRSAS_MFI_SENSE_SIZE                    128
1299
1300 /*
1301  * During FW init, clear pending cmds & reset state using inbound_msg_0
1302  *
1303  * ABORT        : Abort all pending cmds READY        : Move from OPERATIONAL to
1304  * READY state; discard queue info MFIMODE      : Discard (possible) low MFA
1305  * posted in 64-bit mode (??) CLR_HANDSHAKE: FW is waiting for HANDSHAKE from
1306  * BIOS or Driver HOTPLUG      : Resume from Hotplug MFI_STOP_ADP : Send
1307  * signal to FW to stop processing
1308  */
1309
1310 #define WRITE_SEQUENCE_OFFSET           (0x0000000FC)
1311 #define HOST_DIAGNOSTIC_OFFSET          (0x000000F8)
1312 #define DIAG_WRITE_ENABLE                       (0x00000080)
1313 #define DIAG_RESET_ADAPTER                      (0x00000004)
1314
1315 #define MFI_ADP_RESET                           0x00000040
1316 #define MFI_INIT_ABORT                          0x00000001
1317 #define MFI_INIT_READY                          0x00000002
1318 #define MFI_INIT_MFIMODE                        0x00000004
1319 #define MFI_INIT_CLEAR_HANDSHAKE        0x00000008
1320 #define MFI_INIT_HOTPLUG                        0x00000010
1321 #define MFI_STOP_ADP                            0x00000020
1322 #define MFI_RESET_FLAGS                         MFI_INIT_READY|         \
1323                                                                         MFI_INIT_MFIMODE|       \
1324                                                                         MFI_INIT_ABORT
1325
1326 /*
1327  * MFI frame flags
1328  */
1329 #define MFI_FRAME_POST_IN_REPLY_QUEUE                   0x0000
1330 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE              0x0001
1331 #define MFI_FRAME_SGL32                                                 0x0000
1332 #define MFI_FRAME_SGL64                                                 0x0002
1333 #define MFI_FRAME_SENSE32                                               0x0000
1334 #define MFI_FRAME_SENSE64                                               0x0004
1335 #define MFI_FRAME_DIR_NONE                                              0x0000
1336 #define MFI_FRAME_DIR_WRITE                                             0x0008
1337 #define MFI_FRAME_DIR_READ                                              0x0010
1338 #define MFI_FRAME_DIR_BOTH                                              0x0018
1339 #define MFI_FRAME_IEEE                                                  0x0020
1340
1341 /*
1342  * Definition for cmd_status
1343  */
1344 #define MFI_CMD_STATUS_POLL_MODE                                0xFF
1345
1346 /*
1347  * MFI command opcodes
1348  */
1349 #define MFI_CMD_INIT                                                    0x00
1350 #define MFI_CMD_LD_READ                                                 0x01
1351 #define MFI_CMD_LD_WRITE                                                0x02
1352 #define MFI_CMD_LD_SCSI_IO                                              0x03
1353 #define MFI_CMD_PD_SCSI_IO                                              0x04
1354 #define MFI_CMD_DCMD                                                    0x05
1355 #define MFI_CMD_ABORT                                                   0x06
1356 #define MFI_CMD_SMP                                                             0x07
1357 #define MFI_CMD_STP                                                             0x08
1358 #define MFI_CMD_INVALID                                                 0xff
1359
1360 #define MR_DCMD_CTRL_GET_INFO                                   0x01010000
1361 #define MR_DCMD_LD_GET_LIST                                             0x03010000
1362 #define MR_DCMD_CTRL_CACHE_FLUSH                                0x01101000
1363 #define MR_FLUSH_CTRL_CACHE                                             0x01
1364 #define MR_FLUSH_DISK_CACHE                                             0x02
1365
1366 #define MR_DCMD_CTRL_SHUTDOWN                                   0x01050000
1367 #define MR_DCMD_HIBERNATE_SHUTDOWN                              0x01060000
1368 #define MR_ENABLE_DRIVE_SPINDOWN                                0x01
1369
1370 #define MR_DCMD_CTRL_EVENT_GET_INFO                             0x01040100
1371 #define MR_DCMD_CTRL_EVENT_GET                                  0x01040300
1372 #define MR_DCMD_CTRL_EVENT_WAIT                                 0x01040500
1373 #define MR_DCMD_LD_GET_PROPERTIES                               0x03030000
1374
1375 #define MR_DCMD_CLUSTER                                                 0x08000000
1376 #define MR_DCMD_CLUSTER_RESET_ALL                               0x08010100
1377 #define MR_DCMD_CLUSTER_RESET_LD                                0x08010200
1378 #define MR_DCMD_PD_LIST_QUERY                                   0x02010100
1379
1380 #define MR_DCMD_CTRL_MISC_CPX                                   0x0100e200
1381 #define MR_DCMD_CTRL_MISC_CPX_INIT_DATA_GET             0x0100e201
1382 #define MR_DCMD_CTRL_MISC_CPX_QUEUE_DATA                0x0100e202
1383 #define MR_DCMD_CTRL_MISC_CPX_UNREGISTER                0x0100e203
1384 #define MAX_MR_ROW_SIZE                                                 32
1385 #define MR_CPX_DIR_WRITE                                                1
1386 #define MR_CPX_DIR_READ                                                 0
1387 #define MR_CPX_VERSION                                                  1
1388
1389 #define MR_DCMD_CTRL_IO_METRICS_GET                             0x01170200
1390
1391 #define MR_EVT_CFG_CLEARED                                              0x0004
1392
1393 #define MR_EVT_LD_STATE_CHANGE                                  0x0051
1394 #define MR_EVT_PD_INSERTED                                              0x005b
1395 #define MR_EVT_PD_REMOVED                                               0x0070
1396 #define MR_EVT_LD_CREATED                                               0x008a
1397 #define MR_EVT_LD_DELETED                                               0x008b
1398 #define MR_EVT_FOREIGN_CFG_IMPORTED                             0x00db
1399 #define MR_EVT_LD_OFFLINE                                               0x00fc
1400 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED             0x0152
1401 #define MR_EVT_CTRL_PERF_COLLECTION                             0x017e
1402
1403 /*
1404  * MFI command completion codes
1405  */
1406 enum MFI_STAT {
1407         MFI_STAT_OK = 0x00,
1408         MFI_STAT_INVALID_CMD = 0x01,
1409         MFI_STAT_INVALID_DCMD = 0x02,
1410         MFI_STAT_INVALID_PARAMETER = 0x03,
1411         MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04,
1412         MFI_STAT_ABORT_NOT_POSSIBLE = 0x05,
1413         MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06,
1414         MFI_STAT_APP_IN_USE = 0x07,
1415         MFI_STAT_APP_NOT_INITIALIZED = 0x08,
1416         MFI_STAT_ARRAY_INDEX_INVALID = 0x09,
1417         MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a,
1418         MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b,
1419         MFI_STAT_DEVICE_NOT_FOUND = 0x0c,
1420         MFI_STAT_DRIVE_TOO_SMALL = 0x0d,
1421         MFI_STAT_FLASH_ALLOC_FAIL = 0x0e,
1422         MFI_STAT_FLASH_BUSY = 0x0f,
1423         MFI_STAT_FLASH_ERROR = 0x10,
1424         MFI_STAT_FLASH_IMAGE_BAD = 0x11,
1425         MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12,
1426         MFI_STAT_FLASH_NOT_OPEN = 0x13,
1427         MFI_STAT_FLASH_NOT_STARTED = 0x14,
1428         MFI_STAT_FLUSH_FAILED = 0x15,
1429         MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16,
1430         MFI_STAT_LD_CC_IN_PROGRESS = 0x17,
1431         MFI_STAT_LD_INIT_IN_PROGRESS = 0x18,
1432         MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19,
1433         MFI_STAT_LD_MAX_CONFIGURED = 0x1a,
1434         MFI_STAT_LD_NOT_OPTIMAL = 0x1b,
1435         MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c,
1436         MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d,
1437         MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e,
1438         MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f,
1439         MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
1440         MFI_STAT_MFC_HW_ERROR = 0x21,
1441         MFI_STAT_NO_HW_PRESENT = 0x22,
1442         MFI_STAT_NOT_FOUND = 0x23,
1443         MFI_STAT_NOT_IN_ENCL = 0x24,
1444         MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25,
1445         MFI_STAT_PD_TYPE_WRONG = 0x26,
1446         MFI_STAT_PR_DISABLED = 0x27,
1447         MFI_STAT_ROW_INDEX_INVALID = 0x28,
1448         MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29,
1449         MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a,
1450         MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b,
1451         MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c,
1452         MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d,
1453         MFI_STAT_SCSI_IO_FAILED = 0x2e,
1454         MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f,
1455         MFI_STAT_SHUTDOWN_FAILED = 0x30,
1456         MFI_STAT_TIME_NOT_SET = 0x31,
1457         MFI_STAT_WRONG_STATE = 0x32,
1458         MFI_STAT_LD_OFFLINE = 0x33,
1459         MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34,
1460         MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35,
1461         MFI_STAT_RESERVATION_IN_PROGRESS = 0x36,
1462         MFI_STAT_I2C_ERRORS_DETECTED = 0x37,
1463         MFI_STAT_PCI_ERRORS_DETECTED = 0x38,
1464         MFI_STAT_CONFIG_SEQ_MISMATCH = 0x67,
1465
1466         MFI_STAT_INVALID_STATUS = 0xFF
1467 };
1468
1469 /*
1470  * Number of mailbox bytes in DCMD message frame
1471  */
1472 #define MFI_MBOX_SIZE   12
1473
1474 enum MR_EVT_CLASS {
1475
1476         MR_EVT_CLASS_DEBUG = -2,
1477         MR_EVT_CLASS_PROGRESS = -1,
1478         MR_EVT_CLASS_INFO = 0,
1479         MR_EVT_CLASS_WARNING = 1,
1480         MR_EVT_CLASS_CRITICAL = 2,
1481         MR_EVT_CLASS_FATAL = 3,
1482         MR_EVT_CLASS_DEAD = 4,
1483
1484 };
1485
1486 enum MR_EVT_LOCALE {
1487
1488         MR_EVT_LOCALE_LD = 0x0001,
1489         MR_EVT_LOCALE_PD = 0x0002,
1490         MR_EVT_LOCALE_ENCL = 0x0004,
1491         MR_EVT_LOCALE_BBU = 0x0008,
1492         MR_EVT_LOCALE_SAS = 0x0010,
1493         MR_EVT_LOCALE_CTRL = 0x0020,
1494         MR_EVT_LOCALE_CONFIG = 0x0040,
1495         MR_EVT_LOCALE_CLUSTER = 0x0080,
1496         MR_EVT_LOCALE_ALL = 0xffff,
1497
1498 };
1499
1500 enum MR_EVT_ARGS {
1501
1502         MR_EVT_ARGS_NONE,
1503         MR_EVT_ARGS_CDB_SENSE,
1504         MR_EVT_ARGS_LD,
1505         MR_EVT_ARGS_LD_COUNT,
1506         MR_EVT_ARGS_LD_LBA,
1507         MR_EVT_ARGS_LD_OWNER,
1508         MR_EVT_ARGS_LD_LBA_PD_LBA,
1509         MR_EVT_ARGS_LD_PROG,
1510         MR_EVT_ARGS_LD_STATE,
1511         MR_EVT_ARGS_LD_STRIP,
1512         MR_EVT_ARGS_PD,
1513         MR_EVT_ARGS_PD_ERR,
1514         MR_EVT_ARGS_PD_LBA,
1515         MR_EVT_ARGS_PD_LBA_LD,
1516         MR_EVT_ARGS_PD_PROG,
1517         MR_EVT_ARGS_PD_STATE,
1518         MR_EVT_ARGS_PCI,
1519         MR_EVT_ARGS_RATE,
1520         MR_EVT_ARGS_STR,
1521         MR_EVT_ARGS_TIME,
1522         MR_EVT_ARGS_ECC,
1523         MR_EVT_ARGS_LD_PROP,
1524         MR_EVT_ARGS_PD_SPARE,
1525         MR_EVT_ARGS_PD_INDEX,
1526         MR_EVT_ARGS_DIAG_PASS,
1527         MR_EVT_ARGS_DIAG_FAIL,
1528         MR_EVT_ARGS_PD_LBA_LBA,
1529         MR_EVT_ARGS_PORT_PHY,
1530         MR_EVT_ARGS_PD_MISSING,
1531         MR_EVT_ARGS_PD_ADDRESS,
1532         MR_EVT_ARGS_BITMAP,
1533         MR_EVT_ARGS_CONNECTOR,
1534         MR_EVT_ARGS_PD_PD,
1535         MR_EVT_ARGS_PD_FRU,
1536         MR_EVT_ARGS_PD_PATHINFO,
1537         MR_EVT_ARGS_PD_POWER_STATE,
1538         MR_EVT_ARGS_GENERIC,
1539 };
1540
1541 /*
1542  * Thunderbolt (and later) Defines
1543  */
1544 #define MEGASAS_CHAIN_FRAME_SZ_MIN                                      1024
1545 #define MFI_FUSION_ENABLE_INTERRUPT_MASK                        (0x00000009)
1546 #define MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE           256
1547 #define MRSAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST         0xF0
1548 #define MRSAS_MPI2_FUNCTION_LD_IO_REQUEST                       0xF1
1549 #define MRSAS_LOAD_BALANCE_FLAG                                         0x1
1550 #define MRSAS_DCMD_MBOX_PEND_FLAG                                       0x1
1551 #define HOST_DIAG_WRITE_ENABLE                                          0x80
1552 #define HOST_DIAG_RESET_ADAPTER                                         0x4
1553 #define MRSAS_TBOLT_MAX_RESET_TRIES                                     3
1554 #define MRSAS_MAX_MFI_CMDS                          16
1555 #define MRSAS_MAX_IOCTL_CMDS                        3
1556
1557 /*
1558  * Invader Defines
1559  */
1560 #define MPI2_TYPE_CUDA                                                          0x2
1561 #define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH       0x4000
1562 #define MR_RL_FLAGS_GRANT_DESTINATION_CPU0                      0x00
1563 #define MR_RL_FLAGS_GRANT_DESTINATION_CPU1                      0x10
1564 #define MR_RL_FLAGS_GRANT_DESTINATION_CUDA                      0x80
1565 #define MR_RL_FLAGS_SEQ_NUM_ENABLE                                      0x8
1566 #define MR_RL_WRITE_THROUGH_MODE                                        0x00
1567 #define MR_RL_WRITE_BACK_MODE                                           0x01
1568
1569 /*
1570  * T10 PI defines
1571  */
1572 #define MR_PROT_INFO_TYPE_CONTROLLER                            0x8
1573 #define MRSAS_SCSI_VARIABLE_LENGTH_CMD                          0x7f
1574 #define MRSAS_SCSI_SERVICE_ACTION_READ32                        0x9
1575 #define MRSAS_SCSI_SERVICE_ACTION_WRITE32                       0xB
1576 #define MRSAS_SCSI_ADDL_CDB_LEN                                         0x18
1577 #define MRSAS_RD_WR_PROTECT_CHECK_ALL                           0x20
1578 #define MRSAS_RD_WR_PROTECT_CHECK_NONE                          0x60
1579 #define MRSAS_SCSIBLOCKSIZE                                                     512
1580
1581 /*
1582  * Raid context flags
1583  */
1584 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_SHIFT        0x4
1585 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_MASK         0x30
1586 typedef enum MR_RAID_FLAGS_IO_SUB_TYPE {
1587         MR_RAID_FLAGS_IO_SUB_TYPE_NONE = 0,
1588         MR_RAID_FLAGS_IO_SUB_TYPE_SYSTEM_PD = 1,
1589         MR_RAID_FLAGS_IO_SUB_TYPE_RMW_DATA = 2,
1590         MR_RAID_FLAGS_IO_SUB_TYPE_RMW_P = 3,
1591         MR_RAID_FLAGS_IO_SUB_TYPE_RMW_Q = 4,
1592         MR_RAID_FLAGS_IO_SUB_TYPE_CACHE_BYPASS = 6,
1593         MR_RAID_FLAGS_IO_SUB_TYPE_LDIO_BW_LIMIT = 7
1594 } MR_RAID_FLAGS_IO_SUB_TYPE;
1595 /*
1596  * Request descriptor types
1597  */
1598 #define MRSAS_REQ_DESCRIPT_FLAGS_LD_IO          0x7
1599 #define MRSAS_REQ_DESCRIPT_FLAGS_MFA            0x1
1600 #define MRSAS_REQ_DESCRIPT_FLAGS_NO_LOCK        0x2
1601 #define MRSAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT     1
1602 #define MRSAS_FP_CMD_LEN                                        16
1603 #define MRSAS_FUSION_IN_RESET                           0
1604
1605 #define RAID_CTX_SPANARM_ARM_SHIFT                      (0)
1606 #define RAID_CTX_SPANARM_ARM_MASK                       (0x1f)
1607 #define RAID_CTX_SPANARM_SPAN_SHIFT                     (5)
1608 #define RAID_CTX_SPANARM_SPAN_MASK                      (0xE0)
1609
1610 /*
1611  * Define region lock types
1612  */
1613 typedef enum _REGION_TYPE {
1614         REGION_TYPE_UNUSED = 0,
1615         REGION_TYPE_SHARED_READ = 1,
1616         REGION_TYPE_SHARED_WRITE = 2,
1617         REGION_TYPE_EXCLUSIVE = 3,
1618 }       REGION_TYPE;
1619
1620
1621 /*
1622  * SCSI-CAM Related Defines
1623  */
1624 #define MRSAS_SCSI_MAX_LUNS                             0
1625 #define MRSAS_SCSI_INITIATOR_ID                 255
1626 #define MRSAS_SCSI_MAX_CMDS                             8
1627 #define MRSAS_SCSI_MAX_CDB_LEN                  16
1628 #define MRSAS_SCSI_SENSE_BUFFERSIZE             96
1629 #define MRSAS_INTERNAL_CMDS                             32
1630 #define MRSAS_FUSION_INT_CMDS                   8
1631
1632 #define MEGASAS_MAX_CHAIN_SIZE_UNITS_MASK       0x400000
1633 #define MEGASAS_MAX_CHAIN_SIZE_MASK             0x3E0
1634 #define MEGASAS_256K_IO                                 128
1635 #define MEGASAS_1MB_IO                                  (MEGASAS_256K_IO * 4)
1636
1637 /* Request types */
1638 #define MRSAS_REQ_TYPE_INTERNAL_CMD             0x0
1639 #define MRSAS_REQ_TYPE_AEN_FETCH                0x1
1640 #define MRSAS_REQ_TYPE_PASSTHRU                 0x2
1641 #define MRSAS_REQ_TYPE_GETSET_PARAM             0x3
1642 #define MRSAS_REQ_TYPE_SCSI_IO                  0x4
1643
1644 /* Request states */
1645 #define MRSAS_REQ_STATE_FREE                    0
1646 #define MRSAS_REQ_STATE_BUSY                    1
1647 #define MRSAS_REQ_STATE_TRAN                    2
1648 #define MRSAS_REQ_STATE_COMPLETE                3
1649
1650 typedef enum _MR_SCSI_CMD_TYPE {
1651         READ_WRITE_LDIO = 0,
1652         NON_READ_WRITE_LDIO = 1,
1653         READ_WRITE_SYSPDIO = 2,
1654         NON_READ_WRITE_SYSPDIO = 3,
1655 }       MR_SCSI_CMD_TYPE;
1656
1657 enum mrsas_req_flags {
1658         MRSAS_DIR_UNKNOWN = 0x1,
1659         MRSAS_DIR_IN = 0x2,
1660         MRSAS_DIR_OUT = 0x4,
1661         MRSAS_DIR_NONE = 0x8,
1662 };
1663
1664 /*
1665  * Adapter Reset States
1666  */
1667 enum {
1668         MRSAS_HBA_OPERATIONAL = 0,
1669         MRSAS_ADPRESET_SM_INFAULT = 1,
1670         MRSAS_ADPRESET_SM_FW_RESET_SUCCESS = 2,
1671         MRSAS_ADPRESET_SM_OPERATIONAL = 3,
1672         MRSAS_HW_CRITICAL_ERROR = 4,
1673         MRSAS_ADPRESET_INPROG_SIGN = 0xDEADDEAD,
1674 };
1675
1676 /*
1677  * MPT Command Structure
1678  */
1679 struct mrsas_mpt_cmd {
1680         MRSAS_RAID_SCSI_IO_REQUEST *io_request;
1681         bus_addr_t io_request_phys_addr;
1682         MPI2_SGE_IO_UNION *chain_frame;
1683         bus_addr_t chain_frame_phys_addr;
1684         u_int32_t sge_count;
1685         u_int8_t *sense;
1686         bus_addr_t sense_phys_addr;
1687         u_int8_t retry_for_fw_reset;
1688         MRSAS_REQUEST_DESCRIPTOR_UNION *request_desc;
1689         u_int32_t sync_cmd_idx;
1690         u_int32_t index;
1691         u_int8_t flags;
1692         u_int8_t pd_r1_lb;
1693         u_int8_t load_balance;
1694         bus_size_t length;
1695         u_int32_t error_code;
1696         bus_dmamap_t data_dmamap;
1697         void   *data;
1698         union ccb *ccb_ptr;
1699         struct callout cm_callout;
1700         struct mrsas_softc *sc;
1701         boolean_t tmCapable;
1702         u_int16_t r1_alt_dev_handle;
1703         boolean_t cmd_completed;
1704         struct mrsas_mpt_cmd *peer_cmd;
1705         bool    callout_owner;
1706         TAILQ_ENTRY(mrsas_mpt_cmd) next;
1707         u_int8_t pdInterface;
1708 };
1709
1710 /*
1711  * MFI Command Structure
1712  */
1713 struct mrsas_mfi_cmd {
1714         union mrsas_frame *frame;
1715         bus_dmamap_t frame_dmamap;
1716         void   *frame_mem;
1717         bus_addr_t frame_phys_addr;
1718         u_int8_t *sense;
1719         bus_dmamap_t sense_dmamap;
1720         void   *sense_mem;
1721         bus_addr_t sense_phys_addr;
1722         u_int32_t index;
1723         u_int8_t sync_cmd;
1724         u_int8_t cmd_status;
1725         u_int8_t abort_aen;
1726         u_int8_t retry_for_fw_reset;
1727         struct mrsas_softc *sc;
1728         union ccb *ccb_ptr;
1729         union {
1730                 struct {
1731                         u_int16_t smid;
1732                         u_int16_t resvd;
1733                 }       context;
1734                 u_int32_t frame_count;
1735         }       cmd_id;
1736         TAILQ_ENTRY(mrsas_mfi_cmd) next;
1737 };
1738
1739
1740 /*
1741  * define constants for device list query options
1742  */
1743 enum MR_PD_QUERY_TYPE {
1744         MR_PD_QUERY_TYPE_ALL = 0,
1745         MR_PD_QUERY_TYPE_STATE = 1,
1746         MR_PD_QUERY_TYPE_POWER_STATE = 2,
1747         MR_PD_QUERY_TYPE_MEDIA_TYPE = 3,
1748         MR_PD_QUERY_TYPE_SPEED = 4,
1749         MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5,
1750 };
1751
1752 #define MR_EVT_CFG_CLEARED                                              0x0004
1753 #define MR_EVT_LD_STATE_CHANGE                                  0x0051
1754 #define MR_EVT_PD_INSERTED                                              0x005b
1755 #define MR_EVT_PD_REMOVED                                               0x0070
1756 #define MR_EVT_LD_CREATED                                               0x008a
1757 #define MR_EVT_LD_DELETED                                               0x008b
1758 #define MR_EVT_FOREIGN_CFG_IMPORTED                             0x00db
1759 #define MR_EVT_LD_OFFLINE                                               0x00fc
1760 #define MR_EVT_CTRL_PROP_CHANGED                                0x012f
1761 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED             0x0152
1762
1763 enum MR_PD_STATE {
1764         MR_PD_STATE_UNCONFIGURED_GOOD = 0x00,
1765         MR_PD_STATE_UNCONFIGURED_BAD = 0x01,
1766         MR_PD_STATE_HOT_SPARE = 0x02,
1767         MR_PD_STATE_OFFLINE = 0x10,
1768         MR_PD_STATE_FAILED = 0x11,
1769         MR_PD_STATE_REBUILD = 0x14,
1770         MR_PD_STATE_ONLINE = 0x18,
1771         MR_PD_STATE_COPYBACK = 0x20,
1772         MR_PD_STATE_SYSTEM = 0x40,
1773 };
1774
1775 /*
1776  * defines the physical drive address structure
1777  */
1778 #pragma pack(1)
1779 struct MR_PD_ADDRESS {
1780         u_int16_t deviceId;
1781         u_int16_t enclDeviceId;
1782
1783         union {
1784                 struct {
1785                         u_int8_t enclIndex;
1786                         u_int8_t slotNumber;
1787                 }       mrPdAddress;
1788                 struct {
1789                         u_int8_t enclPosition;
1790                         u_int8_t enclConnectorIndex;
1791                 }       mrEnclAddress;
1792         }       u1;
1793         u_int8_t scsiDevType;
1794         union {
1795                 u_int8_t connectedPortBitmap;
1796                 u_int8_t connectedPortNumbers;
1797         }       u2;
1798         u_int64_t sasAddr[2];
1799 };
1800
1801 #pragma pack()
1802
1803 /*
1804  * defines the physical drive list structure
1805  */
1806 #pragma pack(1)
1807 struct MR_PD_LIST {
1808         u_int32_t size;
1809         u_int32_t count;
1810         struct MR_PD_ADDRESS addr[1];
1811 };
1812
1813 #pragma pack()
1814
1815 #pragma pack(1)
1816 struct mrsas_pd_list {
1817         u_int16_t tid;
1818         u_int8_t driveType;
1819         u_int8_t driveState;
1820 };
1821
1822 #pragma pack()
1823
1824 /*
1825  * defines the logical drive reference structure
1826  */
1827 typedef union _MR_LD_REF {
1828         struct {
1829                 u_int8_t targetId;
1830                 u_int8_t reserved;
1831                 u_int16_t seqNum;
1832         }       ld_context;
1833         u_int32_t ref;
1834 }       MR_LD_REF;
1835
1836
1837 /*
1838  * defines the logical drive list structure
1839  */
1840 #pragma pack(1)
1841 struct MR_LD_LIST {
1842         u_int32_t ldCount;
1843         u_int32_t reserved;
1844         struct {
1845                 MR_LD_REF ref;
1846                 u_int8_t state;
1847                 u_int8_t reserved[3];
1848                 u_int64_t size;
1849         }       ldList[MAX_LOGICAL_DRIVES_EXT];
1850 };
1851
1852 #pragma pack()
1853
1854 /*
1855  * SAS controller properties
1856  */
1857 #pragma pack(1)
1858 struct mrsas_ctrl_prop {
1859         u_int16_t seq_num;
1860         u_int16_t pred_fail_poll_interval;
1861         u_int16_t intr_throttle_count;
1862         u_int16_t intr_throttle_timeouts;
1863         u_int8_t rebuild_rate;
1864         u_int8_t patrol_read_rate;
1865         u_int8_t bgi_rate;
1866         u_int8_t cc_rate;
1867         u_int8_t recon_rate;
1868         u_int8_t cache_flush_interval;
1869         u_int8_t spinup_drv_count;
1870         u_int8_t spinup_delay;
1871         u_int8_t cluster_enable;
1872         u_int8_t coercion_mode;
1873         u_int8_t alarm_enable;
1874         u_int8_t disable_auto_rebuild;
1875         u_int8_t disable_battery_warn;
1876         u_int8_t ecc_bucket_size;
1877         u_int16_t ecc_bucket_leak_rate;
1878         u_int8_t restore_hotspare_on_insertion;
1879         u_int8_t expose_encl_devices;
1880         u_int8_t maintainPdFailHistory;
1881         u_int8_t disallowHostRequestReordering;
1882         u_int8_t abortCCOnError;
1883         u_int8_t loadBalanceMode;
1884         u_int8_t disableAutoDetectBackplane;
1885         u_int8_t snapVDSpace;
1886         /*
1887          * Add properties that can be controlled by a bit in the following
1888          * structure.
1889          */
1890         struct {
1891                 u_int32_t copyBackDisabled:1;
1892                 u_int32_t SMARTerEnabled:1;
1893                 u_int32_t prCorrectUnconfiguredAreas:1;
1894                 u_int32_t useFdeOnly:1;
1895                 u_int32_t disableNCQ:1;
1896                 u_int32_t SSDSMARTerEnabled:1;
1897                 u_int32_t SSDPatrolReadEnabled:1;
1898                 u_int32_t enableSpinDownUnconfigured:1;
1899                 u_int32_t autoEnhancedImport:1;
1900                 u_int32_t enableSecretKeyControl:1;
1901                 u_int32_t disableOnlineCtrlReset:1;
1902                 u_int32_t allowBootWithPinnedCache:1;
1903                 u_int32_t disableSpinDownHS:1;
1904                 u_int32_t enableJBOD:1;
1905                 u_int32_t disableCacheBypass:1;
1906                 u_int32_t useDiskActivityForLocate:1;
1907                 u_int32_t enablePI:1;
1908                 u_int32_t preventPIImport:1;
1909                 u_int32_t useGlobalSparesForEmergency:1;
1910                 u_int32_t useUnconfGoodForEmergency:1;
1911                 u_int32_t useEmergencySparesforSMARTer:1;
1912                 u_int32_t forceSGPIOForQuadOnly:1;
1913                 u_int32_t enableConfigAutoBalance:1;
1914                 u_int32_t enableVirtualCache:1;
1915                 u_int32_t enableAutoLockRecovery:1;
1916                 u_int32_t disableImmediateIO:1;
1917                 u_int32_t disableT10RebuildAssist:1;
1918                 u_int32_t ignore64ldRestriction:1;
1919                 u_int32_t enableSwZone:1;
1920                 u_int32_t limitMaxRateSATA3G:1;
1921                 u_int32_t reserved:2;
1922         }       OnOffProperties;
1923         u_int8_t autoSnapVDSpace;
1924         u_int8_t viewSpace;
1925         u_int16_t spinDownTime;
1926         u_int8_t reserved[24];
1927
1928 };
1929
1930 #pragma pack()
1931
1932
1933 /*
1934  * SAS controller information
1935  */
1936 struct mrsas_ctrl_info {
1937         /*
1938          * PCI device information
1939          */
1940         struct {
1941                 u_int16_t vendor_id;
1942                 u_int16_t device_id;
1943                 u_int16_t sub_vendor_id;
1944                 u_int16_t sub_device_id;
1945                 u_int8_t reserved[24];
1946         } __packed pci;
1947         /*
1948          * Host interface information
1949          */
1950         struct {
1951                 u_int8_t PCIX:1;
1952                 u_int8_t PCIE:1;
1953                 u_int8_t iSCSI:1;
1954                 u_int8_t SAS_3G:1;
1955                 u_int8_t reserved_0:4;
1956                 u_int8_t reserved_1[6];
1957                 u_int8_t port_count;
1958                 u_int64_t port_addr[8];
1959         } __packed host_interface;
1960         /*
1961          * Device (backend) interface information
1962          */
1963         struct {
1964                 u_int8_t SPI:1;
1965                 u_int8_t SAS_3G:1;
1966                 u_int8_t SATA_1_5G:1;
1967                 u_int8_t SATA_3G:1;
1968                 u_int8_t reserved_0:4;
1969                 u_int8_t reserved_1[6];
1970                 u_int8_t port_count;
1971                 u_int64_t port_addr[8];
1972         } __packed device_interface;
1973
1974         u_int32_t image_check_word;
1975         u_int32_t image_component_count;
1976
1977         struct {
1978                 char    name[8];
1979                 char    version[32];
1980                 char    build_date[16];
1981                 char    built_time[16];
1982         } __packed image_component[8];
1983
1984         u_int32_t pending_image_component_count;
1985
1986         struct {
1987                 char    name[8];
1988                 char    version[32];
1989                 char    build_date[16];
1990                 char    build_time[16];
1991         } __packed pending_image_component[8];
1992
1993         u_int8_t max_arms;
1994         u_int8_t max_spans;
1995         u_int8_t max_arrays;
1996         u_int8_t max_lds;
1997         char    product_name[80];
1998         char    serial_no[32];
1999
2000         /*
2001          * Other physical/controller/operation information. Indicates the
2002          * presence of the hardware
2003          */
2004         struct {
2005                 u_int32_t bbu:1;
2006                 u_int32_t alarm:1;
2007                 u_int32_t nvram:1;
2008                 u_int32_t uart:1;
2009                 u_int32_t reserved:28;
2010         } __packed hw_present;
2011
2012         u_int32_t current_fw_time;
2013
2014         /*
2015          * Maximum data transfer sizes
2016          */
2017         u_int16_t max_concurrent_cmds;
2018         u_int16_t max_sge_count;
2019         u_int32_t max_request_size;
2020
2021         /*
2022          * Logical and physical device counts
2023          */
2024         u_int16_t ld_present_count;
2025         u_int16_t ld_degraded_count;
2026         u_int16_t ld_offline_count;
2027
2028         u_int16_t pd_present_count;
2029         u_int16_t pd_disk_present_count;
2030         u_int16_t pd_disk_pred_failure_count;
2031         u_int16_t pd_disk_failed_count;
2032
2033         /*
2034          * Memory size information
2035          */
2036         u_int16_t nvram_size;
2037         u_int16_t memory_size;
2038         u_int16_t flash_size;
2039
2040         /*
2041          * Error counters
2042          */
2043         u_int16_t mem_correctable_error_count;
2044         u_int16_t mem_uncorrectable_error_count;
2045
2046         /*
2047          * Cluster information
2048          */
2049         u_int8_t cluster_permitted;
2050         u_int8_t cluster_active;
2051
2052         /*
2053          * Additional max data transfer sizes
2054          */
2055         u_int16_t max_strips_per_io;
2056
2057         /*
2058          * Controller capabilities structures
2059          */
2060         struct {
2061                 u_int32_t raid_level_0:1;
2062                 u_int32_t raid_level_1:1;
2063                 u_int32_t raid_level_5:1;
2064                 u_int32_t raid_level_1E:1;
2065                 u_int32_t raid_level_6:1;
2066                 u_int32_t reserved:27;
2067         } __packed raid_levels;
2068
2069         struct {
2070                 u_int32_t rbld_rate:1;
2071                 u_int32_t cc_rate:1;
2072                 u_int32_t bgi_rate:1;
2073                 u_int32_t recon_rate:1;
2074                 u_int32_t patrol_rate:1;
2075                 u_int32_t alarm_control:1;
2076                 u_int32_t cluster_supported:1;
2077                 u_int32_t bbu:1;
2078                 u_int32_t spanning_allowed:1;
2079                 u_int32_t dedicated_hotspares:1;
2080                 u_int32_t revertible_hotspares:1;
2081                 u_int32_t foreign_config_import:1;
2082                 u_int32_t self_diagnostic:1;
2083                 u_int32_t mixed_redundancy_arr:1;
2084                 u_int32_t global_hot_spares:1;
2085                 u_int32_t reserved:17;
2086         } __packed adapter_operations;
2087
2088         struct {
2089                 u_int32_t read_policy:1;
2090                 u_int32_t write_policy:1;
2091                 u_int32_t io_policy:1;
2092                 u_int32_t access_policy:1;
2093                 u_int32_t disk_cache_policy:1;
2094                 u_int32_t reserved:27;
2095         } __packed ld_operations;
2096
2097         struct {
2098                 u_int8_t min;
2099                 u_int8_t max;
2100                 u_int8_t reserved[2];
2101         } __packed stripe_sz_ops;
2102
2103         struct {
2104                 u_int32_t force_online:1;
2105                 u_int32_t force_offline:1;
2106                 u_int32_t force_rebuild:1;
2107                 u_int32_t reserved:29;
2108         } __packed pd_operations;
2109
2110         struct {
2111                 u_int32_t ctrl_supports_sas:1;
2112                 u_int32_t ctrl_supports_sata:1;
2113                 u_int32_t allow_mix_in_encl:1;
2114                 u_int32_t allow_mix_in_ld:1;
2115                 u_int32_t allow_sata_in_cluster:1;
2116                 u_int32_t reserved:27;
2117         } __packed pd_mix_support;
2118
2119         /*
2120          * Define ECC single-bit-error bucket information
2121          */
2122         u_int8_t ecc_bucket_count;
2123         u_int8_t reserved_2[11];
2124
2125         /*
2126          * Include the controller properties (changeable items)
2127          */
2128         struct mrsas_ctrl_prop properties;
2129
2130         /*
2131          * Define FW pkg version (set in envt v'bles on OEM basis)
2132          */
2133         char    package_version[0x60];
2134
2135         u_int64_t deviceInterfacePortAddr2[8];
2136         u_int8_t reserved3[128];
2137
2138         struct {
2139                 u_int16_t minPdRaidLevel_0:4;
2140                 u_int16_t maxPdRaidLevel_0:12;
2141
2142                 u_int16_t minPdRaidLevel_1:4;
2143                 u_int16_t maxPdRaidLevel_1:12;
2144
2145                 u_int16_t minPdRaidLevel_5:4;
2146                 u_int16_t maxPdRaidLevel_5:12;
2147
2148                 u_int16_t minPdRaidLevel_1E:4;
2149                 u_int16_t maxPdRaidLevel_1E:12;
2150
2151                 u_int16_t minPdRaidLevel_6:4;
2152                 u_int16_t maxPdRaidLevel_6:12;
2153
2154                 u_int16_t minPdRaidLevel_10:4;
2155                 u_int16_t maxPdRaidLevel_10:12;
2156
2157                 u_int16_t minPdRaidLevel_50:4;
2158                 u_int16_t maxPdRaidLevel_50:12;
2159
2160                 u_int16_t minPdRaidLevel_60:4;
2161                 u_int16_t maxPdRaidLevel_60:12;
2162
2163                 u_int16_t minPdRaidLevel_1E_RLQ0:4;
2164                 u_int16_t maxPdRaidLevel_1E_RLQ0:12;
2165
2166                 u_int16_t minPdRaidLevel_1E0_RLQ0:4;
2167                 u_int16_t maxPdRaidLevel_1E0_RLQ0:12;
2168
2169                 u_int16_t reserved[6];
2170         }       pdsForRaidLevels;
2171
2172         u_int16_t maxPds;               /* 0x780 */
2173         u_int16_t maxDedHSPs;           /* 0x782 */
2174         u_int16_t maxGlobalHSPs;        /* 0x784 */
2175         u_int16_t ddfSize;              /* 0x786 */
2176         u_int8_t maxLdsPerArray;        /* 0x788 */
2177         u_int8_t partitionsInDDF;       /* 0x789 */
2178         u_int8_t lockKeyBinding;        /* 0x78a */
2179         u_int8_t maxPITsPerLd;          /* 0x78b */
2180         u_int8_t maxViewsPerLd;         /* 0x78c */
2181         u_int8_t maxTargetId;           /* 0x78d */
2182         u_int16_t maxBvlVdSize;         /* 0x78e */
2183
2184         u_int16_t maxConfigurableSSCSize;       /* 0x790 */
2185         u_int16_t currentSSCsize;       /* 0x792 */
2186
2187         char    expanderFwVersion[12];  /* 0x794 */
2188
2189         u_int16_t PFKTrialTimeRemaining;/* 0x7A0 */
2190
2191         u_int16_t cacheMemorySize;      /* 0x7A2 */
2192
2193         struct {                        /* 0x7A4 */
2194                 u_int32_t supportPIcontroller:1;
2195                 u_int32_t supportLdPIType1:1;
2196                 u_int32_t supportLdPIType2:1;
2197                 u_int32_t supportLdPIType3:1;
2198                 u_int32_t supportLdBBMInfo:1;
2199                 u_int32_t supportShieldState:1;
2200                 u_int32_t blockSSDWriteCacheChange:1;
2201                 u_int32_t supportSuspendResumeBGops:1;
2202                 u_int32_t supportEmergencySpares:1;
2203                 u_int32_t supportSetLinkSpeed:1;
2204                 u_int32_t supportBootTimePFKChange:1;
2205                 u_int32_t supportJBOD:1;
2206                 u_int32_t disableOnlinePFKChange:1;
2207                 u_int32_t supportPerfTuning:1;
2208                 u_int32_t supportSSDPatrolRead:1;
2209                 u_int32_t realTimeScheduler:1;
2210
2211                 u_int32_t supportResetNow:1;
2212                 u_int32_t supportEmulatedDrives:1;
2213                 u_int32_t headlessMode:1;
2214                 u_int32_t dedicatedHotSparesLimited:1;
2215
2216
2217                 u_int32_t supportUnevenSpans:1;
2218                 u_int32_t reserved:11;
2219         }       adapterOperations2;
2220
2221         u_int8_t driverVersion[32];     /* 0x7A8 */
2222         u_int8_t maxDAPdCountSpinup60;  /* 0x7C8 */
2223         u_int8_t temperatureROC;        /* 0x7C9 */
2224         u_int8_t temperatureCtrl;       /* 0x7CA */
2225         u_int8_t reserved4;             /* 0x7CB */
2226         u_int16_t maxConfigurablePds;   /* 0x7CC */
2227
2228
2229         u_int8_t reserved5[2];          /* 0x7CD reserved */
2230
2231         struct {
2232                 u_int32_t peerIsPresent:1;
2233                 u_int32_t peerIsIncompatible:1;
2234
2235                 u_int32_t hwIncompatible:1;
2236                 u_int32_t fwVersionMismatch:1;
2237                 u_int32_t ctrlPropIncompatible:1;
2238                 u_int32_t premiumFeatureMismatch:1;
2239                 u_int32_t reserved:26;
2240         }       cluster;
2241
2242         char    clusterId[16];          /* 0x7D4 */
2243
2244         char    reserved6[4];           /* 0x7E4 RESERVED FOR IOV */
2245
2246         struct {                        /* 0x7E8 */
2247                 u_int32_t supportPersonalityChange:2;
2248                 u_int32_t supportThermalPollInterval:1;
2249                 u_int32_t supportDisableImmediateIO:1;
2250                 u_int32_t supportT10RebuildAssist:1;
2251                 u_int32_t supportMaxExtLDs:1;
2252                 u_int32_t supportCrashDump:1;
2253                 u_int32_t supportSwZone:1;
2254                 u_int32_t supportDebugQueue:1;
2255                 u_int32_t supportNVCacheErase:1;
2256                 u_int32_t supportForceTo512e:1;
2257                 u_int32_t supportHOQRebuild:1;
2258                 u_int32_t supportAllowedOpsforDrvRemoval:1;
2259                 u_int32_t supportDrvActivityLEDSetting:1;
2260                 u_int32_t supportNVDRAM:1;
2261                 u_int32_t supportForceFlash:1;
2262                 u_int32_t supportDisableSESMonitoring:1;
2263                 u_int32_t supportCacheBypassModes:1;
2264                 u_int32_t supportSecurityonJBOD:1;
2265                 u_int32_t discardCacheDuringLDDelete:1;
2266                 u_int32_t supportTTYLogCompression:1;
2267                 u_int32_t supportCPLDUpdate:1;
2268                 u_int32_t supportDiskCacheSettingForSysPDs:1;
2269                 u_int32_t supportExtendedSSCSize:1;
2270                 u_int32_t useSeqNumJbodFP:1;
2271                 u_int32_t reserved:7;
2272         }       adapterOperations3;
2273
2274         u_int8_t pad_cpld[16];
2275
2276         struct {
2277                 u_int16_t ctrlInfoExtSupported:1;
2278                 u_int16_t supportIbuttonLess:1;
2279                 u_int16_t supportedEncAlgo:1;
2280                 u_int16_t supportEncryptedMfc:1;
2281                 u_int16_t imageUploadSupported:1;
2282                 u_int16_t supportSESCtrlInMultipathCfg:1;
2283                 u_int16_t supportPdMapTargetId:1;
2284                 u_int16_t FWSwapsBBUVPDInfo:1;
2285                 u_int16_t reserved:8;
2286         }       adapterOperations4;
2287
2288         u_int8_t pad[0x800 - 0x7FE];    /* 0x7FE */
2289 } __packed;
2290
2291 /*
2292  * When SCSI mid-layer calls driver's reset routine, driver waits for
2293  * MRSAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note
2294  * that the driver cannot _actually_ abort or reset pending commands. While
2295  * it is waiting for the commands to complete, it prints a diagnostic message
2296  * every MRSAS_RESET_NOTICE_INTERVAL seconds
2297  */
2298 #define MRSAS_RESET_WAIT_TIME                   180
2299 #define MRSAS_INTERNAL_CMD_WAIT_TIME    180
2300 #define MRSAS_RESET_NOTICE_INTERVAL             5
2301 #define MRSAS_IOCTL_CMD                                 0
2302 #define MRSAS_DEFAULT_CMD_TIMEOUT               90
2303 #define MRSAS_THROTTLE_QUEUE_DEPTH              16
2304
2305 /*
2306  * MSI-x regsiters offset defines
2307  */
2308 #define MPI2_SUP_REPLY_POST_HOST_INDEX_OFFSET   (0x0000030C)
2309 #define MPI2_REPLY_POST_HOST_INDEX_OFFSET               (0x0000006C)
2310 #define MR_MAX_REPLY_QUEUES_OFFSET                              (0x0000001F)
2311 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET                  (0x003FC000)
2312 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET_SHIFT    14
2313 #define MR_MAX_MSIX_REG_ARRAY                                   16
2314
2315 /*
2316  * SYNC CACHE offset define
2317  */
2318 #define MR_CAN_HANDLE_SYNC_CACHE_OFFSET     0X01000000
2319
2320 #define MR_ATOMIC_DESCRIPTOR_SUPPORT_OFFSET (1 << 24)
2321
2322 /*
2323  * FW reports the maximum of number of commands that it can accept (maximum
2324  * commands that can be outstanding) at any time. The driver must report a
2325  * lower number to the mid layer because it can issue a few internal commands
2326  * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs
2327  * is shown below
2328  */
2329 #define MRSAS_INT_CMDS                  32
2330 #define MRSAS_SKINNY_INT_CMDS   5
2331 #define MRSAS_MAX_MSIX_QUEUES   128
2332
2333 /*
2334  * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit SGLs
2335  * based on the size of bus_addr_t
2336  */
2337 #define IS_DMA64                                                        (sizeof(bus_addr_t) == 8)
2338
2339 #define MFI_XSCALE_OMR0_CHANGE_INTERRUPT        0x00000001
2340 #define MFI_INTR_FLAG_REPLY_MESSAGE                     0x00000001
2341 #define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE     0x00000002
2342 #define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT       0x00000004
2343
2344 #define MFI_OB_INTR_STATUS_MASK                         0x00000002
2345 #define MFI_POLL_TIMEOUT_SECS                           60
2346
2347 #define MFI_REPLY_1078_MESSAGE_INTERRUPT        0x80000000
2348 #define MFI_REPLY_GEN2_MESSAGE_INTERRUPT        0x00000001
2349 #define MFI_GEN2_ENABLE_INTERRUPT_MASK          0x00000001
2350 #define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT      0x40000000
2351 #define MFI_SKINNY_ENABLE_INTERRUPT_MASK        (0x00000001)
2352 #define MFI_1068_PCSR_OFFSET                            0x84
2353 #define MFI_1068_FW_HANDSHAKE_OFFSET            0x64
2354 #define MFI_1068_FW_READY                                       0xDDDD0000
2355
2356 typedef union _MFI_CAPABILITIES {
2357         struct {
2358                 u_int32_t support_fp_remote_lun:1;
2359                 u_int32_t support_additional_msix:1;
2360                 u_int32_t support_fastpath_wb:1;
2361                 u_int32_t support_max_255lds:1;
2362                 u_int32_t support_ndrive_r1_lb:1;
2363                 u_int32_t support_core_affinity:1;
2364                 u_int32_t security_protocol_cmds_fw:1;
2365                 u_int32_t support_ext_queue_depth:1;
2366                 u_int32_t support_ext_io_size:1;
2367                 u_int32_t reserved:23;
2368         }       mfi_capabilities;
2369         u_int32_t reg;
2370 }       MFI_CAPABILITIES;
2371
2372 #pragma pack(1)
2373 struct mrsas_sge32 {
2374         u_int32_t phys_addr;
2375         u_int32_t length;
2376 };
2377
2378 #pragma pack()
2379
2380 #pragma pack(1)
2381 struct mrsas_sge64 {
2382         u_int64_t phys_addr;
2383         u_int32_t length;
2384 };
2385
2386 #pragma pack()
2387
2388 #pragma pack()
2389 union mrsas_sgl {
2390         struct mrsas_sge32 sge32[1];
2391         struct mrsas_sge64 sge64[1];
2392 };
2393
2394 #pragma pack()
2395
2396 #pragma pack(1)
2397 struct mrsas_header {
2398         u_int8_t cmd;                   /* 00e */
2399         u_int8_t sense_len;             /* 01h */
2400         u_int8_t cmd_status;            /* 02h */
2401         u_int8_t scsi_status;           /* 03h */
2402
2403         u_int8_t target_id;             /* 04h */
2404         u_int8_t lun;                   /* 05h */
2405         u_int8_t cdb_len;               /* 06h */
2406         u_int8_t sge_count;             /* 07h */
2407
2408         u_int32_t context;              /* 08h */
2409         u_int32_t pad_0;                /* 0Ch */
2410
2411         u_int16_t flags;                /* 10h */
2412         u_int16_t timeout;              /* 12h */
2413         u_int32_t data_xferlen;         /* 14h */
2414 };
2415
2416 #pragma pack()
2417
2418 #pragma pack(1)
2419 struct mrsas_init_frame {
2420         u_int8_t cmd;                   /* 00h */
2421         u_int8_t reserved_0;            /* 01h */
2422         u_int8_t cmd_status;            /* 02h */
2423
2424         u_int8_t reserved_1;            /* 03h */
2425         MFI_CAPABILITIES driver_operations;     /* 04h */
2426         u_int32_t context;              /* 08h */
2427         u_int32_t pad_0;                /* 0Ch */
2428
2429         u_int16_t flags;                /* 10h */
2430         u_int16_t reserved_3;           /* 12h */
2431         u_int32_t data_xfer_len;        /* 14h */
2432
2433         u_int32_t queue_info_new_phys_addr_lo;  /* 18h */
2434         u_int32_t queue_info_new_phys_addr_hi;  /* 1Ch */
2435         u_int32_t queue_info_old_phys_addr_lo;  /* 20h */
2436         u_int32_t queue_info_old_phys_addr_hi;  /* 24h */
2437         u_int32_t driver_ver_lo;        /* 28h */
2438         u_int32_t driver_ver_hi;        /* 2Ch */
2439         u_int32_t reserved_4[4];        /* 30h */
2440 };
2441
2442 #pragma pack()
2443
2444 #pragma pack(1)
2445 struct mrsas_io_frame {
2446         u_int8_t cmd;                   /* 00h */
2447         u_int8_t sense_len;             /* 01h */
2448         u_int8_t cmd_status;            /* 02h */
2449         u_int8_t scsi_status;           /* 03h */
2450
2451         u_int8_t target_id;             /* 04h */
2452         u_int8_t access_byte;           /* 05h */
2453         u_int8_t reserved_0;            /* 06h */
2454         u_int8_t sge_count;             /* 07h */
2455
2456         u_int32_t context;              /* 08h */
2457         u_int32_t pad_0;                /* 0Ch */
2458
2459         u_int16_t flags;                /* 10h */
2460         u_int16_t timeout;              /* 12h */
2461         u_int32_t lba_count;            /* 14h */
2462
2463         u_int32_t sense_buf_phys_addr_lo;       /* 18h */
2464         u_int32_t sense_buf_phys_addr_hi;       /* 1Ch */
2465
2466         u_int32_t start_lba_lo;         /* 20h */
2467         u_int32_t start_lba_hi;         /* 24h */
2468
2469         union mrsas_sgl sgl;            /* 28h */
2470 };
2471
2472 #pragma pack()
2473
2474 #pragma pack(1)
2475 struct mrsas_pthru_frame {
2476         u_int8_t cmd;                   /* 00h */
2477         u_int8_t sense_len;             /* 01h */
2478         u_int8_t cmd_status;            /* 02h */
2479         u_int8_t scsi_status;           /* 03h */
2480
2481         u_int8_t target_id;             /* 04h */
2482         u_int8_t lun;                   /* 05h */
2483         u_int8_t cdb_len;               /* 06h */
2484         u_int8_t sge_count;             /* 07h */
2485
2486         u_int32_t context;              /* 08h */
2487         u_int32_t pad_0;                /* 0Ch */
2488
2489         u_int16_t flags;                /* 10h */
2490         u_int16_t timeout;              /* 12h */
2491         u_int32_t data_xfer_len;        /* 14h */
2492
2493         u_int32_t sense_buf_phys_addr_lo;       /* 18h */
2494         u_int32_t sense_buf_phys_addr_hi;       /* 1Ch */
2495
2496         u_int8_t cdb[16];               /* 20h */
2497         union mrsas_sgl sgl;            /* 30h */
2498 };
2499
2500 #pragma pack()
2501
2502 #pragma pack(1)
2503 struct mrsas_dcmd_frame {
2504         u_int8_t cmd;                   /* 00h */
2505         u_int8_t reserved_0;            /* 01h */
2506         u_int8_t cmd_status;            /* 02h */
2507         u_int8_t reserved_1[4];         /* 03h */
2508         u_int8_t sge_count;             /* 07h */
2509
2510         u_int32_t context;              /* 08h */
2511         u_int32_t pad_0;                /* 0Ch */
2512
2513         u_int16_t flags;                /* 10h */
2514         u_int16_t timeout;              /* 12h */
2515
2516         u_int32_t data_xfer_len;        /* 14h */
2517         u_int32_t opcode;               /* 18h */
2518
2519         union {                         /* 1Ch */
2520                 u_int8_t b[12];
2521                 u_int16_t s[6];
2522                 u_int32_t w[3];
2523         }       mbox;
2524
2525         union mrsas_sgl sgl;            /* 28h */
2526 };
2527
2528 #pragma pack()
2529
2530 #pragma pack(1)
2531 struct mrsas_abort_frame {
2532         u_int8_t cmd;                   /* 00h */
2533         u_int8_t reserved_0;            /* 01h */
2534         u_int8_t cmd_status;            /* 02h */
2535
2536         u_int8_t reserved_1;            /* 03h */
2537         MFI_CAPABILITIES driver_operations;     /* 04h */
2538         u_int32_t context;              /* 08h */
2539         u_int32_t pad_0;                /* 0Ch */
2540
2541         u_int16_t flags;                /* 10h */
2542         u_int16_t reserved_3;           /* 12h */
2543         u_int32_t reserved_4;           /* 14h */
2544
2545         u_int32_t abort_context;        /* 18h */
2546         u_int32_t pad_1;                /* 1Ch */
2547
2548         u_int32_t abort_mfi_phys_addr_lo;       /* 20h */
2549         u_int32_t abort_mfi_phys_addr_hi;       /* 24h */
2550
2551         u_int32_t reserved_5[6];        /* 28h */
2552 };
2553
2554 #pragma pack()
2555
2556 #pragma pack(1)
2557 struct mrsas_smp_frame {
2558         u_int8_t cmd;                   /* 00h */
2559         u_int8_t reserved_1;            /* 01h */
2560         u_int8_t cmd_status;            /* 02h */
2561         u_int8_t connection_status;     /* 03h */
2562
2563         u_int8_t reserved_2[3];         /* 04h */
2564         u_int8_t sge_count;             /* 07h */
2565
2566         u_int32_t context;              /* 08h */
2567         u_int32_t pad_0;                /* 0Ch */
2568
2569         u_int16_t flags;                /* 10h */
2570         u_int16_t timeout;              /* 12h */
2571
2572         u_int32_t data_xfer_len;        /* 14h */
2573         u_int64_t sas_addr;             /* 18h */
2574
2575         union {
2576                 struct mrsas_sge32 sge32[2];    /* [0]: resp [1]: req */
2577                 struct mrsas_sge64 sge64[2];    /* [0]: resp [1]: req */
2578         }       sgl;
2579 };
2580
2581 #pragma pack()
2582
2583
2584 #pragma pack(1)
2585 struct mrsas_stp_frame {
2586         u_int8_t cmd;                   /* 00h */
2587         u_int8_t reserved_1;            /* 01h */
2588         u_int8_t cmd_status;            /* 02h */
2589         u_int8_t reserved_2;            /* 03h */
2590
2591         u_int8_t target_id;             /* 04h */
2592         u_int8_t reserved_3[2];         /* 05h */
2593         u_int8_t sge_count;             /* 07h */
2594
2595         u_int32_t context;              /* 08h */
2596         u_int32_t pad_0;                /* 0Ch */
2597
2598         u_int16_t flags;                /* 10h */
2599         u_int16_t timeout;              /* 12h */
2600
2601         u_int32_t data_xfer_len;        /* 14h */
2602
2603         u_int16_t fis[10];              /* 18h */
2604         u_int32_t stp_flags;
2605
2606         union {
2607                 struct mrsas_sge32 sge32[2];    /* [0]: resp [1]: data */
2608                 struct mrsas_sge64 sge64[2];    /* [0]: resp [1]: data */
2609         }       sgl;
2610 };
2611
2612 #pragma pack()
2613
2614 union mrsas_frame {
2615         struct mrsas_header hdr;
2616         struct mrsas_init_frame init;
2617         struct mrsas_io_frame io;
2618         struct mrsas_pthru_frame pthru;
2619         struct mrsas_dcmd_frame dcmd;
2620         struct mrsas_abort_frame abort;
2621         struct mrsas_smp_frame smp;
2622         struct mrsas_stp_frame stp;
2623         u_int8_t raw_bytes[64];
2624 };
2625
2626 #pragma pack(1)
2627 union mrsas_evt_class_locale {
2628
2629         struct {
2630                 u_int16_t locale;
2631                 u_int8_t reserved;
2632                 int8_t  class;
2633         } __packed members;
2634
2635         u_int32_t word;
2636
2637 } __packed;
2638
2639 #pragma pack()
2640
2641
2642 #pragma pack(1)
2643 struct mrsas_evt_log_info {
2644         u_int32_t newest_seq_num;
2645         u_int32_t oldest_seq_num;
2646         u_int32_t clear_seq_num;
2647         u_int32_t shutdown_seq_num;
2648         u_int32_t boot_seq_num;
2649
2650 } __packed;
2651
2652 #pragma pack()
2653
2654 struct mrsas_progress {
2655
2656         u_int16_t progress;
2657         u_int16_t elapsed_seconds;
2658
2659 } __packed;
2660
2661 struct mrsas_evtarg_ld {
2662
2663         u_int16_t target_id;
2664         u_int8_t ld_index;
2665         u_int8_t reserved;
2666
2667 } __packed;
2668
2669 struct mrsas_evtarg_pd {
2670         u_int16_t device_id;
2671         u_int8_t encl_index;
2672         u_int8_t slot_number;
2673
2674 } __packed;
2675
2676 struct mrsas_evt_detail {
2677
2678         u_int32_t seq_num;
2679         u_int32_t time_stamp;
2680         u_int32_t code;
2681         union mrsas_evt_class_locale cl;
2682         u_int8_t arg_type;
2683         u_int8_t reserved1[15];
2684
2685         union {
2686                 struct {
2687                         struct mrsas_evtarg_pd pd;
2688                         u_int8_t cdb_length;
2689                         u_int8_t sense_length;
2690                         u_int8_t reserved[2];
2691                         u_int8_t cdb[16];
2692                         u_int8_t sense[64];
2693                 } __packed cdbSense;
2694
2695                 struct mrsas_evtarg_ld ld;
2696
2697                 struct {
2698                         struct mrsas_evtarg_ld ld;
2699                         u_int64_t count;
2700                 } __packed ld_count;
2701
2702                 struct {
2703                         u_int64_t lba;
2704                         struct mrsas_evtarg_ld ld;
2705                 } __packed ld_lba;
2706
2707                 struct {
2708                         struct mrsas_evtarg_ld ld;
2709                         u_int32_t prevOwner;
2710                         u_int32_t newOwner;
2711                 } __packed ld_owner;
2712
2713                 struct {
2714                         u_int64_t ld_lba;
2715                         u_int64_t pd_lba;
2716                         struct mrsas_evtarg_ld ld;
2717                         struct mrsas_evtarg_pd pd;
2718                 } __packed ld_lba_pd_lba;
2719
2720                 struct {
2721                         struct mrsas_evtarg_ld ld;
2722                         struct mrsas_progress prog;
2723                 } __packed ld_prog;
2724
2725                 struct {
2726                         struct mrsas_evtarg_ld ld;
2727                         u_int32_t prev_state;
2728                         u_int32_t new_state;
2729                 } __packed ld_state;
2730
2731                 struct {
2732                         u_int64_t strip;
2733                         struct mrsas_evtarg_ld ld;
2734                 } __packed ld_strip;
2735
2736                 struct mrsas_evtarg_pd pd;
2737
2738                 struct {
2739                         struct mrsas_evtarg_pd pd;
2740                         u_int32_t err;
2741                 } __packed pd_err;
2742
2743                 struct {
2744                         u_int64_t lba;
2745                         struct mrsas_evtarg_pd pd;
2746                 } __packed pd_lba;
2747
2748                 struct {
2749                         u_int64_t lba;
2750                         struct mrsas_evtarg_pd pd;
2751                         struct mrsas_evtarg_ld ld;
2752                 } __packed pd_lba_ld;
2753
2754                 struct {
2755                         struct mrsas_evtarg_pd pd;
2756                         struct mrsas_progress prog;
2757                 } __packed pd_prog;
2758
2759                 struct {
2760                         struct mrsas_evtarg_pd pd;
2761                         u_int32_t prevState;
2762                         u_int32_t newState;
2763                 } __packed pd_state;
2764
2765                 struct {
2766                         u_int16_t vendorId;
2767                         u_int16_t deviceId;
2768                         u_int16_t subVendorId;
2769                         u_int16_t subDeviceId;
2770                 } __packed pci;
2771
2772                 u_int32_t rate;
2773                 char    str[96];
2774
2775                 struct {
2776                         u_int32_t rtc;
2777                         u_int32_t elapsedSeconds;
2778                 } __packed time;
2779
2780                 struct {
2781                         u_int32_t ecar;
2782                         u_int32_t elog;
2783                         char    str[64];
2784                 } __packed ecc;
2785
2786                 u_int8_t b[96];
2787                 u_int16_t s[48];
2788                 u_int32_t w[24];
2789                 u_int64_t d[12];
2790         }       args;
2791
2792         char    description[128];
2793
2794 } __packed;
2795
2796 struct mrsas_irq_context {
2797         struct mrsas_softc *sc;
2798         uint32_t MSIxIndex;
2799 };
2800
2801 enum MEGASAS_OCR_REASON {
2802         FW_FAULT_OCR = 0,
2803         MFI_DCMD_TIMEOUT_OCR = 1,
2804 };
2805
2806 /* Controller management info added to support Linux Emulator */
2807 #define MAX_MGMT_ADAPTERS               1024
2808
2809 struct mrsas_mgmt_info {
2810         u_int16_t count;
2811         struct mrsas_softc *sc_ptr[MAX_MGMT_ADAPTERS];
2812         int     max_index;
2813 };
2814
2815 #define PCI_TYPE0_ADDRESSES             6
2816 #define PCI_TYPE1_ADDRESSES             2
2817 #define PCI_TYPE2_ADDRESSES             5
2818
2819 typedef struct _MRSAS_DRV_PCI_COMMON_HEADER {
2820         u_int16_t vendorID;
2821               //(ro)
2822         u_int16_t deviceID;
2823               //(ro)
2824         u_int16_t command;
2825               //Device control
2826         u_int16_t status;
2827         u_int8_t revisionID;
2828               //(ro)
2829         u_int8_t progIf;
2830               //(ro)
2831         u_int8_t subClass;
2832               //(ro)
2833         u_int8_t baseClass;
2834               //(ro)
2835         u_int8_t cacheLineSize;
2836               //(ro +)
2837         u_int8_t latencyTimer;
2838               //(ro +)
2839         u_int8_t headerType;
2840               //(ro)
2841         u_int8_t bist;
2842               //Built in self test
2843
2844         union {
2845                 struct _MRSAS_DRV_PCI_HEADER_TYPE_0 {
2846                         u_int32_t baseAddresses[PCI_TYPE0_ADDRESSES];
2847                         u_int32_t cis;
2848                         u_int16_t subVendorID;
2849                         u_int16_t subSystemID;
2850                         u_int32_t romBaseAddress;
2851                         u_int8_t capabilitiesPtr;
2852                         u_int8_t reserved1[3];
2853                         u_int32_t reserved2;
2854                         u_int8_t interruptLine;
2855                         u_int8_t interruptPin;
2856                               //(ro)
2857                         u_int8_t minimumGrant;
2858                               //(ro)
2859                         u_int8_t maximumLatency;
2860                               //(ro)
2861                 }       type0;
2862
2863                 /*
2864                  * PCI to PCI Bridge
2865                  */
2866
2867                 struct _MRSAS_DRV_PCI_HEADER_TYPE_1 {
2868                         u_int32_t baseAddresses[PCI_TYPE1_ADDRESSES];
2869                         u_int8_t primaryBus;
2870                         u_int8_t secondaryBus;
2871                         u_int8_t subordinateBus;
2872                         u_int8_t secondaryLatency;
2873                         u_int8_t ioBase;
2874                         u_int8_t ioLimit;
2875                         u_int16_t secondaryStatus;
2876                         u_int16_t memoryBase;
2877                         u_int16_t memoryLimit;
2878                         u_int16_t prefetchBase;
2879                         u_int16_t prefetchLimit;
2880                         u_int32_t prefetchBaseUpper32;
2881                         u_int32_t prefetchLimitUpper32;
2882                         u_int16_t ioBaseUpper16;
2883                         u_int16_t ioLimitUpper16;
2884                         u_int8_t capabilitiesPtr;
2885                         u_int8_t reserved1[3];
2886                         u_int32_t romBaseAddress;
2887                         u_int8_t interruptLine;
2888                         u_int8_t interruptPin;
2889                         u_int16_t bridgeControl;
2890                 }       type1;
2891
2892                 /*
2893                  * PCI to CARDBUS Bridge
2894                  */
2895
2896                 struct _MRSAS_DRV_PCI_HEADER_TYPE_2 {
2897                         u_int32_t socketRegistersBaseAddress;
2898                         u_int8_t capabilitiesPtr;
2899                         u_int8_t reserved;
2900                         u_int16_t secondaryStatus;
2901                         u_int8_t primaryBus;
2902                         u_int8_t secondaryBus;
2903                         u_int8_t subordinateBus;
2904                         u_int8_t secondaryLatency;
2905                         struct {
2906                                 u_int32_t base;
2907                                 u_int32_t limit;
2908                         }       range [PCI_TYPE2_ADDRESSES - 1];
2909                         u_int8_t interruptLine;
2910                         u_int8_t interruptPin;
2911                         u_int16_t bridgeControl;
2912                 }       type2;
2913         }       u;
2914
2915 }       MRSAS_DRV_PCI_COMMON_HEADER, *PMRSAS_DRV_PCI_COMMON_HEADER;
2916
2917 #define MRSAS_DRV_PCI_COMMON_HEADER_SIZE sizeof(MRSAS_DRV_PCI_COMMON_HEADER)   //64 bytes
2918
2919 typedef struct _MRSAS_DRV_PCI_LINK_CAPABILITY {
2920         union {
2921                 struct {
2922                         u_int32_t linkSpeed:4;
2923                         u_int32_t linkWidth:6;
2924                         u_int32_t aspmSupport:2;
2925                         u_int32_t losExitLatency:3;
2926                         u_int32_t l1ExitLatency:3;
2927                         u_int32_t rsvdp:6;
2928                         u_int32_t portNumber:8;
2929                 }       bits;
2930
2931                 u_int32_t asUlong;
2932         }       u;
2933 }       MRSAS_DRV_PCI_LINK_CAPABILITY, *PMRSAS_DRV_PCI_LINK_CAPABILITY;
2934
2935 #define MRSAS_DRV_PCI_LINK_CAPABILITY_SIZE sizeof(MRSAS_DRV_PCI_LINK_CAPABILITY)
2936
2937 typedef struct _MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY {
2938         union {
2939                 struct {
2940                         u_int16_t linkSpeed:4;
2941                         u_int16_t negotiatedLinkWidth:6;
2942                         u_int16_t linkTrainingError:1;
2943                         u_int16_t linkTraning:1;
2944                         u_int16_t slotClockConfig:1;
2945                         u_int16_t rsvdZ:3;
2946                 }       bits;
2947
2948                 u_int16_t asUshort;
2949         }       u;
2950         u_int16_t reserved;
2951 }       MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY, *PMRSAS_DRV_PCI_LINK_STATUS_CAPABILITY;
2952
2953 #define MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY_SIZE sizeof(MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY)
2954
2955
2956 typedef struct _MRSAS_DRV_PCI_CAPABILITIES {
2957         MRSAS_DRV_PCI_LINK_CAPABILITY linkCapability;
2958         MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY linkStatusCapability;
2959 }       MRSAS_DRV_PCI_CAPABILITIES, *PMRSAS_DRV_PCI_CAPABILITIES;
2960
2961 #define MRSAS_DRV_PCI_CAPABILITIES_SIZE sizeof(MRSAS_DRV_PCI_CAPABILITIES)
2962
2963 /* PCI information */
2964 typedef struct _MRSAS_DRV_PCI_INFORMATION {
2965         u_int32_t busNumber;
2966         u_int8_t deviceNumber;
2967         u_int8_t functionNumber;
2968         u_int8_t interruptVector;
2969         u_int8_t reserved1;
2970         MRSAS_DRV_PCI_COMMON_HEADER pciHeaderInfo;
2971         MRSAS_DRV_PCI_CAPABILITIES capability;
2972         u_int32_t domainID;
2973         u_int8_t reserved2[28];
2974 }       MRSAS_DRV_PCI_INFORMATION, *PMRSAS_DRV_PCI_INFORMATION;
2975
2976 typedef enum _MR_PD_TYPE {
2977         UNKNOWN_DRIVE = 0,
2978         PARALLEL_SCSI = 1,
2979         SAS_PD = 2,
2980         SATA_PD = 3,
2981         FC_PD = 4,
2982         NVME_PD = 5,
2983 } MR_PD_TYPE;
2984
2985 typedef union   _MR_PD_REF {
2986         struct {
2987                 u_int16_t        deviceId;
2988                 u_int16_t        seqNum;
2989         } mrPdRef;
2990         u_int32_t        ref;
2991 } MR_PD_REF;
2992
2993 /*
2994  * define the DDF Type bit structure
2995  */
2996 union MR_PD_DDF_TYPE {
2997         struct {
2998                 union {
2999                         struct {
3000                                 u_int16_t forcedPDGUID:1;
3001                                 u_int16_t inVD:1;
3002                                 u_int16_t isGlobalSpare:1;
3003                                 u_int16_t isSpare:1;
3004                                 u_int16_t isForeign:1;
3005                                 u_int16_t reserved:7;
3006                                 u_int16_t intf:4;
3007                         } pdType;
3008                         u_int16_t type;
3009                 };
3010                 u_int16_t reserved;
3011         } ddf;
3012         struct {
3013                 u_int32_t reserved;
3014         } nonDisk;
3015         u_int32_t type;
3016 } __packed;
3017
3018 /*
3019  * defines the progress structure
3020  */
3021 union MR_PROGRESS {
3022         struct  {
3023                 u_int16_t progress;
3024                 union {
3025                         u_int16_t elapsedSecs;
3026                         u_int16_t elapsedSecsForLastPercent;
3027                 };
3028         } mrProgress;
3029         u_int32_t w;
3030 } __packed;
3031
3032 /*
3033  * defines the physical drive progress structure
3034  */
3035 struct MR_PD_PROGRESS {
3036     struct {
3037         u_int32_t     rbld:1;
3038         u_int32_t     patrol:1;
3039         u_int32_t     clear:1;
3040         u_int32_t     copyBack:1;
3041         u_int32_t     erase:1;
3042         u_int32_t     locate:1;
3043         u_int32_t     reserved:26;
3044     } active;
3045     union MR_PROGRESS     rbld;
3046     union MR_PROGRESS     patrol;
3047     union {
3048         union MR_PROGRESS     clear;
3049         union MR_PROGRESS     erase;
3050     };
3051
3052     struct {
3053         u_int32_t     rbld:1;
3054         u_int32_t     patrol:1;
3055         u_int32_t     clear:1;
3056         u_int32_t     copyBack:1;
3057         u_int32_t     erase:1;
3058         u_int32_t     reserved:27;
3059     } pause;
3060
3061     union MR_PROGRESS     reserved[3];
3062 } __packed;
3063
3064
3065 struct  mrsas_pd_info {
3066          MR_PD_REF       ref;
3067          u_int8_t                inquiryData[96];
3068          u_int8_t                vpdPage83[64];
3069
3070          u_int8_t                notSupported;
3071          u_int8_t                scsiDevType;
3072
3073          union {
3074                  u_int8_t                connectedPortBitmap;
3075                  u_int8_t                connectedPortNumbers;
3076          };
3077
3078          u_int8_t                deviceSpeed;
3079          u_int32_t       mediaErrCount;
3080          u_int32_t       otherErrCount;
3081          u_int32_t       predFailCount;
3082          u_int32_t       lastPredFailEventSeqNum;
3083
3084          u_int16_t       fwState;
3085          u_int8_t                disabledForRemoval;
3086          u_int8_t                linkSpeed;
3087          union MR_PD_DDF_TYPE  state;
3088
3089          struct {
3090                  u_int8_t                count;
3091                  u_int8_t                isPathBroken:4;
3092                  u_int8_t                reserved3:3;
3093                  u_int8_t                widePortCapable:1;
3094
3095                  u_int8_t                connectorIndex[2];
3096                  u_int8_t                reserved[4];
3097                  u_int64_t       sasAddr[2];
3098                  u_int8_t                reserved2[16];
3099          } pathInfo;
3100
3101          u_int64_t       rawSize;
3102          u_int64_t       nonCoercedSize;
3103          u_int64_t       coercedSize;
3104          u_int16_t       enclDeviceId;
3105          u_int8_t                enclIndex;
3106
3107          union {
3108                  u_int8_t                slotNumber;
3109                  u_int8_t                enclConnectorIndex;
3110          };
3111
3112         struct MR_PD_PROGRESS progInfo;
3113          u_int8_t                badBlockTableFull;
3114          u_int8_t                unusableInCurrentConfig;
3115          u_int8_t                vpdPage83Ext[64];
3116          u_int8_t                powerState;
3117          u_int8_t                enclPosition;
3118          u_int32_t              allowedOps;
3119          u_int16_t       copyBackPartnerId;
3120          u_int16_t       enclPartnerDeviceId;
3121         struct {
3122                  u_int16_t fdeCapable:1;
3123                  u_int16_t fdeEnabled:1;
3124                  u_int16_t secured:1;
3125                  u_int16_t locked:1;
3126                  u_int16_t foreign:1;
3127                  u_int16_t needsEKM:1;
3128                  u_int16_t reserved:10;
3129          } security;
3130          u_int8_t                mediaType;
3131          u_int8_t                notCertified;
3132          u_int8_t                bridgeVendor[8];
3133          u_int8_t                bridgeProductIdentification[16];
3134          u_int8_t                bridgeProductRevisionLevel[4];
3135          u_int8_t                satBridgeExists;
3136
3137          u_int8_t                interfaceType;
3138          u_int8_t                temperature;
3139          u_int8_t                emulatedBlockSize;
3140          u_int16_t       userDataBlockSize;
3141          u_int16_t       reserved2;
3142
3143          struct {
3144                  u_int32_t piType:3;
3145                  u_int32_t piFormatted:1;
3146                  u_int32_t piEligible:1;
3147                  u_int32_t NCQ:1;
3148                  u_int32_t WCE:1;
3149                  u_int32_t commissionedSpare:1;
3150                  u_int32_t emergencySpare:1;
3151                  u_int32_t ineligibleForSSCD:1;
3152                  u_int32_t ineligibleForLd:1;
3153                  u_int32_t useSSEraseType:1;
3154                  u_int32_t wceUnchanged:1;
3155                  u_int32_t supportScsiUnmap:1;
3156                  u_int32_t reserved:18;
3157          } properties;
3158
3159          u_int64_t   shieldDiagCompletionTime;
3160          u_int8_t    shieldCounter;
3161
3162          u_int8_t linkSpeedOther;
3163          u_int8_t reserved4[2];
3164
3165          struct {
3166                 u_int32_t bbmErrCountSupported:1;
3167                 u_int32_t bbmErrCount:31;
3168          } bbmErr;
3169
3170          u_int8_t reserved1[512-428];
3171 } __packed;
3172
3173 struct mrsas_target {
3174         u_int16_t target_id;
3175         u_int32_t queue_depth;
3176         u_int8_t interface_type;
3177         u_int32_t max_io_size_kb;
3178 } __packed;
3179
3180 #define MR_NVME_PAGE_SIZE_MASK          0x000000FF
3181 #define MR_DEFAULT_NVME_PAGE_SIZE       4096
3182 #define MR_DEFAULT_NVME_PAGE_SHIFT      12
3183
3184 /*******************************************************************
3185  * per-instance data
3186  ********************************************************************/
3187 struct mrsas_softc {
3188         device_t mrsas_dev;
3189         struct cdev *mrsas_cdev;
3190         struct intr_config_hook mrsas_ich;
3191         struct cdev *mrsas_linux_emulator_cdev;
3192         uint16_t device_id;
3193         struct resource *reg_res;
3194         int     reg_res_id;
3195         bus_space_tag_t bus_tag;
3196         bus_space_handle_t bus_handle;
3197         bus_dma_tag_t mrsas_parent_tag;
3198         bus_dma_tag_t verbuf_tag;
3199         bus_dmamap_t verbuf_dmamap;
3200         void   *verbuf_mem;
3201         bus_addr_t verbuf_phys_addr;
3202         bus_dma_tag_t sense_tag;
3203         bus_dmamap_t sense_dmamap;
3204         void   *sense_mem;
3205         bus_addr_t sense_phys_addr;
3206         bus_dma_tag_t io_request_tag;
3207         bus_dmamap_t io_request_dmamap;
3208         void   *io_request_mem;
3209         bus_addr_t io_request_phys_addr;
3210         bus_dma_tag_t chain_frame_tag;
3211         bus_dmamap_t chain_frame_dmamap;
3212         void   *chain_frame_mem;
3213         bus_addr_t chain_frame_phys_addr;
3214         bus_dma_tag_t reply_desc_tag;
3215         bus_dmamap_t reply_desc_dmamap;
3216         void   *reply_desc_mem;
3217         bus_addr_t reply_desc_phys_addr;
3218         bus_dma_tag_t ioc_init_tag;
3219         bus_dmamap_t ioc_init_dmamap;
3220         void   *ioc_init_mem;
3221         bus_addr_t ioc_init_phys_mem;
3222         bus_dma_tag_t data_tag;
3223         struct cam_sim *sim_0;
3224         struct cam_sim *sim_1;
3225         struct cam_path *path_0;
3226         struct cam_path *path_1;
3227         struct mtx sim_lock;
3228         struct mtx pci_lock;
3229         struct mtx io_lock;
3230         struct mtx ioctl_lock;
3231         struct mtx mpt_cmd_pool_lock;
3232         struct mtx mfi_cmd_pool_lock;
3233         struct mtx raidmap_lock;
3234         struct mtx aen_lock;
3235         struct mtx stream_lock;
3236         struct selinfo mrsas_select;
3237         uint32_t mrsas_aen_triggered;
3238         uint32_t mrsas_poll_waiting;
3239
3240         struct sema ioctl_count_sema;
3241         uint32_t max_fw_cmds;
3242         uint16_t max_scsi_cmds;
3243         uint32_t max_num_sge;
3244         struct resource *mrsas_irq[MAX_MSIX_COUNT];
3245         void   *intr_handle[MAX_MSIX_COUNT];
3246         int     irq_id[MAX_MSIX_COUNT];
3247         struct mrsas_irq_context irq_context[MAX_MSIX_COUNT];
3248         int     msix_vectors;
3249         int     msix_enable;
3250         uint32_t msix_reg_offset[16];
3251         uint8_t mask_interrupts;
3252         uint16_t max_chain_frame_sz;
3253         struct mrsas_mpt_cmd **mpt_cmd_list;
3254         struct mrsas_mfi_cmd **mfi_cmd_list;
3255         TAILQ_HEAD(, mrsas_mpt_cmd) mrsas_mpt_cmd_list_head;
3256         TAILQ_HEAD(, mrsas_mfi_cmd) mrsas_mfi_cmd_list_head;
3257         bus_addr_t req_frames_desc_phys;
3258         u_int8_t *req_frames_desc;
3259         u_int8_t *req_desc;
3260         bus_addr_t io_request_frames_phys;
3261         u_int8_t *io_request_frames;
3262         bus_addr_t reply_frames_desc_phys;
3263         u_int16_t last_reply_idx[MAX_MSIX_COUNT];
3264         u_int32_t reply_q_depth;
3265         u_int32_t request_alloc_sz;
3266         u_int32_t reply_alloc_sz;
3267         u_int32_t io_frames_alloc_sz;
3268         u_int32_t chain_frames_alloc_sz;
3269         u_int16_t max_sge_in_main_msg;
3270         u_int16_t max_sge_in_chain;
3271         u_int8_t chain_offset_io_request;
3272         u_int8_t chain_offset_mfi_pthru;
3273         u_int32_t map_sz;
3274         u_int64_t map_id;
3275         u_int64_t pd_seq_map_id;
3276         struct mrsas_mfi_cmd *map_update_cmd;
3277         struct mrsas_mfi_cmd *jbod_seq_cmd;
3278         struct mrsas_mfi_cmd *aen_cmd;
3279         u_int8_t fast_path_io;
3280         void   *chan;
3281         void   *ocr_chan;
3282         u_int8_t adprecovery;
3283         u_int8_t remove_in_progress;
3284         u_int8_t ocr_thread_active;
3285         u_int8_t do_timedout_reset;
3286         u_int32_t reset_in_progress;
3287         u_int32_t reset_count;
3288         u_int32_t block_sync_cache;
3289         u_int32_t drv_stream_detection;
3290         u_int8_t fw_sync_cache_support;
3291         mrsas_atomic_t target_reset_outstanding;
3292 #define MRSAS_MAX_TM_TARGETS (MRSAS_MAX_PD + MRSAS_MAX_LD_IDS)
3293     struct mrsas_mpt_cmd *target_reset_pool[MRSAS_MAX_TM_TARGETS];
3294
3295         bus_dma_tag_t jbodmap_tag[2];
3296         bus_dmamap_t jbodmap_dmamap[2];
3297         void   *jbodmap_mem[2];
3298         bus_addr_t jbodmap_phys_addr[2];
3299
3300         bus_dma_tag_t raidmap_tag[2];
3301         bus_dmamap_t raidmap_dmamap[2];
3302         void   *raidmap_mem[2];
3303         bus_addr_t raidmap_phys_addr[2];
3304         bus_dma_tag_t mficmd_frame_tag;
3305         bus_dma_tag_t mficmd_sense_tag;
3306         bus_addr_t evt_detail_phys_addr;
3307         bus_dma_tag_t evt_detail_tag;
3308         bus_dmamap_t evt_detail_dmamap;
3309         struct mrsas_evt_detail *evt_detail_mem;
3310         bus_addr_t pd_info_phys_addr;
3311         bus_dma_tag_t pd_info_tag;
3312         bus_dmamap_t pd_info_dmamap;
3313         struct mrsas_pd_info *pd_info_mem;
3314         struct mrsas_ctrl_info *ctrl_info;
3315         bus_dma_tag_t ctlr_info_tag;
3316         bus_dmamap_t ctlr_info_dmamap;
3317         void   *ctlr_info_mem;
3318         bus_addr_t ctlr_info_phys_addr;
3319         u_int32_t max_sectors_per_req;
3320         u_int32_t disableOnlineCtrlReset;
3321         mrsas_atomic_t fw_outstanding;
3322         mrsas_atomic_t prp_count;
3323         mrsas_atomic_t sge_holes;
3324
3325         u_int32_t mrsas_debug;
3326         u_int32_t mrsas_io_timeout;
3327         u_int32_t mrsas_fw_fault_check_delay;
3328         u_int32_t io_cmds_highwater;
3329         u_int8_t UnevenSpanSupport;
3330         struct sysctl_ctx_list sysctl_ctx;
3331         struct sysctl_oid *sysctl_tree;
3332         struct proc *ocr_thread;
3333         u_int32_t last_seq_num;
3334         bus_dma_tag_t el_info_tag;
3335         bus_dmamap_t el_info_dmamap;
3336         void   *el_info_mem;
3337         bus_addr_t el_info_phys_addr;
3338         struct mrsas_pd_list pd_list[MRSAS_MAX_PD];
3339         struct mrsas_pd_list local_pd_list[MRSAS_MAX_PD];
3340         struct mrsas_target target_list[MRSAS_MAX_TM_TARGETS];
3341         u_int8_t ld_ids[MRSAS_MAX_LD_IDS];
3342         struct taskqueue *ev_tq;
3343         struct task ev_task;
3344         u_int32_t CurLdCount;
3345         u_int64_t reset_flags;
3346         int     lb_pending_cmds;
3347         LD_LOAD_BALANCE_INFO load_balance_info[MAX_LOGICAL_DRIVES_EXT];
3348         LD_SPAN_INFO log_to_span[MAX_LOGICAL_DRIVES_EXT];
3349
3350         u_int8_t mrsas_gen3_ctrl;
3351         u_int8_t secure_jbod_support;
3352         u_int8_t use_seqnum_jbod_fp;
3353         /* FW suport for more than 256 PD/JBOD */
3354         u_int32_t support_morethan256jbod;
3355         u_int8_t max256vdSupport;
3356         u_int16_t fw_supported_vd_count;
3357         u_int16_t fw_supported_pd_count;
3358
3359         u_int16_t drv_supported_vd_count;
3360         u_int16_t drv_supported_pd_count;
3361
3362         u_int32_t max_map_sz;
3363         u_int32_t current_map_sz;
3364         u_int32_t old_map_sz;
3365         u_int32_t new_map_sz;
3366         u_int32_t drv_map_sz;
3367
3368         u_int32_t nvme_page_size;
3369         boolean_t is_ventura;
3370         boolean_t is_aero;
3371         boolean_t msix_combined;
3372         boolean_t atomic_desc_support;
3373         u_int16_t maxRaidMapSize;
3374
3375         /* Non dma-able memory. Driver local copy. */
3376         MR_DRV_RAID_MAP_ALL *ld_drv_map[2];
3377         PTR_LD_STREAM_DETECT  *streamDetectByLD;
3378 };
3379
3380 /* Compatibility shims for different OS versions */
3381 #if __FreeBSD_version >= 800001
3382 #define mrsas_kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) \
3383     kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg)
3384 #define mrsas_kproc_exit(arg)   kproc_exit(arg)
3385 #else
3386 #define mrsas_kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) \
3387     kthread_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg)
3388 #define mrsas_kproc_exit(arg)   kthread_exit(arg)
3389 #endif
3390
3391 static __inline void
3392 mrsas_clear_bit(int b, volatile void *p)
3393 {
3394         atomic_clear_int(((volatile int *)p) + (b >> 5), 1 << (b & 0x1f));
3395 }
3396
3397 static __inline void
3398 mrsas_set_bit(int b, volatile void *p)
3399 {
3400         atomic_set_int(((volatile int *)p) + (b >> 5), 1 << (b & 0x1f));
3401 }
3402
3403 static __inline int
3404 mrsas_test_bit(int b, volatile void *p)
3405 {
3406         return ((volatile int *)p)[b >> 5] & (1 << (b & 0x1f));
3407 }
3408
3409 #endif                                  /* MRSAS_H */