2 * Copyright (c) 2015, AVAGO Tech. All rights reserved. Authors: Marian Choy
3 * Copyright (c) 2014, LSI Corp. All rights reserved. Authors: Marian Choy
4 * Support: freebsdraid@avagotech.com
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer. 2. Redistributions
12 * in binary form must reproduce the above copyright notice, this list of
13 * conditions and the following disclaimer in the documentation and/or other
14 * materials provided with the distribution. 3. Neither the name of the
15 * <ORGANIZATION> nor the names of its contributors may be used to endorse or
16 * promote products derived from this software without specific prior written
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
31 * The views and conclusions contained in the software and documentation are
32 * those of the authors and should not be interpreted as representing
33 * official policies,either expressed or implied, of the FreeBSD Project.
35 * Send feedback to: <megaraidfbsd@avagotech.com> Mail to: AVAGO TECHNOLOGIES, 1621
36 * Barber Lane, Milpitas, CA 95035 ATTN: MegaRaid FreeBSD
40 #include <sys/cdefs.h>
41 __FBSDID("$FreeBSD$");
46 #include <sys/param.h> /* defines used in kernel.h */
47 #include <sys/module.h>
48 #include <sys/systm.h>
50 #include <sys/errno.h>
51 #include <sys/kernel.h> /* types used in module initialization */
52 #include <sys/conf.h> /* cdevsw struct */
53 #include <sys/uio.h> /* uio struct */
54 #include <sys/malloc.h>
55 #include <sys/bus.h> /* structs, prototypes for pci bus
58 #include <sys/types.h>
61 #include <sys/sysctl.h>
63 #include <sys/taskqueue.h>
65 #include <sys/selinfo.h>
67 #include <machine/bus.h>
68 #include <machine/resource.h>
69 #include <machine/atomic.h>
71 #include <dev/pci/pcivar.h> /* For pci_get macros! */
72 #include <dev/pci/pcireg.h>
75 #define IOCTL_SEMA_DESCRIPTION "mrsas semaphore for MFI pool"
80 #define MRSAS_TBOLT 0x005b
81 #define MRSAS_INVADER 0x005d
82 #define MRSAS_FURY 0x005f
83 #define MRSAS_INTRUDER 0x00ce
84 #define MRSAS_INTRUDER_24 0x00cf
85 #define MRSAS_CUTLASS_52 0x0052
86 #define MRSAS_CUTLASS_53 0x0053
87 #define MRSAS_PCI_BAR0 0x10
88 #define MRSAS_PCI_BAR1 0x14
89 #define MRSAS_PCI_BAR2 0x1C
92 * Firmware State Defines
94 #define MRSAS_FWSTATE_MAXCMD_MASK 0x0000FFFF
95 #define MRSAS_FWSTATE_SGE_MASK 0x00FF0000
96 #define MRSAS_FW_STATE_CHNG_INTERRUPT 1
99 * Message Frame Defines
101 #define MRSAS_SENSE_LEN 96
102 #define MRSAS_FUSION_MAX_RESET_TRIES 3
105 * Miscellaneous Defines
107 #define BYTE_ALIGNMENT 1
108 #define MRSAS_MAX_NAME_LENGTH 32
109 #define MRSAS_VERSION "06.712.04.00-fbsd"
110 #define MRSAS_ULONG_MAX 0xFFFFFFFFFFFFFFFF
111 #define MRSAS_DEFAULT_TIMEOUT 0x14 /* Temporarily set */
113 #define MRSAS_PAGE_SIZE 4096
114 #define MRSAS_RESET_NOTICE_INTERVAL 5
115 #define MRSAS_IO_TIMEOUT 180000 /* 180 second timeout */
116 #define MRSAS_LDIO_QUEUE_DEPTH 70 /* 70 percent as default */
117 #define THRESHOLD_REPLY_COUNT 50
118 #define MAX_MSIX_COUNT 128
123 #if (__FreeBSD_version < 901000)
124 typedef enum _boolean {
133 MALLOC_DECLARE(M_MRSAS);
134 SYSCTL_DECL(_hw_mrsas);
136 #define MRSAS_INFO (1 << 0)
137 #define MRSAS_TRACE (1 << 1)
138 #define MRSAS_FAULT (1 << 2)
139 #define MRSAS_OCR (1 << 3)
140 #define MRSAS_TOUT MRSAS_OCR
141 #define MRSAS_AEN (1 << 4)
142 #define MRSAS_PRL11 (1 << 5)
144 #define mrsas_dprint(sc, level, msg, args...) \
146 if (sc->mrsas_debug & level) \
147 device_printf(sc->mrsas_dev, msg, ##args); \
151 /****************************************************************************
152 * Raid Context structure which describes MegaRAID specific IO Paramenters
153 * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames
154 ****************************************************************************/
156 typedef struct _RAID_CONTEXT {
160 u_int16_t timeoutValue;
161 u_int8_t regLockFlags;
163 u_int16_t VirtualDiskTgtId;
164 u_int64_t regLockRowLBA;
165 u_int32_t regLockLength;
171 u_int16_t configSeqNum;
173 u_int8_t priority; /* 0x1D MR_PRIORITY_RANGE */
174 u_int8_t numSGEExt; /* 0x1E 1M IO support */
175 u_int8_t resvd2; /* 0x1F */
179 /*************************************************************************
181 ************************************************************************/
183 #define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */
184 #define MPI2_WHOINIT_HOST_DRIVER (0x04)
185 #define MPI2_VERSION_MAJOR (0x02)
186 #define MPI2_VERSION_MINOR (0x00)
187 #define MPI2_VERSION_MAJOR_MASK (0xFF00)
188 #define MPI2_VERSION_MAJOR_SHIFT (8)
189 #define MPI2_VERSION_MINOR_MASK (0x00FF)
190 #define MPI2_VERSION_MINOR_SHIFT (0)
191 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
193 #define MPI2_HEADER_VERSION_UNIT (0x10)
194 #define MPI2_HEADER_VERSION_DEV (0x00)
195 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00)
196 #define MPI2_HEADER_VERSION_UNIT_SHIFT (8)
197 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF)
198 #define MPI2_HEADER_VERSION_DEV_SHIFT (0)
199 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | MPI2_HEADER_VERSION_DEV)
200 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03)
201 #define MPI2_SCSIIO_EEDPFLAGS_INC_PRI_REFTAG (0x8000)
202 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REFTAG (0x0400)
203 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REMOVE_OP (0x0003)
204 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_APPTAG (0x0200)
205 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_GUARD (0x0100)
206 #define MPI2_SCSIIO_EEDPFLAGS_INSERT_OP (0x0004)
207 #define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */
208 #define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01)
209 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x03)
210 #define MPI2_REQ_DESCRIPT_FLAGS_FP_IO (0x06)
211 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00)
212 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02)
213 #define MPI2_SCSIIO_CONTROL_WRITE (0x01000000)
214 #define MPI2_SCSIIO_CONTROL_READ (0x02000000)
215 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E)
216 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F)
217 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00)
218 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F)
219 #define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0)
220 #define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004)
221 #define MPI2_WRSEQ_1ST_KEY_VALUE (0xF)
222 #define MPI2_WRSEQ_2ND_KEY_VALUE (0x4)
223 #define MPI2_WRSEQ_3RD_KEY_VALUE (0xB)
224 #define MPI2_WRSEQ_4TH_KEY_VALUE (0x2)
225 #define MPI2_WRSEQ_5TH_KEY_VALUE (0x7)
226 #define MPI2_WRSEQ_6TH_KEY_VALUE (0xD)
229 #define MPI2_POINTER *
233 /***************************************
235 ***************************************/
237 typedef struct _MPI25_IEEE_SGE_CHAIN64 {
241 u_int8_t NextChainOffset;
243 } MPI25_IEEE_SGE_CHAIN64, MPI2_POINTER PTR_MPI25_IEEE_SGE_CHAIN64,
244 Mpi25IeeeSgeChain64_t, MPI2_POINTER pMpi25IeeeSgeChain64_t;
246 typedef struct _MPI2_SGE_SIMPLE_UNION {
247 u_int32_t FlagsLength;
252 } MPI2_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_SIMPLE_UNION,
253 Mpi2SGESimpleUnion_t, MPI2_POINTER pMpi2SGESimpleUnion_t;
256 u_int8_t CDB[20]; /* 0x00 */
257 u_int32_t PrimaryReferenceTag; /* 0x14 */
258 u_int16_t PrimaryApplicationTag;/* 0x18 */
259 u_int16_t PrimaryApplicationTagMask; /* 0x1A */
260 u_int32_t TransferLength; /* 0x1C */
261 } MPI2_SCSI_IO_CDB_EEDP32, MPI2_POINTER PTR_MPI2_SCSI_IO_CDB_EEDP32,
262 Mpi2ScsiIoCdbEedp32_t, MPI2_POINTER pMpi2ScsiIoCdbEedp32_t;
264 typedef struct _MPI2_SGE_CHAIN_UNION {
266 u_int8_t NextChainOffset;
272 } MPI2_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_SGE_CHAIN_UNION,
273 Mpi2SGEChainUnion_t, MPI2_POINTER pMpi2SGEChainUnion_t;
275 typedef struct _MPI2_IEEE_SGE_SIMPLE32 {
277 u_int32_t FlagsLength;
278 } MPI2_IEEE_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE32,
279 Mpi2IeeeSgeSimple32_t, MPI2_POINTER pMpi2IeeeSgeSimple32_t;
280 typedef struct _MPI2_IEEE_SGE_SIMPLE64 {
286 } MPI2_IEEE_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE64,
287 Mpi2IeeeSgeSimple64_t, MPI2_POINTER pMpi2IeeeSgeSimple64_t;
289 typedef union _MPI2_IEEE_SGE_SIMPLE_UNION {
290 MPI2_IEEE_SGE_SIMPLE32 Simple32;
291 MPI2_IEEE_SGE_SIMPLE64 Simple64;
292 } MPI2_IEEE_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE_UNION,
293 Mpi2IeeeSgeSimpleUnion_t, MPI2_POINTER pMpi2IeeeSgeSimpleUnion_t;
295 typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32;
296 typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64;
298 typedef union _MPI2_IEEE_SGE_CHAIN_UNION {
299 MPI2_IEEE_SGE_CHAIN32 Chain32;
300 MPI2_IEEE_SGE_CHAIN64 Chain64;
301 } MPI2_IEEE_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_CHAIN_UNION,
302 Mpi2IeeeSgeChainUnion_t, MPI2_POINTER pMpi2IeeeSgeChainUnion_t;
304 typedef union _MPI2_SGE_IO_UNION {
305 MPI2_SGE_SIMPLE_UNION MpiSimple;
306 MPI2_SGE_CHAIN_UNION MpiChain;
307 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
308 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain;
309 } MPI2_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_SGE_IO_UNION,
310 Mpi2SGEIOUnion_t, MPI2_POINTER pMpi2SGEIOUnion_t;
314 MPI2_SCSI_IO_CDB_EEDP32 EEDP32;
315 MPI2_SGE_SIMPLE_UNION SGE;
316 } MPI2_SCSI_IO_CDB_UNION, MPI2_POINTER PTR_MPI2_SCSI_IO_CDB_UNION,
317 Mpi2ScsiIoCdb_t, MPI2_POINTER pMpi2ScsiIoCdb_t;
319 /****************************************************************************
320 * * SCSI Task Management messages
321 * ****************************************************************************/
323 /*SCSI Task Management Request Message */
324 typedef struct _MPI2_SCSI_TASK_MANAGE_REQUEST {
325 u_int16_t DevHandle; /*0x00 */
326 u_int8_t ChainOffset; /*0x02 */
327 u_int8_t Function; /*0x03 */
328 u_int8_t Reserved1; /*0x04 */
329 u_int8_t TaskType; /*0x05 */
330 u_int8_t Reserved2; /*0x06 */
331 u_int8_t MsgFlags; /*0x07 */
332 u_int8_t VP_ID; /*0x08 */
333 u_int8_t VF_ID; /*0x09 */
334 u_int16_t Reserved3; /*0x0A */
335 u_int8_t LUN[8]; /*0x0C */
336 u_int32_t Reserved4[7]; /*0x14 */
337 u_int16_t TaskMID; /*0x30 */
338 u_int16_t Reserved5; /*0x32 */
339 } MPI2_SCSI_TASK_MANAGE_REQUEST;
341 /*SCSI Task Management Reply Message */
342 typedef struct _MPI2_SCSI_TASK_MANAGE_REPLY {
343 u_int16_t DevHandle; /*0x00 */
344 u_int8_t MsgLength; /*0x02 */
345 u_int8_t Function; /*0x03 */
346 u_int8_t ResponseCode; /*0x04 */
347 u_int8_t TaskType; /*0x05 */
348 u_int8_t Reserved1; /*0x06 */
349 u_int8_t MsgFlags; /*0x07 */
350 u_int8_t VP_ID; /*0x08 */
351 u_int8_t VF_ID; /*0x09 */
352 u_int16_t Reserved2; /*0x0A */
353 u_int16_t Reserved3; /*0x0C */
354 u_int16_t IOCStatus; /*0x0E */
355 u_int32_t IOCLogInfo; /*0x10 */
356 u_int32_t TerminationCount; /*0x14 */
357 u_int32_t ResponseInfo; /*0x18 */
358 } MPI2_SCSI_TASK_MANAGE_REPLY;
360 typedef struct _MR_TM_REQUEST {
364 typedef struct _MR_TM_REPLY {
368 /* SCSI Task Management Request Message */
369 typedef struct _MR_TASK_MANAGE_REQUEST {
370 /*To be type casted to struct MPI2_SCSI_TASK_MANAGE_REQUEST */
371 MR_TM_REQUEST TmRequest;
374 u_int32_t isTMForLD:1;
375 u_int32_t isTMForPD:1;
376 u_int32_t reserved1:30;
381 } MR_TASK_MANAGE_REQUEST;
383 /* TaskType values */
384 #define MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK (0x01)
385 #define MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET (0x02)
386 #define MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET (0x03)
387 #define MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET (0x05)
388 #define MPI2_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET (0x06)
389 #define MPI2_SCSITASKMGMT_TASKTYPE_QUERY_TASK (0x07)
390 #define MPI2_SCSITASKMGMT_TASKTYPE_CLR_ACA (0x08)
391 #define MPI2_SCSITASKMGMT_TASKTYPE_QRY_TASK_SET (0x09)
392 #define MPI2_SCSITASKMGMT_TASKTYPE_QRY_ASYNC_EVENT (0x0A)
394 /* ResponseCode values */
395 #define MPI2_SCSITASKMGMT_RSP_TM_COMPLETE (0x00)
396 #define MPI2_SCSITASKMGMT_RSP_INVALID_FRAME (0x02)
397 #define MPI2_SCSITASKMGMT_RSP_TM_NOT_SUPPORTED (0x04)
398 #define MPI2_SCSITASKMGMT_RSP_TM_FAILED (0x05)
399 #define MPI2_SCSITASKMGMT_RSP_TM_SUCCEEDED (0x08)
400 #define MPI2_SCSITASKMGMT_RSP_TM_INVALID_LUN (0x09)
401 #define MPI2_SCSITASKMGMT_RSP_TM_OVERLAPPED_TAG (0x0A)
402 #define MPI2_SCSITASKMGMT_RSP_IO_QUEUED_ON_IOC (0x80)
405 * RAID SCSI IO Request Message Total SGE count will be one less than
406 * _MPI2_SCSI_IO_REQUEST
408 typedef struct _MPI2_RAID_SCSI_IO_REQUEST {
409 u_int16_t DevHandle; /* 0x00 */
410 u_int8_t ChainOffset; /* 0x02 */
411 u_int8_t Function; /* 0x03 */
412 u_int16_t Reserved1; /* 0x04 */
413 u_int8_t Reserved2; /* 0x06 */
414 u_int8_t MsgFlags; /* 0x07 */
415 u_int8_t VP_ID; /* 0x08 */
416 u_int8_t VF_ID; /* 0x09 */
417 u_int16_t Reserved3; /* 0x0A */
418 u_int32_t SenseBufferLowAddress;/* 0x0C */
419 u_int16_t SGLFlags; /* 0x10 */
420 u_int8_t SenseBufferLength; /* 0x12 */
421 u_int8_t Reserved4; /* 0x13 */
422 u_int8_t SGLOffset0; /* 0x14 */
423 u_int8_t SGLOffset1; /* 0x15 */
424 u_int8_t SGLOffset2; /* 0x16 */
425 u_int8_t SGLOffset3; /* 0x17 */
426 u_int32_t SkipCount; /* 0x18 */
427 u_int32_t DataLength; /* 0x1C */
428 u_int32_t BidirectionalDataLength; /* 0x20 */
429 u_int16_t IoFlags; /* 0x24 */
430 u_int16_t EEDPFlags; /* 0x26 */
431 u_int32_t EEDPBlockSize; /* 0x28 */
432 u_int32_t SecondaryReferenceTag;/* 0x2C */
433 u_int16_t SecondaryApplicationTag; /* 0x30 */
434 u_int16_t ApplicationTagTranslationMask; /* 0x32 */
435 u_int8_t LUN[8]; /* 0x34 */
436 u_int32_t Control; /* 0x3C */
437 MPI2_SCSI_IO_CDB_UNION CDB; /* 0x40 */
438 RAID_CONTEXT RaidContext; /* 0x60 */
439 MPI2_SGE_IO_UNION SGL; /* 0x80 */
440 } MRSAS_RAID_SCSI_IO_REQUEST, MPI2_POINTER PTR_MRSAS_RAID_SCSI_IO_REQUEST,
441 MRSASRaidSCSIIORequest_t, MPI2_POINTER pMRSASRaidSCSIIORequest_t;
444 * MPT RAID MFA IO Descriptor.
446 typedef struct _MRSAS_RAID_MFA_IO_DESCRIPTOR {
447 u_int32_t RequestFlags:8;
448 u_int32_t MessageAddress1:24; /* bits 31:8 */
449 u_int32_t MessageAddress2; /* bits 61:32 */
450 } MRSAS_RAID_MFA_IO_REQUEST_DESCRIPTOR, *PMRSAS_RAID_MFA_IO_REQUEST_DESCRIPTOR;
452 /* Default Request Descriptor */
453 typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR {
454 u_int8_t RequestFlags; /* 0x00 */
455 u_int8_t MSIxIndex; /* 0x01 */
456 u_int16_t SMID; /* 0x02 */
457 u_int16_t LMID; /* 0x04 */
458 u_int16_t DescriptorTypeDependent; /* 0x06 */
459 } MPI2_DEFAULT_REQUEST_DESCRIPTOR,
461 MPI2_POINTER PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR,
462 Mpi2DefaultRequestDescriptor_t, MPI2_POINTER pMpi2DefaultRequestDescriptor_t;
464 /* High Priority Request Descriptor */
465 typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR {
466 u_int8_t RequestFlags; /* 0x00 */
467 u_int8_t MSIxIndex; /* 0x01 */
468 u_int16_t SMID; /* 0x02 */
469 u_int16_t LMID; /* 0x04 */
470 u_int16_t Reserved1; /* 0x06 */
471 } MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
473 MPI2_POINTER PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
474 Mpi2HighPriorityRequestDescriptor_t, MPI2_POINTER pMpi2HighPriorityRequestDescriptor_t;
476 /* SCSI IO Request Descriptor */
477 typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR {
478 u_int8_t RequestFlags; /* 0x00 */
479 u_int8_t MSIxIndex; /* 0x01 */
480 u_int16_t SMID; /* 0x02 */
481 u_int16_t LMID; /* 0x04 */
482 u_int16_t DevHandle; /* 0x06 */
483 } MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
485 MPI2_POINTER PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
486 Mpi2SCSIIORequestDescriptor_t, MPI2_POINTER pMpi2SCSIIORequestDescriptor_t;
488 /* SCSI Target Request Descriptor */
489 typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR {
490 u_int8_t RequestFlags; /* 0x00 */
491 u_int8_t MSIxIndex; /* 0x01 */
492 u_int16_t SMID; /* 0x02 */
493 u_int16_t LMID; /* 0x04 */
494 u_int16_t IoIndex; /* 0x06 */
495 } MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
497 MPI2_POINTER PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
498 Mpi2SCSITargetRequestDescriptor_t, MPI2_POINTER pMpi2SCSITargetRequestDescriptor_t;
500 /* RAID Accelerator Request Descriptor */
501 typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR {
502 u_int8_t RequestFlags; /* 0x00 */
503 u_int8_t MSIxIndex; /* 0x01 */
504 u_int16_t SMID; /* 0x02 */
505 u_int16_t LMID; /* 0x04 */
506 u_int16_t Reserved; /* 0x06 */
507 } MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
509 MPI2_POINTER PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
510 Mpi2RAIDAcceleratorRequestDescriptor_t, MPI2_POINTER pMpi2RAIDAcceleratorRequestDescriptor_t;
512 /* union of Request Descriptors */
513 typedef union _MRSAS_REQUEST_DESCRIPTOR_UNION {
514 MPI2_DEFAULT_REQUEST_DESCRIPTOR Default;
515 MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority;
516 MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO;
517 MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget;
518 MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator;
519 MRSAS_RAID_MFA_IO_REQUEST_DESCRIPTOR MFAIo;
527 } MRSAS_REQUEST_DESCRIPTOR_UNION;
529 /* Default Reply Descriptor */
530 typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR {
531 u_int8_t ReplyFlags; /* 0x00 */
532 u_int8_t MSIxIndex; /* 0x01 */
533 u_int16_t DescriptorTypeDependent1; /* 0x02 */
534 u_int32_t DescriptorTypeDependent2; /* 0x04 */
535 } MPI2_DEFAULT_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR,
536 Mpi2DefaultReplyDescriptor_t, MPI2_POINTER pMpi2DefaultReplyDescriptor_t;
538 /* Address Reply Descriptor */
539 typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR {
540 u_int8_t ReplyFlags; /* 0x00 */
541 u_int8_t MSIxIndex; /* 0x01 */
542 u_int16_t SMID; /* 0x02 */
543 u_int32_t ReplyFrameAddress; /* 0x04 */
544 } MPI2_ADDRESS_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR,
545 Mpi2AddressReplyDescriptor_t, MPI2_POINTER pMpi2AddressReplyDescriptor_t;
547 /* SCSI IO Success Reply Descriptor */
548 typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR {
549 u_int8_t ReplyFlags; /* 0x00 */
550 u_int8_t MSIxIndex; /* 0x01 */
551 u_int16_t SMID; /* 0x02 */
552 u_int16_t TaskTag; /* 0x04 */
553 u_int16_t Reserved1; /* 0x06 */
554 } MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
556 MPI2_POINTER PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
557 Mpi2SCSIIOSuccessReplyDescriptor_t, MPI2_POINTER pMpi2SCSIIOSuccessReplyDescriptor_t;
559 /* TargetAssist Success Reply Descriptor */
560 typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR {
561 u_int8_t ReplyFlags; /* 0x00 */
562 u_int8_t MSIxIndex; /* 0x01 */
563 u_int16_t SMID; /* 0x02 */
564 u_int8_t SequenceNumber; /* 0x04 */
565 u_int8_t Reserved1; /* 0x05 */
566 u_int16_t IoIndex; /* 0x06 */
567 } MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
569 MPI2_POINTER PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
570 Mpi2TargetAssistSuccessReplyDescriptor_t, MPI2_POINTER pMpi2TargetAssistSuccessReplyDescriptor_t;
572 /* Target Command Buffer Reply Descriptor */
573 typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR {
574 u_int8_t ReplyFlags; /* 0x00 */
575 u_int8_t MSIxIndex; /* 0x01 */
576 u_int8_t VP_ID; /* 0x02 */
577 u_int8_t Flags; /* 0x03 */
578 u_int16_t InitiatorDevHandle; /* 0x04 */
579 u_int16_t IoIndex; /* 0x06 */
580 } MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
582 MPI2_POINTER PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
583 Mpi2TargetCommandBufferReplyDescriptor_t, MPI2_POINTER pMpi2TargetCommandBufferReplyDescriptor_t;
585 /* RAID Accelerator Success Reply Descriptor */
586 typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR {
587 u_int8_t ReplyFlags; /* 0x00 */
588 u_int8_t MSIxIndex; /* 0x01 */
589 u_int16_t SMID; /* 0x02 */
590 u_int32_t Reserved; /* 0x04 */
591 } MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
593 MPI2_POINTER PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
594 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t, MPI2_POINTER pMpi2RAIDAcceleratorSuccessReplyDescriptor_t;
596 /* union of Reply Descriptors */
597 typedef union _MPI2_REPLY_DESCRIPTORS_UNION {
598 MPI2_DEFAULT_REPLY_DESCRIPTOR Default;
599 MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply;
600 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess;
601 MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess;
602 MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer;
603 MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess;
605 } MPI2_REPLY_DESCRIPTORS_UNION, MPI2_POINTER PTR_MPI2_REPLY_DESCRIPTORS_UNION,
606 Mpi2ReplyDescriptorsUnion_t, MPI2_POINTER pMpi2ReplyDescriptorsUnion_t;
609 volatile unsigned int val;
610 unsigned int val_rdonly;
613 #define mrsas_atomic_read(v) atomic_load_acq_int(&(v)->val)
614 #define mrsas_atomic_set(v,i) atomic_store_rel_int(&(v)->val, i)
615 #define mrsas_atomic_dec(v) atomic_fetchadd_int(&(v)->val, -1)
616 #define mrsas_atomic_inc(v) atomic_fetchadd_int(&(v)->val, 1)
618 /* IOCInit Request message */
619 typedef struct _MPI2_IOC_INIT_REQUEST {
620 u_int8_t WhoInit; /* 0x00 */
621 u_int8_t Reserved1; /* 0x01 */
622 u_int8_t ChainOffset; /* 0x02 */
623 u_int8_t Function; /* 0x03 */
624 u_int16_t Reserved2; /* 0x04 */
625 u_int8_t Reserved3; /* 0x06 */
626 u_int8_t MsgFlags; /* 0x07 */
627 u_int8_t VP_ID; /* 0x08 */
628 u_int8_t VF_ID; /* 0x09 */
629 u_int16_t Reserved4; /* 0x0A */
630 u_int16_t MsgVersion; /* 0x0C */
631 u_int16_t HeaderVersion; /* 0x0E */
632 u_int32_t Reserved5; /* 0x10 */
633 u_int16_t Reserved6; /* 0x14 */
634 u_int8_t Reserved7; /* 0x16 */
635 u_int8_t HostMSIxVectors; /* 0x17 */
636 u_int16_t Reserved8; /* 0x18 */
637 u_int16_t SystemRequestFrameSize; /* 0x1A */
638 u_int16_t ReplyDescriptorPostQueueDepth; /* 0x1C */
639 u_int16_t ReplyFreeQueueDepth; /* 0x1E */
640 u_int32_t SenseBufferAddressHigh; /* 0x20 */
641 u_int32_t SystemReplyAddressHigh; /* 0x24 */
642 u_int64_t SystemRequestFrameBaseAddress; /* 0x28 */
643 u_int64_t ReplyDescriptorPostQueueAddress; /* 0x30 */
644 u_int64_t ReplyFreeQueueAddress;/* 0x38 */
645 u_int64_t TimeStamp; /* 0x40 */
646 } MPI2_IOC_INIT_REQUEST, MPI2_POINTER PTR_MPI2_IOC_INIT_REQUEST,
647 Mpi2IOCInitRequest_t, MPI2_POINTER pMpi2IOCInitRequest_t;
652 #define MR_PD_INVALID 0xFFFF
653 #define MAX_SPAN_DEPTH 8
654 #define MAX_QUAD_DEPTH MAX_SPAN_DEPTH
655 #define MAX_RAIDMAP_SPAN_DEPTH (MAX_SPAN_DEPTH)
656 #define MAX_ROW_SIZE 32
657 #define MAX_RAIDMAP_ROW_SIZE (MAX_ROW_SIZE)
658 #define MAX_LOGICAL_DRIVES 64
659 #define MAX_LOGICAL_DRIVES_EXT 256
661 #define MAX_RAIDMAP_LOGICAL_DRIVES (MAX_LOGICAL_DRIVES)
662 #define MAX_RAIDMAP_VIEWS (MAX_LOGICAL_DRIVES)
664 #define MAX_ARRAYS 128
665 #define MAX_RAIDMAP_ARRAYS (MAX_ARRAYS)
667 #define MAX_ARRAYS_EXT 256
668 #define MAX_API_ARRAYS_EXT MAX_ARRAYS_EXT
670 #define MAX_PHYSICAL_DEVICES 256
671 #define MAX_RAIDMAP_PHYSICAL_DEVICES (MAX_PHYSICAL_DEVICES)
672 #define MR_DCMD_LD_MAP_GET_INFO 0x0300e101
673 #define MR_DCMD_SYSTEM_PD_MAP_GET_INFO 0x0200e102
674 #define MR_DCMD_PD_MFI_TASK_MGMT 0x0200e100
676 #define MRSAS_MAX_PD_CHANNELS 1
677 #define MRSAS_MAX_LD_CHANNELS 1
678 #define MRSAS_MAX_DEV_PER_CHANNEL 256
679 #define MRSAS_DEFAULT_INIT_ID -1
680 #define MRSAS_MAX_LUN 8
681 #define MRSAS_DEFAULT_CMD_PER_LUN 256
682 #define MRSAS_MAX_PD (MRSAS_MAX_PD_CHANNELS * \
683 MRSAS_MAX_DEV_PER_CHANNEL)
684 #define MRSAS_MAX_LD_IDS (MRSAS_MAX_LD_CHANNELS * \
685 MRSAS_MAX_DEV_PER_CHANNEL)
688 #define VD_EXT_DEBUG 0
691 /*******************************************************************
692 * RAID map related structures
693 ********************************************************************/
695 typedef struct _MR_DEV_HANDLE_INFO {
697 u_int8_t validHandles;
699 u_int16_t devHandle[2];
700 } MR_DEV_HANDLE_INFO;
704 typedef struct _MR_ARRAY_INFO {
705 u_int16_t pd[MAX_RAIDMAP_ROW_SIZE];
708 typedef struct _MR_QUAD_ELEMENT {
711 u_int64_t offsetInSpan;
716 typedef struct _MR_SPAN_INFO {
717 u_int32_t noElements;
719 MR_QUAD_ELEMENT quad[MAX_RAIDMAP_SPAN_DEPTH];
722 typedef struct _MR_LD_SPAN_ {
726 u_int8_t spanRowSize;
727 u_int8_t spanRowDataSize;
728 u_int8_t reserved[4];
731 typedef struct _MR_SPAN_BLOCK_INFO {
734 MR_SPAN_INFO block_span_info;
735 } MR_SPAN_BLOCK_INFO;
737 typedef struct _MR_LD_RAID {
739 u_int32_t fpCapable:1;
740 u_int32_t reserved5:3;
741 u_int32_t ldPiMode:4;
742 u_int32_t pdPiMode:4;
743 u_int32_t encryptionType:8;
744 u_int32_t fpWriteCapable:1;
745 u_int32_t fpReadCapable:1;
746 u_int32_t fpWriteAcrossStripe:1;
747 u_int32_t fpReadAcrossStripe:1;
748 u_int32_t fpNonRWCapable:1;
749 u_int32_t tmCapable:1;
750 u_int32_t reserved4:6;
757 u_int8_t stripeShift;
760 u_int8_t rowDataSize;
767 u_int8_t regTypeReqOnWrite;
769 u_int8_t regTypeReqOnRead;
773 u_int32_t ldSyncRequired:1;
774 u_int32_t regTypeReqOnReadLsValid:1;
775 u_int32_t reserved:30;
779 u_int8_t fpIoTimeoutForLd;
780 u_int8_t reserved2[3];
781 u_int32_t logicalBlockLength;
784 u_int32_t LdLogicalBlockExp:4;
785 u_int32_t reserved1:24;
787 u_int8_t reserved3[0x80 - 0x38];
790 typedef struct _MR_LD_SPAN_MAP {
792 u_int8_t dataArmMap[MAX_RAIDMAP_ROW_SIZE];
793 MR_SPAN_BLOCK_INFO spanBlock[MAX_RAIDMAP_SPAN_DEPTH];
796 typedef struct _MR_FW_RAID_MAP {
801 u_int32_t maxSpanDepth;
802 u_int32_t maxRowSize;
803 u_int32_t maxPdCount;
806 u_int32_t version[5];
807 u_int32_t reserved1[5];
813 * This doesn't correspond to FW Ld Tgt Id to LD, but will purge. For
814 * example: if tgt Id is 4 and FW LD is 2, and there is only one LD,
815 * FW will populate the array like this. [0xFF, 0xFF, 0xFF, 0xFF,
816 * 0x0,.....]. This is to help reduce the entire strcture size if
817 * there are few LDs or driver is looking info for 1 LD only.
819 u_int8_t ldTgtIdToLd[MAX_RAIDMAP_LOGICAL_DRIVES + MAX_RAIDMAP_VIEWS];
820 u_int8_t fpPdIoTimeoutSec;
821 u_int8_t reserved2[7];
822 MR_ARRAY_INFO arMapInfo[MAX_RAIDMAP_ARRAYS];
823 MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES];
824 MR_LD_SPAN_MAP ldSpanMap[1];
828 typedef struct _MR_FW_RAID_MAP_EXT {
829 /* Not used in new map */
835 u_int32_t maxSpanDepth;
836 u_int32_t maxRowSize;
837 u_int32_t maxPdCount;
840 u_int32_t version[5];
841 u_int32_t reserved1[5];
844 u_int8_t fpPdIoTimeoutSec;
845 u_int8_t reserved2[7];
852 MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES];
853 u_int8_t ldTgtIdToLd[MAX_LOGICAL_DRIVES_EXT];
854 MR_ARRAY_INFO arMapInfo[MAX_API_ARRAYS_EXT];
855 MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES_EXT];
856 } MR_FW_RAID_MAP_EXT;
859 typedef struct _MR_DRV_RAID_MAP {
861 * Total size of this structure, including this field. This feild
862 * will be manupulated by driver for ext raid map, else pick the
863 * value from firmware raid map.
870 u_int32_t maxSpanDepth;
871 u_int32_t maxRowSize;
872 u_int32_t maxPdCount;
875 u_int32_t version[5];
876 u_int32_t reserved1[5];
879 /* timeout value used by driver in FP IOs */
880 u_int8_t fpPdIoTimeoutSec;
881 u_int8_t reserved2[7];
888 MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES];
889 u_int8_t ldTgtIdToLd[MAX_LOGICAL_DRIVES_EXT];
890 MR_ARRAY_INFO arMapInfo[MAX_API_ARRAYS_EXT];
891 MR_LD_SPAN_MAP ldSpanMap[1];
896 * Driver raid map size is same as raid map ext MR_DRV_RAID_MAP_ALL is
897 * created to sync with old raid. And it is mainly for code re-use purpose.
901 typedef struct _MR_DRV_RAID_MAP_ALL {
903 MR_DRV_RAID_MAP raidMap;
904 MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES_EXT - 1];
905 } MR_DRV_RAID_MAP_ALL;
909 typedef struct _LD_LOAD_BALANCE_INFO {
910 u_int8_t loadBalanceFlag;
912 mrsas_atomic_t scsi_pending_cmds[MAX_PHYSICAL_DEVICES];
913 u_int64_t last_accessed_block[MAX_PHYSICAL_DEVICES];
914 } LD_LOAD_BALANCE_INFO, *PLD_LOAD_BALANCE_INFO;
916 /* SPAN_SET is info caclulated from span info from Raid map per ld */
917 typedef struct _LD_SPAN_SET {
918 u_int64_t log_start_lba;
919 u_int64_t log_end_lba;
920 u_int64_t span_row_start;
921 u_int64_t span_row_end;
922 u_int64_t data_strip_start;
923 u_int64_t data_strip_end;
924 u_int64_t data_row_start;
925 u_int64_t data_row_end;
926 u_int8_t strip_offset[MAX_SPAN_DEPTH];
927 u_int32_t span_row_data_width;
929 u_int32_t reserved[2];
930 } LD_SPAN_SET, *PLD_SPAN_SET;
932 typedef struct LOG_BLOCK_SPAN_INFO {
933 LD_SPAN_SET span_set[MAX_SPAN_DEPTH];
934 } LD_SPAN_INFO, *PLD_SPAN_INFO;
937 typedef struct _MR_FW_RAID_MAP_ALL {
938 MR_FW_RAID_MAP raidMap;
939 MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES - 1];
940 } MR_FW_RAID_MAP_ALL;
944 struct IO_REQUEST_INFO {
945 u_int64_t ldStartBlock;
952 u_int8_t IoforUnevenSpan;
956 /* span[7:5], arm[4:0] */
958 u_int8_t pd_after_lb;
962 * define MR_PD_CFG_SEQ structure for system PDs
964 struct MR_PD_CFG_SEQ {
968 u_int8_t tmCapable:1;
971 u_int8_t reserved[3];
974 struct MR_PD_CFG_SEQ_NUM_SYNC {
977 struct MR_PD_CFG_SEQ seq[1];
981 typedef struct _MR_LD_TARGET_SYNC {
987 #define IEEE_SGE_FLAGS_ADDR_MASK (0x03)
988 #define IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00)
989 #define IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01)
990 #define IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02)
991 #define IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03)
992 #define IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80)
993 #define IEEE_SGE_FLAGS_END_OF_LIST (0x40)
1003 /*******************************************************************
1005 ********************************************************************/
1006 struct mrsas_tmp_dcmd {
1007 bus_dma_tag_t tmp_dcmd_tag;
1008 bus_dmamap_t tmp_dcmd_dmamap;
1010 bus_addr_t tmp_dcmd_phys_addr;
1013 /*******************************************************************
1014 * Register set, included legacy controllers 1068 and 1078,
1015 * structure extended for 1078 registers
1016 *******************************************************************/
1018 typedef struct _mrsas_register_set {
1019 u_int32_t doorbell; /* 0000h */
1020 u_int32_t fusion_seq_offset; /* 0004h */
1021 u_int32_t fusion_host_diag; /* 0008h */
1022 u_int32_t reserved_01; /* 000Ch */
1024 u_int32_t inbound_msg_0; /* 0010h */
1025 u_int32_t inbound_msg_1; /* 0014h */
1026 u_int32_t outbound_msg_0; /* 0018h */
1027 u_int32_t outbound_msg_1; /* 001Ch */
1029 u_int32_t inbound_doorbell; /* 0020h */
1030 u_int32_t inbound_intr_status; /* 0024h */
1031 u_int32_t inbound_intr_mask; /* 0028h */
1033 u_int32_t outbound_doorbell; /* 002Ch */
1034 u_int32_t outbound_intr_status; /* 0030h */
1035 u_int32_t outbound_intr_mask; /* 0034h */
1037 u_int32_t reserved_1[2]; /* 0038h */
1039 u_int32_t inbound_queue_port; /* 0040h */
1040 u_int32_t outbound_queue_port; /* 0044h */
1042 u_int32_t reserved_2[9]; /* 0048h */
1043 u_int32_t reply_post_host_index;/* 006Ch */
1044 u_int32_t reserved_2_2[12]; /* 0070h */
1046 u_int32_t outbound_doorbell_clear; /* 00A0h */
1048 u_int32_t reserved_3[3]; /* 00A4h */
1050 u_int32_t outbound_scratch_pad; /* 00B0h */
1051 u_int32_t outbound_scratch_pad_2; /* 00B4h */
1053 u_int32_t reserved_4[2]; /* 00B8h */
1055 u_int32_t inbound_low_queue_port; /* 00C0h */
1057 u_int32_t inbound_high_queue_port; /* 00C4h */
1059 u_int32_t reserved_5; /* 00C8h */
1060 u_int32_t res_6[11]; /* CCh */
1061 u_int32_t host_diag;
1062 u_int32_t seq_offset;
1063 u_int32_t index_registers[807]; /* 00CCh */
1068 /*******************************************************************
1069 * Firmware Interface Defines
1070 *******************************************************************
1071 * MFI stands for MegaRAID SAS FW Interface. This is just a moniker
1072 * for protocol between the software and firmware. Commands are
1073 * issued using "message frames".
1074 ******************************************************************/
1076 * FW posts its state in upper 4 bits of outbound_msg_0 register
1078 #define MFI_STATE_MASK 0xF0000000
1079 #define MFI_STATE_UNDEFINED 0x00000000
1080 #define MFI_STATE_BB_INIT 0x10000000
1081 #define MFI_STATE_FW_INIT 0x40000000
1082 #define MFI_STATE_WAIT_HANDSHAKE 0x60000000
1083 #define MFI_STATE_FW_INIT_2 0x70000000
1084 #define MFI_STATE_DEVICE_SCAN 0x80000000
1085 #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000
1086 #define MFI_STATE_FLUSH_CACHE 0xA0000000
1087 #define MFI_STATE_READY 0xB0000000
1088 #define MFI_STATE_OPERATIONAL 0xC0000000
1089 #define MFI_STATE_FAULT 0xF0000000
1090 #define MFI_RESET_REQUIRED 0x00000001
1091 #define MFI_RESET_ADAPTER 0x00000002
1092 #define MEGAMFI_FRAME_SIZE 64
1093 #define MRSAS_MFI_FRAME_SIZE 1024
1094 #define MRSAS_MFI_SENSE_SIZE 128
1097 * During FW init, clear pending cmds & reset state using inbound_msg_0
1099 * ABORT : Abort all pending cmds READY : Move from OPERATIONAL to
1100 * READY state; discard queue info MFIMODE : Discard (possible) low MFA
1101 * posted in 64-bit mode (??) CLR_HANDSHAKE: FW is waiting for HANDSHAKE from
1102 * BIOS or Driver HOTPLUG : Resume from Hotplug MFI_STOP_ADP : Send
1103 * signal to FW to stop processing
1106 #define WRITE_SEQUENCE_OFFSET (0x0000000FC)
1107 #define HOST_DIAGNOSTIC_OFFSET (0x000000F8)
1108 #define DIAG_WRITE_ENABLE (0x00000080)
1109 #define DIAG_RESET_ADAPTER (0x00000004)
1111 #define MFI_ADP_RESET 0x00000040
1112 #define MFI_INIT_ABORT 0x00000001
1113 #define MFI_INIT_READY 0x00000002
1114 #define MFI_INIT_MFIMODE 0x00000004
1115 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008
1116 #define MFI_INIT_HOTPLUG 0x00000010
1117 #define MFI_STOP_ADP 0x00000020
1118 #define MFI_RESET_FLAGS MFI_INIT_READY| \
1125 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000
1126 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001
1127 #define MFI_FRAME_SGL32 0x0000
1128 #define MFI_FRAME_SGL64 0x0002
1129 #define MFI_FRAME_SENSE32 0x0000
1130 #define MFI_FRAME_SENSE64 0x0004
1131 #define MFI_FRAME_DIR_NONE 0x0000
1132 #define MFI_FRAME_DIR_WRITE 0x0008
1133 #define MFI_FRAME_DIR_READ 0x0010
1134 #define MFI_FRAME_DIR_BOTH 0x0018
1135 #define MFI_FRAME_IEEE 0x0020
1138 * Definition for cmd_status
1140 #define MFI_CMD_STATUS_POLL_MODE 0xFF
1143 * MFI command opcodes
1145 #define MFI_CMD_INIT 0x00
1146 #define MFI_CMD_LD_READ 0x01
1147 #define MFI_CMD_LD_WRITE 0x02
1148 #define MFI_CMD_LD_SCSI_IO 0x03
1149 #define MFI_CMD_PD_SCSI_IO 0x04
1150 #define MFI_CMD_DCMD 0x05
1151 #define MFI_CMD_ABORT 0x06
1152 #define MFI_CMD_SMP 0x07
1153 #define MFI_CMD_STP 0x08
1154 #define MFI_CMD_INVALID 0xff
1156 #define MR_DCMD_CTRL_GET_INFO 0x01010000
1157 #define MR_DCMD_LD_GET_LIST 0x03010000
1158 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000
1159 #define MR_FLUSH_CTRL_CACHE 0x01
1160 #define MR_FLUSH_DISK_CACHE 0x02
1162 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000
1163 #define MR_DCMD_HIBERNATE_SHUTDOWN 0x01060000
1164 #define MR_ENABLE_DRIVE_SPINDOWN 0x01
1166 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100
1167 #define MR_DCMD_CTRL_EVENT_GET 0x01040300
1168 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500
1169 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000
1171 #define MR_DCMD_CLUSTER 0x08000000
1172 #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100
1173 #define MR_DCMD_CLUSTER_RESET_LD 0x08010200
1174 #define MR_DCMD_PD_LIST_QUERY 0x02010100
1176 #define MR_DCMD_CTRL_MISC_CPX 0x0100e200
1177 #define MR_DCMD_CTRL_MISC_CPX_INIT_DATA_GET 0x0100e201
1178 #define MR_DCMD_CTRL_MISC_CPX_QUEUE_DATA 0x0100e202
1179 #define MR_DCMD_CTRL_MISC_CPX_UNREGISTER 0x0100e203
1180 #define MAX_MR_ROW_SIZE 32
1181 #define MR_CPX_DIR_WRITE 1
1182 #define MR_CPX_DIR_READ 0
1183 #define MR_CPX_VERSION 1
1185 #define MR_DCMD_CTRL_IO_METRICS_GET 0x01170200
1187 #define MR_EVT_CFG_CLEARED 0x0004
1189 #define MR_EVT_LD_STATE_CHANGE 0x0051
1190 #define MR_EVT_PD_INSERTED 0x005b
1191 #define MR_EVT_PD_REMOVED 0x0070
1192 #define MR_EVT_LD_CREATED 0x008a
1193 #define MR_EVT_LD_DELETED 0x008b
1194 #define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db
1195 #define MR_EVT_LD_OFFLINE 0x00fc
1196 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152
1197 #define MR_EVT_CTRL_PERF_COLLECTION 0x017e
1200 * MFI command completion codes
1204 MFI_STAT_INVALID_CMD = 0x01,
1205 MFI_STAT_INVALID_DCMD = 0x02,
1206 MFI_STAT_INVALID_PARAMETER = 0x03,
1207 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04,
1208 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05,
1209 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06,
1210 MFI_STAT_APP_IN_USE = 0x07,
1211 MFI_STAT_APP_NOT_INITIALIZED = 0x08,
1212 MFI_STAT_ARRAY_INDEX_INVALID = 0x09,
1213 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a,
1214 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b,
1215 MFI_STAT_DEVICE_NOT_FOUND = 0x0c,
1216 MFI_STAT_DRIVE_TOO_SMALL = 0x0d,
1217 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e,
1218 MFI_STAT_FLASH_BUSY = 0x0f,
1219 MFI_STAT_FLASH_ERROR = 0x10,
1220 MFI_STAT_FLASH_IMAGE_BAD = 0x11,
1221 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12,
1222 MFI_STAT_FLASH_NOT_OPEN = 0x13,
1223 MFI_STAT_FLASH_NOT_STARTED = 0x14,
1224 MFI_STAT_FLUSH_FAILED = 0x15,
1225 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16,
1226 MFI_STAT_LD_CC_IN_PROGRESS = 0x17,
1227 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18,
1228 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19,
1229 MFI_STAT_LD_MAX_CONFIGURED = 0x1a,
1230 MFI_STAT_LD_NOT_OPTIMAL = 0x1b,
1231 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c,
1232 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d,
1233 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e,
1234 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f,
1235 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
1236 MFI_STAT_MFC_HW_ERROR = 0x21,
1237 MFI_STAT_NO_HW_PRESENT = 0x22,
1238 MFI_STAT_NOT_FOUND = 0x23,
1239 MFI_STAT_NOT_IN_ENCL = 0x24,
1240 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25,
1241 MFI_STAT_PD_TYPE_WRONG = 0x26,
1242 MFI_STAT_PR_DISABLED = 0x27,
1243 MFI_STAT_ROW_INDEX_INVALID = 0x28,
1244 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29,
1245 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a,
1246 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b,
1247 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c,
1248 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d,
1249 MFI_STAT_SCSI_IO_FAILED = 0x2e,
1250 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f,
1251 MFI_STAT_SHUTDOWN_FAILED = 0x30,
1252 MFI_STAT_TIME_NOT_SET = 0x31,
1253 MFI_STAT_WRONG_STATE = 0x32,
1254 MFI_STAT_LD_OFFLINE = 0x33,
1255 MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34,
1256 MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35,
1257 MFI_STAT_RESERVATION_IN_PROGRESS = 0x36,
1258 MFI_STAT_I2C_ERRORS_DETECTED = 0x37,
1259 MFI_STAT_PCI_ERRORS_DETECTED = 0x38,
1260 MFI_STAT_CONFIG_SEQ_MISMATCH = 0x67,
1262 MFI_STAT_INVALID_STATUS = 0xFF
1266 * Number of mailbox bytes in DCMD message frame
1268 #define MFI_MBOX_SIZE 12
1272 MR_EVT_CLASS_DEBUG = -2,
1273 MR_EVT_CLASS_PROGRESS = -1,
1274 MR_EVT_CLASS_INFO = 0,
1275 MR_EVT_CLASS_WARNING = 1,
1276 MR_EVT_CLASS_CRITICAL = 2,
1277 MR_EVT_CLASS_FATAL = 3,
1278 MR_EVT_CLASS_DEAD = 4,
1282 enum MR_EVT_LOCALE {
1284 MR_EVT_LOCALE_LD = 0x0001,
1285 MR_EVT_LOCALE_PD = 0x0002,
1286 MR_EVT_LOCALE_ENCL = 0x0004,
1287 MR_EVT_LOCALE_BBU = 0x0008,
1288 MR_EVT_LOCALE_SAS = 0x0010,
1289 MR_EVT_LOCALE_CTRL = 0x0020,
1290 MR_EVT_LOCALE_CONFIG = 0x0040,
1291 MR_EVT_LOCALE_CLUSTER = 0x0080,
1292 MR_EVT_LOCALE_ALL = 0xffff,
1299 MR_EVT_ARGS_CDB_SENSE,
1301 MR_EVT_ARGS_LD_COUNT,
1303 MR_EVT_ARGS_LD_OWNER,
1304 MR_EVT_ARGS_LD_LBA_PD_LBA,
1305 MR_EVT_ARGS_LD_PROG,
1306 MR_EVT_ARGS_LD_STATE,
1307 MR_EVT_ARGS_LD_STRIP,
1311 MR_EVT_ARGS_PD_LBA_LD,
1312 MR_EVT_ARGS_PD_PROG,
1313 MR_EVT_ARGS_PD_STATE,
1319 MR_EVT_ARGS_LD_PROP,
1320 MR_EVT_ARGS_PD_SPARE,
1321 MR_EVT_ARGS_PD_INDEX,
1322 MR_EVT_ARGS_DIAG_PASS,
1323 MR_EVT_ARGS_DIAG_FAIL,
1324 MR_EVT_ARGS_PD_LBA_LBA,
1325 MR_EVT_ARGS_PORT_PHY,
1326 MR_EVT_ARGS_PD_MISSING,
1327 MR_EVT_ARGS_PD_ADDRESS,
1329 MR_EVT_ARGS_CONNECTOR,
1332 MR_EVT_ARGS_PD_PATHINFO,
1333 MR_EVT_ARGS_PD_POWER_STATE,
1334 MR_EVT_ARGS_GENERIC,
1338 * Thunderbolt (and later) Defines
1340 #define MEGASAS_CHAIN_FRAME_SZ_MIN 1024
1341 #define MFI_FUSION_ENABLE_INTERRUPT_MASK (0x00000009)
1342 #define MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE 256
1343 #define MRSAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0
1344 #define MRSAS_MPI2_FUNCTION_LD_IO_REQUEST 0xF1
1345 #define MRSAS_LOAD_BALANCE_FLAG 0x1
1346 #define MRSAS_DCMD_MBOX_PEND_FLAG 0x1
1347 #define HOST_DIAG_WRITE_ENABLE 0x80
1348 #define HOST_DIAG_RESET_ADAPTER 0x4
1349 #define MRSAS_TBOLT_MAX_RESET_TRIES 3
1350 #define MRSAS_MAX_MFI_CMDS 16
1351 #define MRSAS_MAX_IOCTL_CMDS 3
1356 #define MPI2_TYPE_CUDA 0x2
1357 #define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH 0x4000
1358 #define MR_RL_FLAGS_GRANT_DESTINATION_CPU0 0x00
1359 #define MR_RL_FLAGS_GRANT_DESTINATION_CPU1 0x10
1360 #define MR_RL_FLAGS_GRANT_DESTINATION_CUDA 0x80
1361 #define MR_RL_FLAGS_SEQ_NUM_ENABLE 0x8
1366 #define MR_PROT_INFO_TYPE_CONTROLLER 0x8
1367 #define MRSAS_SCSI_VARIABLE_LENGTH_CMD 0x7f
1368 #define MRSAS_SCSI_SERVICE_ACTION_READ32 0x9
1369 #define MRSAS_SCSI_SERVICE_ACTION_WRITE32 0xB
1370 #define MRSAS_SCSI_ADDL_CDB_LEN 0x18
1371 #define MRSAS_RD_WR_PROTECT_CHECK_ALL 0x20
1372 #define MRSAS_RD_WR_PROTECT_CHECK_NONE 0x60
1373 #define MRSAS_SCSIBLOCKSIZE 512
1376 * Raid context flags
1378 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_SHIFT 0x4
1379 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_MASK 0x30
1380 typedef enum MR_RAID_FLAGS_IO_SUB_TYPE {
1381 MR_RAID_FLAGS_IO_SUB_TYPE_NONE = 0,
1382 MR_RAID_FLAGS_IO_SUB_TYPE_SYSTEM_PD = 1,
1383 } MR_RAID_FLAGS_IO_SUB_TYPE;
1386 * Request descriptor types
1388 #define MRSAS_REQ_DESCRIPT_FLAGS_LD_IO 0x7
1389 #define MRSAS_REQ_DESCRIPT_FLAGS_MFA 0x1
1390 #define MRSAS_REQ_DESCRIPT_FLAGS_NO_LOCK 0x2
1391 #define MRSAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT 1
1392 #define MRSAS_FP_CMD_LEN 16
1393 #define MRSAS_FUSION_IN_RESET 0
1395 #define RAID_CTX_SPANARM_ARM_SHIFT (0)
1396 #define RAID_CTX_SPANARM_ARM_MASK (0x1f)
1397 #define RAID_CTX_SPANARM_SPAN_SHIFT (5)
1398 #define RAID_CTX_SPANARM_SPAN_MASK (0xE0)
1401 * Define region lock types
1403 typedef enum _REGION_TYPE {
1404 REGION_TYPE_UNUSED = 0,
1405 REGION_TYPE_SHARED_READ = 1,
1406 REGION_TYPE_SHARED_WRITE = 2,
1407 REGION_TYPE_EXCLUSIVE = 3,
1412 * SCSI-CAM Related Defines
1414 #define MRSAS_SCSI_MAX_LUNS 0
1415 #define MRSAS_SCSI_INITIATOR_ID 255
1416 #define MRSAS_SCSI_MAX_CMDS 8
1417 #define MRSAS_SCSI_MAX_CDB_LEN 16
1418 #define MRSAS_SCSI_SENSE_BUFFERSIZE 96
1419 #define MRSAS_INTERNAL_CMDS 32
1421 #define MEGASAS_MAX_CHAIN_SIZE_UNITS_MASK 0x400000
1422 #define MEGASAS_MAX_CHAIN_SIZE_MASK 0x3E0
1423 #define MEGASAS_256K_IO 128
1424 #define MEGASAS_1MB_IO (MEGASAS_256K_IO * 4)
1427 #define MRSAS_REQ_TYPE_INTERNAL_CMD 0x0
1428 #define MRSAS_REQ_TYPE_AEN_FETCH 0x1
1429 #define MRSAS_REQ_TYPE_PASSTHRU 0x2
1430 #define MRSAS_REQ_TYPE_GETSET_PARAM 0x3
1431 #define MRSAS_REQ_TYPE_SCSI_IO 0x4
1433 /* Request states */
1434 #define MRSAS_REQ_STATE_FREE 0
1435 #define MRSAS_REQ_STATE_BUSY 1
1436 #define MRSAS_REQ_STATE_TRAN 2
1437 #define MRSAS_REQ_STATE_COMPLETE 3
1439 typedef enum _MR_SCSI_CMD_TYPE {
1440 READ_WRITE_LDIO = 0,
1441 NON_READ_WRITE_LDIO = 1,
1442 READ_WRITE_SYSPDIO = 2,
1443 NON_READ_WRITE_SYSPDIO = 3,
1446 enum mrsas_req_flags {
1447 MRSAS_DIR_UNKNOWN = 0x1,
1449 MRSAS_DIR_OUT = 0x4,
1450 MRSAS_DIR_NONE = 0x8,
1454 * Adapter Reset States
1457 MRSAS_HBA_OPERATIONAL = 0,
1458 MRSAS_ADPRESET_SM_INFAULT = 1,
1459 MRSAS_ADPRESET_SM_FW_RESET_SUCCESS = 2,
1460 MRSAS_ADPRESET_SM_OPERATIONAL = 3,
1461 MRSAS_HW_CRITICAL_ERROR = 4,
1462 MRSAS_ADPRESET_INPROG_SIGN = 0xDEADDEAD,
1466 * MPT Command Structure
1468 struct mrsas_mpt_cmd {
1469 MRSAS_RAID_SCSI_IO_REQUEST *io_request;
1470 bus_addr_t io_request_phys_addr;
1471 MPI2_SGE_IO_UNION *chain_frame;
1472 bus_addr_t chain_frame_phys_addr;
1473 u_int32_t sge_count;
1475 bus_addr_t sense_phys_addr;
1476 u_int8_t retry_for_fw_reset;
1477 MRSAS_REQUEST_DESCRIPTOR_UNION *request_desc;
1478 u_int32_t sync_cmd_idx;
1482 u_int8_t load_balance;
1484 u_int32_t error_code;
1485 bus_dmamap_t data_dmamap;
1488 struct callout cm_callout;
1489 struct mrsas_softc *sc;
1490 boolean_t tmCapable;
1491 TAILQ_ENTRY(mrsas_mpt_cmd) next;
1495 * MFI Command Structure
1497 struct mrsas_mfi_cmd {
1498 union mrsas_frame *frame;
1499 bus_dmamap_t frame_dmamap;
1501 bus_addr_t frame_phys_addr;
1503 bus_dmamap_t sense_dmamap;
1505 bus_addr_t sense_phys_addr;
1508 u_int8_t cmd_status;
1510 u_int8_t retry_for_fw_reset;
1511 struct mrsas_softc *sc;
1518 u_int32_t frame_count;
1520 TAILQ_ENTRY(mrsas_mfi_cmd) next;
1525 * define constants for device list query options
1527 enum MR_PD_QUERY_TYPE {
1528 MR_PD_QUERY_TYPE_ALL = 0,
1529 MR_PD_QUERY_TYPE_STATE = 1,
1530 MR_PD_QUERY_TYPE_POWER_STATE = 2,
1531 MR_PD_QUERY_TYPE_MEDIA_TYPE = 3,
1532 MR_PD_QUERY_TYPE_SPEED = 4,
1533 MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5,
1536 #define MR_EVT_CFG_CLEARED 0x0004
1537 #define MR_EVT_LD_STATE_CHANGE 0x0051
1538 #define MR_EVT_PD_INSERTED 0x005b
1539 #define MR_EVT_PD_REMOVED 0x0070
1540 #define MR_EVT_LD_CREATED 0x008a
1541 #define MR_EVT_LD_DELETED 0x008b
1542 #define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db
1543 #define MR_EVT_LD_OFFLINE 0x00fc
1544 #define MR_EVT_CTRL_PROP_CHANGED 0x012f
1545 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152
1548 MR_PD_STATE_UNCONFIGURED_GOOD = 0x00,
1549 MR_PD_STATE_UNCONFIGURED_BAD = 0x01,
1550 MR_PD_STATE_HOT_SPARE = 0x02,
1551 MR_PD_STATE_OFFLINE = 0x10,
1552 MR_PD_STATE_FAILED = 0x11,
1553 MR_PD_STATE_REBUILD = 0x14,
1554 MR_PD_STATE_ONLINE = 0x18,
1555 MR_PD_STATE_COPYBACK = 0x20,
1556 MR_PD_STATE_SYSTEM = 0x40,
1560 * defines the physical drive address structure
1563 struct MR_PD_ADDRESS {
1565 u_int16_t enclDeviceId;
1570 u_int8_t slotNumber;
1573 u_int8_t enclPosition;
1574 u_int8_t enclConnectorIndex;
1577 u_int8_t scsiDevType;
1579 u_int8_t connectedPortBitmap;
1580 u_int8_t connectedPortNumbers;
1582 u_int64_t sasAddr[2];
1588 * defines the physical drive list structure
1594 struct MR_PD_ADDRESS addr[1];
1600 struct mrsas_pd_list {
1603 u_int8_t driveState;
1609 * defines the logical drive reference structure
1611 typedef union _MR_LD_REF {
1622 * defines the logical drive list structure
1631 u_int8_t reserved[3];
1633 } ldList[MAX_LOGICAL_DRIVES_EXT];
1639 * SAS controller properties
1642 struct mrsas_ctrl_prop {
1644 u_int16_t pred_fail_poll_interval;
1645 u_int16_t intr_throttle_count;
1646 u_int16_t intr_throttle_timeouts;
1647 u_int8_t rebuild_rate;
1648 u_int8_t patrol_read_rate;
1651 u_int8_t recon_rate;
1652 u_int8_t cache_flush_interval;
1653 u_int8_t spinup_drv_count;
1654 u_int8_t spinup_delay;
1655 u_int8_t cluster_enable;
1656 u_int8_t coercion_mode;
1657 u_int8_t alarm_enable;
1658 u_int8_t disable_auto_rebuild;
1659 u_int8_t disable_battery_warn;
1660 u_int8_t ecc_bucket_size;
1661 u_int16_t ecc_bucket_leak_rate;
1662 u_int8_t restore_hotspare_on_insertion;
1663 u_int8_t expose_encl_devices;
1664 u_int8_t maintainPdFailHistory;
1665 u_int8_t disallowHostRequestReordering;
1666 u_int8_t abortCCOnError;
1667 u_int8_t loadBalanceMode;
1668 u_int8_t disableAutoDetectBackplane;
1669 u_int8_t snapVDSpace;
1671 * Add properties that can be controlled by a bit in the following
1675 u_int32_t copyBackDisabled:1;
1676 u_int32_t SMARTerEnabled:1;
1677 u_int32_t prCorrectUnconfiguredAreas:1;
1678 u_int32_t useFdeOnly:1;
1679 u_int32_t disableNCQ:1;
1680 u_int32_t SSDSMARTerEnabled:1;
1681 u_int32_t SSDPatrolReadEnabled:1;
1682 u_int32_t enableSpinDownUnconfigured:1;
1683 u_int32_t autoEnhancedImport:1;
1684 u_int32_t enableSecretKeyControl:1;
1685 u_int32_t disableOnlineCtrlReset:1;
1686 u_int32_t allowBootWithPinnedCache:1;
1687 u_int32_t disableSpinDownHS:1;
1688 u_int32_t enableJBOD:1;
1689 u_int32_t disableCacheBypass:1;
1690 u_int32_t useDiskActivityForLocate:1;
1691 u_int32_t enablePI:1;
1692 u_int32_t preventPIImport:1;
1693 u_int32_t useGlobalSparesForEmergency:1;
1694 u_int32_t useUnconfGoodForEmergency:1;
1695 u_int32_t useEmergencySparesforSMARTer:1;
1696 u_int32_t forceSGPIOForQuadOnly:1;
1697 u_int32_t enableConfigAutoBalance:1;
1698 u_int32_t enableVirtualCache:1;
1699 u_int32_t enableAutoLockRecovery:1;
1700 u_int32_t disableImmediateIO:1;
1701 u_int32_t disableT10RebuildAssist:1;
1702 u_int32_t ignore64ldRestriction:1;
1703 u_int32_t enableSwZone:1;
1704 u_int32_t limitMaxRateSATA3G:1;
1705 u_int32_t reserved:2;
1707 u_int8_t autoSnapVDSpace;
1709 u_int16_t spinDownTime;
1710 u_int8_t reserved[24];
1718 * SAS controller information
1720 struct mrsas_ctrl_info {
1722 * PCI device information
1725 u_int16_t vendor_id;
1726 u_int16_t device_id;
1727 u_int16_t sub_vendor_id;
1728 u_int16_t sub_device_id;
1729 u_int8_t reserved[24];
1732 * Host interface information
1739 u_int8_t reserved_0:4;
1740 u_int8_t reserved_1[6];
1741 u_int8_t port_count;
1742 u_int64_t port_addr[8];
1743 } __packed host_interface;
1745 * Device (backend) interface information
1750 u_int8_t SATA_1_5G:1;
1752 u_int8_t reserved_0:4;
1753 u_int8_t reserved_1[6];
1754 u_int8_t port_count;
1755 u_int64_t port_addr[8];
1756 } __packed device_interface;
1758 u_int32_t image_check_word;
1759 u_int32_t image_component_count;
1764 char build_date[16];
1765 char built_time[16];
1766 } __packed image_component[8];
1768 u_int32_t pending_image_component_count;
1773 char build_date[16];
1774 char build_time[16];
1775 } __packed pending_image_component[8];
1779 u_int8_t max_arrays;
1781 char product_name[80];
1785 * Other physical/controller/operation information. Indicates the
1786 * presence of the hardware
1793 u_int32_t reserved:28;
1794 } __packed hw_present;
1796 u_int32_t current_fw_time;
1799 * Maximum data transfer sizes
1801 u_int16_t max_concurrent_cmds;
1802 u_int16_t max_sge_count;
1803 u_int32_t max_request_size;
1806 * Logical and physical device counts
1808 u_int16_t ld_present_count;
1809 u_int16_t ld_degraded_count;
1810 u_int16_t ld_offline_count;
1812 u_int16_t pd_present_count;
1813 u_int16_t pd_disk_present_count;
1814 u_int16_t pd_disk_pred_failure_count;
1815 u_int16_t pd_disk_failed_count;
1818 * Memory size information
1820 u_int16_t nvram_size;
1821 u_int16_t memory_size;
1822 u_int16_t flash_size;
1827 u_int16_t mem_correctable_error_count;
1828 u_int16_t mem_uncorrectable_error_count;
1831 * Cluster information
1833 u_int8_t cluster_permitted;
1834 u_int8_t cluster_active;
1837 * Additional max data transfer sizes
1839 u_int16_t max_strips_per_io;
1842 * Controller capabilities structures
1845 u_int32_t raid_level_0:1;
1846 u_int32_t raid_level_1:1;
1847 u_int32_t raid_level_5:1;
1848 u_int32_t raid_level_1E:1;
1849 u_int32_t raid_level_6:1;
1850 u_int32_t reserved:27;
1851 } __packed raid_levels;
1854 u_int32_t rbld_rate:1;
1855 u_int32_t cc_rate:1;
1856 u_int32_t bgi_rate:1;
1857 u_int32_t recon_rate:1;
1858 u_int32_t patrol_rate:1;
1859 u_int32_t alarm_control:1;
1860 u_int32_t cluster_supported:1;
1862 u_int32_t spanning_allowed:1;
1863 u_int32_t dedicated_hotspares:1;
1864 u_int32_t revertible_hotspares:1;
1865 u_int32_t foreign_config_import:1;
1866 u_int32_t self_diagnostic:1;
1867 u_int32_t mixed_redundancy_arr:1;
1868 u_int32_t global_hot_spares:1;
1869 u_int32_t reserved:17;
1870 } __packed adapter_operations;
1873 u_int32_t read_policy:1;
1874 u_int32_t write_policy:1;
1875 u_int32_t io_policy:1;
1876 u_int32_t access_policy:1;
1877 u_int32_t disk_cache_policy:1;
1878 u_int32_t reserved:27;
1879 } __packed ld_operations;
1884 u_int8_t reserved[2];
1885 } __packed stripe_sz_ops;
1888 u_int32_t force_online:1;
1889 u_int32_t force_offline:1;
1890 u_int32_t force_rebuild:1;
1891 u_int32_t reserved:29;
1892 } __packed pd_operations;
1895 u_int32_t ctrl_supports_sas:1;
1896 u_int32_t ctrl_supports_sata:1;
1897 u_int32_t allow_mix_in_encl:1;
1898 u_int32_t allow_mix_in_ld:1;
1899 u_int32_t allow_sata_in_cluster:1;
1900 u_int32_t reserved:27;
1901 } __packed pd_mix_support;
1904 * Define ECC single-bit-error bucket information
1906 u_int8_t ecc_bucket_count;
1907 u_int8_t reserved_2[11];
1910 * Include the controller properties (changeable items)
1912 struct mrsas_ctrl_prop properties;
1915 * Define FW pkg version (set in envt v'bles on OEM basis)
1917 char package_version[0x60];
1919 u_int64_t deviceInterfacePortAddr2[8];
1920 u_int8_t reserved3[128];
1923 u_int16_t minPdRaidLevel_0:4;
1924 u_int16_t maxPdRaidLevel_0:12;
1926 u_int16_t minPdRaidLevel_1:4;
1927 u_int16_t maxPdRaidLevel_1:12;
1929 u_int16_t minPdRaidLevel_5:4;
1930 u_int16_t maxPdRaidLevel_5:12;
1932 u_int16_t minPdRaidLevel_1E:4;
1933 u_int16_t maxPdRaidLevel_1E:12;
1935 u_int16_t minPdRaidLevel_6:4;
1936 u_int16_t maxPdRaidLevel_6:12;
1938 u_int16_t minPdRaidLevel_10:4;
1939 u_int16_t maxPdRaidLevel_10:12;
1941 u_int16_t minPdRaidLevel_50:4;
1942 u_int16_t maxPdRaidLevel_50:12;
1944 u_int16_t minPdRaidLevel_60:4;
1945 u_int16_t maxPdRaidLevel_60:12;
1947 u_int16_t minPdRaidLevel_1E_RLQ0:4;
1948 u_int16_t maxPdRaidLevel_1E_RLQ0:12;
1950 u_int16_t minPdRaidLevel_1E0_RLQ0:4;
1951 u_int16_t maxPdRaidLevel_1E0_RLQ0:12;
1953 u_int16_t reserved[6];
1956 u_int16_t maxPds; /* 0x780 */
1957 u_int16_t maxDedHSPs; /* 0x782 */
1958 u_int16_t maxGlobalHSPs; /* 0x784 */
1959 u_int16_t ddfSize; /* 0x786 */
1960 u_int8_t maxLdsPerArray; /* 0x788 */
1961 u_int8_t partitionsInDDF; /* 0x789 */
1962 u_int8_t lockKeyBinding; /* 0x78a */
1963 u_int8_t maxPITsPerLd; /* 0x78b */
1964 u_int8_t maxViewsPerLd; /* 0x78c */
1965 u_int8_t maxTargetId; /* 0x78d */
1966 u_int16_t maxBvlVdSize; /* 0x78e */
1968 u_int16_t maxConfigurableSSCSize; /* 0x790 */
1969 u_int16_t currentSSCsize; /* 0x792 */
1971 char expanderFwVersion[12]; /* 0x794 */
1973 u_int16_t PFKTrialTimeRemaining;/* 0x7A0 */
1975 u_int16_t cacheMemorySize; /* 0x7A2 */
1977 struct { /* 0x7A4 */
1978 u_int32_t supportPIcontroller:1;
1979 u_int32_t supportLdPIType1:1;
1980 u_int32_t supportLdPIType2:1;
1981 u_int32_t supportLdPIType3:1;
1982 u_int32_t supportLdBBMInfo:1;
1983 u_int32_t supportShieldState:1;
1984 u_int32_t blockSSDWriteCacheChange:1;
1985 u_int32_t supportSuspendResumeBGops:1;
1986 u_int32_t supportEmergencySpares:1;
1987 u_int32_t supportSetLinkSpeed:1;
1988 u_int32_t supportBootTimePFKChange:1;
1989 u_int32_t supportJBOD:1;
1990 u_int32_t disableOnlinePFKChange:1;
1991 u_int32_t supportPerfTuning:1;
1992 u_int32_t supportSSDPatrolRead:1;
1993 u_int32_t realTimeScheduler:1;
1995 u_int32_t supportResetNow:1;
1996 u_int32_t supportEmulatedDrives:1;
1997 u_int32_t headlessMode:1;
1998 u_int32_t dedicatedHotSparesLimited:1;
2001 u_int32_t supportUnevenSpans:1;
2002 u_int32_t reserved:11;
2003 } adapterOperations2;
2005 u_int8_t driverVersion[32]; /* 0x7A8 */
2006 u_int8_t maxDAPdCountSpinup60; /* 0x7C8 */
2007 u_int8_t temperatureROC; /* 0x7C9 */
2008 u_int8_t temperatureCtrl; /* 0x7CA */
2009 u_int8_t reserved4; /* 0x7CB */
2010 u_int16_t maxConfigurablePds; /* 0x7CC */
2013 u_int8_t reserved5[2]; /* 0x7CD reserved */
2016 u_int32_t peerIsPresent:1;
2017 u_int32_t peerIsIncompatible:1;
2019 u_int32_t hwIncompatible:1;
2020 u_int32_t fwVersionMismatch:1;
2021 u_int32_t ctrlPropIncompatible:1;
2022 u_int32_t premiumFeatureMismatch:1;
2023 u_int32_t reserved:26;
2026 char clusterId[16]; /* 0x7D4 */
2028 char reserved6[4]; /* 0x7E4 RESERVED FOR IOV */
2030 struct { /* 0x7E8 */
2031 u_int32_t supportPersonalityChange:2;
2032 u_int32_t supportThermalPollInterval:1;
2033 u_int32_t supportDisableImmediateIO:1;
2034 u_int32_t supportT10RebuildAssist:1;
2035 u_int32_t supportMaxExtLDs:1;
2036 u_int32_t supportCrashDump:1;
2037 u_int32_t supportSwZone:1;
2038 u_int32_t supportDebugQueue:1;
2039 u_int32_t supportNVCacheErase:1;
2040 u_int32_t supportForceTo512e:1;
2041 u_int32_t supportHOQRebuild:1;
2042 u_int32_t supportAllowedOpsforDrvRemoval:1;
2043 u_int32_t supportDrvActivityLEDSetting:1;
2044 u_int32_t supportNVDRAM:1;
2045 u_int32_t supportForceFlash:1;
2046 u_int32_t supportDisableSESMonitoring:1;
2047 u_int32_t supportCacheBypassModes:1;
2048 u_int32_t supportSecurityonJBOD:1;
2049 u_int32_t discardCacheDuringLDDelete:1;
2050 u_int32_t supportTTYLogCompression:1;
2051 u_int32_t supportCPLDUpdate:1;
2052 u_int32_t supportDiskCacheSettingForSysPDs:1;
2053 u_int32_t supportExtendedSSCSize:1;
2054 u_int32_t useSeqNumJbodFP:1;
2055 u_int32_t reserved:7;
2056 } adapterOperations3;
2058 u_int8_t pad[0x800 - 0x7EC]; /* 0x7EC */
2062 * When SCSI mid-layer calls driver's reset routine, driver waits for
2063 * MRSAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note
2064 * that the driver cannot _actually_ abort or reset pending commands. While
2065 * it is waiting for the commands to complete, it prints a diagnostic message
2066 * every MRSAS_RESET_NOTICE_INTERVAL seconds
2068 #define MRSAS_RESET_WAIT_TIME 180
2069 #define MRSAS_INTERNAL_CMD_WAIT_TIME 180
2070 #define MRSAS_IOC_INIT_WAIT_TIME 60
2071 #define MRSAS_RESET_NOTICE_INTERVAL 5
2072 #define MRSAS_IOCTL_CMD 0
2073 #define MRSAS_DEFAULT_CMD_TIMEOUT 90
2074 #define MRSAS_THROTTLE_QUEUE_DEPTH 16
2077 * MSI-x regsiters offset defines
2079 #define MPI2_SUP_REPLY_POST_HOST_INDEX_OFFSET (0x0000030C)
2080 #define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C)
2081 #define MR_MAX_REPLY_QUEUES_OFFSET (0x0000001F)
2082 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET (0x003FC000)
2083 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET_SHIFT 14
2084 #define MR_MAX_MSIX_REG_ARRAY 16
2087 * SYNC CACHE offset define
2089 #define MR_CAN_HANDLE_SYNC_CACHE_OFFSET 0X01000000
2092 * FW reports the maximum of number of commands that it can accept (maximum
2093 * commands that can be outstanding) at any time. The driver must report a
2094 * lower number to the mid layer because it can issue a few internal commands
2095 * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs
2098 #define MRSAS_INT_CMDS 32
2099 #define MRSAS_SKINNY_INT_CMDS 5
2100 #define MRSAS_MAX_MSIX_QUEUES 128
2103 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit SGLs
2104 * based on the size of bus_addr_t
2106 #define IS_DMA64 (sizeof(bus_addr_t) == 8)
2108 #define MFI_XSCALE_OMR0_CHANGE_INTERRUPT 0x00000001
2109 #define MFI_INTR_FLAG_REPLY_MESSAGE 0x00000001
2110 #define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE 0x00000002
2111 #define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT 0x00000004
2113 #define MFI_OB_INTR_STATUS_MASK 0x00000002
2114 #define MFI_POLL_TIMEOUT_SECS 60
2116 #define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000
2117 #define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001
2118 #define MFI_GEN2_ENABLE_INTERRUPT_MASK 0x00000001
2119 #define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000
2120 #define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001)
2121 #define MFI_1068_PCSR_OFFSET 0x84
2122 #define MFI_1068_FW_HANDSHAKE_OFFSET 0x64
2123 #define MFI_1068_FW_READY 0xDDDD0000
2125 typedef union _MFI_CAPABILITIES {
2127 u_int32_t support_fp_remote_lun:1;
2128 u_int32_t support_additional_msix:1;
2129 u_int32_t support_fastpath_wb:1;
2130 u_int32_t support_max_255lds:1;
2131 u_int32_t support_ndrive_r1_lb:1;
2132 u_int32_t support_core_affinity:1;
2133 u_int32_t security_protocol_cmds_fw:1;
2134 u_int32_t support_ext_queue_depth:1;
2135 u_int32_t support_ext_io_size:1;
2136 u_int32_t reserved:23;
2142 struct mrsas_sge32 {
2143 u_int32_t phys_addr;
2150 struct mrsas_sge64 {
2151 u_int64_t phys_addr;
2159 struct mrsas_sge32 sge32[1];
2160 struct mrsas_sge64 sge64[1];
2166 struct mrsas_header {
2167 u_int8_t cmd; /* 00e */
2168 u_int8_t sense_len; /* 01h */
2169 u_int8_t cmd_status; /* 02h */
2170 u_int8_t scsi_status; /* 03h */
2172 u_int8_t target_id; /* 04h */
2173 u_int8_t lun; /* 05h */
2174 u_int8_t cdb_len; /* 06h */
2175 u_int8_t sge_count; /* 07h */
2177 u_int32_t context; /* 08h */
2178 u_int32_t pad_0; /* 0Ch */
2180 u_int16_t flags; /* 10h */
2181 u_int16_t timeout; /* 12h */
2182 u_int32_t data_xferlen; /* 14h */
2188 struct mrsas_init_frame {
2189 u_int8_t cmd; /* 00h */
2190 u_int8_t reserved_0; /* 01h */
2191 u_int8_t cmd_status; /* 02h */
2193 u_int8_t reserved_1; /* 03h */
2194 MFI_CAPABILITIES driver_operations; /* 04h */
2195 u_int32_t context; /* 08h */
2196 u_int32_t pad_0; /* 0Ch */
2198 u_int16_t flags; /* 10h */
2199 u_int16_t reserved_3; /* 12h */
2200 u_int32_t data_xfer_len; /* 14h */
2202 u_int32_t queue_info_new_phys_addr_lo; /* 18h */
2203 u_int32_t queue_info_new_phys_addr_hi; /* 1Ch */
2204 u_int32_t queue_info_old_phys_addr_lo; /* 20h */
2205 u_int32_t queue_info_old_phys_addr_hi; /* 24h */
2206 u_int32_t driver_ver_lo; /* 28h */
2207 u_int32_t driver_ver_hi; /* 2Ch */
2208 u_int32_t reserved_4[4]; /* 30h */
2214 struct mrsas_io_frame {
2215 u_int8_t cmd; /* 00h */
2216 u_int8_t sense_len; /* 01h */
2217 u_int8_t cmd_status; /* 02h */
2218 u_int8_t scsi_status; /* 03h */
2220 u_int8_t target_id; /* 04h */
2221 u_int8_t access_byte; /* 05h */
2222 u_int8_t reserved_0; /* 06h */
2223 u_int8_t sge_count; /* 07h */
2225 u_int32_t context; /* 08h */
2226 u_int32_t pad_0; /* 0Ch */
2228 u_int16_t flags; /* 10h */
2229 u_int16_t timeout; /* 12h */
2230 u_int32_t lba_count; /* 14h */
2232 u_int32_t sense_buf_phys_addr_lo; /* 18h */
2233 u_int32_t sense_buf_phys_addr_hi; /* 1Ch */
2235 u_int32_t start_lba_lo; /* 20h */
2236 u_int32_t start_lba_hi; /* 24h */
2238 union mrsas_sgl sgl; /* 28h */
2244 struct mrsas_pthru_frame {
2245 u_int8_t cmd; /* 00h */
2246 u_int8_t sense_len; /* 01h */
2247 u_int8_t cmd_status; /* 02h */
2248 u_int8_t scsi_status; /* 03h */
2250 u_int8_t target_id; /* 04h */
2251 u_int8_t lun; /* 05h */
2252 u_int8_t cdb_len; /* 06h */
2253 u_int8_t sge_count; /* 07h */
2255 u_int32_t context; /* 08h */
2256 u_int32_t pad_0; /* 0Ch */
2258 u_int16_t flags; /* 10h */
2259 u_int16_t timeout; /* 12h */
2260 u_int32_t data_xfer_len; /* 14h */
2262 u_int32_t sense_buf_phys_addr_lo; /* 18h */
2263 u_int32_t sense_buf_phys_addr_hi; /* 1Ch */
2265 u_int8_t cdb[16]; /* 20h */
2266 union mrsas_sgl sgl; /* 30h */
2272 struct mrsas_dcmd_frame {
2273 u_int8_t cmd; /* 00h */
2274 u_int8_t reserved_0; /* 01h */
2275 u_int8_t cmd_status; /* 02h */
2276 u_int8_t reserved_1[4]; /* 03h */
2277 u_int8_t sge_count; /* 07h */
2279 u_int32_t context; /* 08h */
2280 u_int32_t pad_0; /* 0Ch */
2282 u_int16_t flags; /* 10h */
2283 u_int16_t timeout; /* 12h */
2285 u_int32_t data_xfer_len; /* 14h */
2286 u_int32_t opcode; /* 18h */
2294 union mrsas_sgl sgl; /* 28h */
2300 struct mrsas_abort_frame {
2301 u_int8_t cmd; /* 00h */
2302 u_int8_t reserved_0; /* 01h */
2303 u_int8_t cmd_status; /* 02h */
2305 u_int8_t reserved_1; /* 03h */
2306 MFI_CAPABILITIES driver_operations; /* 04h */
2307 u_int32_t context; /* 08h */
2308 u_int32_t pad_0; /* 0Ch */
2310 u_int16_t flags; /* 10h */
2311 u_int16_t reserved_3; /* 12h */
2312 u_int32_t reserved_4; /* 14h */
2314 u_int32_t abort_context; /* 18h */
2315 u_int32_t pad_1; /* 1Ch */
2317 u_int32_t abort_mfi_phys_addr_lo; /* 20h */
2318 u_int32_t abort_mfi_phys_addr_hi; /* 24h */
2320 u_int32_t reserved_5[6]; /* 28h */
2326 struct mrsas_smp_frame {
2327 u_int8_t cmd; /* 00h */
2328 u_int8_t reserved_1; /* 01h */
2329 u_int8_t cmd_status; /* 02h */
2330 u_int8_t connection_status; /* 03h */
2332 u_int8_t reserved_2[3]; /* 04h */
2333 u_int8_t sge_count; /* 07h */
2335 u_int32_t context; /* 08h */
2336 u_int32_t pad_0; /* 0Ch */
2338 u_int16_t flags; /* 10h */
2339 u_int16_t timeout; /* 12h */
2341 u_int32_t data_xfer_len; /* 14h */
2342 u_int64_t sas_addr; /* 18h */
2345 struct mrsas_sge32 sge32[2]; /* [0]: resp [1]: req */
2346 struct mrsas_sge64 sge64[2]; /* [0]: resp [1]: req */
2354 struct mrsas_stp_frame {
2355 u_int8_t cmd; /* 00h */
2356 u_int8_t reserved_1; /* 01h */
2357 u_int8_t cmd_status; /* 02h */
2358 u_int8_t reserved_2; /* 03h */
2360 u_int8_t target_id; /* 04h */
2361 u_int8_t reserved_3[2]; /* 05h */
2362 u_int8_t sge_count; /* 07h */
2364 u_int32_t context; /* 08h */
2365 u_int32_t pad_0; /* 0Ch */
2367 u_int16_t flags; /* 10h */
2368 u_int16_t timeout; /* 12h */
2370 u_int32_t data_xfer_len; /* 14h */
2372 u_int16_t fis[10]; /* 18h */
2373 u_int32_t stp_flags;
2376 struct mrsas_sge32 sge32[2]; /* [0]: resp [1]: data */
2377 struct mrsas_sge64 sge64[2]; /* [0]: resp [1]: data */
2384 struct mrsas_header hdr;
2385 struct mrsas_init_frame init;
2386 struct mrsas_io_frame io;
2387 struct mrsas_pthru_frame pthru;
2388 struct mrsas_dcmd_frame dcmd;
2389 struct mrsas_abort_frame abort;
2390 struct mrsas_smp_frame smp;
2391 struct mrsas_stp_frame stp;
2392 u_int8_t raw_bytes[64];
2396 union mrsas_evt_class_locale {
2412 struct mrsas_evt_log_info {
2413 u_int32_t newest_seq_num;
2414 u_int32_t oldest_seq_num;
2415 u_int32_t clear_seq_num;
2416 u_int32_t shutdown_seq_num;
2417 u_int32_t boot_seq_num;
2423 struct mrsas_progress {
2426 u_int16_t elapsed_seconds;
2430 struct mrsas_evtarg_ld {
2432 u_int16_t target_id;
2438 struct mrsas_evtarg_pd {
2439 u_int16_t device_id;
2440 u_int8_t encl_index;
2441 u_int8_t slot_number;
2445 struct mrsas_evt_detail {
2448 u_int32_t time_stamp;
2450 union mrsas_evt_class_locale cl;
2452 u_int8_t reserved1[15];
2456 struct mrsas_evtarg_pd pd;
2457 u_int8_t cdb_length;
2458 u_int8_t sense_length;
2459 u_int8_t reserved[2];
2462 } __packed cdbSense;
2464 struct mrsas_evtarg_ld ld;
2467 struct mrsas_evtarg_ld ld;
2469 } __packed ld_count;
2473 struct mrsas_evtarg_ld ld;
2477 struct mrsas_evtarg_ld ld;
2478 u_int32_t prevOwner;
2480 } __packed ld_owner;
2485 struct mrsas_evtarg_ld ld;
2486 struct mrsas_evtarg_pd pd;
2487 } __packed ld_lba_pd_lba;
2490 struct mrsas_evtarg_ld ld;
2491 struct mrsas_progress prog;
2495 struct mrsas_evtarg_ld ld;
2496 u_int32_t prev_state;
2497 u_int32_t new_state;
2498 } __packed ld_state;
2502 struct mrsas_evtarg_ld ld;
2503 } __packed ld_strip;
2505 struct mrsas_evtarg_pd pd;
2508 struct mrsas_evtarg_pd pd;
2514 struct mrsas_evtarg_pd pd;
2519 struct mrsas_evtarg_pd pd;
2520 struct mrsas_evtarg_ld ld;
2521 } __packed pd_lba_ld;
2524 struct mrsas_evtarg_pd pd;
2525 struct mrsas_progress prog;
2529 struct mrsas_evtarg_pd pd;
2530 u_int32_t prevState;
2532 } __packed pd_state;
2537 u_int16_t subVendorId;
2538 u_int16_t subDeviceId;
2546 u_int32_t elapsedSeconds;
2561 char description[128];
2565 struct mrsas_irq_context {
2566 struct mrsas_softc *sc;
2570 enum MEGASAS_OCR_REASON {
2572 MFI_DCMD_TIMEOUT_OCR = 1,
2575 /* Controller management info added to support Linux Emulator */
2576 #define MAX_MGMT_ADAPTERS 1024
2578 struct mrsas_mgmt_info {
2580 struct mrsas_softc *sc_ptr[MAX_MGMT_ADAPTERS];
2584 #define PCI_TYPE0_ADDRESSES 6
2585 #define PCI_TYPE1_ADDRESSES 2
2586 #define PCI_TYPE2_ADDRESSES 5
2588 typedef struct _MRSAS_DRV_PCI_COMMON_HEADER {
2596 u_int8_t revisionID;
2604 u_int8_t cacheLineSize;
2606 u_int8_t latencyTimer;
2608 u_int8_t headerType;
2611 //Built in self test
2614 struct _MRSAS_DRV_PCI_HEADER_TYPE_0 {
2615 u_int32_t baseAddresses[PCI_TYPE0_ADDRESSES];
2617 u_int16_t subVendorID;
2618 u_int16_t subSystemID;
2619 u_int32_t romBaseAddress;
2620 u_int8_t capabilitiesPtr;
2621 u_int8_t reserved1[3];
2622 u_int32_t reserved2;
2623 u_int8_t interruptLine;
2624 u_int8_t interruptPin;
2626 u_int8_t minimumGrant;
2628 u_int8_t maximumLatency;
2636 struct _MRSAS_DRV_PCI_HEADER_TYPE_1 {
2637 u_int32_t baseAddresses[PCI_TYPE1_ADDRESSES];
2638 u_int8_t primaryBus;
2639 u_int8_t secondaryBus;
2640 u_int8_t subordinateBus;
2641 u_int8_t secondaryLatency;
2644 u_int16_t secondaryStatus;
2645 u_int16_t memoryBase;
2646 u_int16_t memoryLimit;
2647 u_int16_t prefetchBase;
2648 u_int16_t prefetchLimit;
2649 u_int32_t prefetchBaseUpper32;
2650 u_int32_t prefetchLimitUpper32;
2651 u_int16_t ioBaseUpper16;
2652 u_int16_t ioLimitUpper16;
2653 u_int8_t capabilitiesPtr;
2654 u_int8_t reserved1[3];
2655 u_int32_t romBaseAddress;
2656 u_int8_t interruptLine;
2657 u_int8_t interruptPin;
2658 u_int16_t bridgeControl;
2662 * PCI to CARDBUS Bridge
2665 struct _MRSAS_DRV_PCI_HEADER_TYPE_2 {
2666 u_int32_t socketRegistersBaseAddress;
2667 u_int8_t capabilitiesPtr;
2669 u_int16_t secondaryStatus;
2670 u_int8_t primaryBus;
2671 u_int8_t secondaryBus;
2672 u_int8_t subordinateBus;
2673 u_int8_t secondaryLatency;
2677 } range [PCI_TYPE2_ADDRESSES - 1];
2678 u_int8_t interruptLine;
2679 u_int8_t interruptPin;
2680 u_int16_t bridgeControl;
2684 } MRSAS_DRV_PCI_COMMON_HEADER, *PMRSAS_DRV_PCI_COMMON_HEADER;
2686 #define MRSAS_DRV_PCI_COMMON_HEADER_SIZE sizeof(MRSAS_DRV_PCI_COMMON_HEADER) //64 bytes
2688 typedef struct _MRSAS_DRV_PCI_LINK_CAPABILITY {
2691 u_int32_t linkSpeed:4;
2692 u_int32_t linkWidth:6;
2693 u_int32_t aspmSupport:2;
2694 u_int32_t losExitLatency:3;
2695 u_int32_t l1ExitLatency:3;
2697 u_int32_t portNumber:8;
2702 } MRSAS_DRV_PCI_LINK_CAPABILITY, *PMRSAS_DRV_PCI_LINK_CAPABILITY;
2704 #define MRSAS_DRV_PCI_LINK_CAPABILITY_SIZE sizeof(MRSAS_DRV_PCI_LINK_CAPABILITY)
2706 typedef struct _MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY {
2709 u_int16_t linkSpeed:4;
2710 u_int16_t negotiatedLinkWidth:6;
2711 u_int16_t linkTrainingError:1;
2712 u_int16_t linkTraning:1;
2713 u_int16_t slotClockConfig:1;
2720 } MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY, *PMRSAS_DRV_PCI_LINK_STATUS_CAPABILITY;
2722 #define MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY_SIZE sizeof(MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY)
2725 typedef struct _MRSAS_DRV_PCI_CAPABILITIES {
2726 MRSAS_DRV_PCI_LINK_CAPABILITY linkCapability;
2727 MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY linkStatusCapability;
2728 } MRSAS_DRV_PCI_CAPABILITIES, *PMRSAS_DRV_PCI_CAPABILITIES;
2730 #define MRSAS_DRV_PCI_CAPABILITIES_SIZE sizeof(MRSAS_DRV_PCI_CAPABILITIES)
2732 /* PCI information */
2733 typedef struct _MRSAS_DRV_PCI_INFORMATION {
2734 u_int32_t busNumber;
2735 u_int8_t deviceNumber;
2736 u_int8_t functionNumber;
2737 u_int8_t interruptVector;
2739 MRSAS_DRV_PCI_COMMON_HEADER pciHeaderInfo;
2740 MRSAS_DRV_PCI_CAPABILITIES capability;
2742 u_int8_t reserved2[28];
2743 } MRSAS_DRV_PCI_INFORMATION, *PMRSAS_DRV_PCI_INFORMATION;
2745 /*******************************************************************
2747 ********************************************************************/
2748 struct mrsas_softc {
2750 struct cdev *mrsas_cdev;
2751 struct intr_config_hook mrsas_ich;
2752 struct cdev *mrsas_linux_emulator_cdev;
2754 struct resource *reg_res;
2756 bus_space_tag_t bus_tag;
2757 bus_space_handle_t bus_handle;
2758 bus_dma_tag_t mrsas_parent_tag;
2759 bus_dma_tag_t verbuf_tag;
2760 bus_dmamap_t verbuf_dmamap;
2762 bus_addr_t verbuf_phys_addr;
2763 bus_dma_tag_t sense_tag;
2764 bus_dmamap_t sense_dmamap;
2766 bus_addr_t sense_phys_addr;
2767 bus_dma_tag_t io_request_tag;
2768 bus_dmamap_t io_request_dmamap;
2769 void *io_request_mem;
2770 bus_addr_t io_request_phys_addr;
2771 bus_dma_tag_t chain_frame_tag;
2772 bus_dmamap_t chain_frame_dmamap;
2773 void *chain_frame_mem;
2774 bus_addr_t chain_frame_phys_addr;
2775 bus_dma_tag_t reply_desc_tag;
2776 bus_dmamap_t reply_desc_dmamap;
2777 void *reply_desc_mem;
2778 bus_addr_t reply_desc_phys_addr;
2779 bus_dma_tag_t ioc_init_tag;
2780 bus_dmamap_t ioc_init_dmamap;
2782 bus_addr_t ioc_init_phys_mem;
2783 bus_dma_tag_t data_tag;
2784 struct cam_sim *sim_0;
2785 struct cam_sim *sim_1;
2786 struct cam_path *path_0;
2787 struct cam_path *path_1;
2788 struct mtx sim_lock;
2789 struct mtx pci_lock;
2791 struct mtx ioctl_lock;
2792 struct mtx mpt_cmd_pool_lock;
2793 struct mtx mfi_cmd_pool_lock;
2794 struct mtx raidmap_lock;
2795 struct mtx aen_lock;
2796 struct selinfo mrsas_select;
2797 uint32_t mrsas_aen_triggered;
2798 uint32_t mrsas_poll_waiting;
2800 struct sema ioctl_count_sema;
2801 uint32_t max_fw_cmds;
2802 uint32_t max_num_sge;
2803 struct resource *mrsas_irq[MAX_MSIX_COUNT];
2804 void *intr_handle[MAX_MSIX_COUNT];
2805 int irq_id[MAX_MSIX_COUNT];
2806 struct mrsas_irq_context irq_context[MAX_MSIX_COUNT];
2809 uint32_t msix_reg_offset[16];
2810 uint8_t mask_interrupts;
2811 uint16_t max_chain_frame_sz;
2812 struct mrsas_mpt_cmd **mpt_cmd_list;
2813 struct mrsas_mfi_cmd **mfi_cmd_list;
2814 TAILQ_HEAD(, mrsas_mpt_cmd) mrsas_mpt_cmd_list_head;
2815 TAILQ_HEAD(, mrsas_mfi_cmd) mrsas_mfi_cmd_list_head;
2816 bus_addr_t req_frames_desc_phys;
2817 u_int8_t *req_frames_desc;
2819 bus_addr_t io_request_frames_phys;
2820 u_int8_t *io_request_frames;
2821 bus_addr_t reply_frames_desc_phys;
2822 u_int16_t last_reply_idx[MAX_MSIX_COUNT];
2823 u_int32_t reply_q_depth;
2824 u_int32_t request_alloc_sz;
2825 u_int32_t reply_alloc_sz;
2826 u_int32_t io_frames_alloc_sz;
2827 u_int32_t chain_frames_alloc_sz;
2828 u_int16_t max_sge_in_main_msg;
2829 u_int16_t max_sge_in_chain;
2830 u_int8_t chain_offset_io_request;
2831 u_int8_t chain_offset_mfi_pthru;
2834 u_int64_t pd_seq_map_id;
2835 struct mrsas_mfi_cmd *map_update_cmd;
2836 struct mrsas_mfi_cmd *jbod_seq_cmd;
2837 struct mrsas_mfi_cmd *aen_cmd;
2838 u_int8_t fast_path_io;
2841 u_int8_t adprecovery;
2842 u_int8_t remove_in_progress;
2843 u_int8_t ocr_thread_active;
2844 u_int8_t do_timedout_reset;
2845 u_int32_t reset_in_progress;
2846 u_int32_t reset_count;
2847 u_int32_t block_sync_cache;
2848 u_int8_t fw_sync_cache_support;
2849 mrsas_atomic_t target_reset_outstanding;
2850 #define MRSAS_MAX_TM_TARGETS (MRSAS_MAX_PD + MRSAS_MAX_LD_IDS)
2851 struct mrsas_mpt_cmd *target_reset_pool[MRSAS_MAX_TM_TARGETS];
2853 bus_dma_tag_t jbodmap_tag[2];
2854 bus_dmamap_t jbodmap_dmamap[2];
2855 void *jbodmap_mem[2];
2856 bus_addr_t jbodmap_phys_addr[2];
2858 bus_dma_tag_t raidmap_tag[2];
2859 bus_dmamap_t raidmap_dmamap[2];
2860 void *raidmap_mem[2];
2861 bus_addr_t raidmap_phys_addr[2];
2862 bus_dma_tag_t mficmd_frame_tag;
2863 bus_dma_tag_t mficmd_sense_tag;
2864 bus_dma_tag_t evt_detail_tag;
2865 bus_dmamap_t evt_detail_dmamap;
2866 struct mrsas_evt_detail *evt_detail_mem;
2867 bus_addr_t evt_detail_phys_addr;
2868 struct mrsas_ctrl_info *ctrl_info;
2869 bus_dma_tag_t ctlr_info_tag;
2870 bus_dmamap_t ctlr_info_dmamap;
2871 void *ctlr_info_mem;
2872 bus_addr_t ctlr_info_phys_addr;
2873 u_int32_t max_sectors_per_req;
2874 u_int32_t disableOnlineCtrlReset;
2875 mrsas_atomic_t fw_outstanding;
2876 u_int32_t mrsas_debug;
2877 u_int32_t mrsas_io_timeout;
2878 u_int32_t mrsas_fw_fault_check_delay;
2879 u_int32_t io_cmds_highwater;
2880 u_int8_t UnevenSpanSupport;
2881 struct sysctl_ctx_list sysctl_ctx;
2882 struct sysctl_oid *sysctl_tree;
2883 struct proc *ocr_thread;
2884 u_int32_t last_seq_num;
2885 bus_dma_tag_t el_info_tag;
2886 bus_dmamap_t el_info_dmamap;
2888 bus_addr_t el_info_phys_addr;
2889 struct mrsas_pd_list pd_list[MRSAS_MAX_PD];
2890 struct mrsas_pd_list local_pd_list[MRSAS_MAX_PD];
2891 u_int8_t ld_ids[MRSAS_MAX_LD_IDS];
2892 struct taskqueue *ev_tq;
2893 struct task ev_task;
2894 u_int32_t CurLdCount;
2895 u_int64_t reset_flags;
2896 int lb_pending_cmds;
2897 LD_LOAD_BALANCE_INFO load_balance_info[MAX_LOGICAL_DRIVES_EXT];
2898 LD_SPAN_INFO log_to_span[MAX_LOGICAL_DRIVES_EXT];
2900 u_int8_t mrsas_gen3_ctrl;
2901 u_int8_t secure_jbod_support;
2902 u_int8_t use_seqnum_jbod_fp;
2903 u_int8_t max256vdSupport;
2904 u_int16_t fw_supported_vd_count;
2905 u_int16_t fw_supported_pd_count;
2907 u_int16_t drv_supported_vd_count;
2908 u_int16_t drv_supported_pd_count;
2910 u_int32_t max_map_sz;
2911 u_int32_t current_map_sz;
2912 u_int32_t old_map_sz;
2913 u_int32_t new_map_sz;
2914 u_int32_t drv_map_sz;
2916 /* Non dma-able memory. Driver local copy. */
2917 MR_DRV_RAID_MAP_ALL *ld_drv_map[2];
2920 /* Compatibility shims for different OS versions */
2921 #if __FreeBSD_version >= 800001
2922 #define mrsas_kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) \
2923 kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg)
2924 #define mrsas_kproc_exit(arg) kproc_exit(arg)
2926 #define mrsas_kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) \
2927 kthread_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg)
2928 #define mrsas_kproc_exit(arg) kthread_exit(arg)
2931 static __inline void
2932 mrsas_clear_bit(int b, volatile void *p)
2934 atomic_clear_int(((volatile int *)p) + (b >> 5), 1 << (b & 0x1f));
2937 static __inline void
2938 mrsas_set_bit(int b, volatile void *p)
2940 atomic_set_int(((volatile int *)p) + (b >> 5), 1 << (b & 0x1f));
2944 mrsas_test_bit(int b, volatile void *p)
2946 return ((volatile int *)p)[b >> 5] & (1 << (b & 0x1f));
2949 #endif /* MRSAS_H */