sys/dev/mrsas/mrsas.h

   1 /*
   2  * Copyright (c) 2015, AVAGO Tech. All rights reserved. Authors: Marian Choy
   3  * Copyright (c) 2014, LSI Corp. All rights reserved. Authors: Marian Choy
   4  * Support: freebsdraid@avagotech.com
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are
   8  * met:
   9  *
  10  * 1. Redistributions of source code must retain the above copyright notice,
  11  * this list of conditions and the following disclaimer. 2. Redistributions
  12  * in binary form must reproduce the above copyright notice, this list of
  13  * conditions and the following disclaimer in the documentation and/or other
  14  * materials provided with the distribution. 3. Neither the name of the
  15  * <ORGANIZATION> nor the names of its contributors may be used to endorse or
  16  * promote products derived from this software without specific prior written
  17  * permission.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  *
  31  * The views and conclusions contained in the software and documentation are
  32  * those of the authors and should not be interpreted as representing
  33  * official policies,either expressed or implied, of the FreeBSD Project.
  34  *
  35  * Send feedback to: <megaraidfbsd@avagotech.com> Mail to: AVAGO TECHNOLOGIES, 1621
  36  * Barber Lane, Milpitas, CA 95035 ATTN: MegaRaid FreeBSD
  37  *
  38  */
  39
  40 #include <sys/cdefs.h>
  41 __FBSDID("$FreeBSD$");
  42
  43 #ifndef MRSAS_H
  44 #define MRSAS_H
  45
  46 #include <sys/param.h>                  /* defines used in kernel.h */
  47 #include <sys/module.h>
  48 #include <sys/systm.h>
  49 #include <sys/proc.h>
  50 #include <sys/errno.h>
  51 #include <sys/kernel.h>                 /* types used in module initialization */
  52 #include <sys/conf.h>                   /* cdevsw struct */
  53 #include <sys/uio.h>                    /* uio struct */
  54 #include <sys/malloc.h>
  55 #include <sys/bus.h>                    /* structs, prototypes for pci bus
  56                                          * stuff */
  57 #include <sys/rman.h>
  58 #include <sys/types.h>
  59 #include <sys/lock.h>
  60 #include <sys/sema.h>
  61 #include <sys/sysctl.h>
  62 #include <sys/stat.h>
  63 #include <sys/taskqueue.h>
  64 #include <sys/poll.h>
  65 #include <sys/selinfo.h>
  66
  67 #include <machine/bus.h>
  68 #include <machine/resource.h>
  69 #include <machine/atomic.h>
  70
  71 #include <dev/pci/pcivar.h>             /* For pci_get macros! */
  72 #include <dev/pci/pcireg.h>
  73
  74
  75 #define IOCTL_SEMA_DESCRIPTION  "mrsas semaphore for MFI pool"
  76
  77 /*
  78  * Device IDs and PCI
  79  */
  80 #define MRSAS_TBOLT                     0x005b
  81 #define MRSAS_INVADER           0x005d
  82 #define MRSAS_FURY                      0x005f
  83 #define MRSAS_INTRUDER          0x00ce
  84 #define MRSAS_INTRUDER_24       0x00cf
  85 #define MRSAS_CUTLASS_52        0x0052
  86 #define MRSAS_CUTLASS_53        0x0053
  87 #define MRSAS_PCI_BAR0          0x10
  88 #define MRSAS_PCI_BAR1          0x14
  89 #define MRSAS_PCI_BAR2          0x1C
  90
  91 /*
  92  * Firmware State Defines
  93  */
  94 #define MRSAS_FWSTATE_MAXCMD_MASK               0x0000FFFF
  95 #define MRSAS_FWSTATE_SGE_MASK                  0x00FF0000
  96 #define MRSAS_FW_STATE_CHNG_INTERRUPT   1
  97
  98 /*
  99  * Message Frame Defines
 100  */
 101 #define MRSAS_SENSE_LEN                                 96
 102 #define MRSAS_FUSION_MAX_RESET_TRIES    3
 103
 104 /*
 105  * Miscellaneous Defines
 106  */
 107 #define BYTE_ALIGNMENT                                  1
 108 #define MRSAS_MAX_NAME_LENGTH                   32
 109 #define MRSAS_VERSION                                   "06.709.07.00-fbsd"
 110 #define MRSAS_ULONG_MAX                                 0xFFFFFFFFFFFFFFFF
 111 #define MRSAS_DEFAULT_TIMEOUT                   0x14    /* Temporarily set */
 112 #define DONE                                                    0
 113 #define MRSAS_PAGE_SIZE                                 4096
 114 #define MRSAS_RESET_NOTICE_INTERVAL             5
 115 #define MRSAS_IO_TIMEOUT                                180000  /* 180 second timeout */
 116 #define MRSAS_LDIO_QUEUE_DEPTH                  70      /* 70 percent as default */
 117 #define THRESHOLD_REPLY_COUNT                   50
 118 #define MAX_MSIX_COUNT                                  128
 119
 120 /*
 121  * Boolean types
 122  */
 123 #if (__FreeBSD_version < 901000)
 124 typedef enum _boolean {
 125         false, true
 126 }       boolean;
 127
 128 #endif
 129 enum err {
 130         SUCCESS, FAIL
 131 };
 132
 133 MALLOC_DECLARE(M_MRSAS);
 134 SYSCTL_DECL(_hw_mrsas);
 135
 136 #define MRSAS_INFO              (1 << 0)
 137 #define MRSAS_TRACE             (1 << 1)
 138 #define MRSAS_FAULT             (1 << 2)
 139 #define MRSAS_OCR               (1 << 3)
 140 #define MRSAS_TOUT              MRSAS_OCR
 141 #define MRSAS_AEN               (1 << 4)
 142 #define MRSAS_PRL11             (1 << 5)
 143
 144 #define mrsas_dprint(sc, level, msg, args...)       \
 145 do {                                                \
 146     if (sc->mrsas_debug & level)                    \
 147         device_printf(sc->mrsas_dev, msg, ##args);  \
 148 } while (0)
 149
 150
 151 /****************************************************************************
 152  * Raid Context structure which describes MegaRAID specific IO Paramenters
 153  * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames
 154  ****************************************************************************/
 155
 156 typedef struct _RAID_CONTEXT {
 157         u_int8_t Type:4;
 158         u_int8_t nseg:4;
 159         u_int8_t resvd0;
 160         u_int16_t timeoutValue;
 161         u_int8_t regLockFlags;
 162         u_int8_t resvd1;
 163         u_int16_t VirtualDiskTgtId;
 164         u_int64_t regLockRowLBA;
 165         u_int32_t regLockLength;
 166         u_int16_t nextLMId;
 167         u_int8_t exStatus;
 168         u_int8_t status;
 169         u_int8_t RAIDFlags;
 170         u_int8_t numSGE;
 171         u_int16_t configSeqNum;
 172         u_int8_t spanArm;
 173         u_int8_t priority;              /* 0x1D MR_PRIORITY_RANGE */
 174         u_int8_t numSGEExt;             /* 0x1E 1M IO support */
 175         u_int8_t resvd2;                /* 0x1F */
 176 }       RAID_CONTEXT;
 177
 178
 179 /*************************************************************************
 180  * MPI2 Defines
 181  ************************************************************************/
 182
 183 #define MPI2_FUNCTION_IOC_INIT                                  (0x02)  /* IOC Init */
 184 #define MPI2_WHOINIT_HOST_DRIVER                                (0x04)
 185 #define MPI2_VERSION_MAJOR                                              (0x02)
 186 #define MPI2_VERSION_MINOR                                              (0x00)
 187 #define MPI2_VERSION_MAJOR_MASK                                 (0xFF00)
 188 #define MPI2_VERSION_MAJOR_SHIFT                                (8)
 189 #define MPI2_VERSION_MINOR_MASK                                 (0x00FF)
 190 #define MPI2_VERSION_MINOR_SHIFT                                (0)
 191 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
 192                       MPI2_VERSION_MINOR)
 193 #define MPI2_HEADER_VERSION_UNIT                                (0x10)
 194 #define MPI2_HEADER_VERSION_DEV                                 (0x00)
 195 #define MPI2_HEADER_VERSION_UNIT_MASK                   (0xFF00)
 196 #define MPI2_HEADER_VERSION_UNIT_SHIFT                  (8)
 197 #define MPI2_HEADER_VERSION_DEV_MASK                    (0x00FF)
 198 #define MPI2_HEADER_VERSION_DEV_SHIFT                   (0)
 199 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | MPI2_HEADER_VERSION_DEV)
 200 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR              (0x03)
 201 #define MPI2_SCSIIO_EEDPFLAGS_INC_PRI_REFTAG    (0x8000)
 202 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REFTAG              (0x0400)
 203 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REMOVE_OP   (0x0003)
 204 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_APPTAG              (0x0200)
 205 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_GUARD               (0x0100)
 206 #define MPI2_SCSIIO_EEDPFLAGS_INSERT_OP                 (0x0004)
 207 #define MPI2_FUNCTION_SCSI_IO_REQUEST                   (0x00)  /* SCSI IO */
 208 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY   (0x06)
 209 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO                 (0x00)
 210 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING                (0x02)
 211 #define MPI2_SCSIIO_CONTROL_WRITE                               (0x01000000)
 212 #define MPI2_SCSIIO_CONTROL_READ                                (0x02000000)
 213 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK               (0x0E)
 214 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED                  (0x0F)
 215 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00)
 216 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK               (0x0F)
 217 #define MPI2_WRSEQ_FLUSH_KEY_VALUE                              (0x0)
 218 #define MPI2_WRITE_SEQUENCE_OFFSET                              (0x00000004)
 219 #define MPI2_WRSEQ_1ST_KEY_VALUE                                (0xF)
 220 #define MPI2_WRSEQ_2ND_KEY_VALUE                                (0x4)
 221 #define MPI2_WRSEQ_3RD_KEY_VALUE                                (0xB)
 222 #define MPI2_WRSEQ_4TH_KEY_VALUE                                (0x2)
 223 #define MPI2_WRSEQ_5TH_KEY_VALUE                                (0x7)
 224 #define MPI2_WRSEQ_6TH_KEY_VALUE                                (0xD)
 225
 226 #ifndef MPI2_POINTER
 227 #define MPI2_POINTER    *
 228 #endif
 229
 230
 231 /***************************************
 232  * MPI2 Structures
 233  ***************************************/
 234
 235 typedef struct _MPI25_IEEE_SGE_CHAIN64 {
 236         u_int64_t Address;
 237         u_int32_t Length;
 238         u_int16_t Reserved1;
 239         u_int8_t NextChainOffset;
 240         u_int8_t Flags;
 241 }       MPI25_IEEE_SGE_CHAIN64, MPI2_POINTER PTR_MPI25_IEEE_SGE_CHAIN64,
 242 Mpi25IeeeSgeChain64_t, MPI2_POINTER pMpi25IeeeSgeChain64_t;
 243
 244 typedef struct _MPI2_SGE_SIMPLE_UNION {
 245         u_int32_t FlagsLength;
 246         union {
 247                 u_int32_t Address32;
 248                 u_int64_t Address64;
 249         }       u;
 250 }       MPI2_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_SIMPLE_UNION,
 251 Mpi2SGESimpleUnion_t, MPI2_POINTER pMpi2SGESimpleUnion_t;
 252
 253 typedef struct {
 254         u_int8_t CDB[20];               /* 0x00 */
 255         u_int32_t PrimaryReferenceTag;  /* 0x14 */
 256         u_int16_t PrimaryApplicationTag;/* 0x18 */
 257         u_int16_t PrimaryApplicationTagMask;    /* 0x1A */
 258         u_int32_t TransferLength;       /* 0x1C */
 259 }       MPI2_SCSI_IO_CDB_EEDP32, MPI2_POINTER PTR_MPI2_SCSI_IO_CDB_EEDP32,
 260 Mpi2ScsiIoCdbEedp32_t, MPI2_POINTER pMpi2ScsiIoCdbEedp32_t;
 261
 262 typedef struct _MPI2_SGE_CHAIN_UNION {
 263         u_int16_t Length;
 264         u_int8_t NextChainOffset;
 265         u_int8_t Flags;
 266         union {
 267                 u_int32_t Address32;
 268                 u_int64_t Address64;
 269         }       u;
 270 }       MPI2_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_SGE_CHAIN_UNION,
 271 Mpi2SGEChainUnion_t, MPI2_POINTER pMpi2SGEChainUnion_t;
 272
 273 typedef struct _MPI2_IEEE_SGE_SIMPLE32 {
 274         u_int32_t Address;
 275         u_int32_t FlagsLength;
 276 }       MPI2_IEEE_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE32,
 277 Mpi2IeeeSgeSimple32_t, MPI2_POINTER pMpi2IeeeSgeSimple32_t;
 278 typedef struct _MPI2_IEEE_SGE_SIMPLE64 {
 279         u_int64_t Address;
 280         u_int32_t Length;
 281         u_int16_t Reserved1;
 282         u_int8_t Reserved2;
 283         u_int8_t Flags;
 284 }       MPI2_IEEE_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE64,
 285 Mpi2IeeeSgeSimple64_t, MPI2_POINTER pMpi2IeeeSgeSimple64_t;
 286
 287 typedef union _MPI2_IEEE_SGE_SIMPLE_UNION {
 288         MPI2_IEEE_SGE_SIMPLE32 Simple32;
 289         MPI2_IEEE_SGE_SIMPLE64 Simple64;
 290 }       MPI2_IEEE_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE_UNION,
 291 Mpi2IeeeSgeSimpleUnion_t, MPI2_POINTER pMpi2IeeeSgeSimpleUnion_t;
 292
 293 typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32;
 294 typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64;
 295
 296 typedef union _MPI2_IEEE_SGE_CHAIN_UNION {
 297         MPI2_IEEE_SGE_CHAIN32 Chain32;
 298         MPI2_IEEE_SGE_CHAIN64 Chain64;
 299 }       MPI2_IEEE_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_CHAIN_UNION,
 300 Mpi2IeeeSgeChainUnion_t, MPI2_POINTER pMpi2IeeeSgeChainUnion_t;
 301
 302 typedef union _MPI2_SGE_IO_UNION {
 303         MPI2_SGE_SIMPLE_UNION MpiSimple;
 304         MPI2_SGE_CHAIN_UNION MpiChain;
 305         MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
 306         MPI2_IEEE_SGE_CHAIN_UNION IeeeChain;
 307 }       MPI2_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_SGE_IO_UNION,
 308 Mpi2SGEIOUnion_t, MPI2_POINTER pMpi2SGEIOUnion_t;
 309
 310 typedef union {
 311         u_int8_t CDB32[32];
 312         MPI2_SCSI_IO_CDB_EEDP32 EEDP32;
 313         MPI2_SGE_SIMPLE_UNION SGE;
 314 }       MPI2_SCSI_IO_CDB_UNION, MPI2_POINTER PTR_MPI2_SCSI_IO_CDB_UNION,
 315 Mpi2ScsiIoCdb_t, MPI2_POINTER pMpi2ScsiIoCdb_t;
 316
 317 /*
 318  * RAID SCSI IO Request Message Total SGE count will be one less than
 319  * _MPI2_SCSI_IO_REQUEST
 320  */
 321 typedef struct _MPI2_RAID_SCSI_IO_REQUEST {
 322         u_int16_t DevHandle;            /* 0x00 */
 323         u_int8_t ChainOffset;           /* 0x02 */
 324         u_int8_t Function;              /* 0x03 */
 325         u_int16_t Reserved1;            /* 0x04 */
 326         u_int8_t Reserved2;             /* 0x06 */
 327         u_int8_t MsgFlags;              /* 0x07 */
 328         u_int8_t VP_ID;                 /* 0x08 */
 329         u_int8_t VF_ID;                 /* 0x09 */
 330         u_int16_t Reserved3;            /* 0x0A */
 331         u_int32_t SenseBufferLowAddress;/* 0x0C */
 332         u_int16_t SGLFlags;             /* 0x10 */
 333         u_int8_t SenseBufferLength;     /* 0x12 */
 334         u_int8_t Reserved4;             /* 0x13 */
 335         u_int8_t SGLOffset0;            /* 0x14 */
 336         u_int8_t SGLOffset1;            /* 0x15 */
 337         u_int8_t SGLOffset2;            /* 0x16 */
 338         u_int8_t SGLOffset3;            /* 0x17 */
 339         u_int32_t SkipCount;            /* 0x18 */
 340         u_int32_t DataLength;           /* 0x1C */
 341         u_int32_t BidirectionalDataLength;      /* 0x20 */
 342         u_int16_t IoFlags;              /* 0x24 */
 343         u_int16_t EEDPFlags;            /* 0x26 */
 344         u_int32_t EEDPBlockSize;        /* 0x28 */
 345         u_int32_t SecondaryReferenceTag;/* 0x2C */
 346         u_int16_t SecondaryApplicationTag;      /* 0x30 */
 347         u_int16_t ApplicationTagTranslationMask;        /* 0x32 */
 348         u_int8_t LUN[8];                /* 0x34 */
 349         u_int32_t Control;              /* 0x3C */
 350         MPI2_SCSI_IO_CDB_UNION CDB;     /* 0x40 */
 351         RAID_CONTEXT RaidContext;       /* 0x60 */
 352         MPI2_SGE_IO_UNION SGL;          /* 0x80 */
 353 }       MRSAS_RAID_SCSI_IO_REQUEST, MPI2_POINTER PTR_MRSAS_RAID_SCSI_IO_REQUEST,
 354 MRSASRaidSCSIIORequest_t, MPI2_POINTER pMRSASRaidSCSIIORequest_t;
 355
 356 /*
 357  * MPT RAID MFA IO Descriptor.
 358  */
 359 typedef struct _MRSAS_RAID_MFA_IO_DESCRIPTOR {
 360         u_int32_t RequestFlags:8;
 361         u_int32_t MessageAddress1:24;   /* bits 31:8 */
 362         u_int32_t MessageAddress2;      /* bits 61:32 */
 363 }       MRSAS_RAID_MFA_IO_REQUEST_DESCRIPTOR, *PMRSAS_RAID_MFA_IO_REQUEST_DESCRIPTOR;
 364
 365 /* Default Request Descriptor */
 366 typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR {
 367         u_int8_t RequestFlags;          /* 0x00 */
 368         u_int8_t MSIxIndex;             /* 0x01 */
 369         u_int16_t SMID;                 /* 0x02 */
 370         u_int16_t LMID;                 /* 0x04 */
 371         u_int16_t DescriptorTypeDependent;      /* 0x06 */
 372 }       MPI2_DEFAULT_REQUEST_DESCRIPTOR,
 373
 374         MPI2_POINTER PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR,
 375 Mpi2DefaultRequestDescriptor_t, MPI2_POINTER pMpi2DefaultRequestDescriptor_t;
 376
 377 /* High Priority Request Descriptor */
 378 typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR {
 379         u_int8_t RequestFlags;          /* 0x00 */
 380         u_int8_t MSIxIndex;             /* 0x01 */
 381         u_int16_t SMID;                 /* 0x02 */
 382         u_int16_t LMID;                 /* 0x04 */
 383         u_int16_t Reserved1;            /* 0x06 */
 384 }       MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
 385
 386         MPI2_POINTER PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
 387 Mpi2HighPriorityRequestDescriptor_t, MPI2_POINTER pMpi2HighPriorityRequestDescriptor_t;
 388
 389 /* SCSI IO Request Descriptor */
 390 typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR {
 391         u_int8_t RequestFlags;          /* 0x00 */
 392         u_int8_t MSIxIndex;             /* 0x01 */
 393         u_int16_t SMID;                 /* 0x02 */
 394         u_int16_t LMID;                 /* 0x04 */
 395         u_int16_t DevHandle;            /* 0x06 */
 396 }       MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
 397
 398         MPI2_POINTER PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
 399 Mpi2SCSIIORequestDescriptor_t, MPI2_POINTER pMpi2SCSIIORequestDescriptor_t;
 400
 401 /* SCSI Target Request Descriptor */
 402 typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR {
 403         u_int8_t RequestFlags;          /* 0x00 */
 404         u_int8_t MSIxIndex;             /* 0x01 */
 405         u_int16_t SMID;                 /* 0x02 */
 406         u_int16_t LMID;                 /* 0x04 */
 407         u_int16_t IoIndex;              /* 0x06 */
 408 }       MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
 409
 410         MPI2_POINTER PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
 411 Mpi2SCSITargetRequestDescriptor_t, MPI2_POINTER pMpi2SCSITargetRequestDescriptor_t;
 412
 413 /* RAID Accelerator Request Descriptor */
 414 typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR {
 415         u_int8_t RequestFlags;          /* 0x00 */
 416         u_int8_t MSIxIndex;             /* 0x01 */
 417         u_int16_t SMID;                 /* 0x02 */
 418         u_int16_t LMID;                 /* 0x04 */
 419         u_int16_t Reserved;             /* 0x06 */
 420 }       MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
 421
 422         MPI2_POINTER PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
 423 Mpi2RAIDAcceleratorRequestDescriptor_t, MPI2_POINTER pMpi2RAIDAcceleratorRequestDescriptor_t;
 424
 425 /* union of Request Descriptors */
 426 typedef union _MRSAS_REQUEST_DESCRIPTOR_UNION {
 427         MPI2_DEFAULT_REQUEST_DESCRIPTOR Default;
 428         MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority;
 429         MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO;
 430         MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget;
 431         MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator;
 432         MRSAS_RAID_MFA_IO_REQUEST_DESCRIPTOR MFAIo;
 433         union {
 434                 struct {
 435                         u_int32_t low;
 436                         u_int32_t high;
 437                 }       u;
 438                 u_int64_t Words;
 439         }       addr;
 440 }       MRSAS_REQUEST_DESCRIPTOR_UNION;
 441
 442 /* Default Reply Descriptor */
 443 typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR {
 444         u_int8_t ReplyFlags;            /* 0x00 */
 445         u_int8_t MSIxIndex;             /* 0x01 */
 446         u_int16_t DescriptorTypeDependent1;     /* 0x02 */
 447         u_int32_t DescriptorTypeDependent2;     /* 0x04 */
 448 }       MPI2_DEFAULT_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR,
 449 Mpi2DefaultReplyDescriptor_t, MPI2_POINTER pMpi2DefaultReplyDescriptor_t;
 450
 451 /* Address Reply Descriptor */
 452 typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR {
 453         u_int8_t ReplyFlags;            /* 0x00 */
 454         u_int8_t MSIxIndex;             /* 0x01 */
 455         u_int16_t SMID;                 /* 0x02 */
 456         u_int32_t ReplyFrameAddress;    /* 0x04 */
 457 }       MPI2_ADDRESS_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR,
 458 Mpi2AddressReplyDescriptor_t, MPI2_POINTER pMpi2AddressReplyDescriptor_t;
 459
 460 /* SCSI IO Success Reply Descriptor */
 461 typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR {
 462         u_int8_t ReplyFlags;            /* 0x00 */
 463         u_int8_t MSIxIndex;             /* 0x01 */
 464         u_int16_t SMID;                 /* 0x02 */
 465         u_int16_t TaskTag;              /* 0x04 */
 466         u_int16_t Reserved1;            /* 0x06 */
 467 }       MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
 468
 469         MPI2_POINTER PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
 470 Mpi2SCSIIOSuccessReplyDescriptor_t, MPI2_POINTER pMpi2SCSIIOSuccessReplyDescriptor_t;
 471
 472 /* TargetAssist Success Reply Descriptor */
 473 typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR {
 474         u_int8_t ReplyFlags;            /* 0x00 */
 475         u_int8_t MSIxIndex;             /* 0x01 */
 476         u_int16_t SMID;                 /* 0x02 */
 477         u_int8_t SequenceNumber;        /* 0x04 */
 478         u_int8_t Reserved1;             /* 0x05 */
 479         u_int16_t IoIndex;              /* 0x06 */
 480 }       MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
 481
 482         MPI2_POINTER PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
 483 Mpi2TargetAssistSuccessReplyDescriptor_t, MPI2_POINTER pMpi2TargetAssistSuccessReplyDescriptor_t;
 484
 485 /* Target Command Buffer Reply Descriptor */
 486 typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR {
 487         u_int8_t ReplyFlags;            /* 0x00 */
 488         u_int8_t MSIxIndex;             /* 0x01 */
 489         u_int8_t VP_ID;                 /* 0x02 */
 490         u_int8_t Flags;                 /* 0x03 */
 491         u_int16_t InitiatorDevHandle;   /* 0x04 */
 492         u_int16_t IoIndex;              /* 0x06 */
 493 }       MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
 494
 495         MPI2_POINTER PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
 496 Mpi2TargetCommandBufferReplyDescriptor_t, MPI2_POINTER pMpi2TargetCommandBufferReplyDescriptor_t;
 497
 498 /* RAID Accelerator Success Reply Descriptor */
 499 typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR {
 500         u_int8_t ReplyFlags;            /* 0x00 */
 501         u_int8_t MSIxIndex;             /* 0x01 */
 502         u_int16_t SMID;                 /* 0x02 */
 503         u_int32_t Reserved;             /* 0x04 */
 504 }       MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
 505
 506         MPI2_POINTER PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
 507 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t, MPI2_POINTER pMpi2RAIDAcceleratorSuccessReplyDescriptor_t;
 508
 509 /* union of Reply Descriptors */
 510 typedef union _MPI2_REPLY_DESCRIPTORS_UNION {
 511         MPI2_DEFAULT_REPLY_DESCRIPTOR Default;
 512         MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply;
 513         MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess;
 514         MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess;
 515         MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer;
 516         MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess;
 517         u_int64_t Words;
 518 }       MPI2_REPLY_DESCRIPTORS_UNION, MPI2_POINTER PTR_MPI2_REPLY_DESCRIPTORS_UNION,
 519 Mpi2ReplyDescriptorsUnion_t, MPI2_POINTER pMpi2ReplyDescriptorsUnion_t;
 520
 521 typedef union {
 522         volatile unsigned int val;
 523         unsigned int val_rdonly;
 524 } mrsas_atomic_t;
 525
 526 #define mrsas_atomic_read(v)    atomic_load_acq_int(&(v)->val)
 527 #define mrsas_atomic_set(v,i)   atomic_store_rel_int(&(v)->val, i)
 528 #define mrsas_atomic_dec(v)     atomic_fetchadd_int(&(v)->val, -1)
 529 #define mrsas_atomic_inc(v)     atomic_fetchadd_int(&(v)->val, 1)
 530
 531 /* IOCInit Request message */
 532 typedef struct _MPI2_IOC_INIT_REQUEST {
 533         u_int8_t WhoInit;               /* 0x00 */
 534         u_int8_t Reserved1;             /* 0x01 */
 535         u_int8_t ChainOffset;           /* 0x02 */
 536         u_int8_t Function;              /* 0x03 */
 537         u_int16_t Reserved2;            /* 0x04 */
 538         u_int8_t Reserved3;             /* 0x06 */
 539         u_int8_t MsgFlags;              /* 0x07 */
 540         u_int8_t VP_ID;                 /* 0x08 */
 541         u_int8_t VF_ID;                 /* 0x09 */
 542         u_int16_t Reserved4;            /* 0x0A */
 543         u_int16_t MsgVersion;           /* 0x0C */
 544         u_int16_t HeaderVersion;        /* 0x0E */
 545         u_int32_t Reserved5;            /* 0x10 */
 546         u_int16_t Reserved6;            /* 0x14 */
 547         u_int8_t Reserved7;             /* 0x16 */
 548         u_int8_t HostMSIxVectors;       /* 0x17 */
 549         u_int16_t Reserved8;            /* 0x18 */
 550         u_int16_t SystemRequestFrameSize;       /* 0x1A */
 551         u_int16_t ReplyDescriptorPostQueueDepth;        /* 0x1C */
 552         u_int16_t ReplyFreeQueueDepth;  /* 0x1E */
 553         u_int32_t SenseBufferAddressHigh;       /* 0x20 */
 554         u_int32_t SystemReplyAddressHigh;       /* 0x24 */
 555         u_int64_t SystemRequestFrameBaseAddress;        /* 0x28 */
 556         u_int64_t ReplyDescriptorPostQueueAddress;      /* 0x30 */
 557         u_int64_t ReplyFreeQueueAddress;/* 0x38 */
 558         u_int64_t TimeStamp;            /* 0x40 */
 559 }       MPI2_IOC_INIT_REQUEST, MPI2_POINTER PTR_MPI2_IOC_INIT_REQUEST,
 560 Mpi2IOCInitRequest_t, MPI2_POINTER pMpi2IOCInitRequest_t;
 561
 562 /*
 563  * MR private defines
 564  */
 565 #define MR_PD_INVALID                   0xFFFF
 566 #define MAX_SPAN_DEPTH                  8
 567 #define MAX_QUAD_DEPTH                  MAX_SPAN_DEPTH
 568 #define MAX_RAIDMAP_SPAN_DEPTH  (MAX_SPAN_DEPTH)
 569 #define MAX_ROW_SIZE                    32
 570 #define MAX_RAIDMAP_ROW_SIZE    (MAX_ROW_SIZE)
 571 #define MAX_LOGICAL_DRIVES              64
 572 #define MAX_LOGICAL_DRIVES_EXT  256
 573
 574 #define MAX_RAIDMAP_LOGICAL_DRIVES      (MAX_LOGICAL_DRIVES)
 575 #define MAX_RAIDMAP_VIEWS                       (MAX_LOGICAL_DRIVES)
 576
 577 #define MAX_ARRAYS                              128
 578 #define MAX_RAIDMAP_ARRAYS              (MAX_ARRAYS)
 579
 580 #define MAX_ARRAYS_EXT                  256
 581 #define MAX_API_ARRAYS_EXT              MAX_ARRAYS_EXT
 582
 583 #define MAX_PHYSICAL_DEVICES    256
 584 #define MAX_RAIDMAP_PHYSICAL_DEVICES    (MAX_PHYSICAL_DEVICES)
 585 #define MR_DCMD_LD_MAP_GET_INFO 0x0300e101
 586 #define MR_DCMD_SYSTEM_PD_MAP_GET_INFO  0x0200e102
 587
 588
 589 #define MRSAS_MAX_PD_CHANNELS           1
 590 #define MRSAS_MAX_LD_CHANNELS           1
 591 #define MRSAS_MAX_DEV_PER_CHANNEL       256
 592 #define MRSAS_DEFAULT_INIT_ID           -1
 593 #define MRSAS_MAX_LUN                           8
 594 #define MRSAS_DEFAULT_CMD_PER_LUN       256
 595 #define MRSAS_MAX_PD                            (MRSAS_MAX_PD_CHANNELS * \
 596                         MRSAS_MAX_DEV_PER_CHANNEL)
 597 #define MRSAS_MAX_LD_IDS                        (MRSAS_MAX_LD_CHANNELS * \
 598                         MRSAS_MAX_DEV_PER_CHANNEL)
 599
 600
 601 #define VD_EXT_DEBUG    0
 602
 603
 604 /*******************************************************************
 605  * RAID map related structures
 606  ********************************************************************/
 607 #pragma pack(1)
 608 typedef struct _MR_DEV_HANDLE_INFO {
 609         u_int16_t curDevHdl;
 610         u_int8_t validHandles;
 611         u_int8_t reserved;
 612         u_int16_t devHandle[2];
 613 }       MR_DEV_HANDLE_INFO;
 614
 615 #pragma pack()
 616
 617 typedef struct _MR_ARRAY_INFO {
 618         u_int16_t pd[MAX_RAIDMAP_ROW_SIZE];
 619 }       MR_ARRAY_INFO;
 620
 621 typedef struct _MR_QUAD_ELEMENT {
 622         u_int64_t logStart;
 623         u_int64_t logEnd;
 624         u_int64_t offsetInSpan;
 625         u_int32_t diff;
 626         u_int32_t reserved1;
 627 }       MR_QUAD_ELEMENT;
 628
 629 typedef struct _MR_SPAN_INFO {
 630         u_int32_t noElements;
 631         u_int32_t reserved1;
 632         MR_QUAD_ELEMENT quad[MAX_RAIDMAP_SPAN_DEPTH];
 633 }       MR_SPAN_INFO;
 634
 635 typedef struct _MR_LD_SPAN_ {
 636         u_int64_t startBlk;
 637         u_int64_t numBlks;
 638         u_int16_t arrayRef;
 639         u_int8_t spanRowSize;
 640         u_int8_t spanRowDataSize;
 641         u_int8_t reserved[4];
 642 }       MR_LD_SPAN;
 643
 644 typedef struct _MR_SPAN_BLOCK_INFO {
 645         u_int64_t num_rows;
 646         MR_LD_SPAN span;
 647         MR_SPAN_INFO block_span_info;
 648 }       MR_SPAN_BLOCK_INFO;
 649
 650 typedef struct _MR_LD_RAID {
 651         struct {
 652                 u_int32_t fpCapable:1;
 653                 u_int32_t reserved5:3;
 654                 u_int32_t ldPiMode:4;
 655                 u_int32_t pdPiMode:4;
 656                 u_int32_t encryptionType:8;
 657                 u_int32_t fpWriteCapable:1;
 658                 u_int32_t fpReadCapable:1;
 659                 u_int32_t fpWriteAcrossStripe:1;
 660                 u_int32_t fpReadAcrossStripe:1;
 661                 u_int32_t fpNonRWCapable:1;
 662                 u_int32_t reserved4:7;
 663         }       capability;
 664         u_int32_t reserved6;
 665         u_int64_t size;
 666
 667         u_int8_t spanDepth;
 668         u_int8_t level;
 669         u_int8_t stripeShift;
 670         u_int8_t rowSize;
 671
 672         u_int8_t rowDataSize;
 673         u_int8_t writeMode;
 674         u_int8_t PRL;
 675         u_int8_t SRL;
 676
 677         u_int16_t targetId;
 678         u_int8_t ldState;
 679         u_int8_t regTypeReqOnWrite;
 680         u_int8_t modFactor;
 681         u_int8_t regTypeReqOnRead;
 682         u_int16_t seqNum;
 683
 684         struct {
 685                 u_int32_t ldSyncRequired:1;
 686                 u_int32_t regTypeReqOnReadLsValid:1;
 687                 u_int32_t reserved:30;
 688         }       flags;
 689
 690         u_int8_t LUN[8];
 691         u_int8_t fpIoTimeoutForLd;
 692         u_int8_t reserved2[3];
 693         u_int32_t logicalBlockLength;
 694         struct {
 695                 u_int32_t LdPiExp:4;
 696                 u_int32_t LdLogicalBlockExp:4;
 697                 u_int32_t reserved1:24;
 698         }       exponent;
 699         u_int8_t reserved3[0x80 - 0x38];
 700 }       MR_LD_RAID;
 701
 702 typedef struct _MR_LD_SPAN_MAP {
 703         MR_LD_RAID ldRaid;
 704         u_int8_t dataArmMap[MAX_RAIDMAP_ROW_SIZE];
 705         MR_SPAN_BLOCK_INFO spanBlock[MAX_RAIDMAP_SPAN_DEPTH];
 706 }       MR_LD_SPAN_MAP;
 707
 708 typedef struct _MR_FW_RAID_MAP {
 709         u_int32_t totalSize;
 710         union {
 711                 struct {
 712                         u_int32_t maxLd;
 713                         u_int32_t maxSpanDepth;
 714                         u_int32_t maxRowSize;
 715                         u_int32_t maxPdCount;
 716                         u_int32_t maxArrays;
 717                 }       validationInfo;
 718                 u_int32_t version[5];
 719                 u_int32_t reserved1[5];
 720         }       raid_desc;
 721         u_int32_t ldCount;
 722         u_int32_t Reserved1;
 723
 724         /*
 725          * This doesn't correspond to FW Ld Tgt Id to LD, but will purge. For
 726          * example: if tgt Id is 4 and FW LD is 2, and there is only one LD,
 727          * FW will populate the array like this. [0xFF, 0xFF, 0xFF, 0xFF,
 728          * 0x0,.....]. This is to help reduce the entire strcture size if
 729          * there are few LDs or driver is looking info for 1 LD only.
 730          */
 731         u_int8_t ldTgtIdToLd[MAX_RAIDMAP_LOGICAL_DRIVES + MAX_RAIDMAP_VIEWS];
 732         u_int8_t fpPdIoTimeoutSec;
 733         u_int8_t reserved2[7];
 734         MR_ARRAY_INFO arMapInfo[MAX_RAIDMAP_ARRAYS];
 735         MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES];
 736         MR_LD_SPAN_MAP ldSpanMap[1];
 737 }       MR_FW_RAID_MAP;
 738
 739
 740 typedef struct _MR_FW_RAID_MAP_EXT {
 741         /* Not used in new map */
 742         u_int32_t reserved;
 743
 744         union {
 745                 struct {
 746                         u_int32_t maxLd;
 747                         u_int32_t maxSpanDepth;
 748                         u_int32_t maxRowSize;
 749                         u_int32_t maxPdCount;
 750                         u_int32_t maxArrays;
 751                 }       validationInfo;
 752                 u_int32_t version[5];
 753                 u_int32_t reserved1[5];
 754         }       fw_raid_desc;
 755
 756         u_int8_t fpPdIoTimeoutSec;
 757         u_int8_t reserved2[7];
 758
 759         u_int16_t ldCount;
 760         u_int16_t arCount;
 761         u_int16_t spanCount;
 762         u_int16_t reserve3;
 763
 764         MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES];
 765         u_int8_t ldTgtIdToLd[MAX_LOGICAL_DRIVES_EXT];
 766         MR_ARRAY_INFO arMapInfo[MAX_API_ARRAYS_EXT];
 767         MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES_EXT];
 768 }       MR_FW_RAID_MAP_EXT;
 769
 770
 771 typedef struct _MR_DRV_RAID_MAP {
 772         /*
 773          * Total size of this structure, including this field. This feild
 774          * will be manupulated by driver for ext raid map, else pick the
 775          * value from firmware raid map.
 776          */
 777         u_int32_t totalSize;
 778
 779         union {
 780                 struct {
 781                         u_int32_t maxLd;
 782                         u_int32_t maxSpanDepth;
 783                         u_int32_t maxRowSize;
 784                         u_int32_t maxPdCount;
 785                         u_int32_t maxArrays;
 786                 }       validationInfo;
 787                 u_int32_t version[5];
 788                 u_int32_t reserved1[5];
 789         }       drv_raid_desc;
 790
 791         /* timeout value used by driver in FP IOs */
 792         u_int8_t fpPdIoTimeoutSec;
 793         u_int8_t reserved2[7];
 794
 795         u_int16_t ldCount;
 796         u_int16_t arCount;
 797         u_int16_t spanCount;
 798         u_int16_t reserve3;
 799
 800         MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES];
 801         u_int8_t ldTgtIdToLd[MAX_LOGICAL_DRIVES_EXT];
 802         MR_ARRAY_INFO arMapInfo[MAX_API_ARRAYS_EXT];
 803         MR_LD_SPAN_MAP ldSpanMap[1];
 804
 805 }       MR_DRV_RAID_MAP;
 806
 807 /*
 808  * Driver raid map size is same as raid map ext MR_DRV_RAID_MAP_ALL is
 809  * created to sync with old raid. And it is mainly for code re-use purpose.
 810  */
 811
 812 #pragma pack(1)
 813 typedef struct _MR_DRV_RAID_MAP_ALL {
 814
 815         MR_DRV_RAID_MAP raidMap;
 816         MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES_EXT - 1];
 817 }       MR_DRV_RAID_MAP_ALL;
 818
 819 #pragma pack()
 820
 821 typedef struct _LD_LOAD_BALANCE_INFO {
 822         u_int8_t loadBalanceFlag;
 823         u_int8_t reserved1;
 824         mrsas_atomic_t scsi_pending_cmds[MAX_PHYSICAL_DEVICES];
 825         u_int64_t last_accessed_block[MAX_PHYSICAL_DEVICES];
 826 }       LD_LOAD_BALANCE_INFO, *PLD_LOAD_BALANCE_INFO;
 827
 828 /* SPAN_SET is info caclulated from span info from Raid map per ld */
 829 typedef struct _LD_SPAN_SET {
 830         u_int64_t log_start_lba;
 831         u_int64_t log_end_lba;
 832         u_int64_t span_row_start;
 833         u_int64_t span_row_end;
 834         u_int64_t data_strip_start;
 835         u_int64_t data_strip_end;
 836         u_int64_t data_row_start;
 837         u_int64_t data_row_end;
 838         u_int8_t strip_offset[MAX_SPAN_DEPTH];
 839         u_int32_t span_row_data_width;
 840         u_int32_t diff;
 841         u_int32_t reserved[2];
 842 }       LD_SPAN_SET, *PLD_SPAN_SET;
 843
 844 typedef struct LOG_BLOCK_SPAN_INFO {
 845         LD_SPAN_SET span_set[MAX_SPAN_DEPTH];
 846 }       LD_SPAN_INFO, *PLD_SPAN_INFO;
 847
 848 #pragma pack(1)
 849 typedef struct _MR_FW_RAID_MAP_ALL {
 850         MR_FW_RAID_MAP raidMap;
 851         MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES - 1];
 852 }       MR_FW_RAID_MAP_ALL;
 853
 854 #pragma pack()
 855
 856 struct IO_REQUEST_INFO {
 857         u_int64_t ldStartBlock;
 858         u_int32_t numBlocks;
 859         u_int16_t ldTgtId;
 860         u_int8_t isRead;
 861         u_int16_t devHandle;
 862         u_int64_t pdBlock;
 863         u_int8_t fpOkForIo;
 864         u_int8_t IoforUnevenSpan;
 865         u_int8_t start_span;
 866         u_int8_t reserved;
 867         u_int64_t start_row;
 868         /* span[7:5], arm[4:0] */
 869         u_int8_t span_arm;
 870         u_int8_t pd_after_lb;
 871 };
 872
 873 /*
 874  * define MR_PD_CFG_SEQ structure for system PDs
 875  */
 876 struct MR_PD_CFG_SEQ {
 877         u_int16_t seqNum;
 878         u_int16_t devHandle;
 879         u_int8_t reserved[4];
 880 } __packed;
 881
 882 struct MR_PD_CFG_SEQ_NUM_SYNC {
 883         u_int32_t size;
 884         u_int32_t count;
 885         struct MR_PD_CFG_SEQ seq[1];
 886 } __packed;
 887
 888
 889 typedef struct _MR_LD_TARGET_SYNC {
 890         u_int8_t targetId;
 891         u_int8_t reserved;
 892         u_int16_t seqNum;
 893 }       MR_LD_TARGET_SYNC;
 894
 895 #define IEEE_SGE_FLAGS_ADDR_MASK                (0x03)
 896 #define IEEE_SGE_FLAGS_SYSTEM_ADDR              (0x00)
 897 #define IEEE_SGE_FLAGS_IOCDDR_ADDR              (0x01)
 898 #define IEEE_SGE_FLAGS_IOCPLB_ADDR              (0x02)
 899 #define IEEE_SGE_FLAGS_IOCPLBNTA_ADDR   (0x03)
 900 #define IEEE_SGE_FLAGS_CHAIN_ELEMENT    (0x80)
 901 #define IEEE_SGE_FLAGS_END_OF_LIST              (0x40)
 902
 903 union desc_value {
 904         u_int64_t word;
 905         struct {
 906                 u_int32_t low;
 907                 u_int32_t high;
 908         }       u;
 909 };
 910
 911 /*******************************************************************
 912  * Temporary command
 913  ********************************************************************/
 914 struct mrsas_tmp_dcmd {
 915         bus_dma_tag_t tmp_dcmd_tag;
 916         bus_dmamap_t tmp_dcmd_dmamap;
 917         void   *tmp_dcmd_mem;
 918         bus_addr_t tmp_dcmd_phys_addr;
 919 };
 920
 921 /*******************************************************************
 922  * Register set, included legacy controllers 1068 and 1078,
 923  * structure extended for 1078 registers
 924  *******************************************************************/
 925 #pragma pack(1)
 926 typedef struct _mrsas_register_set {
 927         u_int32_t doorbell;             /* 0000h */
 928         u_int32_t fusion_seq_offset;    /* 0004h */
 929         u_int32_t fusion_host_diag;     /* 0008h */
 930         u_int32_t reserved_01;          /* 000Ch */
 931
 932         u_int32_t inbound_msg_0;        /* 0010h */
 933         u_int32_t inbound_msg_1;        /* 0014h */
 934         u_int32_t outbound_msg_0;       /* 0018h */
 935         u_int32_t outbound_msg_1;       /* 001Ch */
 936
 937         u_int32_t inbound_doorbell;     /* 0020h */
 938         u_int32_t inbound_intr_status;  /* 0024h */
 939         u_int32_t inbound_intr_mask;    /* 0028h */
 940
 941         u_int32_t outbound_doorbell;    /* 002Ch */
 942         u_int32_t outbound_intr_status; /* 0030h */
 943         u_int32_t outbound_intr_mask;   /* 0034h */
 944
 945         u_int32_t reserved_1[2];        /* 0038h */
 946
 947         u_int32_t inbound_queue_port;   /* 0040h */
 948         u_int32_t outbound_queue_port;  /* 0044h */
 949
 950         u_int32_t reserved_2[9];        /* 0048h */
 951         u_int32_t reply_post_host_index;/* 006Ch */
 952         u_int32_t reserved_2_2[12];     /* 0070h */
 953
 954         u_int32_t outbound_doorbell_clear;      /* 00A0h */
 955
 956         u_int32_t reserved_3[3];        /* 00A4h */
 957
 958         u_int32_t outbound_scratch_pad; /* 00B0h */
 959         u_int32_t outbound_scratch_pad_2;       /* 00B4h */
 960
 961         u_int32_t reserved_4[2];        /* 00B8h */
 962
 963         u_int32_t inbound_low_queue_port;       /* 00C0h */
 964
 965         u_int32_t inbound_high_queue_port;      /* 00C4h */
 966
 967         u_int32_t reserved_5;           /* 00C8h */
 968         u_int32_t res_6[11];            /* CCh */
 969         u_int32_t host_diag;
 970         u_int32_t seq_offset;
 971         u_int32_t index_registers[807]; /* 00CCh */
 972 }       mrsas_reg_set;
 973
 974 #pragma pack()
 975
 976 /*******************************************************************
 977  * Firmware Interface Defines
 978  *******************************************************************
 979  * MFI stands for MegaRAID SAS FW Interface. This is just a moniker
 980  * for protocol between the software and firmware. Commands are
 981  * issued using "message frames".
 982  ******************************************************************/
 983 /*
 984  * FW posts its state in upper 4 bits of outbound_msg_0 register
 985  */
 986 #define MFI_STATE_MASK                                  0xF0000000
 987 #define MFI_STATE_UNDEFINED                             0x00000000
 988 #define MFI_STATE_BB_INIT                               0x10000000
 989 #define MFI_STATE_FW_INIT                               0x40000000
 990 #define MFI_STATE_WAIT_HANDSHAKE                0x60000000
 991 #define MFI_STATE_FW_INIT_2                             0x70000000
 992 #define MFI_STATE_DEVICE_SCAN                   0x80000000
 993 #define MFI_STATE_BOOT_MESSAGE_PENDING  0x90000000
 994 #define MFI_STATE_FLUSH_CACHE                   0xA0000000
 995 #define MFI_STATE_READY                                 0xB0000000
 996 #define MFI_STATE_OPERATIONAL                   0xC0000000
 997 #define MFI_STATE_FAULT                                 0xF0000000
 998 #define MFI_RESET_REQUIRED                              0x00000001
 999 #define MFI_RESET_ADAPTER                               0x00000002
1000 #define MEGAMFI_FRAME_SIZE                              64
1001 #define MRSAS_MFI_FRAME_SIZE                    1024
1002 #define MRSAS_MFI_SENSE_SIZE                    128
1003
1004 /*
1005  * During FW init, clear pending cmds & reset state using inbound_msg_0
1006  *
1007  * ABORT        : Abort all pending cmds READY        : Move from OPERATIONAL to
1008  * READY state; discard queue info MFIMODE      : Discard (possible) low MFA
1009  * posted in 64-bit mode (??) CLR_HANDSHAKE: FW is waiting for HANDSHAKE from
1010  * BIOS or Driver HOTPLUG      : Resume from Hotplug MFI_STOP_ADP : Send
1011  * signal to FW to stop processing
1012  */
1013
1014 #define WRITE_SEQUENCE_OFFSET           (0x0000000FC)
1015 #define HOST_DIAGNOSTIC_OFFSET          (0x000000F8)
1016 #define DIAG_WRITE_ENABLE                       (0x00000080)
1017 #define DIAG_RESET_ADAPTER                      (0x00000004)
1018
1019 #define MFI_ADP_RESET                           0x00000040
1020 #define MFI_INIT_ABORT                          0x00000001
1021 #define MFI_INIT_READY                          0x00000002
1022 #define MFI_INIT_MFIMODE                        0x00000004
1023 #define MFI_INIT_CLEAR_HANDSHAKE        0x00000008
1024 #define MFI_INIT_HOTPLUG                        0x00000010
1025 #define MFI_STOP_ADP                            0x00000020
1026 #define MFI_RESET_FLAGS                         MFI_INIT_READY|         \
1027                                                                         MFI_INIT_MFIMODE|       \
1028                                                                         MFI_INIT_ABORT
1029
1030 /*
1031  * MFI frame flags
1032  */
1033 #define MFI_FRAME_POST_IN_REPLY_QUEUE                   0x0000
1034 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE              0x0001
1035 #define MFI_FRAME_SGL32                                                 0x0000
1036 #define MFI_FRAME_SGL64                                                 0x0002
1037 #define MFI_FRAME_SENSE32                                               0x0000
1038 #define MFI_FRAME_SENSE64                                               0x0004
1039 #define MFI_FRAME_DIR_NONE                                              0x0000
1040 #define MFI_FRAME_DIR_WRITE                                             0x0008
1041 #define MFI_FRAME_DIR_READ                                              0x0010
1042 #define MFI_FRAME_DIR_BOTH                                              0x0018
1043 #define MFI_FRAME_IEEE                                                  0x0020
1044
1045 /*
1046  * Definition for cmd_status
1047  */
1048 #define MFI_CMD_STATUS_POLL_MODE                                0xFF
1049
1050 /*
1051  * MFI command opcodes
1052  */
1053 #define MFI_CMD_INIT                                                    0x00
1054 #define MFI_CMD_LD_READ                                                 0x01
1055 #define MFI_CMD_LD_WRITE                                                0x02
1056 #define MFI_CMD_LD_SCSI_IO                                              0x03
1057 #define MFI_CMD_PD_SCSI_IO                                              0x04
1058 #define MFI_CMD_DCMD                                                    0x05
1059 #define MFI_CMD_ABORT                                                   0x06
1060 #define MFI_CMD_SMP                                                             0x07
1061 #define MFI_CMD_STP                                                             0x08
1062 #define MFI_CMD_INVALID                                                 0xff
1063
1064 #define MR_DCMD_CTRL_GET_INFO                                   0x01010000
1065 #define MR_DCMD_LD_GET_LIST                                             0x03010000
1066 #define MR_DCMD_CTRL_CACHE_FLUSH                                0x01101000
1067 #define MR_FLUSH_CTRL_CACHE                                             0x01
1068 #define MR_FLUSH_DISK_CACHE                                             0x02
1069
1070 #define MR_DCMD_CTRL_SHUTDOWN                                   0x01050000
1071 #define MR_DCMD_HIBERNATE_SHUTDOWN                              0x01060000
1072 #define MR_ENABLE_DRIVE_SPINDOWN                                0x01
1073
1074 #define MR_DCMD_CTRL_EVENT_GET_INFO                             0x01040100
1075 #define MR_DCMD_CTRL_EVENT_GET                                  0x01040300
1076 #define MR_DCMD_CTRL_EVENT_WAIT                                 0x01040500
1077 #define MR_DCMD_LD_GET_PROPERTIES                               0x03030000
1078
1079 #define MR_DCMD_CLUSTER                                                 0x08000000
1080 #define MR_DCMD_CLUSTER_RESET_ALL                               0x08010100
1081 #define MR_DCMD_CLUSTER_RESET_LD                                0x08010200
1082 #define MR_DCMD_PD_LIST_QUERY                                   0x02010100
1083
1084 #define MR_DCMD_CTRL_MISC_CPX                                   0x0100e200
1085 #define MR_DCMD_CTRL_MISC_CPX_INIT_DATA_GET             0x0100e201
1086 #define MR_DCMD_CTRL_MISC_CPX_QUEUE_DATA                0x0100e202
1087 #define MR_DCMD_CTRL_MISC_CPX_UNREGISTER                0x0100e203
1088 #define MAX_MR_ROW_SIZE                                                 32
1089 #define MR_CPX_DIR_WRITE                                                1
1090 #define MR_CPX_DIR_READ                                                 0
1091 #define MR_CPX_VERSION                                                  1
1092
1093 #define MR_DCMD_CTRL_IO_METRICS_GET                             0x01170200
1094
1095 #define MR_EVT_CFG_CLEARED                                              0x0004
1096
1097 #define MR_EVT_LD_STATE_CHANGE                                  0x0051
1098 #define MR_EVT_PD_INSERTED                                              0x005b
1099 #define MR_EVT_PD_REMOVED                                               0x0070
1100 #define MR_EVT_LD_CREATED                                               0x008a
1101 #define MR_EVT_LD_DELETED                                               0x008b
1102 #define MR_EVT_FOREIGN_CFG_IMPORTED                             0x00db
1103 #define MR_EVT_LD_OFFLINE                                               0x00fc
1104 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED             0x0152
1105 #define MR_EVT_CTRL_PERF_COLLECTION                             0x017e
1106
1107 /*
1108  * MFI command completion codes
1109  */
1110 enum MFI_STAT {
1111         MFI_STAT_OK = 0x00,
1112         MFI_STAT_INVALID_CMD = 0x01,
1113         MFI_STAT_INVALID_DCMD = 0x02,
1114         MFI_STAT_INVALID_PARAMETER = 0x03,
1115         MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04,
1116         MFI_STAT_ABORT_NOT_POSSIBLE = 0x05,
1117         MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06,
1118         MFI_STAT_APP_IN_USE = 0x07,
1119         MFI_STAT_APP_NOT_INITIALIZED = 0x08,
1120         MFI_STAT_ARRAY_INDEX_INVALID = 0x09,
1121         MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a,
1122         MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b,
1123         MFI_STAT_DEVICE_NOT_FOUND = 0x0c,
1124         MFI_STAT_DRIVE_TOO_SMALL = 0x0d,
1125         MFI_STAT_FLASH_ALLOC_FAIL = 0x0e,
1126         MFI_STAT_FLASH_BUSY = 0x0f,
1127         MFI_STAT_FLASH_ERROR = 0x10,
1128         MFI_STAT_FLASH_IMAGE_BAD = 0x11,
1129         MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12,
1130         MFI_STAT_FLASH_NOT_OPEN = 0x13,
1131         MFI_STAT_FLASH_NOT_STARTED = 0x14,
1132         MFI_STAT_FLUSH_FAILED = 0x15,
1133         MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16,
1134         MFI_STAT_LD_CC_IN_PROGRESS = 0x17,
1135         MFI_STAT_LD_INIT_IN_PROGRESS = 0x18,
1136         MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19,
1137         MFI_STAT_LD_MAX_CONFIGURED = 0x1a,
1138         MFI_STAT_LD_NOT_OPTIMAL = 0x1b,
1139         MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c,
1140         MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d,
1141         MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e,
1142         MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f,
1143         MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
1144         MFI_STAT_MFC_HW_ERROR = 0x21,
1145         MFI_STAT_NO_HW_PRESENT = 0x22,
1146         MFI_STAT_NOT_FOUND = 0x23,
1147         MFI_STAT_NOT_IN_ENCL = 0x24,
1148         MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25,
1149         MFI_STAT_PD_TYPE_WRONG = 0x26,
1150         MFI_STAT_PR_DISABLED = 0x27,
1151         MFI_STAT_ROW_INDEX_INVALID = 0x28,
1152         MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29,
1153         MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a,
1154         MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b,
1155         MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c,
1156         MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d,
1157         MFI_STAT_SCSI_IO_FAILED = 0x2e,
1158         MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f,
1159         MFI_STAT_SHUTDOWN_FAILED = 0x30,
1160         MFI_STAT_TIME_NOT_SET = 0x31,
1161         MFI_STAT_WRONG_STATE = 0x32,
1162         MFI_STAT_LD_OFFLINE = 0x33,
1163         MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34,
1164         MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35,
1165         MFI_STAT_RESERVATION_IN_PROGRESS = 0x36,
1166         MFI_STAT_I2C_ERRORS_DETECTED = 0x37,
1167         MFI_STAT_PCI_ERRORS_DETECTED = 0x38,
1168         MFI_STAT_CONFIG_SEQ_MISMATCH = 0x67,
1169
1170         MFI_STAT_INVALID_STATUS = 0xFF
1171 };
1172
1173 /*
1174  * Number of mailbox bytes in DCMD message frame
1175  */
1176 #define MFI_MBOX_SIZE   12
1177
1178 enum MR_EVT_CLASS {
1179
1180         MR_EVT_CLASS_DEBUG = -2,
1181         MR_EVT_CLASS_PROGRESS = -1,
1182         MR_EVT_CLASS_INFO = 0,
1183         MR_EVT_CLASS_WARNING = 1,
1184         MR_EVT_CLASS_CRITICAL = 2,
1185         MR_EVT_CLASS_FATAL = 3,
1186         MR_EVT_CLASS_DEAD = 4,
1187
1188 };
1189
1190 enum MR_EVT_LOCALE {
1191
1192         MR_EVT_LOCALE_LD = 0x0001,
1193         MR_EVT_LOCALE_PD = 0x0002,
1194         MR_EVT_LOCALE_ENCL = 0x0004,
1195         MR_EVT_LOCALE_BBU = 0x0008,
1196         MR_EVT_LOCALE_SAS = 0x0010,
1197         MR_EVT_LOCALE_CTRL = 0x0020,
1198         MR_EVT_LOCALE_CONFIG = 0x0040,
1199         MR_EVT_LOCALE_CLUSTER = 0x0080,
1200         MR_EVT_LOCALE_ALL = 0xffff,
1201
1202 };
1203
1204 enum MR_EVT_ARGS {
1205
1206         MR_EVT_ARGS_NONE,
1207         MR_EVT_ARGS_CDB_SENSE,
1208         MR_EVT_ARGS_LD,
1209         MR_EVT_ARGS_LD_COUNT,
1210         MR_EVT_ARGS_LD_LBA,
1211         MR_EVT_ARGS_LD_OWNER,
1212         MR_EVT_ARGS_LD_LBA_PD_LBA,
1213         MR_EVT_ARGS_LD_PROG,
1214         MR_EVT_ARGS_LD_STATE,
1215         MR_EVT_ARGS_LD_STRIP,
1216         MR_EVT_ARGS_PD,
1217         MR_EVT_ARGS_PD_ERR,
1218         MR_EVT_ARGS_PD_LBA,
1219         MR_EVT_ARGS_PD_LBA_LD,
1220         MR_EVT_ARGS_PD_PROG,
1221         MR_EVT_ARGS_PD_STATE,
1222         MR_EVT_ARGS_PCI,
1223         MR_EVT_ARGS_RATE,
1224         MR_EVT_ARGS_STR,
1225         MR_EVT_ARGS_TIME,
1226         MR_EVT_ARGS_ECC,
1227         MR_EVT_ARGS_LD_PROP,
1228         MR_EVT_ARGS_PD_SPARE,
1229         MR_EVT_ARGS_PD_INDEX,
1230         MR_EVT_ARGS_DIAG_PASS,
1231         MR_EVT_ARGS_DIAG_FAIL,
1232         MR_EVT_ARGS_PD_LBA_LBA,
1233         MR_EVT_ARGS_PORT_PHY,
1234         MR_EVT_ARGS_PD_MISSING,
1235         MR_EVT_ARGS_PD_ADDRESS,
1236         MR_EVT_ARGS_BITMAP,
1237         MR_EVT_ARGS_CONNECTOR,
1238         MR_EVT_ARGS_PD_PD,
1239         MR_EVT_ARGS_PD_FRU,
1240         MR_EVT_ARGS_PD_PATHINFO,
1241         MR_EVT_ARGS_PD_POWER_STATE,
1242         MR_EVT_ARGS_GENERIC,
1243 };
1244
1245
1246 /*
1247  * Thunderbolt (and later) Defines
1248  */
1249 #define MEGASAS_CHAIN_FRAME_SZ_MIN                                      1024
1250 #define MFI_FUSION_ENABLE_INTERRUPT_MASK                        (0x00000009)
1251 #define MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE           256
1252 #define MRSAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST         0xF0
1253 #define MRSAS_MPI2_FUNCTION_LD_IO_REQUEST                       0xF1
1254 #define MRSAS_LOAD_BALANCE_FLAG                                         0x1
1255 #define MRSAS_DCMD_MBOX_PEND_FLAG                                       0x1
1256 #define HOST_DIAG_WRITE_ENABLE                                          0x80
1257 #define HOST_DIAG_RESET_ADAPTER                                         0x4
1258 #define MRSAS_TBOLT_MAX_RESET_TRIES                                     3
1259 #define MRSAS_MAX_MFI_CMDS                                                      32
1260
1261 /*
1262  * Invader Defines
1263  */
1264 #define MPI2_TYPE_CUDA                                                          0x2
1265 #define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH       0x4000
1266 #define MR_RL_FLAGS_GRANT_DESTINATION_CPU0                      0x00
1267 #define MR_RL_FLAGS_GRANT_DESTINATION_CPU1                      0x10
1268 #define MR_RL_FLAGS_GRANT_DESTINATION_CUDA                      0x80
1269 #define MR_RL_FLAGS_SEQ_NUM_ENABLE                                      0x8
1270
1271 /*
1272  * T10 PI defines
1273  */
1274 #define MR_PROT_INFO_TYPE_CONTROLLER                            0x8
1275 #define MRSAS_SCSI_VARIABLE_LENGTH_CMD                          0x7f
1276 #define MRSAS_SCSI_SERVICE_ACTION_READ32                        0x9
1277 #define MRSAS_SCSI_SERVICE_ACTION_WRITE32                       0xB
1278 #define MRSAS_SCSI_ADDL_CDB_LEN                                         0x18
1279 #define MRSAS_RD_WR_PROTECT_CHECK_ALL                           0x20
1280 #define MRSAS_RD_WR_PROTECT_CHECK_NONE                          0x60
1281 #define MRSAS_SCSIBLOCKSIZE                                                     512
1282
1283 /*
1284  * Raid context flags
1285  */
1286 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_SHIFT        0x4
1287 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_MASK         0x30
1288 typedef enum MR_RAID_FLAGS_IO_SUB_TYPE {
1289         MR_RAID_FLAGS_IO_SUB_TYPE_NONE = 0,
1290         MR_RAID_FLAGS_IO_SUB_TYPE_SYSTEM_PD = 1,
1291 }       MR_RAID_FLAGS_IO_SUB_TYPE;
1292
1293 /*
1294  * Request descriptor types
1295  */
1296 #define MRSAS_REQ_DESCRIPT_FLAGS_LD_IO          0x7
1297 #define MRSAS_REQ_DESCRIPT_FLAGS_MFA            0x1
1298 #define MRSAS_REQ_DESCRIPT_FLAGS_NO_LOCK        0x2
1299 #define MRSAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT     1
1300 #define MRSAS_FP_CMD_LEN                                        16
1301 #define MRSAS_FUSION_IN_RESET                           0
1302
1303 #define RAID_CTX_SPANARM_ARM_SHIFT                      (0)
1304 #define RAID_CTX_SPANARM_ARM_MASK                       (0x1f)
1305 #define RAID_CTX_SPANARM_SPAN_SHIFT                     (5)
1306 #define RAID_CTX_SPANARM_SPAN_MASK                      (0xE0)
1307
1308 /*
1309  * Define region lock types
1310  */
1311 typedef enum _REGION_TYPE {
1312         REGION_TYPE_UNUSED = 0,
1313         REGION_TYPE_SHARED_READ = 1,
1314         REGION_TYPE_SHARED_WRITE = 2,
1315         REGION_TYPE_EXCLUSIVE = 3,
1316 }       REGION_TYPE;
1317
1318
1319 /*
1320  * SCSI-CAM Related Defines
1321  */
1322 #define MRSAS_SCSI_MAX_LUNS                             0
1323 #define MRSAS_SCSI_INITIATOR_ID                 255
1324 #define MRSAS_SCSI_MAX_CMDS                             8
1325 #define MRSAS_SCSI_MAX_CDB_LEN                  16
1326 #define MRSAS_SCSI_SENSE_BUFFERSIZE             96
1327 #define MRSAS_INTERNAL_CMDS                             32
1328
1329 #define MEGASAS_MAX_CHAIN_SIZE_UNITS_MASK       0x400000
1330 #define MEGASAS_MAX_CHAIN_SIZE_MASK             0x3E0
1331 #define MEGASAS_256K_IO                                 128
1332 #define MEGASAS_1MB_IO                                  (MEGASAS_256K_IO * 4)
1333
1334 /* Request types */
1335 #define MRSAS_REQ_TYPE_INTERNAL_CMD             0x0
1336 #define MRSAS_REQ_TYPE_AEN_FETCH                0x1
1337 #define MRSAS_REQ_TYPE_PASSTHRU                 0x2
1338 #define MRSAS_REQ_TYPE_GETSET_PARAM             0x3
1339 #define MRSAS_REQ_TYPE_SCSI_IO                  0x4
1340
1341 /* Request states */
1342 #define MRSAS_REQ_STATE_FREE                    0
1343 #define MRSAS_REQ_STATE_BUSY                    1
1344 #define MRSAS_REQ_STATE_TRAN                    2
1345 #define MRSAS_REQ_STATE_COMPLETE                3
1346
1347 typedef enum _MR_SCSI_CMD_TYPE {
1348         READ_WRITE_LDIO = 0,
1349         NON_READ_WRITE_LDIO = 1,
1350         READ_WRITE_SYSPDIO = 2,
1351         NON_READ_WRITE_SYSPDIO = 3,
1352 }       MR_SCSI_CMD_TYPE;
1353
1354 enum mrsas_req_flags {
1355         MRSAS_DIR_UNKNOWN = 0x1,
1356         MRSAS_DIR_IN = 0x2,
1357         MRSAS_DIR_OUT = 0x4,
1358         MRSAS_DIR_NONE = 0x8,
1359 };
1360
1361 /*
1362  * Adapter Reset States
1363  */
1364 enum {
1365         MRSAS_HBA_OPERATIONAL = 0,
1366         MRSAS_ADPRESET_SM_INFAULT = 1,
1367         MRSAS_ADPRESET_SM_FW_RESET_SUCCESS = 2,
1368         MRSAS_ADPRESET_SM_OPERATIONAL = 3,
1369         MRSAS_HW_CRITICAL_ERROR = 4,
1370         MRSAS_ADPRESET_INPROG_SIGN = 0xDEADDEAD,
1371 };
1372
1373 /*
1374  * MPT Command Structure
1375  */
1376 struct mrsas_mpt_cmd {
1377         MRSAS_RAID_SCSI_IO_REQUEST *io_request;
1378         bus_addr_t io_request_phys_addr;
1379         MPI2_SGE_IO_UNION *chain_frame;
1380         bus_addr_t chain_frame_phys_addr;
1381         u_int32_t sge_count;
1382         u_int8_t *sense;
1383         bus_addr_t sense_phys_addr;
1384         u_int8_t retry_for_fw_reset;
1385         MRSAS_REQUEST_DESCRIPTOR_UNION *request_desc;
1386         u_int32_t sync_cmd_idx;
1387         u_int32_t index;
1388         u_int8_t flags;
1389         u_int8_t pd_r1_lb;
1390         u_int8_t load_balance;
1391         bus_size_t length;
1392         u_int32_t error_code;
1393         bus_dmamap_t data_dmamap;
1394         void   *data;
1395         union ccb *ccb_ptr;
1396         struct callout cm_callout;
1397         struct mrsas_softc *sc;
1398         TAILQ_ENTRY(mrsas_mpt_cmd) next;
1399 };
1400
1401 /*
1402  * MFI Command Structure
1403  */
1404 struct mrsas_mfi_cmd {
1405         union mrsas_frame *frame;
1406         bus_dmamap_t frame_dmamap;
1407         void   *frame_mem;
1408         bus_addr_t frame_phys_addr;
1409         u_int8_t *sense;
1410         bus_dmamap_t sense_dmamap;
1411         void   *sense_mem;
1412         bus_addr_t sense_phys_addr;
1413         u_int32_t index;
1414         u_int8_t sync_cmd;
1415         u_int8_t cmd_status;
1416         u_int8_t abort_aen;
1417         u_int8_t retry_for_fw_reset;
1418         struct mrsas_softc *sc;
1419         union ccb *ccb_ptr;
1420         union {
1421                 struct {
1422                         u_int16_t smid;
1423                         u_int16_t resvd;
1424                 }       context;
1425                 u_int32_t frame_count;
1426         }       cmd_id;
1427         TAILQ_ENTRY(mrsas_mfi_cmd) next;
1428 };
1429
1430
1431 /*
1432  * define constants for device list query options
1433  */
1434 enum MR_PD_QUERY_TYPE {
1435         MR_PD_QUERY_TYPE_ALL = 0,
1436         MR_PD_QUERY_TYPE_STATE = 1,
1437         MR_PD_QUERY_TYPE_POWER_STATE = 2,
1438         MR_PD_QUERY_TYPE_MEDIA_TYPE = 3,
1439         MR_PD_QUERY_TYPE_SPEED = 4,
1440         MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5,
1441 };
1442
1443 #define MR_EVT_CFG_CLEARED                                              0x0004
1444 #define MR_EVT_LD_STATE_CHANGE                                  0x0051
1445 #define MR_EVT_PD_INSERTED                                              0x005b
1446 #define MR_EVT_PD_REMOVED                                               0x0070
1447 #define MR_EVT_LD_CREATED                                               0x008a
1448 #define MR_EVT_LD_DELETED                                               0x008b
1449 #define MR_EVT_FOREIGN_CFG_IMPORTED                             0x00db
1450 #define MR_EVT_LD_OFFLINE                                               0x00fc
1451 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED             0x0152
1452
1453 enum MR_PD_STATE {
1454         MR_PD_STATE_UNCONFIGURED_GOOD = 0x00,
1455         MR_PD_STATE_UNCONFIGURED_BAD = 0x01,
1456         MR_PD_STATE_HOT_SPARE = 0x02,
1457         MR_PD_STATE_OFFLINE = 0x10,
1458         MR_PD_STATE_FAILED = 0x11,
1459         MR_PD_STATE_REBUILD = 0x14,
1460         MR_PD_STATE_ONLINE = 0x18,
1461         MR_PD_STATE_COPYBACK = 0x20,
1462         MR_PD_STATE_SYSTEM = 0x40,
1463 };
1464
1465 /*
1466  * defines the physical drive address structure
1467  */
1468 #pragma pack(1)
1469 struct MR_PD_ADDRESS {
1470         u_int16_t deviceId;
1471         u_int16_t enclDeviceId;
1472
1473         union {
1474                 struct {
1475                         u_int8_t enclIndex;
1476                         u_int8_t slotNumber;
1477                 }       mrPdAddress;
1478                 struct {
1479                         u_int8_t enclPosition;
1480                         u_int8_t enclConnectorIndex;
1481                 }       mrEnclAddress;
1482         }       u1;
1483         u_int8_t scsiDevType;
1484         union {
1485                 u_int8_t connectedPortBitmap;
1486                 u_int8_t connectedPortNumbers;
1487         }       u2;
1488         u_int64_t sasAddr[2];
1489 };
1490
1491 #pragma pack()
1492
1493 /*
1494  * defines the physical drive list structure
1495  */
1496 #pragma pack(1)
1497 struct MR_PD_LIST {
1498         u_int32_t size;
1499         u_int32_t count;
1500         struct MR_PD_ADDRESS addr[1];
1501 };
1502
1503 #pragma pack()
1504
1505 #pragma pack(1)
1506 struct mrsas_pd_list {
1507         u_int16_t tid;
1508         u_int8_t driveType;
1509         u_int8_t driveState;
1510 };
1511
1512 #pragma pack()
1513
1514 /*
1515  * defines the logical drive reference structure
1516  */
1517 typedef union _MR_LD_REF {
1518         struct {
1519                 u_int8_t targetId;
1520                 u_int8_t reserved;
1521                 u_int16_t seqNum;
1522         }       ld_context;
1523         u_int32_t ref;
1524 }       MR_LD_REF;
1525
1526
1527 /*
1528  * defines the logical drive list structure
1529  */
1530 #pragma pack(1)
1531 struct MR_LD_LIST {
1532         u_int32_t ldCount;
1533         u_int32_t reserved;
1534         struct {
1535                 MR_LD_REF ref;
1536                 u_int8_t state;
1537                 u_int8_t reserved[3];
1538                 u_int64_t size;
1539         }       ldList[MAX_LOGICAL_DRIVES_EXT];
1540 };
1541
1542 #pragma pack()
1543
1544 /*
1545  * SAS controller properties
1546  */
1547 #pragma pack(1)
1548 struct mrsas_ctrl_prop {
1549         u_int16_t seq_num;
1550         u_int16_t pred_fail_poll_interval;
1551         u_int16_t intr_throttle_count;
1552         u_int16_t intr_throttle_timeouts;
1553         u_int8_t rebuild_rate;
1554         u_int8_t patrol_read_rate;
1555         u_int8_t bgi_rate;
1556         u_int8_t cc_rate;
1557         u_int8_t recon_rate;
1558         u_int8_t cache_flush_interval;
1559         u_int8_t spinup_drv_count;
1560         u_int8_t spinup_delay;
1561         u_int8_t cluster_enable;
1562         u_int8_t coercion_mode;
1563         u_int8_t alarm_enable;
1564         u_int8_t disable_auto_rebuild;
1565         u_int8_t disable_battery_warn;
1566         u_int8_t ecc_bucket_size;
1567         u_int16_t ecc_bucket_leak_rate;
1568         u_int8_t restore_hotspare_on_insertion;
1569         u_int8_t expose_encl_devices;
1570         u_int8_t maintainPdFailHistory;
1571         u_int8_t disallowHostRequestReordering;
1572         u_int8_t abortCCOnError;
1573         u_int8_t loadBalanceMode;
1574         u_int8_t disableAutoDetectBackplane;
1575         u_int8_t snapVDSpace;
1576         /*
1577          * Add properties that can be controlled by a bit in the following
1578          * structure.
1579          */
1580         struct {
1581                 u_int32_t copyBackDisabled:1;
1582                 u_int32_t SMARTerEnabled:1;
1583                 u_int32_t prCorrectUnconfiguredAreas:1;
1584                 u_int32_t useFdeOnly:1;
1585                 u_int32_t disableNCQ:1;
1586                 u_int32_t SSDSMARTerEnabled:1;
1587                 u_int32_t SSDPatrolReadEnabled:1;
1588                 u_int32_t enableSpinDownUnconfigured:1;
1589                 u_int32_t autoEnhancedImport:1;
1590                 u_int32_t enableSecretKeyControl:1;
1591                 u_int32_t disableOnlineCtrlReset:1;
1592                 u_int32_t allowBootWithPinnedCache:1;
1593                 u_int32_t disableSpinDownHS:1;
1594                 u_int32_t enableJBOD:1;
1595                 u_int32_t disableCacheBypass:1;
1596                 u_int32_t useDiskActivityForLocate:1;
1597                 u_int32_t enablePI:1;
1598                 u_int32_t preventPIImport:1;
1599                 u_int32_t useGlobalSparesForEmergency:1;
1600                 u_int32_t useUnconfGoodForEmergency:1;
1601                 u_int32_t useEmergencySparesforSMARTer:1;
1602                 u_int32_t forceSGPIOForQuadOnly:1;
1603                 u_int32_t enableConfigAutoBalance:1;
1604                 u_int32_t enableVirtualCache:1;
1605                 u_int32_t enableAutoLockRecovery:1;
1606                 u_int32_t disableImmediateIO:1;
1607                 u_int32_t disableT10RebuildAssist:1;
1608                 u_int32_t ignore64ldRestriction:1;
1609                 u_int32_t enableSwZone:1;
1610                 u_int32_t limitMaxRateSATA3G:1;
1611                 u_int32_t reserved:2;
1612         }       OnOffProperties;
1613         u_int8_t autoSnapVDSpace;
1614         u_int8_t viewSpace;
1615         u_int16_t spinDownTime;
1616         u_int8_t reserved[24];
1617
1618 };
1619
1620 #pragma pack()
1621
1622
1623 /*
1624  * SAS controller information
1625  */
1626 struct mrsas_ctrl_info {
1627         /*
1628          * PCI device information
1629          */
1630         struct {
1631                 u_int16_t vendor_id;
1632                 u_int16_t device_id;
1633                 u_int16_t sub_vendor_id;
1634                 u_int16_t sub_device_id;
1635                 u_int8_t reserved[24];
1636         } __packed pci;
1637         /*
1638          * Host interface information
1639          */
1640         struct {
1641                 u_int8_t PCIX:1;
1642                 u_int8_t PCIE:1;
1643                 u_int8_t iSCSI:1;
1644                 u_int8_t SAS_3G:1;
1645                 u_int8_t reserved_0:4;
1646                 u_int8_t reserved_1[6];
1647                 u_int8_t port_count;
1648                 u_int64_t port_addr[8];
1649         } __packed host_interface;
1650         /*
1651          * Device (backend) interface information
1652          */
1653         struct {
1654                 u_int8_t SPI:1;
1655                 u_int8_t SAS_3G:1;
1656                 u_int8_t SATA_1_5G:1;
1657                 u_int8_t SATA_3G:1;
1658                 u_int8_t reserved_0:4;
1659                 u_int8_t reserved_1[6];
1660                 u_int8_t port_count;
1661                 u_int64_t port_addr[8];
1662         } __packed device_interface;
1663
1664         u_int32_t image_check_word;
1665         u_int32_t image_component_count;
1666
1667         struct {
1668                 char    name[8];
1669                 char    version[32];
1670                 char    build_date[16];
1671                 char    built_time[16];
1672         } __packed image_component[8];
1673
1674         u_int32_t pending_image_component_count;
1675
1676         struct {
1677                 char    name[8];
1678                 char    version[32];
1679                 char    build_date[16];
1680                 char    build_time[16];
1681         } __packed pending_image_component[8];
1682
1683         u_int8_t max_arms;
1684         u_int8_t max_spans;
1685         u_int8_t max_arrays;
1686         u_int8_t max_lds;
1687         char    product_name[80];
1688         char    serial_no[32];
1689
1690         /*
1691          * Other physical/controller/operation information. Indicates the
1692          * presence of the hardware
1693          */
1694         struct {
1695                 u_int32_t bbu:1;
1696                 u_int32_t alarm:1;
1697                 u_int32_t nvram:1;
1698                 u_int32_t uart:1;
1699                 u_int32_t reserved:28;
1700         } __packed hw_present;
1701
1702         u_int32_t current_fw_time;
1703
1704         /*
1705          * Maximum data transfer sizes
1706          */
1707         u_int16_t max_concurrent_cmds;
1708         u_int16_t max_sge_count;
1709         u_int32_t max_request_size;
1710
1711         /*
1712          * Logical and physical device counts
1713          */
1714         u_int16_t ld_present_count;
1715         u_int16_t ld_degraded_count;
1716         u_int16_t ld_offline_count;
1717
1718         u_int16_t pd_present_count;
1719         u_int16_t pd_disk_present_count;
1720         u_int16_t pd_disk_pred_failure_count;
1721         u_int16_t pd_disk_failed_count;
1722
1723         /*
1724          * Memory size information
1725          */
1726         u_int16_t nvram_size;
1727         u_int16_t memory_size;
1728         u_int16_t flash_size;
1729
1730         /*
1731          * Error counters
1732          */
1733         u_int16_t mem_correctable_error_count;
1734         u_int16_t mem_uncorrectable_error_count;
1735
1736         /*
1737          * Cluster information
1738          */
1739         u_int8_t cluster_permitted;
1740         u_int8_t cluster_active;
1741
1742         /*
1743          * Additional max data transfer sizes
1744          */
1745         u_int16_t max_strips_per_io;
1746
1747         /*
1748          * Controller capabilities structures
1749          */
1750         struct {
1751                 u_int32_t raid_level_0:1;
1752                 u_int32_t raid_level_1:1;
1753                 u_int32_t raid_level_5:1;
1754                 u_int32_t raid_level_1E:1;
1755                 u_int32_t raid_level_6:1;
1756                 u_int32_t reserved:27;
1757         } __packed raid_levels;
1758
1759         struct {
1760                 u_int32_t rbld_rate:1;
1761                 u_int32_t cc_rate:1;
1762                 u_int32_t bgi_rate:1;
1763                 u_int32_t recon_rate:1;
1764                 u_int32_t patrol_rate:1;
1765                 u_int32_t alarm_control:1;
1766                 u_int32_t cluster_supported:1;
1767                 u_int32_t bbu:1;
1768                 u_int32_t spanning_allowed:1;
1769                 u_int32_t dedicated_hotspares:1;
1770                 u_int32_t revertible_hotspares:1;
1771                 u_int32_t foreign_config_import:1;
1772                 u_int32_t self_diagnostic:1;
1773                 u_int32_t mixed_redundancy_arr:1;
1774                 u_int32_t global_hot_spares:1;
1775                 u_int32_t reserved:17;
1776         } __packed adapter_operations;
1777
1778         struct {
1779                 u_int32_t read_policy:1;
1780                 u_int32_t write_policy:1;
1781                 u_int32_t io_policy:1;
1782                 u_int32_t access_policy:1;
1783                 u_int32_t disk_cache_policy:1;
1784                 u_int32_t reserved:27;
1785         } __packed ld_operations;
1786
1787         struct {
1788                 u_int8_t min;
1789                 u_int8_t max;
1790                 u_int8_t reserved[2];
1791         } __packed stripe_sz_ops;
1792
1793         struct {
1794                 u_int32_t force_online:1;
1795                 u_int32_t force_offline:1;
1796                 u_int32_t force_rebuild:1;
1797                 u_int32_t reserved:29;
1798         } __packed pd_operations;
1799
1800         struct {
1801                 u_int32_t ctrl_supports_sas:1;
1802                 u_int32_t ctrl_supports_sata:1;
1803                 u_int32_t allow_mix_in_encl:1;
1804                 u_int32_t allow_mix_in_ld:1;
1805                 u_int32_t allow_sata_in_cluster:1;
1806                 u_int32_t reserved:27;
1807         } __packed pd_mix_support;
1808
1809         /*
1810          * Define ECC single-bit-error bucket information
1811          */
1812         u_int8_t ecc_bucket_count;
1813         u_int8_t reserved_2[11];
1814
1815         /*
1816          * Include the controller properties (changeable items)
1817          */
1818         struct mrsas_ctrl_prop properties;
1819
1820         /*
1821          * Define FW pkg version (set in envt v'bles on OEM basis)
1822          */
1823         char    package_version[0x60];
1824
1825         u_int64_t deviceInterfacePortAddr2[8];
1826         u_int8_t reserved3[128];
1827
1828         struct {
1829                 u_int16_t minPdRaidLevel_0:4;
1830                 u_int16_t maxPdRaidLevel_0:12;
1831
1832                 u_int16_t minPdRaidLevel_1:4;
1833                 u_int16_t maxPdRaidLevel_1:12;
1834
1835                 u_int16_t minPdRaidLevel_5:4;
1836                 u_int16_t maxPdRaidLevel_5:12;
1837
1838                 u_int16_t minPdRaidLevel_1E:4;
1839                 u_int16_t maxPdRaidLevel_1E:12;
1840
1841                 u_int16_t minPdRaidLevel_6:4;
1842                 u_int16_t maxPdRaidLevel_6:12;
1843
1844                 u_int16_t minPdRaidLevel_10:4;
1845                 u_int16_t maxPdRaidLevel_10:12;
1846
1847                 u_int16_t minPdRaidLevel_50:4;
1848                 u_int16_t maxPdRaidLevel_50:12;
1849
1850                 u_int16_t minPdRaidLevel_60:4;
1851                 u_int16_t maxPdRaidLevel_60:12;
1852
1853                 u_int16_t minPdRaidLevel_1E_RLQ0:4;
1854                 u_int16_t maxPdRaidLevel_1E_RLQ0:12;
1855
1856                 u_int16_t minPdRaidLevel_1E0_RLQ0:4;
1857                 u_int16_t maxPdRaidLevel_1E0_RLQ0:12;
1858
1859                 u_int16_t reserved[6];
1860         }       pdsForRaidLevels;
1861
1862         u_int16_t maxPds;               /* 0x780 */
1863         u_int16_t maxDedHSPs;           /* 0x782 */
1864         u_int16_t maxGlobalHSPs;        /* 0x784 */
1865         u_int16_t ddfSize;              /* 0x786 */
1866         u_int8_t maxLdsPerArray;        /* 0x788 */
1867         u_int8_t partitionsInDDF;       /* 0x789 */
1868         u_int8_t lockKeyBinding;        /* 0x78a */
1869         u_int8_t maxPITsPerLd;          /* 0x78b */
1870         u_int8_t maxViewsPerLd;         /* 0x78c */
1871         u_int8_t maxTargetId;           /* 0x78d */
1872         u_int16_t maxBvlVdSize;         /* 0x78e */
1873
1874         u_int16_t maxConfigurableSSCSize;       /* 0x790 */
1875         u_int16_t currentSSCsize;       /* 0x792 */
1876
1877         char    expanderFwVersion[12];  /* 0x794 */
1878
1879         u_int16_t PFKTrialTimeRemaining;/* 0x7A0 */
1880
1881         u_int16_t cacheMemorySize;      /* 0x7A2 */
1882
1883         struct {                        /* 0x7A4 */
1884                 u_int32_t supportPIcontroller:1;
1885                 u_int32_t supportLdPIType1:1;
1886                 u_int32_t supportLdPIType2:1;
1887                 u_int32_t supportLdPIType3:1;
1888                 u_int32_t supportLdBBMInfo:1;
1889                 u_int32_t supportShieldState:1;
1890                 u_int32_t blockSSDWriteCacheChange:1;
1891                 u_int32_t supportSuspendResumeBGops:1;
1892                 u_int32_t supportEmergencySpares:1;
1893                 u_int32_t supportSetLinkSpeed:1;
1894                 u_int32_t supportBootTimePFKChange:1;
1895                 u_int32_t supportJBOD:1;
1896                 u_int32_t disableOnlinePFKChange:1;
1897                 u_int32_t supportPerfTuning:1;
1898                 u_int32_t supportSSDPatrolRead:1;
1899                 u_int32_t realTimeScheduler:1;
1900
1901                 u_int32_t supportResetNow:1;
1902                 u_int32_t supportEmulatedDrives:1;
1903                 u_int32_t headlessMode:1;
1904                 u_int32_t dedicatedHotSparesLimited:1;
1905
1906
1907                 u_int32_t supportUnevenSpans:1;
1908                 u_int32_t reserved:11;
1909         }       adapterOperations2;
1910
1911         u_int8_t driverVersion[32];     /* 0x7A8 */
1912         u_int8_t maxDAPdCountSpinup60;  /* 0x7C8 */
1913         u_int8_t temperatureROC;        /* 0x7C9 */
1914         u_int8_t temperatureCtrl;       /* 0x7CA */
1915         u_int8_t reserved4;             /* 0x7CB */
1916         u_int16_t maxConfigurablePds;   /* 0x7CC */
1917
1918
1919         u_int8_t reserved5[2];          /* 0x7CD reserved */
1920
1921         struct {
1922                 u_int32_t peerIsPresent:1;
1923                 u_int32_t peerIsIncompatible:1;
1924
1925                 u_int32_t hwIncompatible:1;
1926                 u_int32_t fwVersionMismatch:1;
1927                 u_int32_t ctrlPropIncompatible:1;
1928                 u_int32_t premiumFeatureMismatch:1;
1929                 u_int32_t reserved:26;
1930         }       cluster;
1931
1932         char    clusterId[16];          /* 0x7D4 */
1933
1934         char    reserved6[4];           /* 0x7E4 RESERVED FOR IOV */
1935
1936         struct {                        /* 0x7E8 */
1937                 u_int32_t supportPersonalityChange:2;
1938                 u_int32_t supportThermalPollInterval:1;
1939                 u_int32_t supportDisableImmediateIO:1;
1940                 u_int32_t supportT10RebuildAssist:1;
1941                 u_int32_t supportMaxExtLDs:1;
1942                 u_int32_t supportCrashDump:1;
1943                 u_int32_t supportSwZone:1;
1944                 u_int32_t supportDebugQueue:1;
1945                 u_int32_t supportNVCacheErase:1;
1946                 u_int32_t supportForceTo512e:1;
1947                 u_int32_t supportHOQRebuild:1;
1948                 u_int32_t supportAllowedOpsforDrvRemoval:1;
1949                 u_int32_t supportDrvActivityLEDSetting:1;
1950                 u_int32_t supportNVDRAM:1;
1951                 u_int32_t supportForceFlash:1;
1952                 u_int32_t supportDisableSESMonitoring:1;
1953                 u_int32_t supportCacheBypassModes:1;
1954                 u_int32_t supportSecurityonJBOD:1;
1955                 u_int32_t discardCacheDuringLDDelete:1;
1956                 u_int32_t supportTTYLogCompression:1;
1957                 u_int32_t supportCPLDUpdate:1;
1958                 u_int32_t supportDiskCacheSettingForSysPDs:1;
1959                 u_int32_t supportExtendedSSCSize:1;
1960                 u_int32_t useSeqNumJbodFP:1;
1961                 u_int32_t reserved:7;
1962         }       adapterOperations3;
1963
1964         u_int8_t pad[0x800 - 0x7EC];    /* 0x7EC */
1965 } __packed;
1966
1967 /*
1968  * When SCSI mid-layer calls driver's reset routine, driver waits for
1969  * MRSAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note
1970  * that the driver cannot _actually_ abort or reset pending commands. While
1971  * it is waiting for the commands to complete, it prints a diagnostic message
1972  * every MRSAS_RESET_NOTICE_INTERVAL seconds
1973  */
1974 #define MRSAS_RESET_WAIT_TIME                   180
1975 #define MRSAS_INTERNAL_CMD_WAIT_TIME    180
1976 #define MRSAS_IOC_INIT_WAIT_TIME                60
1977 #define MRSAS_RESET_NOTICE_INTERVAL             5
1978 #define MRSAS_IOCTL_CMD                                 0
1979 #define MRSAS_DEFAULT_CMD_TIMEOUT               90
1980 #define MRSAS_THROTTLE_QUEUE_DEPTH              16
1981
1982 /*
1983  * MSI-x regsiters offset defines
1984  */
1985 #define MPI2_SUP_REPLY_POST_HOST_INDEX_OFFSET   (0x0000030C)
1986 #define MPI2_REPLY_POST_HOST_INDEX_OFFSET               (0x0000006C)
1987 #define MR_MAX_REPLY_QUEUES_OFFSET                              (0x0000001F)
1988 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET                  (0x003FC000)
1989 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET_SHIFT    14
1990 #define MR_MAX_MSIX_REG_ARRAY                                   16
1991
1992 /*
1993  * FW reports the maximum of number of commands that it can accept (maximum
1994  * commands that can be outstanding) at any time. The driver must report a
1995  * lower number to the mid layer because it can issue a few internal commands
1996  * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs
1997  * is shown below
1998  */
1999 #define MRSAS_INT_CMDS                  32
2000 #define MRSAS_SKINNY_INT_CMDS   5
2001 #define MRSAS_MAX_MSIX_QUEUES   128
2002
2003 /*
2004  * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit SGLs
2005  * based on the size of bus_addr_t
2006  */
2007 #define IS_DMA64                                                        (sizeof(bus_addr_t) == 8)
2008
2009 #define MFI_XSCALE_OMR0_CHANGE_INTERRUPT        0x00000001
2010 #define MFI_INTR_FLAG_REPLY_MESSAGE                     0x00000001
2011 #define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE     0x00000002
2012 #define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT       0x00000004
2013
2014 #define MFI_OB_INTR_STATUS_MASK                         0x00000002
2015 #define MFI_POLL_TIMEOUT_SECS                           60
2016
2017 #define MFI_REPLY_1078_MESSAGE_INTERRUPT        0x80000000
2018 #define MFI_REPLY_GEN2_MESSAGE_INTERRUPT        0x00000001
2019 #define MFI_GEN2_ENABLE_INTERRUPT_MASK          0x00000001
2020 #define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT      0x40000000
2021 #define MFI_SKINNY_ENABLE_INTERRUPT_MASK        (0x00000001)
2022 #define MFI_1068_PCSR_OFFSET                            0x84
2023 #define MFI_1068_FW_HANDSHAKE_OFFSET            0x64
2024 #define MFI_1068_FW_READY                                       0xDDDD0000
2025
2026 typedef union _MFI_CAPABILITIES {
2027         struct {
2028                 u_int32_t support_fp_remote_lun:1;
2029                 u_int32_t support_additional_msix:1;
2030                 u_int32_t support_fastpath_wb:1;
2031                 u_int32_t support_max_255lds:1;
2032                 u_int32_t support_ndrive_r1_lb:1;
2033                 u_int32_t support_core_affinity:1;
2034                 u_int32_t security_protocol_cmds_fw:1;
2035                 u_int32_t support_ext_queue_depth:1;
2036                 u_int32_t support_ext_io_size:1;
2037                 u_int32_t reserved:23;
2038         }       mfi_capabilities;
2039         u_int32_t reg;
2040 }       MFI_CAPABILITIES;
2041
2042 #pragma pack(1)
2043 struct mrsas_sge32 {
2044         u_int32_t phys_addr;
2045         u_int32_t length;
2046 };
2047
2048 #pragma pack()
2049
2050 #pragma pack(1)
2051 struct mrsas_sge64 {
2052         u_int64_t phys_addr;
2053         u_int32_t length;
2054 };
2055
2056 #pragma pack()
2057
2058 #pragma pack()
2059 union mrsas_sgl {
2060         struct mrsas_sge32 sge32[1];
2061         struct mrsas_sge64 sge64[1];
2062 };
2063
2064 #pragma pack()
2065
2066 #pragma pack(1)
2067 struct mrsas_header {
2068         u_int8_t cmd;                   /* 00e */
2069         u_int8_t sense_len;             /* 01h */
2070         u_int8_t cmd_status;            /* 02h */
2071         u_int8_t scsi_status;           /* 03h */
2072
2073         u_int8_t target_id;             /* 04h */
2074         u_int8_t lun;                   /* 05h */
2075         u_int8_t cdb_len;               /* 06h */
2076         u_int8_t sge_count;             /* 07h */
2077
2078         u_int32_t context;              /* 08h */
2079         u_int32_t pad_0;                /* 0Ch */
2080
2081         u_int16_t flags;                /* 10h */
2082         u_int16_t timeout;              /* 12h */
2083         u_int32_t data_xferlen;         /* 14h */
2084 };
2085
2086 #pragma pack()
2087
2088 #pragma pack(1)
2089 struct mrsas_init_frame {
2090         u_int8_t cmd;                   /* 00h */
2091         u_int8_t reserved_0;            /* 01h */
2092         u_int8_t cmd_status;            /* 02h */
2093
2094         u_int8_t reserved_1;            /* 03h */
2095         MFI_CAPABILITIES driver_operations;     /* 04h */
2096         u_int32_t context;              /* 08h */
2097         u_int32_t pad_0;                /* 0Ch */
2098
2099         u_int16_t flags;                /* 10h */
2100         u_int16_t reserved_3;           /* 12h */
2101         u_int32_t data_xfer_len;        /* 14h */
2102
2103         u_int32_t queue_info_new_phys_addr_lo;  /* 18h */
2104         u_int32_t queue_info_new_phys_addr_hi;  /* 1Ch */
2105         u_int32_t queue_info_old_phys_addr_lo;  /* 20h */
2106         u_int32_t queue_info_old_phys_addr_hi;  /* 24h */
2107         u_int32_t driver_ver_lo;        /* 28h */
2108         u_int32_t driver_ver_hi;        /* 2Ch */
2109         u_int32_t reserved_4[4];        /* 30h */
2110 };
2111
2112 #pragma pack()
2113
2114 #pragma pack(1)
2115 struct mrsas_io_frame {
2116         u_int8_t cmd;                   /* 00h */
2117         u_int8_t sense_len;             /* 01h */
2118         u_int8_t cmd_status;            /* 02h */
2119         u_int8_t scsi_status;           /* 03h */
2120
2121         u_int8_t target_id;             /* 04h */
2122         u_int8_t access_byte;           /* 05h */
2123         u_int8_t reserved_0;            /* 06h */
2124         u_int8_t sge_count;             /* 07h */
2125
2126         u_int32_t context;              /* 08h */
2127         u_int32_t pad_0;                /* 0Ch */
2128
2129         u_int16_t flags;                /* 10h */
2130         u_int16_t timeout;              /* 12h */
2131         u_int32_t lba_count;            /* 14h */
2132
2133         u_int32_t sense_buf_phys_addr_lo;       /* 18h */
2134         u_int32_t sense_buf_phys_addr_hi;       /* 1Ch */
2135
2136         u_int32_t start_lba_lo;         /* 20h */
2137         u_int32_t start_lba_hi;         /* 24h */
2138
2139         union mrsas_sgl sgl;            /* 28h */
2140 };
2141
2142 #pragma pack()
2143
2144 #pragma pack(1)
2145 struct mrsas_pthru_frame {
2146         u_int8_t cmd;                   /* 00h */
2147         u_int8_t sense_len;             /* 01h */
2148         u_int8_t cmd_status;            /* 02h */
2149         u_int8_t scsi_status;           /* 03h */
2150
2151         u_int8_t target_id;             /* 04h */
2152         u_int8_t lun;                   /* 05h */
2153         u_int8_t cdb_len;               /* 06h */
2154         u_int8_t sge_count;             /* 07h */
2155
2156         u_int32_t context;              /* 08h */
2157         u_int32_t pad_0;                /* 0Ch */
2158
2159         u_int16_t flags;                /* 10h */
2160         u_int16_t timeout;              /* 12h */
2161         u_int32_t data_xfer_len;        /* 14h */
2162
2163         u_int32_t sense_buf_phys_addr_lo;       /* 18h */
2164         u_int32_t sense_buf_phys_addr_hi;       /* 1Ch */
2165
2166         u_int8_t cdb[16];               /* 20h */
2167         union mrsas_sgl sgl;            /* 30h */
2168 };
2169
2170 #pragma pack()
2171
2172 #pragma pack(1)
2173 struct mrsas_dcmd_frame {
2174         u_int8_t cmd;                   /* 00h */
2175         u_int8_t reserved_0;            /* 01h */
2176         u_int8_t cmd_status;            /* 02h */
2177         u_int8_t reserved_1[4];         /* 03h */
2178         u_int8_t sge_count;             /* 07h */
2179
2180         u_int32_t context;              /* 08h */
2181         u_int32_t pad_0;                /* 0Ch */
2182
2183         u_int16_t flags;                /* 10h */
2184         u_int16_t timeout;              /* 12h */
2185
2186         u_int32_t data_xfer_len;        /* 14h */
2187         u_int32_t opcode;               /* 18h */
2188
2189         union {                         /* 1Ch */
2190                 u_int8_t b[12];
2191                 u_int16_t s[6];
2192                 u_int32_t w[3];
2193         }       mbox;
2194
2195         union mrsas_sgl sgl;            /* 28h */
2196 };
2197
2198 #pragma pack()
2199
2200 #pragma pack(1)
2201 struct mrsas_abort_frame {
2202         u_int8_t cmd;                   /* 00h */
2203         u_int8_t reserved_0;            /* 01h */
2204         u_int8_t cmd_status;            /* 02h */
2205
2206         u_int8_t reserved_1;            /* 03h */
2207         MFI_CAPABILITIES driver_operations;     /* 04h */
2208         u_int32_t context;              /* 08h */
2209         u_int32_t pad_0;                /* 0Ch */
2210
2211         u_int16_t flags;                /* 10h */
2212         u_int16_t reserved_3;           /* 12h */
2213         u_int32_t reserved_4;           /* 14h */
2214
2215         u_int32_t abort_context;        /* 18h */
2216         u_int32_t pad_1;                /* 1Ch */
2217
2218         u_int32_t abort_mfi_phys_addr_lo;       /* 20h */
2219         u_int32_t abort_mfi_phys_addr_hi;       /* 24h */
2220
2221         u_int32_t reserved_5[6];        /* 28h */
2222 };
2223
2224 #pragma pack()
2225
2226 #pragma pack(1)
2227 struct mrsas_smp_frame {
2228         u_int8_t cmd;                   /* 00h */
2229         u_int8_t reserved_1;            /* 01h */
2230         u_int8_t cmd_status;            /* 02h */
2231         u_int8_t connection_status;     /* 03h */
2232
2233         u_int8_t reserved_2[3];         /* 04h */
2234         u_int8_t sge_count;             /* 07h */
2235
2236         u_int32_t context;              /* 08h */
2237         u_int32_t pad_0;                /* 0Ch */
2238
2239         u_int16_t flags;                /* 10h */
2240         u_int16_t timeout;              /* 12h */
2241
2242         u_int32_t data_xfer_len;        /* 14h */
2243         u_int64_t sas_addr;             /* 18h */
2244
2245         union {
2246                 struct mrsas_sge32 sge32[2];    /* [0]: resp [1]: req */
2247                 struct mrsas_sge64 sge64[2];    /* [0]: resp [1]: req */
2248         }       sgl;
2249 };
2250
2251 #pragma pack()
2252
2253
2254 #pragma pack(1)
2255 struct mrsas_stp_frame {
2256         u_int8_t cmd;                   /* 00h */
2257         u_int8_t reserved_1;            /* 01h */
2258         u_int8_t cmd_status;            /* 02h */
2259         u_int8_t reserved_2;            /* 03h */
2260
2261         u_int8_t target_id;             /* 04h */
2262         u_int8_t reserved_3[2];         /* 05h */
2263         u_int8_t sge_count;             /* 07h */
2264
2265         u_int32_t context;              /* 08h */
2266         u_int32_t pad_0;                /* 0Ch */
2267
2268         u_int16_t flags;                /* 10h */
2269         u_int16_t timeout;              /* 12h */
2270
2271         u_int32_t data_xfer_len;        /* 14h */
2272
2273         u_int16_t fis[10];              /* 18h */
2274         u_int32_t stp_flags;
2275
2276         union {
2277                 struct mrsas_sge32 sge32[2];    /* [0]: resp [1]: data */
2278                 struct mrsas_sge64 sge64[2];    /* [0]: resp [1]: data */
2279         }       sgl;
2280 };
2281
2282 #pragma pack()
2283
2284 union mrsas_frame {
2285         struct mrsas_header hdr;
2286         struct mrsas_init_frame init;
2287         struct mrsas_io_frame io;
2288         struct mrsas_pthru_frame pthru;
2289         struct mrsas_dcmd_frame dcmd;
2290         struct mrsas_abort_frame abort;
2291         struct mrsas_smp_frame smp;
2292         struct mrsas_stp_frame stp;
2293         u_int8_t raw_bytes[64];
2294 };
2295
2296 #pragma pack(1)
2297 union mrsas_evt_class_locale {
2298
2299         struct {
2300                 u_int16_t locale;
2301                 u_int8_t reserved;
2302                 int8_t  class;
2303         } __packed members;
2304
2305         u_int32_t word;
2306
2307 } __packed;
2308
2309 #pragma pack()
2310
2311
2312 #pragma pack(1)
2313 struct mrsas_evt_log_info {
2314         u_int32_t newest_seq_num;
2315         u_int32_t oldest_seq_num;
2316         u_int32_t clear_seq_num;
2317         u_int32_t shutdown_seq_num;
2318         u_int32_t boot_seq_num;
2319
2320 } __packed;
2321
2322 #pragma pack()
2323
2324 struct mrsas_progress {
2325
2326         u_int16_t progress;
2327         u_int16_t elapsed_seconds;
2328
2329 } __packed;
2330
2331 struct mrsas_evtarg_ld {
2332
2333         u_int16_t target_id;
2334         u_int8_t ld_index;
2335         u_int8_t reserved;
2336
2337 } __packed;
2338
2339 struct mrsas_evtarg_pd {
2340         u_int16_t device_id;
2341         u_int8_t encl_index;
2342         u_int8_t slot_number;
2343
2344 } __packed;
2345
2346 struct mrsas_evt_detail {
2347
2348         u_int32_t seq_num;
2349         u_int32_t time_stamp;
2350         u_int32_t code;
2351         union mrsas_evt_class_locale cl;
2352         u_int8_t arg_type;
2353         u_int8_t reserved1[15];
2354
2355         union {
2356                 struct {
2357                         struct mrsas_evtarg_pd pd;
2358                         u_int8_t cdb_length;
2359                         u_int8_t sense_length;
2360                         u_int8_t reserved[2];
2361                         u_int8_t cdb[16];
2362                         u_int8_t sense[64];
2363                 } __packed cdbSense;
2364
2365                 struct mrsas_evtarg_ld ld;
2366
2367                 struct {
2368                         struct mrsas_evtarg_ld ld;
2369                         u_int64_t count;
2370                 } __packed ld_count;
2371
2372                 struct {
2373                         u_int64_t lba;
2374                         struct mrsas_evtarg_ld ld;
2375                 } __packed ld_lba;
2376
2377                 struct {
2378                         struct mrsas_evtarg_ld ld;
2379                         u_int32_t prevOwner;
2380                         u_int32_t newOwner;
2381                 } __packed ld_owner;
2382
2383                 struct {
2384                         u_int64_t ld_lba;
2385                         u_int64_t pd_lba;
2386                         struct mrsas_evtarg_ld ld;
2387                         struct mrsas_evtarg_pd pd;
2388                 } __packed ld_lba_pd_lba;
2389
2390                 struct {
2391                         struct mrsas_evtarg_ld ld;
2392                         struct mrsas_progress prog;
2393                 } __packed ld_prog;
2394
2395                 struct {
2396                         struct mrsas_evtarg_ld ld;
2397                         u_int32_t prev_state;
2398                         u_int32_t new_state;
2399                 } __packed ld_state;
2400
2401                 struct {
2402                         u_int64_t strip;
2403                         struct mrsas_evtarg_ld ld;
2404                 } __packed ld_strip;
2405
2406                 struct mrsas_evtarg_pd pd;
2407
2408                 struct {
2409                         struct mrsas_evtarg_pd pd;
2410                         u_int32_t err;
2411                 } __packed pd_err;
2412
2413                 struct {
2414                         u_int64_t lba;
2415                         struct mrsas_evtarg_pd pd;
2416                 } __packed pd_lba;
2417
2418                 struct {
2419                         u_int64_t lba;
2420                         struct mrsas_evtarg_pd pd;
2421                         struct mrsas_evtarg_ld ld;
2422                 } __packed pd_lba_ld;
2423
2424                 struct {
2425                         struct mrsas_evtarg_pd pd;
2426                         struct mrsas_progress prog;
2427                 } __packed pd_prog;
2428
2429                 struct {
2430                         struct mrsas_evtarg_pd pd;
2431                         u_int32_t prevState;
2432                         u_int32_t newState;
2433                 } __packed pd_state;
2434
2435                 struct {
2436                         u_int16_t vendorId;
2437                         u_int16_t deviceId;
2438                         u_int16_t subVendorId;
2439                         u_int16_t subDeviceId;
2440                 } __packed pci;
2441
2442                 u_int32_t rate;
2443                 char    str[96];
2444
2445                 struct {
2446                         u_int32_t rtc;
2447                         u_int32_t elapsedSeconds;
2448                 } __packed time;
2449
2450                 struct {
2451                         u_int32_t ecar;
2452                         u_int32_t elog;
2453                         char    str[64];
2454                 } __packed ecc;
2455
2456                 u_int8_t b[96];
2457                 u_int16_t s[48];
2458                 u_int32_t w[24];
2459                 u_int64_t d[12];
2460         }       args;
2461
2462         char    description[128];
2463
2464 } __packed;
2465
2466 struct mrsas_irq_context {
2467         struct mrsas_softc *sc;
2468         uint32_t MSIxIndex;
2469 };
2470
2471 enum MEGASAS_OCR_REASON {
2472         FW_FAULT_OCR = 0,
2473         SCSIIO_TIMEOUT_OCR = 1,
2474         MFI_DCMD_TIMEOUT_OCR = 2,
2475 };
2476
2477 /* Controller management info added to support Linux Emulator */
2478 #define MAX_MGMT_ADAPTERS               1024
2479
2480 struct mrsas_mgmt_info {
2481         u_int16_t count;
2482         struct mrsas_softc *sc_ptr[MAX_MGMT_ADAPTERS];
2483         int     max_index;
2484 };
2485
2486 #define PCI_TYPE0_ADDRESSES             6
2487 #define PCI_TYPE1_ADDRESSES             2
2488 #define PCI_TYPE2_ADDRESSES             5
2489
2490 typedef struct _MRSAS_DRV_PCI_COMMON_HEADER {
2491         u_int16_t vendorID;
2492               //(ro)
2493         u_int16_t deviceID;
2494               //(ro)
2495         u_int16_t command;
2496               //Device control
2497         u_int16_t status;
2498         u_int8_t revisionID;
2499               //(ro)
2500         u_int8_t progIf;
2501               //(ro)
2502         u_int8_t subClass;
2503               //(ro)
2504         u_int8_t baseClass;
2505               //(ro)
2506         u_int8_t cacheLineSize;
2507               //(ro +)
2508         u_int8_t latencyTimer;
2509               //(ro +)
2510         u_int8_t headerType;
2511               //(ro)
2512         u_int8_t bist;
2513               //Built in self test
2514
2515         union {
2516                 struct _MRSAS_DRV_PCI_HEADER_TYPE_0 {
2517                         u_int32_t baseAddresses[PCI_TYPE0_ADDRESSES];
2518                         u_int32_t cis;
2519                         u_int16_t subVendorID;
2520                         u_int16_t subSystemID;
2521                         u_int32_t romBaseAddress;
2522                         u_int8_t capabilitiesPtr;
2523                         u_int8_t reserved1[3];
2524                         u_int32_t reserved2;
2525                         u_int8_t interruptLine;
2526                         u_int8_t interruptPin;
2527                               //(ro)
2528                         u_int8_t minimumGrant;
2529                               //(ro)
2530                         u_int8_t maximumLatency;
2531                               //(ro)
2532                 }       type0;
2533
2534                 /*
2535                  * PCI to PCI Bridge
2536                  */
2537
2538                 struct _MRSAS_DRV_PCI_HEADER_TYPE_1 {
2539                         u_int32_t baseAddresses[PCI_TYPE1_ADDRESSES];
2540                         u_int8_t primaryBus;
2541                         u_int8_t secondaryBus;
2542                         u_int8_t subordinateBus;
2543                         u_int8_t secondaryLatency;
2544                         u_int8_t ioBase;
2545                         u_int8_t ioLimit;
2546                         u_int16_t secondaryStatus;
2547                         u_int16_t memoryBase;
2548                         u_int16_t memoryLimit;
2549                         u_int16_t prefetchBase;
2550                         u_int16_t prefetchLimit;
2551                         u_int32_t prefetchBaseUpper32;
2552                         u_int32_t prefetchLimitUpper32;
2553                         u_int16_t ioBaseUpper16;
2554                         u_int16_t ioLimitUpper16;
2555                         u_int8_t capabilitiesPtr;
2556                         u_int8_t reserved1[3];
2557                         u_int32_t romBaseAddress;
2558                         u_int8_t interruptLine;
2559                         u_int8_t interruptPin;
2560                         u_int16_t bridgeControl;
2561                 }       type1;
2562
2563                 /*
2564                  * PCI to CARDBUS Bridge
2565                  */
2566
2567                 struct _MRSAS_DRV_PCI_HEADER_TYPE_2 {
2568                         u_int32_t socketRegistersBaseAddress;
2569                         u_int8_t capabilitiesPtr;
2570                         u_int8_t reserved;
2571                         u_int16_t secondaryStatus;
2572                         u_int8_t primaryBus;
2573                         u_int8_t secondaryBus;
2574                         u_int8_t subordinateBus;
2575                         u_int8_t secondaryLatency;
2576                         struct {
2577                                 u_int32_t base;
2578                                 u_int32_t limit;
2579                         }       range [PCI_TYPE2_ADDRESSES - 1];
2580                         u_int8_t interruptLine;
2581                         u_int8_t interruptPin;
2582                         u_int16_t bridgeControl;
2583                 }       type2;
2584         }       u;
2585
2586 }       MRSAS_DRV_PCI_COMMON_HEADER, *PMRSAS_DRV_PCI_COMMON_HEADER;
2587
2588 #define MRSAS_DRV_PCI_COMMON_HEADER_SIZE sizeof(MRSAS_DRV_PCI_COMMON_HEADER)   //64 bytes
2589
2590 typedef struct _MRSAS_DRV_PCI_LINK_CAPABILITY {
2591         union {
2592                 struct {
2593                         u_int32_t linkSpeed:4;
2594                         u_int32_t linkWidth:6;
2595                         u_int32_t aspmSupport:2;
2596                         u_int32_t losExitLatency:3;
2597                         u_int32_t l1ExitLatency:3;
2598                         u_int32_t rsvdp:6;
2599                         u_int32_t portNumber:8;
2600                 }       bits;
2601
2602                 u_int32_t asUlong;
2603         }       u;
2604 }       MRSAS_DRV_PCI_LINK_CAPABILITY, *PMRSAS_DRV_PCI_LINK_CAPABILITY;
2605
2606 #define MRSAS_DRV_PCI_LINK_CAPABILITY_SIZE sizeof(MRSAS_DRV_PCI_LINK_CAPABILITY)
2607
2608 typedef struct _MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY {
2609         union {
2610                 struct {
2611                         u_int16_t linkSpeed:4;
2612                         u_int16_t negotiatedLinkWidth:6;
2613                         u_int16_t linkTrainingError:1;
2614                         u_int16_t linkTraning:1;
2615                         u_int16_t slotClockConfig:1;
2616                         u_int16_t rsvdZ:3;
2617                 }       bits;
2618
2619                 u_int16_t asUshort;
2620         }       u;
2621         u_int16_t reserved;
2622 }       MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY, *PMRSAS_DRV_PCI_LINK_STATUS_CAPABILITY;
2623
2624 #define MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY_SIZE sizeof(MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY)
2625
2626
2627 typedef struct _MRSAS_DRV_PCI_CAPABILITIES {
2628         MRSAS_DRV_PCI_LINK_CAPABILITY linkCapability;
2629         MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY linkStatusCapability;
2630 }       MRSAS_DRV_PCI_CAPABILITIES, *PMRSAS_DRV_PCI_CAPABILITIES;
2631
2632 #define MRSAS_DRV_PCI_CAPABILITIES_SIZE sizeof(MRSAS_DRV_PCI_CAPABILITIES)
2633
2634 /* PCI information */
2635 typedef struct _MRSAS_DRV_PCI_INFORMATION {
2636         u_int32_t busNumber;
2637         u_int8_t deviceNumber;
2638         u_int8_t functionNumber;
2639         u_int8_t interruptVector;
2640         u_int8_t reserved1;
2641         MRSAS_DRV_PCI_COMMON_HEADER pciHeaderInfo;
2642         MRSAS_DRV_PCI_CAPABILITIES capability;
2643         u_int32_t domainID;
2644         u_int8_t reserved2[28];
2645 }       MRSAS_DRV_PCI_INFORMATION, *PMRSAS_DRV_PCI_INFORMATION;
2646
2647 /*******************************************************************
2648  * per-instance data
2649  ********************************************************************/
2650 struct mrsas_softc {
2651         device_t mrsas_dev;
2652         struct cdev *mrsas_cdev;
2653         struct intr_config_hook mrsas_ich;
2654         struct cdev *mrsas_linux_emulator_cdev;
2655         uint16_t device_id;
2656         struct resource *reg_res;
2657         int     reg_res_id;
2658         bus_space_tag_t bus_tag;
2659         bus_space_handle_t bus_handle;
2660         bus_dma_tag_t mrsas_parent_tag;
2661         bus_dma_tag_t verbuf_tag;
2662         bus_dmamap_t verbuf_dmamap;
2663         void   *verbuf_mem;
2664         bus_addr_t verbuf_phys_addr;
2665         bus_dma_tag_t sense_tag;
2666         bus_dmamap_t sense_dmamap;
2667         void   *sense_mem;
2668         bus_addr_t sense_phys_addr;
2669         bus_dma_tag_t io_request_tag;
2670         bus_dmamap_t io_request_dmamap;
2671         void   *io_request_mem;
2672         bus_addr_t io_request_phys_addr;
2673         bus_dma_tag_t chain_frame_tag;
2674         bus_dmamap_t chain_frame_dmamap;
2675         void   *chain_frame_mem;
2676         bus_addr_t chain_frame_phys_addr;
2677         bus_dma_tag_t reply_desc_tag;
2678         bus_dmamap_t reply_desc_dmamap;
2679         void   *reply_desc_mem;
2680         bus_addr_t reply_desc_phys_addr;
2681         bus_dma_tag_t ioc_init_tag;
2682         bus_dmamap_t ioc_init_dmamap;
2683         void   *ioc_init_mem;
2684         bus_addr_t ioc_init_phys_mem;
2685         bus_dma_tag_t data_tag;
2686         struct cam_sim *sim_0;
2687         struct cam_sim *sim_1;
2688         struct cam_path *path_0;
2689         struct cam_path *path_1;
2690         struct mtx sim_lock;
2691         struct mtx pci_lock;
2692         struct mtx io_lock;
2693         struct mtx ioctl_lock;
2694         struct mtx mpt_cmd_pool_lock;
2695         struct mtx mfi_cmd_pool_lock;
2696         struct mtx raidmap_lock;
2697         struct mtx aen_lock;
2698         struct selinfo mrsas_select;
2699         uint32_t mrsas_aen_triggered;
2700         uint32_t mrsas_poll_waiting;
2701
2702         struct sema ioctl_count_sema;
2703         uint32_t max_fw_cmds;
2704         uint32_t max_num_sge;
2705         struct resource *mrsas_irq[MAX_MSIX_COUNT];
2706         void   *intr_handle[MAX_MSIX_COUNT];
2707         int     irq_id[MAX_MSIX_COUNT];
2708         struct mrsas_irq_context irq_context[MAX_MSIX_COUNT];
2709         int     msix_vectors;
2710         int     msix_enable;
2711         uint32_t msix_reg_offset[16];
2712         uint8_t mask_interrupts;
2713         uint16_t max_chain_frame_sz;
2714         struct mrsas_mpt_cmd **mpt_cmd_list;
2715         struct mrsas_mfi_cmd **mfi_cmd_list;
2716         TAILQ_HEAD(, mrsas_mpt_cmd) mrsas_mpt_cmd_list_head;
2717         TAILQ_HEAD(, mrsas_mfi_cmd) mrsas_mfi_cmd_list_head;
2718         bus_addr_t req_frames_desc_phys;
2719         u_int8_t *req_frames_desc;
2720         u_int8_t *req_desc;
2721         bus_addr_t io_request_frames_phys;
2722         u_int8_t *io_request_frames;
2723         bus_addr_t reply_frames_desc_phys;
2724         u_int16_t last_reply_idx[MAX_MSIX_COUNT];
2725         u_int32_t reply_q_depth;
2726         u_int32_t request_alloc_sz;
2727         u_int32_t reply_alloc_sz;
2728         u_int32_t io_frames_alloc_sz;
2729         u_int32_t chain_frames_alloc_sz;
2730         u_int16_t max_sge_in_main_msg;
2731         u_int16_t max_sge_in_chain;
2732         u_int8_t chain_offset_io_request;
2733         u_int8_t chain_offset_mfi_pthru;
2734         u_int32_t map_sz;
2735         u_int64_t map_id;
2736         u_int64_t pd_seq_map_id;
2737         struct mrsas_mfi_cmd *map_update_cmd;
2738         struct mrsas_mfi_cmd *jbod_seq_cmd;
2739         struct mrsas_mfi_cmd *aen_cmd;
2740         u_int8_t fast_path_io;
2741         void   *chan;
2742         void   *ocr_chan;
2743         u_int8_t adprecovery;
2744         u_int8_t remove_in_progress;
2745         u_int8_t ocr_thread_active;
2746         u_int8_t do_timedout_reset;
2747         u_int32_t reset_in_progress;
2748         u_int32_t reset_count;
2749
2750         bus_dma_tag_t jbodmap_tag[2];
2751         bus_dmamap_t jbodmap_dmamap[2];
2752         void   *jbodmap_mem[2];
2753         bus_addr_t jbodmap_phys_addr[2];
2754
2755         bus_dma_tag_t raidmap_tag[2];
2756         bus_dmamap_t raidmap_dmamap[2];
2757         void   *raidmap_mem[2];
2758         bus_addr_t raidmap_phys_addr[2];
2759         bus_dma_tag_t mficmd_frame_tag;
2760         bus_dma_tag_t mficmd_sense_tag;
2761         bus_dma_tag_t evt_detail_tag;
2762         bus_dmamap_t evt_detail_dmamap;
2763         struct mrsas_evt_detail *evt_detail_mem;
2764         bus_addr_t evt_detail_phys_addr;
2765         struct mrsas_ctrl_info *ctrl_info;
2766         bus_dma_tag_t ctlr_info_tag;
2767         bus_dmamap_t ctlr_info_dmamap;
2768         void   *ctlr_info_mem;
2769         bus_addr_t ctlr_info_phys_addr;
2770         u_int32_t max_sectors_per_req;
2771         u_int32_t disableOnlineCtrlReset;
2772         mrsas_atomic_t fw_outstanding;
2773         u_int32_t mrsas_debug;
2774         u_int32_t mrsas_io_timeout;
2775         u_int32_t mrsas_fw_fault_check_delay;
2776         u_int32_t io_cmds_highwater;
2777         u_int8_t UnevenSpanSupport;
2778         struct sysctl_ctx_list sysctl_ctx;
2779         struct sysctl_oid *sysctl_tree;
2780         struct proc *ocr_thread;
2781         u_int32_t last_seq_num;
2782         bus_dma_tag_t el_info_tag;
2783         bus_dmamap_t el_info_dmamap;
2784         void   *el_info_mem;
2785         bus_addr_t el_info_phys_addr;
2786         struct mrsas_pd_list pd_list[MRSAS_MAX_PD];
2787         struct mrsas_pd_list local_pd_list[MRSAS_MAX_PD];
2788         u_int8_t ld_ids[MRSAS_MAX_LD_IDS];
2789         struct taskqueue *ev_tq;
2790         struct task ev_task;
2791         u_int32_t CurLdCount;
2792         u_int64_t reset_flags;
2793         int     lb_pending_cmds;
2794         LD_LOAD_BALANCE_INFO load_balance_info[MAX_LOGICAL_DRIVES_EXT];
2795         LD_SPAN_INFO log_to_span[MAX_LOGICAL_DRIVES_EXT];
2796
2797         u_int8_t secure_jbod_support;
2798         u_int8_t use_seqnum_jbod_fp;
2799         u_int8_t max256vdSupport;
2800         u_int16_t fw_supported_vd_count;
2801         u_int16_t fw_supported_pd_count;
2802
2803         u_int16_t drv_supported_vd_count;
2804         u_int16_t drv_supported_pd_count;
2805
2806         u_int32_t max_map_sz;
2807         u_int32_t current_map_sz;
2808         u_int32_t old_map_sz;
2809         u_int32_t new_map_sz;
2810         u_int32_t drv_map_sz;
2811
2812         /* Non dma-able memory. Driver local copy. */
2813         MR_DRV_RAID_MAP_ALL *ld_drv_map[2];
2814 };
2815
2816 /* Compatibility shims for different OS versions */
2817 #if __FreeBSD_version >= 800001
2818 #define mrsas_kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) \
2819     kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg)
2820 #define mrsas_kproc_exit(arg)   kproc_exit(arg)
2821 #else
2822 #define mrsas_kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) \
2823     kthread_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg)
2824 #define mrsas_kproc_exit(arg)   kthread_exit(arg)
2825 #endif
2826
2827 static __inline void
2828 mrsas_clear_bit(int b, volatile void *p)
2829 {
2830         atomic_clear_int(((volatile int *)p) + (b >> 5), 1 << (b & 0x1f));
2831 }
2832
2833 static __inline void
2834 mrsas_set_bit(int b, volatile void *p)
2835 {
2836         atomic_set_int(((volatile int *)p) + (b >> 5), 1 << (b & 0x1f));
2837 }
2838
2839 static __inline int
2840 mrsas_test_bit(int b, volatile void *p)
2841 {
2842         return ((volatile int *)p)[b >> 5] & (1 << (b & 0x1f));
2843 }
2844
2845 #endif                                  /* MRSAS_H */