1 /******************************************************************************
4 * Project: Gigabit Ethernet Driver for FreeBSD 5.x/6.x
5 * Version: $Revision: 1.23 $
6 * Date : $Date: 2005/12/22 09:04:11 $
7 * Purpose: Main driver source file
9 *****************************************************************************/
11 /******************************************************************************
14 * Copyright (C) Marvell International Ltd. and/or its affiliates
16 * The computer program files contained in this folder ("Files")
17 * are provided to you under the BSD-type license terms provided
18 * below, and any use of such Files and any derivative works
19 * thereof created by you shall be governed by the following terms
22 * - Redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer.
24 * - Redistributions in binary form must reproduce the above
25 * copyright notice, this list of conditions and the following
26 * disclaimer in the documentation and/or other materials provided
27 * with the distribution.
28 * - Neither the name of Marvell nor the names of its contributors
29 * may be used to endorse or promote products derived from this
30 * software without specific prior written permission.
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
33 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
34 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
35 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
36 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
37 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
38 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
39 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
41 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
42 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
43 * OF THE POSSIBILITY OF SUCH DAMAGE.
46 *****************************************************************************/
49 * Copyright (c) 1997, 1998, 1999, 2000
50 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
52 * Redistribution and use in source and binary forms, with or without
53 * modification, are permitted provided that the following conditions
55 * 1. Redistributions of source code must retain the above copyright
56 * notice, this list of conditions and the following disclaimer.
57 * 2. Redistributions in binary form must reproduce the above copyright
58 * notice, this list of conditions and the following disclaimer in the
59 * documentation and/or other materials provided with the distribution.
60 * 3. All advertising materials mentioning features or use of this software
61 * must display the following acknowledgement:
62 * This product includes software developed by Bill Paul.
63 * 4. Neither the name of the author nor the names of any co-contributors
64 * may be used to endorse or promote products derived from this software
65 * without specific prior written permission.
67 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
68 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
69 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
70 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
71 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
72 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
73 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
74 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
75 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
76 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
77 * THE POSSIBILITY OF SUCH DAMAGE.
80 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu>
82 * Permission to use, copy, modify, and distribute this software for any
83 * purpose with or without fee is hereby granted, provided that the above
84 * copyright notice and this permission notice appear in all copies.
86 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
87 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
88 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
89 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
90 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
91 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
92 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
96 * Device driver for the Marvell Yukon II Ethernet controller.
97 * Due to lack of documentation, this driver is based on the code from
98 * sk(4) and Marvell's myk(4) driver for FreeBSD 5.x.
101 #include <sys/cdefs.h>
102 __FBSDID("$FreeBSD$");
104 #include <sys/param.h>
105 #include <sys/systm.h>
107 #include <sys/endian.h>
108 #include <sys/mbuf.h>
109 #include <sys/malloc.h>
110 #include <sys/kernel.h>
111 #include <sys/module.h>
112 #include <sys/socket.h>
113 #include <sys/sockio.h>
114 #include <sys/queue.h>
115 #include <sys/sysctl.h>
118 #include <net/ethernet.h>
120 #include <net/if_var.h>
121 #include <net/if_arp.h>
122 #include <net/if_dl.h>
123 #include <net/if_media.h>
124 #include <net/if_types.h>
125 #include <net/if_vlan_var.h>
127 #include <netinet/in.h>
128 #include <netinet/in_systm.h>
129 #include <netinet/ip.h>
130 #include <netinet/tcp.h>
131 #include <netinet/udp.h>
133 #include <machine/bus.h>
134 #include <machine/in_cksum.h>
135 #include <machine/resource.h>
136 #include <sys/rman.h>
138 #include <dev/mii/mii.h>
139 #include <dev/mii/miivar.h>
141 #include <dev/pci/pcireg.h>
142 #include <dev/pci/pcivar.h>
144 #include <dev/msk/if_mskreg.h>
146 MODULE_DEPEND(msk, pci, 1, 1, 1);
147 MODULE_DEPEND(msk, ether, 1, 1, 1);
148 MODULE_DEPEND(msk, miibus, 1, 1, 1);
150 /* "device miibus" required. See GENERIC if you get errors here. */
151 #include "miibus_if.h"
154 static int msi_disable = 0;
155 TUNABLE_INT("hw.msk.msi_disable", &msi_disable);
156 static int legacy_intr = 0;
157 TUNABLE_INT("hw.msk.legacy_intr", &legacy_intr);
158 static int jumbo_disable = 0;
159 TUNABLE_INT("hw.msk.jumbo_disable", &jumbo_disable);
161 #define MSK_CSUM_FEATURES (CSUM_TCP | CSUM_UDP)
164 * Devices supported by this driver.
166 static const struct msk_product {
167 uint16_t msk_vendorid;
168 uint16_t msk_deviceid;
169 const char *msk_name;
171 { VENDORID_SK, DEVICEID_SK_YUKON2,
172 "SK-9Sxx Gigabit Ethernet" },
173 { VENDORID_SK, DEVICEID_SK_YUKON2_EXPR,
174 "SK-9Exx Gigabit Ethernet"},
175 { VENDORID_MARVELL, DEVICEID_MRVL_8021CU,
176 "Marvell Yukon 88E8021CU Gigabit Ethernet" },
177 { VENDORID_MARVELL, DEVICEID_MRVL_8021X,
178 "Marvell Yukon 88E8021 SX/LX Gigabit Ethernet" },
179 { VENDORID_MARVELL, DEVICEID_MRVL_8022CU,
180 "Marvell Yukon 88E8022CU Gigabit Ethernet" },
181 { VENDORID_MARVELL, DEVICEID_MRVL_8022X,
182 "Marvell Yukon 88E8022 SX/LX Gigabit Ethernet" },
183 { VENDORID_MARVELL, DEVICEID_MRVL_8061CU,
184 "Marvell Yukon 88E8061CU Gigabit Ethernet" },
185 { VENDORID_MARVELL, DEVICEID_MRVL_8061X,
186 "Marvell Yukon 88E8061 SX/LX Gigabit Ethernet" },
187 { VENDORID_MARVELL, DEVICEID_MRVL_8062CU,
188 "Marvell Yukon 88E8062CU Gigabit Ethernet" },
189 { VENDORID_MARVELL, DEVICEID_MRVL_8062X,
190 "Marvell Yukon 88E8062 SX/LX Gigabit Ethernet" },
191 { VENDORID_MARVELL, DEVICEID_MRVL_8035,
192 "Marvell Yukon 88E8035 Fast Ethernet" },
193 { VENDORID_MARVELL, DEVICEID_MRVL_8036,
194 "Marvell Yukon 88E8036 Fast Ethernet" },
195 { VENDORID_MARVELL, DEVICEID_MRVL_8038,
196 "Marvell Yukon 88E8038 Fast Ethernet" },
197 { VENDORID_MARVELL, DEVICEID_MRVL_8039,
198 "Marvell Yukon 88E8039 Fast Ethernet" },
199 { VENDORID_MARVELL, DEVICEID_MRVL_8040,
200 "Marvell Yukon 88E8040 Fast Ethernet" },
201 { VENDORID_MARVELL, DEVICEID_MRVL_8040T,
202 "Marvell Yukon 88E8040T Fast Ethernet" },
203 { VENDORID_MARVELL, DEVICEID_MRVL_8042,
204 "Marvell Yukon 88E8042 Fast Ethernet" },
205 { VENDORID_MARVELL, DEVICEID_MRVL_8048,
206 "Marvell Yukon 88E8048 Fast Ethernet" },
207 { VENDORID_MARVELL, DEVICEID_MRVL_4361,
208 "Marvell Yukon 88E8050 Gigabit Ethernet" },
209 { VENDORID_MARVELL, DEVICEID_MRVL_4360,
210 "Marvell Yukon 88E8052 Gigabit Ethernet" },
211 { VENDORID_MARVELL, DEVICEID_MRVL_4362,
212 "Marvell Yukon 88E8053 Gigabit Ethernet" },
213 { VENDORID_MARVELL, DEVICEID_MRVL_4363,
214 "Marvell Yukon 88E8055 Gigabit Ethernet" },
215 { VENDORID_MARVELL, DEVICEID_MRVL_4364,
216 "Marvell Yukon 88E8056 Gigabit Ethernet" },
217 { VENDORID_MARVELL, DEVICEID_MRVL_4365,
218 "Marvell Yukon 88E8070 Gigabit Ethernet" },
219 { VENDORID_MARVELL, DEVICEID_MRVL_436A,
220 "Marvell Yukon 88E8058 Gigabit Ethernet" },
221 { VENDORID_MARVELL, DEVICEID_MRVL_436B,
222 "Marvell Yukon 88E8071 Gigabit Ethernet" },
223 { VENDORID_MARVELL, DEVICEID_MRVL_436C,
224 "Marvell Yukon 88E8072 Gigabit Ethernet" },
225 { VENDORID_MARVELL, DEVICEID_MRVL_436D,
226 "Marvell Yukon 88E8055 Gigabit Ethernet" },
227 { VENDORID_MARVELL, DEVICEID_MRVL_4370,
228 "Marvell Yukon 88E8075 Gigabit Ethernet" },
229 { VENDORID_MARVELL, DEVICEID_MRVL_4380,
230 "Marvell Yukon 88E8057 Gigabit Ethernet" },
231 { VENDORID_MARVELL, DEVICEID_MRVL_4381,
232 "Marvell Yukon 88E8059 Gigabit Ethernet" },
233 { VENDORID_DLINK, DEVICEID_DLINK_DGE550SX,
234 "D-Link 550SX Gigabit Ethernet" },
235 { VENDORID_DLINK, DEVICEID_DLINK_DGE560SX,
236 "D-Link 560SX Gigabit Ethernet" },
237 { VENDORID_DLINK, DEVICEID_DLINK_DGE560T,
238 "D-Link 560T Gigabit Ethernet" }
241 static const char *model_name[] = {
254 static int mskc_probe(device_t);
255 static int mskc_attach(device_t);
256 static int mskc_detach(device_t);
257 static int mskc_shutdown(device_t);
258 static int mskc_setup_rambuffer(struct msk_softc *);
259 static int mskc_suspend(device_t);
260 static int mskc_resume(device_t);
261 static bus_dma_tag_t mskc_get_dma_tag(device_t, device_t);
262 static void mskc_reset(struct msk_softc *);
264 static int msk_probe(device_t);
265 static int msk_attach(device_t);
266 static int msk_detach(device_t);
268 static void msk_tick(void *);
269 static void msk_intr(void *);
270 static void msk_intr_phy(struct msk_if_softc *);
271 static void msk_intr_gmac(struct msk_if_softc *);
272 static __inline void msk_rxput(struct msk_if_softc *);
273 static int msk_handle_events(struct msk_softc *);
274 static void msk_handle_hwerr(struct msk_if_softc *, uint32_t);
275 static void msk_intr_hwerr(struct msk_softc *);
276 #ifndef __NO_STRICT_ALIGNMENT
277 static __inline void msk_fixup_rx(struct mbuf *);
279 static __inline void msk_rxcsum(struct msk_if_softc *, uint32_t, struct mbuf *);
280 static void msk_rxeof(struct msk_if_softc *, uint32_t, uint32_t, int);
281 static void msk_jumbo_rxeof(struct msk_if_softc *, uint32_t, uint32_t, int);
282 static void msk_txeof(struct msk_if_softc *, int);
283 static int msk_encap(struct msk_if_softc *, struct mbuf **);
284 static void msk_start(struct ifnet *);
285 static void msk_start_locked(struct ifnet *);
286 static int msk_ioctl(struct ifnet *, u_long, caddr_t);
287 static void msk_set_prefetch(struct msk_softc *, int, bus_addr_t, uint32_t);
288 static void msk_set_rambuffer(struct msk_if_softc *);
289 static void msk_set_tx_stfwd(struct msk_if_softc *);
290 static void msk_init(void *);
291 static void msk_init_locked(struct msk_if_softc *);
292 static void msk_stop(struct msk_if_softc *);
293 static void msk_watchdog(struct msk_if_softc *);
294 static int msk_mediachange(struct ifnet *);
295 static void msk_mediastatus(struct ifnet *, struct ifmediareq *);
296 static void msk_phy_power(struct msk_softc *, int);
297 static void msk_dmamap_cb(void *, bus_dma_segment_t *, int, int);
298 static int msk_status_dma_alloc(struct msk_softc *);
299 static void msk_status_dma_free(struct msk_softc *);
300 static int msk_txrx_dma_alloc(struct msk_if_softc *);
301 static int msk_rx_dma_jalloc(struct msk_if_softc *);
302 static void msk_txrx_dma_free(struct msk_if_softc *);
303 static void msk_rx_dma_jfree(struct msk_if_softc *);
304 static int msk_rx_fill(struct msk_if_softc *, int);
305 static int msk_init_rx_ring(struct msk_if_softc *);
306 static int msk_init_jumbo_rx_ring(struct msk_if_softc *);
307 static void msk_init_tx_ring(struct msk_if_softc *);
308 static __inline void msk_discard_rxbuf(struct msk_if_softc *, int);
309 static __inline void msk_discard_jumbo_rxbuf(struct msk_if_softc *, int);
310 static int msk_newbuf(struct msk_if_softc *, int);
311 static int msk_jumbo_newbuf(struct msk_if_softc *, int);
313 static int msk_phy_readreg(struct msk_if_softc *, int, int);
314 static int msk_phy_writereg(struct msk_if_softc *, int, int, int);
315 static int msk_miibus_readreg(device_t, int, int);
316 static int msk_miibus_writereg(device_t, int, int, int);
317 static void msk_miibus_statchg(device_t);
319 static void msk_rxfilter(struct msk_if_softc *);
320 static void msk_setvlan(struct msk_if_softc *, struct ifnet *);
322 static void msk_stats_clear(struct msk_if_softc *);
323 static void msk_stats_update(struct msk_if_softc *);
324 static int msk_sysctl_stat32(SYSCTL_HANDLER_ARGS);
325 static int msk_sysctl_stat64(SYSCTL_HANDLER_ARGS);
326 static void msk_sysctl_node(struct msk_if_softc *);
327 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
328 static int sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS);
330 static device_method_t mskc_methods[] = {
331 /* Device interface */
332 DEVMETHOD(device_probe, mskc_probe),
333 DEVMETHOD(device_attach, mskc_attach),
334 DEVMETHOD(device_detach, mskc_detach),
335 DEVMETHOD(device_suspend, mskc_suspend),
336 DEVMETHOD(device_resume, mskc_resume),
337 DEVMETHOD(device_shutdown, mskc_shutdown),
339 DEVMETHOD(bus_get_dma_tag, mskc_get_dma_tag),
344 static driver_t mskc_driver = {
347 sizeof(struct msk_softc)
350 static devclass_t mskc_devclass;
352 static device_method_t msk_methods[] = {
353 /* Device interface */
354 DEVMETHOD(device_probe, msk_probe),
355 DEVMETHOD(device_attach, msk_attach),
356 DEVMETHOD(device_detach, msk_detach),
357 DEVMETHOD(device_shutdown, bus_generic_shutdown),
360 DEVMETHOD(miibus_readreg, msk_miibus_readreg),
361 DEVMETHOD(miibus_writereg, msk_miibus_writereg),
362 DEVMETHOD(miibus_statchg, msk_miibus_statchg),
367 static driver_t msk_driver = {
370 sizeof(struct msk_if_softc)
373 static devclass_t msk_devclass;
375 DRIVER_MODULE(mskc, pci, mskc_driver, mskc_devclass, NULL, NULL);
376 DRIVER_MODULE(msk, mskc, msk_driver, msk_devclass, NULL, NULL);
377 DRIVER_MODULE(miibus, msk, miibus_driver, miibus_devclass, NULL, NULL);
379 static struct resource_spec msk_res_spec_io[] = {
380 { SYS_RES_IOPORT, PCIR_BAR(1), RF_ACTIVE },
384 static struct resource_spec msk_res_spec_mem[] = {
385 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
389 static struct resource_spec msk_irq_spec_legacy[] = {
390 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
394 static struct resource_spec msk_irq_spec_msi[] = {
395 { SYS_RES_IRQ, 1, RF_ACTIVE },
400 msk_miibus_readreg(device_t dev, int phy, int reg)
402 struct msk_if_softc *sc_if;
404 sc_if = device_get_softc(dev);
406 return (msk_phy_readreg(sc_if, phy, reg));
410 msk_phy_readreg(struct msk_if_softc *sc_if, int phy, int reg)
412 struct msk_softc *sc;
415 sc = sc_if->msk_softc;
417 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL,
418 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
420 for (i = 0; i < MSK_TIMEOUT; i++) {
422 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL);
423 if ((val & GM_SMI_CT_RD_VAL) != 0) {
424 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_DATA);
429 if (i == MSK_TIMEOUT) {
430 if_printf(sc_if->msk_ifp, "phy failed to come ready\n");
438 msk_miibus_writereg(device_t dev, int phy, int reg, int val)
440 struct msk_if_softc *sc_if;
442 sc_if = device_get_softc(dev);
444 return (msk_phy_writereg(sc_if, phy, reg, val));
448 msk_phy_writereg(struct msk_if_softc *sc_if, int phy, int reg, int val)
450 struct msk_softc *sc;
453 sc = sc_if->msk_softc;
455 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_DATA, val);
456 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL,
457 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg));
458 for (i = 0; i < MSK_TIMEOUT; i++) {
460 if ((GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL) &
461 GM_SMI_CT_BUSY) == 0)
464 if (i == MSK_TIMEOUT)
465 if_printf(sc_if->msk_ifp, "phy write timeout\n");
471 msk_miibus_statchg(device_t dev)
473 struct msk_softc *sc;
474 struct msk_if_softc *sc_if;
475 struct mii_data *mii;
479 sc_if = device_get_softc(dev);
480 sc = sc_if->msk_softc;
482 MSK_IF_LOCK_ASSERT(sc_if);
484 mii = device_get_softc(sc_if->msk_miibus);
485 ifp = sc_if->msk_ifp;
486 if (mii == NULL || ifp == NULL ||
487 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
490 sc_if->msk_flags &= ~MSK_FLAG_LINK;
491 if ((mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) ==
492 (IFM_AVALID | IFM_ACTIVE)) {
493 switch (IFM_SUBTYPE(mii->mii_media_active)) {
496 sc_if->msk_flags |= MSK_FLAG_LINK;
502 if ((sc_if->msk_flags & MSK_FLAG_FASTETHER) == 0)
503 sc_if->msk_flags |= MSK_FLAG_LINK;
510 if ((sc_if->msk_flags & MSK_FLAG_LINK) != 0) {
511 /* Enable Tx FIFO Underrun. */
512 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK),
513 GM_IS_TX_FF_UR | GM_IS_RX_FF_OR);
515 * Because mii(4) notify msk(4) that it detected link status
516 * change, there is no need to enable automatic
517 * speed/flow-control/duplex updates.
519 gmac = GM_GPCR_AU_ALL_DIS;
520 switch (IFM_SUBTYPE(mii->mii_media_active)) {
523 gmac |= GM_GPCR_SPEED_1000;
526 gmac |= GM_GPCR_SPEED_100;
532 if ((IFM_OPTIONS(mii->mii_media_active) &
533 IFM_ETH_RXPAUSE) == 0)
534 gmac |= GM_GPCR_FC_RX_DIS;
535 if ((IFM_OPTIONS(mii->mii_media_active) &
536 IFM_ETH_TXPAUSE) == 0)
537 gmac |= GM_GPCR_FC_TX_DIS;
538 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0)
539 gmac |= GM_GPCR_DUP_FULL;
541 gmac |= GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS;
542 gmac |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
543 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac);
544 /* Read again to ensure writing. */
545 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
546 gmac = GMC_PAUSE_OFF;
547 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
548 if ((IFM_OPTIONS(mii->mii_media_active) &
549 IFM_ETH_RXPAUSE) != 0)
552 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), gmac);
554 /* Enable PHY interrupt for FIFO underrun/overflow. */
555 msk_phy_writereg(sc_if, PHY_ADDR_MARV,
556 PHY_MARV_INT_MASK, PHY_M_IS_FIFO_ERROR);
559 * Link state changed to down.
560 * Disable PHY interrupts.
562 msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0);
563 /* Disable Rx/Tx MAC. */
564 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
565 if ((gmac & (GM_GPCR_RX_ENA | GM_GPCR_TX_ENA)) != 0) {
566 gmac &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
567 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac);
568 /* Read again to ensure writing. */
569 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
575 msk_rxfilter(struct msk_if_softc *sc_if)
577 struct msk_softc *sc;
579 struct ifmultiaddr *ifma;
584 sc = sc_if->msk_softc;
586 MSK_IF_LOCK_ASSERT(sc_if);
588 ifp = sc_if->msk_ifp;
590 bzero(mchash, sizeof(mchash));
591 mode = GMAC_READ_2(sc, sc_if->msk_port, GM_RX_CTRL);
592 if ((ifp->if_flags & IFF_PROMISC) != 0)
593 mode &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
594 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) {
595 mode |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
599 mode |= GM_RXCR_UCF_ENA;
601 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
602 if (ifma->ifma_addr->sa_family != AF_LINK)
604 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
605 ifma->ifma_addr), ETHER_ADDR_LEN);
606 /* Just want the 6 least significant bits. */
608 /* Set the corresponding bit in the hash table. */
609 mchash[crc >> 5] |= 1 << (crc & 0x1f);
611 if_maddr_runlock(ifp);
612 if (mchash[0] != 0 || mchash[1] != 0)
613 mode |= GM_RXCR_MCF_ENA;
616 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H1,
618 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H2,
619 (mchash[0] >> 16) & 0xffff);
620 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H3,
622 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H4,
623 (mchash[1] >> 16) & 0xffff);
624 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, mode);
628 msk_setvlan(struct msk_if_softc *sc_if, struct ifnet *ifp)
630 struct msk_softc *sc;
632 sc = sc_if->msk_softc;
633 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) {
634 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T),
636 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
639 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T),
641 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
647 msk_rx_fill(struct msk_if_softc *sc_if, int jumbo)
652 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 &&
653 (sc_if->msk_ifp->if_capenable & IFCAP_RXCSUM) != 0) {
654 /* Wait until controller executes OP_TCPSTART command. */
655 for (i = 100; i > 0; i--) {
657 idx = CSR_READ_2(sc_if->msk_softc,
658 Y2_PREF_Q_ADDR(sc_if->msk_rxq,
659 PREF_UNIT_GET_IDX_REG));
664 device_printf(sc_if->msk_if_dev,
665 "prefetch unit stuck?\n");
669 * Fill consumed LE with free buffer. This can be done
670 * in Rx handler but we don't want to add special code
674 if (msk_jumbo_newbuf(sc_if, 0) != 0)
676 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
677 sc_if->msk_cdata.msk_jumbo_rx_ring_map,
678 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
680 if (msk_newbuf(sc_if, 0) != 0)
682 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_ring_tag,
683 sc_if->msk_cdata.msk_rx_ring_map,
684 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
686 sc_if->msk_cdata.msk_rx_prod = 0;
687 CSR_WRITE_2(sc_if->msk_softc,
688 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG),
689 sc_if->msk_cdata.msk_rx_prod);
695 msk_init_rx_ring(struct msk_if_softc *sc_if)
697 struct msk_ring_data *rd;
698 struct msk_rxdesc *rxd;
701 MSK_IF_LOCK_ASSERT(sc_if);
703 sc_if->msk_cdata.msk_rx_cons = 0;
704 sc_if->msk_cdata.msk_rx_prod = 0;
705 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM;
707 rd = &sc_if->msk_rdata;
708 bzero(rd->msk_rx_ring, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT);
709 for (i = prod = 0; i < MSK_RX_RING_CNT; i++) {
710 rxd = &sc_if->msk_cdata.msk_rxdesc[prod];
712 rxd->rx_le = &rd->msk_rx_ring[prod];
713 MSK_INC(prod, MSK_RX_RING_CNT);
715 nbuf = MSK_RX_BUF_CNT;
717 /* Have controller know how to compute Rx checksum. */
718 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 &&
719 (sc_if->msk_ifp->if_capenable & IFCAP_RXCSUM) != 0) {
721 rxd = &sc_if->msk_cdata.msk_rxdesc[prod];
723 rxd->rx_le = &rd->msk_rx_ring[prod];
724 rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 |
726 rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER);
727 MSK_INC(prod, MSK_RX_RING_CNT);
728 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT);
730 rxd = &sc_if->msk_cdata.msk_rxdesc[prod];
732 rxd->rx_le = &rd->msk_rx_ring[prod];
733 rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 |
735 rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER);
736 MSK_INC(prod, MSK_RX_RING_CNT);
737 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT);
740 for (i = 0; i < nbuf; i++) {
741 if (msk_newbuf(sc_if, prod) != 0)
743 MSK_RX_INC(prod, MSK_RX_RING_CNT);
746 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_ring_tag,
747 sc_if->msk_cdata.msk_rx_ring_map,
748 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
750 /* Update prefetch unit. */
751 sc_if->msk_cdata.msk_rx_prod = prod;
752 CSR_WRITE_2(sc_if->msk_softc,
753 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG),
754 (sc_if->msk_cdata.msk_rx_prod + MSK_RX_RING_CNT - 1) %
756 if (msk_rx_fill(sc_if, 0) != 0)
762 msk_init_jumbo_rx_ring(struct msk_if_softc *sc_if)
764 struct msk_ring_data *rd;
765 struct msk_rxdesc *rxd;
768 MSK_IF_LOCK_ASSERT(sc_if);
770 sc_if->msk_cdata.msk_rx_cons = 0;
771 sc_if->msk_cdata.msk_rx_prod = 0;
772 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM;
774 rd = &sc_if->msk_rdata;
775 bzero(rd->msk_jumbo_rx_ring,
776 sizeof(struct msk_rx_desc) * MSK_JUMBO_RX_RING_CNT);
777 for (i = prod = 0; i < MSK_JUMBO_RX_RING_CNT; i++) {
778 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod];
780 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod];
781 MSK_INC(prod, MSK_JUMBO_RX_RING_CNT);
783 nbuf = MSK_RX_BUF_CNT;
785 /* Have controller know how to compute Rx checksum. */
786 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 &&
787 (sc_if->msk_ifp->if_capenable & IFCAP_RXCSUM) != 0) {
789 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod];
791 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod];
792 rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 |
794 rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER);
795 MSK_INC(prod, MSK_JUMBO_RX_RING_CNT);
796 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT);
798 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod];
800 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod];
801 rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 |
803 rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER);
804 MSK_INC(prod, MSK_JUMBO_RX_RING_CNT);
805 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT);
808 for (i = 0; i < nbuf; i++) {
809 if (msk_jumbo_newbuf(sc_if, prod) != 0)
811 MSK_RX_INC(prod, MSK_JUMBO_RX_RING_CNT);
814 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
815 sc_if->msk_cdata.msk_jumbo_rx_ring_map,
816 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
818 /* Update prefetch unit. */
819 sc_if->msk_cdata.msk_rx_prod = prod;
820 CSR_WRITE_2(sc_if->msk_softc,
821 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG),
822 (sc_if->msk_cdata.msk_rx_prod + MSK_JUMBO_RX_RING_CNT - 1) %
823 MSK_JUMBO_RX_RING_CNT);
824 if (msk_rx_fill(sc_if, 1) != 0)
830 msk_init_tx_ring(struct msk_if_softc *sc_if)
832 struct msk_ring_data *rd;
833 struct msk_txdesc *txd;
836 sc_if->msk_cdata.msk_tso_mtu = 0;
837 sc_if->msk_cdata.msk_last_csum = 0;
838 sc_if->msk_cdata.msk_tx_prod = 0;
839 sc_if->msk_cdata.msk_tx_cons = 0;
840 sc_if->msk_cdata.msk_tx_cnt = 0;
841 sc_if->msk_cdata.msk_tx_high_addr = 0;
843 rd = &sc_if->msk_rdata;
844 bzero(rd->msk_tx_ring, sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT);
845 for (i = 0; i < MSK_TX_RING_CNT; i++) {
846 txd = &sc_if->msk_cdata.msk_txdesc[i];
848 txd->tx_le = &rd->msk_tx_ring[i];
851 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag,
852 sc_if->msk_cdata.msk_tx_ring_map,
853 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
857 msk_discard_rxbuf(struct msk_if_softc *sc_if, int idx)
859 struct msk_rx_desc *rx_le;
860 struct msk_rxdesc *rxd;
864 rxd = &sc_if->msk_cdata.msk_rxdesc[idx];
866 rx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER);
867 MSK_INC(idx, MSK_RX_RING_CNT);
869 rxd = &sc_if->msk_cdata.msk_rxdesc[idx];
872 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER);
876 msk_discard_jumbo_rxbuf(struct msk_if_softc *sc_if, int idx)
878 struct msk_rx_desc *rx_le;
879 struct msk_rxdesc *rxd;
883 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx];
885 rx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER);
886 MSK_INC(idx, MSK_JUMBO_RX_RING_CNT);
888 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx];
891 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER);
895 msk_newbuf(struct msk_if_softc *sc_if, int idx)
897 struct msk_rx_desc *rx_le;
898 struct msk_rxdesc *rxd;
900 bus_dma_segment_t segs[1];
904 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
908 m->m_len = m->m_pkthdr.len = MCLBYTES;
909 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0)
910 m_adj(m, ETHER_ALIGN);
911 #ifndef __NO_STRICT_ALIGNMENT
913 m_adj(m, MSK_RX_BUF_ALIGN);
916 if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_rx_tag,
917 sc_if->msk_cdata.msk_rx_sparemap, m, segs, &nsegs,
918 BUS_DMA_NOWAIT) != 0) {
922 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
924 rxd = &sc_if->msk_cdata.msk_rxdesc[idx];
927 rx_le->msk_addr = htole32(MSK_ADDR_HI(segs[0].ds_addr));
928 rx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER);
929 MSK_INC(idx, MSK_RX_RING_CNT);
930 rxd = &sc_if->msk_cdata.msk_rxdesc[idx];
932 if (rxd->rx_m != NULL) {
933 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap,
934 BUS_DMASYNC_POSTREAD);
935 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap);
938 map = rxd->rx_dmamap;
939 rxd->rx_dmamap = sc_if->msk_cdata.msk_rx_sparemap;
940 sc_if->msk_cdata.msk_rx_sparemap = map;
941 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap,
942 BUS_DMASYNC_PREREAD);
945 rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr));
947 htole32(segs[0].ds_len | OP_PACKET | HW_OWNER);
953 msk_jumbo_newbuf(struct msk_if_softc *sc_if, int idx)
955 struct msk_rx_desc *rx_le;
956 struct msk_rxdesc *rxd;
958 bus_dma_segment_t segs[1];
962 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES);
965 m->m_len = m->m_pkthdr.len = MJUM9BYTES;
966 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0)
967 m_adj(m, ETHER_ALIGN);
968 #ifndef __NO_STRICT_ALIGNMENT
970 m_adj(m, MSK_RX_BUF_ALIGN);
973 if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_jumbo_rx_tag,
974 sc_if->msk_cdata.msk_jumbo_rx_sparemap, m, segs, &nsegs,
975 BUS_DMA_NOWAIT) != 0) {
979 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
981 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx];
984 rx_le->msk_addr = htole32(MSK_ADDR_HI(segs[0].ds_addr));
985 rx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER);
986 MSK_INC(idx, MSK_JUMBO_RX_RING_CNT);
987 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx];
989 if (rxd->rx_m != NULL) {
990 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag,
991 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
992 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag,
996 map = rxd->rx_dmamap;
997 rxd->rx_dmamap = sc_if->msk_cdata.msk_jumbo_rx_sparemap;
998 sc_if->msk_cdata.msk_jumbo_rx_sparemap = map;
999 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, rxd->rx_dmamap,
1000 BUS_DMASYNC_PREREAD);
1003 rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr));
1004 rx_le->msk_control =
1005 htole32(segs[0].ds_len | OP_PACKET | HW_OWNER);
1011 * Set media options.
1014 msk_mediachange(struct ifnet *ifp)
1016 struct msk_if_softc *sc_if;
1017 struct mii_data *mii;
1020 sc_if = ifp->if_softc;
1023 mii = device_get_softc(sc_if->msk_miibus);
1024 error = mii_mediachg(mii);
1025 MSK_IF_UNLOCK(sc_if);
1031 * Report current media status.
1034 msk_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
1036 struct msk_if_softc *sc_if;
1037 struct mii_data *mii;
1039 sc_if = ifp->if_softc;
1041 if ((ifp->if_flags & IFF_UP) == 0) {
1042 MSK_IF_UNLOCK(sc_if);
1045 mii = device_get_softc(sc_if->msk_miibus);
1048 ifmr->ifm_active = mii->mii_media_active;
1049 ifmr->ifm_status = mii->mii_media_status;
1050 MSK_IF_UNLOCK(sc_if);
1054 msk_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
1056 struct msk_if_softc *sc_if;
1058 struct mii_data *mii;
1059 int error, mask, reinit;
1061 sc_if = ifp->if_softc;
1062 ifr = (struct ifreq *)data;
1068 if (ifr->ifr_mtu > MSK_JUMBO_MTU || ifr->ifr_mtu < ETHERMIN)
1070 else if (ifp->if_mtu != ifr->ifr_mtu) {
1071 if (ifr->ifr_mtu > ETHERMTU) {
1072 if ((sc_if->msk_flags & MSK_FLAG_JUMBO) == 0) {
1074 MSK_IF_UNLOCK(sc_if);
1077 if ((sc_if->msk_flags &
1078 MSK_FLAG_JUMBO_NOCSUM) != 0) {
1080 ~(MSK_CSUM_FEATURES | CSUM_TSO);
1081 ifp->if_capenable &=
1082 ~(IFCAP_TSO4 | IFCAP_TXCSUM);
1083 VLAN_CAPABILITIES(ifp);
1086 ifp->if_mtu = ifr->ifr_mtu;
1087 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1088 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1089 msk_init_locked(sc_if);
1092 MSK_IF_UNLOCK(sc_if);
1096 if ((ifp->if_flags & IFF_UP) != 0) {
1097 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
1098 ((ifp->if_flags ^ sc_if->msk_if_flags) &
1099 (IFF_PROMISC | IFF_ALLMULTI)) != 0)
1100 msk_rxfilter(sc_if);
1101 else if ((sc_if->msk_flags & MSK_FLAG_DETACH) == 0)
1102 msk_init_locked(sc_if);
1103 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1105 sc_if->msk_if_flags = ifp->if_flags;
1106 MSK_IF_UNLOCK(sc_if);
1111 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1112 msk_rxfilter(sc_if);
1113 MSK_IF_UNLOCK(sc_if);
1117 mii = device_get_softc(sc_if->msk_miibus);
1118 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1123 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1124 if ((mask & IFCAP_TXCSUM) != 0 &&
1125 (IFCAP_TXCSUM & ifp->if_capabilities) != 0) {
1126 ifp->if_capenable ^= IFCAP_TXCSUM;
1127 if ((IFCAP_TXCSUM & ifp->if_capenable) != 0)
1128 ifp->if_hwassist |= MSK_CSUM_FEATURES;
1130 ifp->if_hwassist &= ~MSK_CSUM_FEATURES;
1132 if ((mask & IFCAP_RXCSUM) != 0 &&
1133 (IFCAP_RXCSUM & ifp->if_capabilities) != 0) {
1134 ifp->if_capenable ^= IFCAP_RXCSUM;
1135 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0)
1138 if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
1139 (IFCAP_VLAN_HWCSUM & ifp->if_capabilities) != 0)
1140 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
1141 if ((mask & IFCAP_TSO4) != 0 &&
1142 (IFCAP_TSO4 & ifp->if_capabilities) != 0) {
1143 ifp->if_capenable ^= IFCAP_TSO4;
1144 if ((IFCAP_TSO4 & ifp->if_capenable) != 0)
1145 ifp->if_hwassist |= CSUM_TSO;
1147 ifp->if_hwassist &= ~CSUM_TSO;
1149 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
1150 (IFCAP_VLAN_HWTSO & ifp->if_capabilities) != 0)
1151 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
1152 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
1153 (IFCAP_VLAN_HWTAGGING & ifp->if_capabilities) != 0) {
1154 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1155 if ((IFCAP_VLAN_HWTAGGING & ifp->if_capenable) == 0)
1156 ifp->if_capenable &=
1157 ~(IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM);
1158 msk_setvlan(sc_if, ifp);
1160 if (ifp->if_mtu > ETHERMTU &&
1161 (sc_if->msk_flags & MSK_FLAG_JUMBO_NOCSUM) != 0) {
1162 ifp->if_hwassist &= ~(MSK_CSUM_FEATURES | CSUM_TSO);
1163 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TXCSUM);
1165 VLAN_CAPABILITIES(ifp);
1166 if (reinit > 0 && (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1167 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1168 msk_init_locked(sc_if);
1170 MSK_IF_UNLOCK(sc_if);
1173 error = ether_ioctl(ifp, command, data);
1181 mskc_probe(device_t dev)
1183 const struct msk_product *mp;
1184 uint16_t vendor, devid;
1187 vendor = pci_get_vendor(dev);
1188 devid = pci_get_device(dev);
1190 for (i = 0; i < nitems(msk_products); i++, mp++) {
1191 if (vendor == mp->msk_vendorid && devid == mp->msk_deviceid) {
1192 device_set_desc(dev, mp->msk_name);
1193 return (BUS_PROBE_DEFAULT);
1201 mskc_setup_rambuffer(struct msk_softc *sc)
1206 /* Get adapter SRAM size. */
1207 sc->msk_ramsize = CSR_READ_1(sc, B2_E_0) * 4;
1209 device_printf(sc->msk_dev,
1210 "RAM buffer size : %dKB\n", sc->msk_ramsize);
1211 if (sc->msk_ramsize == 0)
1214 sc->msk_pflags |= MSK_FLAG_RAMBUF;
1216 * Give receiver 2/3 of memory and round down to the multiple
1217 * of 1024. Tx/Rx RAM buffer size of Yukon II should be multiple
1220 sc->msk_rxqsize = rounddown((sc->msk_ramsize * 1024 * 2) / 3, 1024);
1221 sc->msk_txqsize = (sc->msk_ramsize * 1024) - sc->msk_rxqsize;
1222 for (i = 0, next = 0; i < sc->msk_num_port; i++) {
1223 sc->msk_rxqstart[i] = next;
1224 sc->msk_rxqend[i] = next + sc->msk_rxqsize - 1;
1225 next = sc->msk_rxqend[i] + 1;
1226 sc->msk_txqstart[i] = next;
1227 sc->msk_txqend[i] = next + sc->msk_txqsize - 1;
1228 next = sc->msk_txqend[i] + 1;
1230 device_printf(sc->msk_dev,
1231 "Port %d : Rx Queue %dKB(0x%08x:0x%08x)\n", i,
1232 sc->msk_rxqsize / 1024, sc->msk_rxqstart[i],
1234 device_printf(sc->msk_dev,
1235 "Port %d : Tx Queue %dKB(0x%08x:0x%08x)\n", i,
1236 sc->msk_txqsize / 1024, sc->msk_txqstart[i],
1245 msk_phy_power(struct msk_softc *sc, int mode)
1251 case MSK_PHY_POWERUP:
1252 /* Switch power to VCC (WA for VAUX problem). */
1253 CSR_WRITE_1(sc, B0_POWER_CTRL,
1254 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
1255 /* Disable Core Clock Division, set Clock Select to 0. */
1256 CSR_WRITE_4(sc, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
1259 if (sc->msk_hw_id == CHIP_ID_YUKON_XL &&
1260 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {
1261 /* Enable bits are inverted. */
1262 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
1263 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
1264 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS;
1267 * Enable PCI & Core Clock, enable clock gating for both Links.
1269 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val);
1271 our = CSR_PCI_READ_4(sc, PCI_OUR_REG_1);
1272 our &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
1273 if (sc->msk_hw_id == CHIP_ID_YUKON_XL) {
1274 if (sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {
1275 /* Deassert Low Power for 1st PHY. */
1276 our |= PCI_Y2_PHY1_COMA;
1277 if (sc->msk_num_port > 1)
1278 our |= PCI_Y2_PHY2_COMA;
1281 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U ||
1282 sc->msk_hw_id == CHIP_ID_YUKON_EX ||
1283 sc->msk_hw_id >= CHIP_ID_YUKON_FE_P) {
1284 val = CSR_PCI_READ_4(sc, PCI_OUR_REG_4);
1285 val &= (PCI_FORCE_ASPM_REQUEST |
1286 PCI_ASPM_GPHY_LINK_DOWN | PCI_ASPM_INT_FIFO_EMPTY |
1287 PCI_ASPM_CLKRUN_REQUEST);
1288 /* Set all bits to 0 except bits 15..12. */
1289 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_4, val);
1290 val = CSR_PCI_READ_4(sc, PCI_OUR_REG_5);
1291 val &= PCI_CTL_TIM_VMAIN_AV_MSK;
1292 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_5, val);
1293 CSR_PCI_WRITE_4(sc, PCI_CFG_REG_1, 0);
1294 CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_ON);
1296 * Disable status race, workaround for
1297 * Yukon EC Ultra & Yukon EX.
1299 val = CSR_READ_4(sc, B2_GP_IO);
1300 val |= GLB_GPIO_STAT_RACE_DIS;
1301 CSR_WRITE_4(sc, B2_GP_IO, val);
1302 CSR_READ_4(sc, B2_GP_IO);
1304 /* Release PHY from PowerDown/COMA mode. */
1305 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_1, our);
1307 for (i = 0; i < sc->msk_num_port; i++) {
1308 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL),
1310 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL),
1314 case MSK_PHY_POWERDOWN:
1315 val = CSR_PCI_READ_4(sc, PCI_OUR_REG_1);
1316 val |= PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD;
1317 if (sc->msk_hw_id == CHIP_ID_YUKON_XL &&
1318 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {
1319 val &= ~PCI_Y2_PHY1_COMA;
1320 if (sc->msk_num_port > 1)
1321 val &= ~PCI_Y2_PHY2_COMA;
1323 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_1, val);
1325 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
1326 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
1327 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS;
1328 if (sc->msk_hw_id == CHIP_ID_YUKON_XL &&
1329 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {
1330 /* Enable bits are inverted. */
1334 * Disable PCI & Core Clock, disable clock gating for
1337 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val);
1338 CSR_WRITE_1(sc, B0_POWER_CTRL,
1339 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF);
1347 mskc_reset(struct msk_softc *sc)
1355 if (sc->msk_hw_id >= CHIP_ID_YUKON_XL &&
1356 sc->msk_hw_id <= CHIP_ID_YUKON_SUPR) {
1357 if (sc->msk_hw_id == CHIP_ID_YUKON_EX ||
1358 sc->msk_hw_id == CHIP_ID_YUKON_SUPR) {
1359 CSR_WRITE_4(sc, B28_Y2_CPU_WDOG, 0);
1360 status = CSR_READ_2(sc, B28_Y2_ASF_HCU_CCSR);
1361 /* Clear AHB bridge & microcontroller reset. */
1362 status &= ~(Y2_ASF_HCU_CCSR_AHB_RST |
1363 Y2_ASF_HCU_CCSR_CPU_RST_MODE);
1364 /* Clear ASF microcontroller state. */
1365 status &= ~Y2_ASF_HCU_CCSR_UC_STATE_MSK;
1366 status &= ~Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE_MSK;
1367 CSR_WRITE_2(sc, B28_Y2_ASF_HCU_CCSR, status);
1368 CSR_WRITE_4(sc, B28_Y2_CPU_WDOG, 0);
1370 CSR_WRITE_1(sc, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
1371 CSR_WRITE_2(sc, B0_CTST, Y2_ASF_DISABLE);
1373 * Since we disabled ASF, S/W reset is required for
1376 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
1377 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR);
1380 /* Clear all error bits in the PCI status register. */
1381 status = pci_read_config(sc->msk_dev, PCIR_STATUS, 2);
1382 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1384 pci_write_config(sc->msk_dev, PCIR_STATUS, status |
1385 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT |
1386 PCIM_STATUS_RTABORT | PCIM_STATUS_MDPERR, 2);
1387 CSR_WRITE_2(sc, B0_CTST, CS_MRST_CLR);
1389 switch (sc->msk_bustype) {
1391 /* Clear all PEX errors. */
1392 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff);
1393 val = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT);
1394 if ((val & PEX_RX_OV) != 0) {
1395 sc->msk_intrmask &= ~Y2_IS_HW_ERR;
1396 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP;
1401 /* Set Cache Line Size to 2(8bytes) if configured to 0. */
1402 val = pci_read_config(sc->msk_dev, PCIR_CACHELNSZ, 1);
1404 pci_write_config(sc->msk_dev, PCIR_CACHELNSZ, 2, 1);
1405 if (sc->msk_bustype == MSK_PCIX_BUS) {
1406 /* Set Cache Line Size opt. */
1407 val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4);
1409 pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4);
1413 /* Set PHY power state. */
1414 msk_phy_power(sc, MSK_PHY_POWERUP);
1416 /* Reset GPHY/GMAC Control */
1417 for (i = 0; i < sc->msk_num_port; i++) {
1418 /* GPHY Control reset. */
1419 CSR_WRITE_1(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_SET);
1420 CSR_WRITE_1(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_CLR);
1421 /* GMAC Control reset. */
1422 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_SET);
1423 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_CLR);
1424 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_F_LOOPB_OFF);
1425 if (sc->msk_hw_id == CHIP_ID_YUKON_EX ||
1426 sc->msk_hw_id == CHIP_ID_YUKON_SUPR)
1427 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL),
1428 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON |
1432 if (sc->msk_hw_id == CHIP_ID_YUKON_SUPR &&
1433 sc->msk_hw_rev > CHIP_REV_YU_SU_B0)
1434 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, PCI_CLK_MACSEC_DIS);
1435 if (sc->msk_hw_id == CHIP_ID_YUKON_OPT && sc->msk_hw_rev == 0) {
1436 /* Disable PCIe PHY powerdown(reg 0x80, bit7). */
1437 CSR_WRITE_4(sc, Y2_PEX_PHY_DATA, (0x0080 << 16) | 0x0080);
1439 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1442 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_ON);
1444 /* Clear TWSI IRQ. */
1445 CSR_WRITE_4(sc, B2_I2C_IRQ, I2C_CLR_IRQ);
1447 /* Turn off hardware timer. */
1448 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_STOP);
1449 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_CLR_IRQ);
1451 /* Turn off descriptor polling. */
1452 CSR_WRITE_1(sc, B28_DPT_CTRL, DPT_STOP);
1454 /* Turn off time stamps. */
1455 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_STOP);
1456 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
1459 if (sc->msk_hw_id == CHIP_ID_YUKON_XL ||
1460 sc->msk_hw_id == CHIP_ID_YUKON_EC ||
1461 sc->msk_hw_id == CHIP_ID_YUKON_FE)
1464 /* Configure timeout values. */
1465 for (i = 0; initram > 0 && i < sc->msk_num_port; i++) {
1466 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_SET);
1467 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
1468 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R1),
1470 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA1),
1472 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS1),
1474 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R1),
1476 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA1),
1478 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS1),
1480 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R2),
1482 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA2),
1484 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS2),
1486 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R2),
1488 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA2),
1490 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS2),
1494 /* Disable all interrupts. */
1495 CSR_WRITE_4(sc, B0_HWE_IMSK, 0);
1496 CSR_READ_4(sc, B0_HWE_IMSK);
1497 CSR_WRITE_4(sc, B0_IMSK, 0);
1498 CSR_READ_4(sc, B0_IMSK);
1501 * On dual port PCI-X card, there is an problem where status
1502 * can be received out of order due to split transactions.
1504 if (sc->msk_pcixcap != 0 && sc->msk_num_port > 1) {
1507 pcix_cmd = pci_read_config(sc->msk_dev,
1508 sc->msk_pcixcap + PCIXR_COMMAND, 2);
1509 /* Clear Max Outstanding Split Transactions. */
1510 pcix_cmd &= ~PCIXM_COMMAND_MAX_SPLITS;
1511 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1512 pci_write_config(sc->msk_dev,
1513 sc->msk_pcixcap + PCIXR_COMMAND, pcix_cmd, 2);
1514 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1516 if (sc->msk_expcap != 0) {
1517 /* Change Max. Read Request Size to 2048 bytes. */
1518 if (pci_get_max_read_req(sc->msk_dev) == 512)
1519 pci_set_max_read_req(sc->msk_dev, 2048);
1522 /* Clear status list. */
1523 bzero(sc->msk_stat_ring,
1524 sizeof(struct msk_stat_desc) * sc->msk_stat_count);
1525 sc->msk_stat_cons = 0;
1526 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map,
1527 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1528 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_SET);
1529 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_CLR);
1530 /* Set the status list base address. */
1531 addr = sc->msk_stat_ring_paddr;
1532 CSR_WRITE_4(sc, STAT_LIST_ADDR_LO, MSK_ADDR_LO(addr));
1533 CSR_WRITE_4(sc, STAT_LIST_ADDR_HI, MSK_ADDR_HI(addr));
1534 /* Set the status list last index. */
1535 CSR_WRITE_2(sc, STAT_LAST_IDX, sc->msk_stat_count - 1);
1536 if (sc->msk_hw_id == CHIP_ID_YUKON_EC &&
1537 sc->msk_hw_rev == CHIP_REV_YU_EC_A1) {
1538 /* WA for dev. #4.3 */
1539 CSR_WRITE_2(sc, STAT_TX_IDX_TH, ST_TXTH_IDX_MASK);
1540 /* WA for dev. #4.18 */
1541 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x21);
1542 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x07);
1544 CSR_WRITE_2(sc, STAT_TX_IDX_TH, 0x0a);
1545 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x10);
1546 if (sc->msk_hw_id == CHIP_ID_YUKON_XL &&
1547 sc->msk_hw_rev == CHIP_REV_YU_XL_A0)
1548 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x04);
1550 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x10);
1551 CSR_WRITE_4(sc, STAT_ISR_TIMER_INI, 0x0190);
1554 * Use default value for STAT_ISR_TIMER_INI, STAT_LEV_TIMER_INI.
1556 CSR_WRITE_4(sc, STAT_TX_TIMER_INI, MSK_USECS(sc, 1000));
1558 /* Enable status unit. */
1559 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_OP_ON);
1561 CSR_WRITE_1(sc, STAT_TX_TIMER_CTRL, TIM_START);
1562 CSR_WRITE_1(sc, STAT_LEV_TIMER_CTRL, TIM_START);
1563 CSR_WRITE_1(sc, STAT_ISR_TIMER_CTRL, TIM_START);
1567 msk_probe(device_t dev)
1569 struct msk_softc *sc;
1572 sc = device_get_softc(device_get_parent(dev));
1574 * Not much to do here. We always know there will be
1575 * at least one GMAC present, and if there are two,
1576 * mskc_attach() will create a second device instance
1579 snprintf(desc, sizeof(desc),
1580 "Marvell Technology Group Ltd. %s Id 0x%02x Rev 0x%02x",
1581 model_name[sc->msk_hw_id - CHIP_ID_YUKON_XL], sc->msk_hw_id,
1583 device_set_desc_copy(dev, desc);
1585 return (BUS_PROBE_DEFAULT);
1589 msk_attach(device_t dev)
1591 struct msk_softc *sc;
1592 struct msk_if_softc *sc_if;
1594 struct msk_mii_data *mmd;
1602 sc_if = device_get_softc(dev);
1603 sc = device_get_softc(device_get_parent(dev));
1604 mmd = device_get_ivars(dev);
1607 sc_if->msk_if_dev = dev;
1608 sc_if->msk_port = port;
1609 sc_if->msk_softc = sc;
1610 sc_if->msk_flags = sc->msk_pflags;
1611 sc->msk_if[port] = sc_if;
1612 /* Setup Tx/Rx queue register offsets. */
1613 if (port == MSK_PORT_A) {
1614 sc_if->msk_txq = Q_XA1;
1615 sc_if->msk_txsq = Q_XS1;
1616 sc_if->msk_rxq = Q_R1;
1618 sc_if->msk_txq = Q_XA2;
1619 sc_if->msk_txsq = Q_XS2;
1620 sc_if->msk_rxq = Q_R2;
1623 callout_init_mtx(&sc_if->msk_tick_ch, &sc_if->msk_softc->msk_mtx, 0);
1624 msk_sysctl_node(sc_if);
1626 if ((error = msk_txrx_dma_alloc(sc_if)) != 0)
1628 msk_rx_dma_jalloc(sc_if);
1630 ifp = sc_if->msk_ifp = if_alloc(IFT_ETHER);
1632 device_printf(sc_if->msk_if_dev, "can not if_alloc()\n");
1636 ifp->if_softc = sc_if;
1637 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1638 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1639 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_TSO4;
1641 * Enable Rx checksum offloading if controller supports
1642 * new descriptor formant and controller is not Yukon XL.
1644 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 &&
1645 sc->msk_hw_id != CHIP_ID_YUKON_XL)
1646 ifp->if_capabilities |= IFCAP_RXCSUM;
1647 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0 &&
1648 (sc_if->msk_flags & MSK_FLAG_NORX_CSUM) == 0)
1649 ifp->if_capabilities |= IFCAP_RXCSUM;
1650 ifp->if_hwassist = MSK_CSUM_FEATURES | CSUM_TSO;
1651 ifp->if_capenable = ifp->if_capabilities;
1652 ifp->if_ioctl = msk_ioctl;
1653 ifp->if_start = msk_start;
1654 ifp->if_init = msk_init;
1655 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1);
1656 ifp->if_snd.ifq_drv_maxlen = MSK_TX_RING_CNT - 1;
1657 IFQ_SET_READY(&ifp->if_snd);
1659 * Get station address for this interface. Note that
1660 * dual port cards actually come with three station
1661 * addresses: one for each port, plus an extra. The
1662 * extra one is used by the SysKonnect driver software
1663 * as a 'virtual' station address for when both ports
1664 * are operating in failover mode. Currently we don't
1665 * use this extra address.
1668 for (i = 0; i < ETHER_ADDR_LEN; i++)
1669 eaddr[i] = CSR_READ_1(sc, B2_MAC_1 + (port * 8) + i);
1672 * Call MI attach routine. Can't hold locks when calling into ether_*.
1674 MSK_IF_UNLOCK(sc_if);
1675 ether_ifattach(ifp, eaddr);
1678 /* VLAN capability setup */
1679 ifp->if_capabilities |= IFCAP_VLAN_MTU;
1680 if ((sc_if->msk_flags & MSK_FLAG_NOHWVLAN) == 0) {
1682 * Due to Tx checksum offload hardware bugs, msk(4) manually
1683 * computes checksum for short frames. For VLAN tagged frames
1684 * this workaround does not work so disable checksum offload
1685 * for VLAN interface.
1687 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWTSO;
1689 * Enable Rx checksum offloading for VLAN tagged frames
1690 * if controller support new descriptor format.
1692 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0 &&
1693 (sc_if->msk_flags & MSK_FLAG_NORX_CSUM) == 0)
1694 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
1696 ifp->if_capenable = ifp->if_capabilities;
1698 * Disable RX checksum offloading on controllers that don't use
1699 * new descriptor format but give chance to enable it.
1701 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0)
1702 ifp->if_capenable &= ~IFCAP_RXCSUM;
1705 * Tell the upper layer(s) we support long frames.
1706 * Must appear after the call to ether_ifattach() because
1707 * ether_ifattach() sets ifi_hdrlen to the default value.
1709 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
1714 MSK_IF_UNLOCK(sc_if);
1715 error = mii_attach(dev, &sc_if->msk_miibus, ifp, msk_mediachange,
1716 msk_mediastatus, BMSR_DEFCAPMASK, PHY_ADDR_MARV, MII_OFFSET_ANY,
1719 device_printf(sc_if->msk_if_dev, "attaching PHYs failed\n");
1720 ether_ifdetach(ifp);
1727 /* Access should be ok even though lock has been dropped */
1728 sc->msk_if[port] = NULL;
1736 * Attach the interface. Allocate softc structures, do ifmedia
1737 * setup and ethernet/BPF attach.
1740 mskc_attach(device_t dev)
1742 struct msk_softc *sc;
1743 struct msk_mii_data *mmd;
1744 int error, msic, msir, reg;
1746 sc = device_get_softc(dev);
1748 mtx_init(&sc->msk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1752 * Map control/status registers.
1754 pci_enable_busmaster(dev);
1756 /* Allocate I/O resource */
1757 #ifdef MSK_USEIOSPACE
1758 sc->msk_res_spec = msk_res_spec_io;
1760 sc->msk_res_spec = msk_res_spec_mem;
1762 sc->msk_irq_spec = msk_irq_spec_legacy;
1763 error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res);
1765 if (sc->msk_res_spec == msk_res_spec_mem)
1766 sc->msk_res_spec = msk_res_spec_io;
1768 sc->msk_res_spec = msk_res_spec_mem;
1769 error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res);
1771 device_printf(dev, "couldn't allocate %s resources\n",
1772 sc->msk_res_spec == msk_res_spec_mem ? "memory" :
1774 mtx_destroy(&sc->msk_mtx);
1779 /* Enable all clocks before accessing any registers. */
1780 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, 0);
1782 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR);
1783 sc->msk_hw_id = CSR_READ_1(sc, B2_CHIP_ID);
1784 sc->msk_hw_rev = (CSR_READ_1(sc, B2_MAC_CFG) >> 4) & 0x0f;
1785 /* Bail out if chip is not recognized. */
1786 if (sc->msk_hw_id < CHIP_ID_YUKON_XL ||
1787 sc->msk_hw_id > CHIP_ID_YUKON_OPT ||
1788 sc->msk_hw_id == CHIP_ID_YUKON_UNKNOWN) {
1789 device_printf(dev, "unknown device: id=0x%02x, rev=0x%02x\n",
1790 sc->msk_hw_id, sc->msk_hw_rev);
1791 mtx_destroy(&sc->msk_mtx);
1795 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
1796 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
1797 OID_AUTO, "process_limit", CTLTYPE_INT | CTLFLAG_RW,
1798 &sc->msk_process_limit, 0, sysctl_hw_msk_proc_limit, "I",
1799 "max number of Rx events to process");
1801 sc->msk_process_limit = MSK_PROC_DEFAULT;
1802 error = resource_int_value(device_get_name(dev), device_get_unit(dev),
1803 "process_limit", &sc->msk_process_limit);
1805 if (sc->msk_process_limit < MSK_PROC_MIN ||
1806 sc->msk_process_limit > MSK_PROC_MAX) {
1807 device_printf(dev, "process_limit value out of range; "
1808 "using default: %d\n", MSK_PROC_DEFAULT);
1809 sc->msk_process_limit = MSK_PROC_DEFAULT;
1813 sc->msk_int_holdoff = MSK_INT_HOLDOFF_DEFAULT;
1814 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
1815 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
1816 "int_holdoff", CTLFLAG_RW, &sc->msk_int_holdoff, 0,
1817 "Maximum number of time to delay interrupts");
1818 resource_int_value(device_get_name(dev), device_get_unit(dev),
1819 "int_holdoff", &sc->msk_int_holdoff);
1821 sc->msk_pmd = CSR_READ_1(sc, B2_PMD_TYP);
1822 /* Check number of MACs. */
1823 sc->msk_num_port = 1;
1824 if ((CSR_READ_1(sc, B2_Y2_HW_RES) & CFG_DUAL_MAC_MSK) ==
1826 if (!(CSR_READ_1(sc, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
1830 /* Check bus type. */
1831 if (pci_find_cap(sc->msk_dev, PCIY_EXPRESS, ®) == 0) {
1832 sc->msk_bustype = MSK_PEX_BUS;
1833 sc->msk_expcap = reg;
1834 } else if (pci_find_cap(sc->msk_dev, PCIY_PCIX, ®) == 0) {
1835 sc->msk_bustype = MSK_PCIX_BUS;
1836 sc->msk_pcixcap = reg;
1838 sc->msk_bustype = MSK_PCI_BUS;
1840 switch (sc->msk_hw_id) {
1841 case CHIP_ID_YUKON_EC:
1842 sc->msk_clock = 125; /* 125 MHz */
1843 sc->msk_pflags |= MSK_FLAG_JUMBO;
1845 case CHIP_ID_YUKON_EC_U:
1846 sc->msk_clock = 125; /* 125 MHz */
1847 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_JUMBO_NOCSUM;
1849 case CHIP_ID_YUKON_EX:
1850 sc->msk_clock = 125; /* 125 MHz */
1851 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_DESCV2 |
1852 MSK_FLAG_AUTOTX_CSUM;
1854 * Yukon Extreme seems to have silicon bug for
1855 * automatic Tx checksum calculation capability.
1857 if (sc->msk_hw_rev == CHIP_REV_YU_EX_B0)
1858 sc->msk_pflags &= ~MSK_FLAG_AUTOTX_CSUM;
1860 * Yukon Extreme A0 could not use store-and-forward
1861 * for jumbo frames, so disable Tx checksum
1862 * offloading for jumbo frames.
1864 if (sc->msk_hw_rev == CHIP_REV_YU_EX_A0)
1865 sc->msk_pflags |= MSK_FLAG_JUMBO_NOCSUM;
1867 case CHIP_ID_YUKON_FE:
1868 sc->msk_clock = 100; /* 100 MHz */
1869 sc->msk_pflags |= MSK_FLAG_FASTETHER;
1871 case CHIP_ID_YUKON_FE_P:
1872 sc->msk_clock = 50; /* 50 MHz */
1873 sc->msk_pflags |= MSK_FLAG_FASTETHER | MSK_FLAG_DESCV2 |
1874 MSK_FLAG_AUTOTX_CSUM;
1875 if (sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) {
1878 * FE+ A0 has status LE writeback bug so msk(4)
1879 * does not rely on status word of received frame
1880 * in msk_rxeof() which in turn disables all
1881 * hardware assistance bits reported by the status
1882 * word as well as validity of the received frame.
1883 * Just pass received frames to upper stack with
1884 * minimal test and let upper stack handle them.
1886 sc->msk_pflags |= MSK_FLAG_NOHWVLAN |
1887 MSK_FLAG_NORXCHK | MSK_FLAG_NORX_CSUM;
1890 case CHIP_ID_YUKON_XL:
1891 sc->msk_clock = 156; /* 156 MHz */
1892 sc->msk_pflags |= MSK_FLAG_JUMBO;
1894 case CHIP_ID_YUKON_SUPR:
1895 sc->msk_clock = 125; /* 125 MHz */
1896 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_DESCV2 |
1897 MSK_FLAG_AUTOTX_CSUM;
1899 case CHIP_ID_YUKON_UL_2:
1900 sc->msk_clock = 125; /* 125 MHz */
1901 sc->msk_pflags |= MSK_FLAG_JUMBO;
1903 case CHIP_ID_YUKON_OPT:
1904 sc->msk_clock = 125; /* 125 MHz */
1905 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_DESCV2;
1908 sc->msk_clock = 156; /* 156 MHz */
1912 /* Allocate IRQ resources. */
1913 msic = pci_msi_count(dev);
1915 device_printf(dev, "MSI count : %d\n", msic);
1916 if (legacy_intr != 0)
1918 if (msi_disable == 0 && msic > 0) {
1920 if (pci_alloc_msi(dev, &msir) == 0) {
1922 sc->msk_pflags |= MSK_FLAG_MSI;
1923 sc->msk_irq_spec = msk_irq_spec_msi;
1925 pci_release_msi(dev);
1929 error = bus_alloc_resources(dev, sc->msk_irq_spec, sc->msk_irq);
1931 device_printf(dev, "couldn't allocate IRQ resources\n");
1935 if ((error = msk_status_dma_alloc(sc)) != 0)
1938 /* Set base interrupt mask. */
1939 sc->msk_intrmask = Y2_IS_HW_ERR | Y2_IS_STAT_BMU;
1940 sc->msk_intrhwemask = Y2_IS_TIST_OV | Y2_IS_MST_ERR |
1941 Y2_IS_IRQ_STAT | Y2_IS_PCI_EXP | Y2_IS_PCI_NEXP;
1943 /* Reset the adapter. */
1946 if ((error = mskc_setup_rambuffer(sc)) != 0)
1949 sc->msk_devs[MSK_PORT_A] = device_add_child(dev, "msk", -1);
1950 if (sc->msk_devs[MSK_PORT_A] == NULL) {
1951 device_printf(dev, "failed to add child for PORT_A\n");
1955 mmd = malloc(sizeof(struct msk_mii_data), M_DEVBUF, M_WAITOK | M_ZERO);
1956 mmd->port = MSK_PORT_A;
1957 mmd->pmd = sc->msk_pmd;
1958 mmd->mii_flags |= MIIF_DOPAUSE;
1959 if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S')
1960 mmd->mii_flags |= MIIF_HAVEFIBER;
1961 if (sc->msk_pmd == 'P')
1962 mmd->mii_flags |= MIIF_HAVEFIBER | MIIF_MACPRIV0;
1963 device_set_ivars(sc->msk_devs[MSK_PORT_A], mmd);
1965 if (sc->msk_num_port > 1) {
1966 sc->msk_devs[MSK_PORT_B] = device_add_child(dev, "msk", -1);
1967 if (sc->msk_devs[MSK_PORT_B] == NULL) {
1968 device_printf(dev, "failed to add child for PORT_B\n");
1972 mmd = malloc(sizeof(struct msk_mii_data), M_DEVBUF, M_WAITOK |
1974 mmd->port = MSK_PORT_B;
1975 mmd->pmd = sc->msk_pmd;
1976 if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S')
1977 mmd->mii_flags |= MIIF_HAVEFIBER;
1978 if (sc->msk_pmd == 'P')
1979 mmd->mii_flags |= MIIF_HAVEFIBER | MIIF_MACPRIV0;
1980 device_set_ivars(sc->msk_devs[MSK_PORT_B], mmd);
1983 error = bus_generic_attach(dev);
1985 device_printf(dev, "failed to attach port(s)\n");
1989 /* Hook interrupt last to avoid having to lock softc. */
1990 error = bus_setup_intr(dev, sc->msk_irq[0], INTR_TYPE_NET |
1991 INTR_MPSAFE, NULL, msk_intr, sc, &sc->msk_intrhand);
1993 device_printf(dev, "couldn't set up interrupt handler\n");
2004 * Shutdown hardware and free up resources. This can be called any
2005 * time after the mutex has been initialized. It is called in both
2006 * the error case in attach and the normal detach case so it needs
2007 * to be careful about only freeing resources that have actually been
2011 msk_detach(device_t dev)
2013 struct msk_softc *sc;
2014 struct msk_if_softc *sc_if;
2017 sc_if = device_get_softc(dev);
2018 KASSERT(mtx_initialized(&sc_if->msk_softc->msk_mtx),
2019 ("msk mutex not initialized in msk_detach"));
2022 ifp = sc_if->msk_ifp;
2023 if (device_is_attached(dev)) {
2025 sc_if->msk_flags |= MSK_FLAG_DETACH;
2027 /* Can't hold locks while calling detach. */
2028 MSK_IF_UNLOCK(sc_if);
2029 callout_drain(&sc_if->msk_tick_ch);
2031 ether_ifdetach(ifp);
2036 * We're generally called from mskc_detach() which is using
2037 * device_delete_child() to get to here. It's already trashed
2038 * miibus for us, so don't do it here or we'll panic.
2040 * if (sc_if->msk_miibus != NULL) {
2041 * device_delete_child(dev, sc_if->msk_miibus);
2042 * sc_if->msk_miibus = NULL;
2046 msk_rx_dma_jfree(sc_if);
2047 msk_txrx_dma_free(sc_if);
2048 bus_generic_detach(dev);
2050 sc = sc_if->msk_softc;
2051 sc->msk_if[sc_if->msk_port] = NULL;
2052 MSK_IF_UNLOCK(sc_if);
2060 mskc_detach(device_t dev)
2062 struct msk_softc *sc;
2064 sc = device_get_softc(dev);
2065 KASSERT(mtx_initialized(&sc->msk_mtx), ("msk mutex not initialized"));
2067 if (device_is_alive(dev)) {
2068 if (sc->msk_devs[MSK_PORT_A] != NULL) {
2069 free(device_get_ivars(sc->msk_devs[MSK_PORT_A]),
2071 device_delete_child(dev, sc->msk_devs[MSK_PORT_A]);
2073 if (sc->msk_devs[MSK_PORT_B] != NULL) {
2074 free(device_get_ivars(sc->msk_devs[MSK_PORT_B]),
2076 device_delete_child(dev, sc->msk_devs[MSK_PORT_B]);
2078 bus_generic_detach(dev);
2081 /* Disable all interrupts. */
2082 CSR_WRITE_4(sc, B0_IMSK, 0);
2083 CSR_READ_4(sc, B0_IMSK);
2084 CSR_WRITE_4(sc, B0_HWE_IMSK, 0);
2085 CSR_READ_4(sc, B0_HWE_IMSK);
2088 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_OFF);
2090 /* Put hardware reset. */
2091 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
2093 msk_status_dma_free(sc);
2095 if (sc->msk_intrhand) {
2096 bus_teardown_intr(dev, sc->msk_irq[0], sc->msk_intrhand);
2097 sc->msk_intrhand = NULL;
2099 bus_release_resources(dev, sc->msk_irq_spec, sc->msk_irq);
2100 if ((sc->msk_pflags & MSK_FLAG_MSI) != 0)
2101 pci_release_msi(dev);
2102 bus_release_resources(dev, sc->msk_res_spec, sc->msk_res);
2103 mtx_destroy(&sc->msk_mtx);
2108 static bus_dma_tag_t
2109 mskc_get_dma_tag(device_t bus, device_t child __unused)
2112 return (bus_get_dma_tag(bus));
2115 struct msk_dmamap_arg {
2116 bus_addr_t msk_busaddr;
2120 msk_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2122 struct msk_dmamap_arg *ctx;
2127 ctx->msk_busaddr = segs[0].ds_addr;
2130 /* Create status DMA region. */
2132 msk_status_dma_alloc(struct msk_softc *sc)
2134 struct msk_dmamap_arg ctx;
2139 * It seems controller requires number of status LE entries
2140 * is power of 2 and the maximum number of status LE entries
2141 * is 4096. For dual-port controllers, the number of status
2142 * LE entries should be large enough to hold both port's
2145 count = 3 * MSK_RX_RING_CNT + MSK_TX_RING_CNT;
2146 count = imin(4096, roundup2(count, 1024));
2147 sc->msk_stat_count = count;
2148 stat_sz = count * sizeof(struct msk_stat_desc);
2149 error = bus_dma_tag_create(
2150 bus_get_dma_tag(sc->msk_dev), /* parent */
2151 MSK_STAT_ALIGN, 0, /* alignment, boundary */
2152 BUS_SPACE_MAXADDR, /* lowaddr */
2153 BUS_SPACE_MAXADDR, /* highaddr */
2154 NULL, NULL, /* filter, filterarg */
2155 stat_sz, /* maxsize */
2157 stat_sz, /* maxsegsize */
2159 NULL, NULL, /* lockfunc, lockarg */
2162 device_printf(sc->msk_dev,
2163 "failed to create status DMA tag\n");
2167 /* Allocate DMA'able memory and load the DMA map for status ring. */
2168 error = bus_dmamem_alloc(sc->msk_stat_tag,
2169 (void **)&sc->msk_stat_ring, BUS_DMA_WAITOK | BUS_DMA_COHERENT |
2170 BUS_DMA_ZERO, &sc->msk_stat_map);
2172 device_printf(sc->msk_dev,
2173 "failed to allocate DMA'able memory for status ring\n");
2177 ctx.msk_busaddr = 0;
2178 error = bus_dmamap_load(sc->msk_stat_tag, sc->msk_stat_map,
2179 sc->msk_stat_ring, stat_sz, msk_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
2181 device_printf(sc->msk_dev,
2182 "failed to load DMA'able memory for status ring\n");
2185 sc->msk_stat_ring_paddr = ctx.msk_busaddr;
2191 msk_status_dma_free(struct msk_softc *sc)
2194 /* Destroy status block. */
2195 if (sc->msk_stat_tag) {
2196 if (sc->msk_stat_ring_paddr) {
2197 bus_dmamap_unload(sc->msk_stat_tag, sc->msk_stat_map);
2198 sc->msk_stat_ring_paddr = 0;
2200 if (sc->msk_stat_ring) {
2201 bus_dmamem_free(sc->msk_stat_tag,
2202 sc->msk_stat_ring, sc->msk_stat_map);
2203 sc->msk_stat_ring = NULL;
2205 bus_dma_tag_destroy(sc->msk_stat_tag);
2206 sc->msk_stat_tag = NULL;
2211 msk_txrx_dma_alloc(struct msk_if_softc *sc_if)
2213 struct msk_dmamap_arg ctx;
2214 struct msk_txdesc *txd;
2215 struct msk_rxdesc *rxd;
2219 /* Create parent DMA tag. */
2220 error = bus_dma_tag_create(
2221 bus_get_dma_tag(sc_if->msk_if_dev), /* parent */
2222 1, 0, /* alignment, boundary */
2223 BUS_SPACE_MAXADDR, /* lowaddr */
2224 BUS_SPACE_MAXADDR, /* highaddr */
2225 NULL, NULL, /* filter, filterarg */
2226 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
2228 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
2230 NULL, NULL, /* lockfunc, lockarg */
2231 &sc_if->msk_cdata.msk_parent_tag);
2233 device_printf(sc_if->msk_if_dev,
2234 "failed to create parent DMA tag\n");
2237 /* Create tag for Tx ring. */
2238 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
2239 MSK_RING_ALIGN, 0, /* alignment, boundary */
2240 BUS_SPACE_MAXADDR, /* lowaddr */
2241 BUS_SPACE_MAXADDR, /* highaddr */
2242 NULL, NULL, /* filter, filterarg */
2243 MSK_TX_RING_SZ, /* maxsize */
2245 MSK_TX_RING_SZ, /* maxsegsize */
2247 NULL, NULL, /* lockfunc, lockarg */
2248 &sc_if->msk_cdata.msk_tx_ring_tag);
2250 device_printf(sc_if->msk_if_dev,
2251 "failed to create Tx ring DMA tag\n");
2255 /* Create tag for Rx ring. */
2256 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
2257 MSK_RING_ALIGN, 0, /* alignment, boundary */
2258 BUS_SPACE_MAXADDR, /* lowaddr */
2259 BUS_SPACE_MAXADDR, /* highaddr */
2260 NULL, NULL, /* filter, filterarg */
2261 MSK_RX_RING_SZ, /* maxsize */
2263 MSK_RX_RING_SZ, /* maxsegsize */
2265 NULL, NULL, /* lockfunc, lockarg */
2266 &sc_if->msk_cdata.msk_rx_ring_tag);
2268 device_printf(sc_if->msk_if_dev,
2269 "failed to create Rx ring DMA tag\n");
2273 /* Create tag for Tx buffers. */
2274 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
2275 1, 0, /* alignment, boundary */
2276 BUS_SPACE_MAXADDR, /* lowaddr */
2277 BUS_SPACE_MAXADDR, /* highaddr */
2278 NULL, NULL, /* filter, filterarg */
2279 MSK_TSO_MAXSIZE, /* maxsize */
2280 MSK_MAXTXSEGS, /* nsegments */
2281 MSK_TSO_MAXSGSIZE, /* maxsegsize */
2283 NULL, NULL, /* lockfunc, lockarg */
2284 &sc_if->msk_cdata.msk_tx_tag);
2286 device_printf(sc_if->msk_if_dev,
2287 "failed to create Tx DMA tag\n");
2293 * Workaround hardware hang which seems to happen when Rx buffer
2294 * is not aligned on multiple of FIFO word(8 bytes).
2296 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0)
2297 rxalign = MSK_RX_BUF_ALIGN;
2298 /* Create tag for Rx buffers. */
2299 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
2300 rxalign, 0, /* alignment, boundary */
2301 BUS_SPACE_MAXADDR, /* lowaddr */
2302 BUS_SPACE_MAXADDR, /* highaddr */
2303 NULL, NULL, /* filter, filterarg */
2304 MCLBYTES, /* maxsize */
2306 MCLBYTES, /* maxsegsize */
2308 NULL, NULL, /* lockfunc, lockarg */
2309 &sc_if->msk_cdata.msk_rx_tag);
2311 device_printf(sc_if->msk_if_dev,
2312 "failed to create Rx DMA tag\n");
2316 /* Allocate DMA'able memory and load the DMA map for Tx ring. */
2317 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_tx_ring_tag,
2318 (void **)&sc_if->msk_rdata.msk_tx_ring, BUS_DMA_WAITOK |
2319 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_tx_ring_map);
2321 device_printf(sc_if->msk_if_dev,
2322 "failed to allocate DMA'able memory for Tx ring\n");
2326 ctx.msk_busaddr = 0;
2327 error = bus_dmamap_load(sc_if->msk_cdata.msk_tx_ring_tag,
2328 sc_if->msk_cdata.msk_tx_ring_map, sc_if->msk_rdata.msk_tx_ring,
2329 MSK_TX_RING_SZ, msk_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
2331 device_printf(sc_if->msk_if_dev,
2332 "failed to load DMA'able memory for Tx ring\n");
2335 sc_if->msk_rdata.msk_tx_ring_paddr = ctx.msk_busaddr;
2337 /* Allocate DMA'able memory and load the DMA map for Rx ring. */
2338 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_rx_ring_tag,
2339 (void **)&sc_if->msk_rdata.msk_rx_ring, BUS_DMA_WAITOK |
2340 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_rx_ring_map);
2342 device_printf(sc_if->msk_if_dev,
2343 "failed to allocate DMA'able memory for Rx ring\n");
2347 ctx.msk_busaddr = 0;
2348 error = bus_dmamap_load(sc_if->msk_cdata.msk_rx_ring_tag,
2349 sc_if->msk_cdata.msk_rx_ring_map, sc_if->msk_rdata.msk_rx_ring,
2350 MSK_RX_RING_SZ, msk_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
2352 device_printf(sc_if->msk_if_dev,
2353 "failed to load DMA'able memory for Rx ring\n");
2356 sc_if->msk_rdata.msk_rx_ring_paddr = ctx.msk_busaddr;
2358 /* Create DMA maps for Tx buffers. */
2359 for (i = 0; i < MSK_TX_RING_CNT; i++) {
2360 txd = &sc_if->msk_cdata.msk_txdesc[i];
2362 txd->tx_dmamap = NULL;
2363 error = bus_dmamap_create(sc_if->msk_cdata.msk_tx_tag, 0,
2366 device_printf(sc_if->msk_if_dev,
2367 "failed to create Tx dmamap\n");
2371 /* Create DMA maps for Rx buffers. */
2372 if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0,
2373 &sc_if->msk_cdata.msk_rx_sparemap)) != 0) {
2374 device_printf(sc_if->msk_if_dev,
2375 "failed to create spare Rx dmamap\n");
2378 for (i = 0; i < MSK_RX_RING_CNT; i++) {
2379 rxd = &sc_if->msk_cdata.msk_rxdesc[i];
2381 rxd->rx_dmamap = NULL;
2382 error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0,
2385 device_printf(sc_if->msk_if_dev,
2386 "failed to create Rx dmamap\n");
2396 msk_rx_dma_jalloc(struct msk_if_softc *sc_if)
2398 struct msk_dmamap_arg ctx;
2399 struct msk_rxdesc *jrxd;
2403 if (jumbo_disable != 0 || (sc_if->msk_flags & MSK_FLAG_JUMBO) == 0) {
2404 sc_if->msk_flags &= ~MSK_FLAG_JUMBO;
2405 device_printf(sc_if->msk_if_dev,
2406 "disabling jumbo frame support\n");
2409 /* Create tag for jumbo Rx ring. */
2410 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
2411 MSK_RING_ALIGN, 0, /* alignment, boundary */
2412 BUS_SPACE_MAXADDR, /* lowaddr */
2413 BUS_SPACE_MAXADDR, /* highaddr */
2414 NULL, NULL, /* filter, filterarg */
2415 MSK_JUMBO_RX_RING_SZ, /* maxsize */
2417 MSK_JUMBO_RX_RING_SZ, /* maxsegsize */
2419 NULL, NULL, /* lockfunc, lockarg */
2420 &sc_if->msk_cdata.msk_jumbo_rx_ring_tag);
2422 device_printf(sc_if->msk_if_dev,
2423 "failed to create jumbo Rx ring DMA tag\n");
2429 * Workaround hardware hang which seems to happen when Rx buffer
2430 * is not aligned on multiple of FIFO word(8 bytes).
2432 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0)
2433 rxalign = MSK_RX_BUF_ALIGN;
2434 /* Create tag for jumbo Rx buffers. */
2435 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
2436 rxalign, 0, /* alignment, boundary */
2437 BUS_SPACE_MAXADDR, /* lowaddr */
2438 BUS_SPACE_MAXADDR, /* highaddr */
2439 NULL, NULL, /* filter, filterarg */
2440 MJUM9BYTES, /* maxsize */
2442 MJUM9BYTES, /* maxsegsize */
2444 NULL, NULL, /* lockfunc, lockarg */
2445 &sc_if->msk_cdata.msk_jumbo_rx_tag);
2447 device_printf(sc_if->msk_if_dev,
2448 "failed to create jumbo Rx DMA tag\n");
2452 /* Allocate DMA'able memory and load the DMA map for jumbo Rx ring. */
2453 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
2454 (void **)&sc_if->msk_rdata.msk_jumbo_rx_ring,
2455 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
2456 &sc_if->msk_cdata.msk_jumbo_rx_ring_map);
2458 device_printf(sc_if->msk_if_dev,
2459 "failed to allocate DMA'able memory for jumbo Rx ring\n");
2463 ctx.msk_busaddr = 0;
2464 error = bus_dmamap_load(sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
2465 sc_if->msk_cdata.msk_jumbo_rx_ring_map,
2466 sc_if->msk_rdata.msk_jumbo_rx_ring, MSK_JUMBO_RX_RING_SZ,
2467 msk_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
2469 device_printf(sc_if->msk_if_dev,
2470 "failed to load DMA'able memory for jumbo Rx ring\n");
2473 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr = ctx.msk_busaddr;
2475 /* Create DMA maps for jumbo Rx buffers. */
2476 if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0,
2477 &sc_if->msk_cdata.msk_jumbo_rx_sparemap)) != 0) {
2478 device_printf(sc_if->msk_if_dev,
2479 "failed to create spare jumbo Rx dmamap\n");
2482 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) {
2483 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i];
2485 jrxd->rx_dmamap = NULL;
2486 error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0,
2489 device_printf(sc_if->msk_if_dev,
2490 "failed to create jumbo Rx dmamap\n");
2498 msk_rx_dma_jfree(sc_if);
2499 device_printf(sc_if->msk_if_dev, "disabling jumbo frame support "
2500 "due to resource shortage\n");
2501 sc_if->msk_flags &= ~MSK_FLAG_JUMBO;
2506 msk_txrx_dma_free(struct msk_if_softc *sc_if)
2508 struct msk_txdesc *txd;
2509 struct msk_rxdesc *rxd;
2513 if (sc_if->msk_cdata.msk_tx_ring_tag) {
2514 if (sc_if->msk_rdata.msk_tx_ring_paddr)
2515 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_ring_tag,
2516 sc_if->msk_cdata.msk_tx_ring_map);
2517 if (sc_if->msk_rdata.msk_tx_ring)
2518 bus_dmamem_free(sc_if->msk_cdata.msk_tx_ring_tag,
2519 sc_if->msk_rdata.msk_tx_ring,
2520 sc_if->msk_cdata.msk_tx_ring_map);
2521 sc_if->msk_rdata.msk_tx_ring = NULL;
2522 sc_if->msk_rdata.msk_tx_ring_paddr = 0;
2523 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_ring_tag);
2524 sc_if->msk_cdata.msk_tx_ring_tag = NULL;
2527 if (sc_if->msk_cdata.msk_rx_ring_tag) {
2528 if (sc_if->msk_rdata.msk_rx_ring_paddr)
2529 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_ring_tag,
2530 sc_if->msk_cdata.msk_rx_ring_map);
2531 if (sc_if->msk_rdata.msk_rx_ring)
2532 bus_dmamem_free(sc_if->msk_cdata.msk_rx_ring_tag,
2533 sc_if->msk_rdata.msk_rx_ring,
2534 sc_if->msk_cdata.msk_rx_ring_map);
2535 sc_if->msk_rdata.msk_rx_ring = NULL;
2536 sc_if->msk_rdata.msk_rx_ring_paddr = 0;
2537 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_ring_tag);
2538 sc_if->msk_cdata.msk_rx_ring_tag = NULL;
2541 if (sc_if->msk_cdata.msk_tx_tag) {
2542 for (i = 0; i < MSK_TX_RING_CNT; i++) {
2543 txd = &sc_if->msk_cdata.msk_txdesc[i];
2544 if (txd->tx_dmamap) {
2545 bus_dmamap_destroy(sc_if->msk_cdata.msk_tx_tag,
2547 txd->tx_dmamap = NULL;
2550 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_tag);
2551 sc_if->msk_cdata.msk_tx_tag = NULL;
2554 if (sc_if->msk_cdata.msk_rx_tag) {
2555 for (i = 0; i < MSK_RX_RING_CNT; i++) {
2556 rxd = &sc_if->msk_cdata.msk_rxdesc[i];
2557 if (rxd->rx_dmamap) {
2558 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag,
2560 rxd->rx_dmamap = NULL;
2563 if (sc_if->msk_cdata.msk_rx_sparemap) {
2564 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag,
2565 sc_if->msk_cdata.msk_rx_sparemap);
2566 sc_if->msk_cdata.msk_rx_sparemap = 0;
2568 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_tag);
2569 sc_if->msk_cdata.msk_rx_tag = NULL;
2571 if (sc_if->msk_cdata.msk_parent_tag) {
2572 bus_dma_tag_destroy(sc_if->msk_cdata.msk_parent_tag);
2573 sc_if->msk_cdata.msk_parent_tag = NULL;
2578 msk_rx_dma_jfree(struct msk_if_softc *sc_if)
2580 struct msk_rxdesc *jrxd;
2583 /* Jumbo Rx ring. */
2584 if (sc_if->msk_cdata.msk_jumbo_rx_ring_tag) {
2585 if (sc_if->msk_rdata.msk_jumbo_rx_ring_paddr)
2586 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
2587 sc_if->msk_cdata.msk_jumbo_rx_ring_map);
2588 if (sc_if->msk_rdata.msk_jumbo_rx_ring)
2589 bus_dmamem_free(sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
2590 sc_if->msk_rdata.msk_jumbo_rx_ring,
2591 sc_if->msk_cdata.msk_jumbo_rx_ring_map);
2592 sc_if->msk_rdata.msk_jumbo_rx_ring = NULL;
2593 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr = 0;
2594 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_ring_tag);
2595 sc_if->msk_cdata.msk_jumbo_rx_ring_tag = NULL;
2597 /* Jumbo Rx buffers. */
2598 if (sc_if->msk_cdata.msk_jumbo_rx_tag) {
2599 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) {
2600 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i];
2601 if (jrxd->rx_dmamap) {
2603 sc_if->msk_cdata.msk_jumbo_rx_tag,
2605 jrxd->rx_dmamap = NULL;
2608 if (sc_if->msk_cdata.msk_jumbo_rx_sparemap) {
2609 bus_dmamap_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag,
2610 sc_if->msk_cdata.msk_jumbo_rx_sparemap);
2611 sc_if->msk_cdata.msk_jumbo_rx_sparemap = 0;
2613 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag);
2614 sc_if->msk_cdata.msk_jumbo_rx_tag = NULL;
2619 msk_encap(struct msk_if_softc *sc_if, struct mbuf **m_head)
2621 struct msk_txdesc *txd, *txd_last;
2622 struct msk_tx_desc *tx_le;
2625 bus_dma_segment_t txsegs[MSK_MAXTXSEGS];
2626 uint32_t control, csum, prod, si;
2627 uint16_t offset, tcp_offset, tso_mtu;
2628 int error, i, nseg, tso;
2630 MSK_IF_LOCK_ASSERT(sc_if);
2632 tcp_offset = offset = 0;
2634 if (((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) == 0 &&
2635 (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) != 0) ||
2636 ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 &&
2637 (m->m_pkthdr.csum_flags & CSUM_TSO) != 0)) {
2639 * Since mbuf has no protocol specific structure information
2640 * in it we have to inspect protocol information here to
2641 * setup TSO and checksum offload. I don't know why Marvell
2642 * made a such decision in chip design because other GigE
2643 * hardwares normally takes care of all these chores in
2644 * hardware. However, TSO performance of Yukon II is very
2645 * good such that it's worth to implement it.
2647 struct ether_header *eh;
2651 if (M_WRITABLE(m) == 0) {
2652 /* Get a writable copy. */
2653 m = m_dup(*m_head, M_NOWAIT);
2662 offset = sizeof(struct ether_header);
2663 m = m_pullup(m, offset);
2668 eh = mtod(m, struct ether_header *);
2669 /* Check if hardware VLAN insertion is off. */
2670 if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
2671 offset = sizeof(struct ether_vlan_header);
2672 m = m_pullup(m, offset);
2678 m = m_pullup(m, offset + sizeof(struct ip));
2683 ip = (struct ip *)(mtod(m, char *) + offset);
2684 offset += (ip->ip_hl << 2);
2685 tcp_offset = offset;
2686 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
2687 m = m_pullup(m, offset + sizeof(struct tcphdr));
2692 tcp = (struct tcphdr *)(mtod(m, char *) + offset);
2693 offset += (tcp->th_off << 2);
2694 } else if ((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) == 0 &&
2695 (m->m_pkthdr.len < MSK_MIN_FRAMELEN) &&
2696 (m->m_pkthdr.csum_flags & CSUM_TCP) != 0) {
2698 * It seems that Yukon II has Tx checksum offload bug
2699 * for small TCP packets that's less than 60 bytes in
2700 * size (e.g. TCP window probe packet, pure ACK packet).
2701 * Common work around like padding with zeros to make
2702 * the frame minimum ethernet frame size didn't work at
2704 * Instead of disabling checksum offload completely we
2705 * resort to S/W checksum routine when we encounter
2707 * Short UDP packets appear to be handled correctly by
2708 * Yukon II. Also I assume this bug does not happen on
2709 * controllers that use newer descriptor format or
2710 * automatic Tx checksum calculation.
2712 m = m_pullup(m, offset + sizeof(struct tcphdr));
2717 *(uint16_t *)(m->m_data + offset +
2718 m->m_pkthdr.csum_data) = in_cksum_skip(m,
2719 m->m_pkthdr.len, offset);
2720 m->m_pkthdr.csum_flags &= ~CSUM_TCP;
2725 prod = sc_if->msk_cdata.msk_tx_prod;
2726 txd = &sc_if->msk_cdata.msk_txdesc[prod];
2728 map = txd->tx_dmamap;
2729 error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag, map,
2730 *m_head, txsegs, &nseg, BUS_DMA_NOWAIT);
2731 if (error == EFBIG) {
2732 m = m_collapse(*m_head, M_NOWAIT, MSK_MAXTXSEGS);
2739 error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag,
2740 map, *m_head, txsegs, &nseg, BUS_DMA_NOWAIT);
2746 } else if (error != 0)
2754 /* Check number of available descriptors. */
2755 if (sc_if->msk_cdata.msk_tx_cnt + nseg >=
2756 (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT)) {
2757 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, map);
2765 /* Check TSO support. */
2766 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
2767 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0)
2768 tso_mtu = m->m_pkthdr.tso_segsz;
2770 tso_mtu = offset + m->m_pkthdr.tso_segsz;
2771 if (tso_mtu != sc_if->msk_cdata.msk_tso_mtu) {
2772 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2773 tx_le->msk_addr = htole32(tso_mtu);
2774 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0)
2775 tx_le->msk_control = htole32(OP_MSS | HW_OWNER);
2777 tx_le->msk_control =
2778 htole32(OP_LRGLEN | HW_OWNER);
2779 sc_if->msk_cdata.msk_tx_cnt++;
2780 MSK_INC(prod, MSK_TX_RING_CNT);
2781 sc_if->msk_cdata.msk_tso_mtu = tso_mtu;
2785 /* Check if we have a VLAN tag to insert. */
2786 if ((m->m_flags & M_VLANTAG) != 0) {
2787 if (tx_le == NULL) {
2788 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2789 tx_le->msk_addr = htole32(0);
2790 tx_le->msk_control = htole32(OP_VLAN | HW_OWNER |
2791 htons(m->m_pkthdr.ether_vtag));
2792 sc_if->msk_cdata.msk_tx_cnt++;
2793 MSK_INC(prod, MSK_TX_RING_CNT);
2795 tx_le->msk_control |= htole32(OP_VLAN |
2796 htons(m->m_pkthdr.ether_vtag));
2798 control |= INS_VLAN;
2800 /* Check if we have to handle checksum offload. */
2801 if (tso == 0 && (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) != 0) {
2802 if ((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) != 0)
2805 control |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
2806 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0)
2808 /* Checksum write position. */
2809 csum = (tcp_offset + m->m_pkthdr.csum_data) & 0xffff;
2810 /* Checksum start position. */
2811 csum |= (uint32_t)tcp_offset << 16;
2812 if (csum != sc_if->msk_cdata.msk_last_csum) {
2813 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2814 tx_le->msk_addr = htole32(csum);
2815 tx_le->msk_control = htole32(1 << 16 |
2816 (OP_TCPLISW | HW_OWNER));
2817 sc_if->msk_cdata.msk_tx_cnt++;
2818 MSK_INC(prod, MSK_TX_RING_CNT);
2819 sc_if->msk_cdata.msk_last_csum = csum;
2824 #ifdef MSK_64BIT_DMA
2825 if (MSK_ADDR_HI(txsegs[0].ds_addr) !=
2826 sc_if->msk_cdata.msk_tx_high_addr) {
2827 sc_if->msk_cdata.msk_tx_high_addr =
2828 MSK_ADDR_HI(txsegs[0].ds_addr);
2829 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2830 tx_le->msk_addr = htole32(MSK_ADDR_HI(txsegs[0].ds_addr));
2831 tx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER);
2832 sc_if->msk_cdata.msk_tx_cnt++;
2833 MSK_INC(prod, MSK_TX_RING_CNT);
2837 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2838 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[0].ds_addr));
2840 tx_le->msk_control = htole32(txsegs[0].ds_len | control |
2843 tx_le->msk_control = htole32(txsegs[0].ds_len | control |
2845 sc_if->msk_cdata.msk_tx_cnt++;
2846 MSK_INC(prod, MSK_TX_RING_CNT);
2848 for (i = 1; i < nseg; i++) {
2849 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2850 #ifdef MSK_64BIT_DMA
2851 if (MSK_ADDR_HI(txsegs[i].ds_addr) !=
2852 sc_if->msk_cdata.msk_tx_high_addr) {
2853 sc_if->msk_cdata.msk_tx_high_addr =
2854 MSK_ADDR_HI(txsegs[i].ds_addr);
2855 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2857 htole32(MSK_ADDR_HI(txsegs[i].ds_addr));
2858 tx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER);
2859 sc_if->msk_cdata.msk_tx_cnt++;
2860 MSK_INC(prod, MSK_TX_RING_CNT);
2861 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2864 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[i].ds_addr));
2865 tx_le->msk_control = htole32(txsegs[i].ds_len | control |
2866 OP_BUFFER | HW_OWNER);
2867 sc_if->msk_cdata.msk_tx_cnt++;
2868 MSK_INC(prod, MSK_TX_RING_CNT);
2870 /* Update producer index. */
2871 sc_if->msk_cdata.msk_tx_prod = prod;
2873 /* Set EOP on the last descriptor. */
2874 prod = (prod + MSK_TX_RING_CNT - 1) % MSK_TX_RING_CNT;
2875 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2876 tx_le->msk_control |= htole32(EOP);
2878 /* Turn the first descriptor ownership to hardware. */
2879 tx_le = &sc_if->msk_rdata.msk_tx_ring[si];
2880 tx_le->msk_control |= htole32(HW_OWNER);
2882 txd = &sc_if->msk_cdata.msk_txdesc[prod];
2883 map = txd_last->tx_dmamap;
2884 txd_last->tx_dmamap = txd->tx_dmamap;
2885 txd->tx_dmamap = map;
2888 /* Sync descriptors. */
2889 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, map, BUS_DMASYNC_PREWRITE);
2890 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag,
2891 sc_if->msk_cdata.msk_tx_ring_map,
2892 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2898 msk_start(struct ifnet *ifp)
2900 struct msk_if_softc *sc_if;
2902 sc_if = ifp->if_softc;
2904 msk_start_locked(ifp);
2905 MSK_IF_UNLOCK(sc_if);
2909 msk_start_locked(struct ifnet *ifp)
2911 struct msk_if_softc *sc_if;
2912 struct mbuf *m_head;
2915 sc_if = ifp->if_softc;
2916 MSK_IF_LOCK_ASSERT(sc_if);
2918 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
2919 IFF_DRV_RUNNING || (sc_if->msk_flags & MSK_FLAG_LINK) == 0)
2922 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
2923 sc_if->msk_cdata.msk_tx_cnt <
2924 (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT); ) {
2925 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2929 * Pack the data into the transmit ring. If we
2930 * don't have room, set the OACTIVE flag and wait
2931 * for the NIC to drain the ring.
2933 if (msk_encap(sc_if, &m_head) != 0) {
2936 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2937 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2943 * If there's a BPF listener, bounce a copy of this frame
2946 ETHER_BPF_MTAP(ifp, m_head);
2951 CSR_WRITE_2(sc_if->msk_softc,
2952 Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_PUT_IDX_REG),
2953 sc_if->msk_cdata.msk_tx_prod);
2955 /* Set a timeout in case the chip goes out to lunch. */
2956 sc_if->msk_watchdog_timer = MSK_TX_TIMEOUT;
2961 msk_watchdog(struct msk_if_softc *sc_if)
2965 MSK_IF_LOCK_ASSERT(sc_if);
2967 if (sc_if->msk_watchdog_timer == 0 || --sc_if->msk_watchdog_timer)
2969 ifp = sc_if->msk_ifp;
2970 if ((sc_if->msk_flags & MSK_FLAG_LINK) == 0) {
2972 if_printf(sc_if->msk_ifp, "watchdog timeout "
2974 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
2975 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2976 msk_init_locked(sc_if);
2980 if_printf(ifp, "watchdog timeout\n");
2981 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
2982 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2983 msk_init_locked(sc_if);
2984 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2985 msk_start_locked(ifp);
2989 mskc_shutdown(device_t dev)
2991 struct msk_softc *sc;
2994 sc = device_get_softc(dev);
2996 for (i = 0; i < sc->msk_num_port; i++) {
2997 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL &&
2998 ((sc->msk_if[i]->msk_ifp->if_drv_flags &
2999 IFF_DRV_RUNNING) != 0))
3000 msk_stop(sc->msk_if[i]);
3004 /* Put hardware reset. */
3005 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
3010 mskc_suspend(device_t dev)
3012 struct msk_softc *sc;
3015 sc = device_get_softc(dev);
3019 for (i = 0; i < sc->msk_num_port; i++) {
3020 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL &&
3021 ((sc->msk_if[i]->msk_ifp->if_drv_flags &
3022 IFF_DRV_RUNNING) != 0))
3023 msk_stop(sc->msk_if[i]);
3026 /* Disable all interrupts. */
3027 CSR_WRITE_4(sc, B0_IMSK, 0);
3028 CSR_READ_4(sc, B0_IMSK);
3029 CSR_WRITE_4(sc, B0_HWE_IMSK, 0);
3030 CSR_READ_4(sc, B0_HWE_IMSK);
3032 msk_phy_power(sc, MSK_PHY_POWERDOWN);
3034 /* Put hardware reset. */
3035 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
3036 sc->msk_pflags |= MSK_FLAG_SUSPEND;
3044 mskc_resume(device_t dev)
3046 struct msk_softc *sc;
3049 sc = device_get_softc(dev);
3053 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, 0);
3055 for (i = 0; i < sc->msk_num_port; i++) {
3056 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL &&
3057 ((sc->msk_if[i]->msk_ifp->if_flags & IFF_UP) != 0)) {
3058 sc->msk_if[i]->msk_ifp->if_drv_flags &=
3060 msk_init_locked(sc->msk_if[i]);
3063 sc->msk_pflags &= ~MSK_FLAG_SUSPEND;
3070 #ifndef __NO_STRICT_ALIGNMENT
3071 static __inline void
3072 msk_fixup_rx(struct mbuf *m)
3075 uint16_t *src, *dst;
3077 src = mtod(m, uint16_t *);
3080 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
3083 m->m_data -= (MSK_RX_BUF_ALIGN - ETHER_ALIGN);
3087 static __inline void
3088 msk_rxcsum(struct msk_if_softc *sc_if, uint32_t control, struct mbuf *m)
3090 struct ether_header *eh;
3093 int32_t hlen, len, pktlen, temp32;
3094 uint16_t csum, *opts;
3096 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0) {
3097 if ((control & (CSS_IPV4 | CSS_IPFRAG)) == CSS_IPV4) {
3098 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
3099 if ((control & CSS_IPV4_CSUM_OK) != 0)
3100 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
3101 if ((control & (CSS_TCP | CSS_UDP)) != 0 &&
3102 (control & (CSS_TCPUDP_CSUM_OK)) != 0) {
3103 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
3105 m->m_pkthdr.csum_data = 0xffff;
3111 * Marvell Yukon controllers that support OP_RXCHKS has known
3112 * to have various Rx checksum offloading bugs. These
3113 * controllers can be configured to compute simple checksum
3114 * at two different positions. So we can compute IP and TCP/UDP
3115 * checksum at the same time. We intentionally have controller
3116 * compute TCP/UDP checksum twice by specifying the same
3117 * checksum start position and compare the result. If the value
3118 * is different it would indicate the hardware logic was wrong.
3120 if ((sc_if->msk_csum & 0xFFFF) != (sc_if->msk_csum >> 16)) {
3122 device_printf(sc_if->msk_if_dev,
3123 "Rx checksum value mismatch!\n");
3126 pktlen = m->m_pkthdr.len;
3127 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip))
3129 eh = mtod(m, struct ether_header *);
3130 if (eh->ether_type != htons(ETHERTYPE_IP))
3132 ip = (struct ip *)(eh + 1);
3133 if (ip->ip_v != IPVERSION)
3136 hlen = ip->ip_hl << 2;
3137 pktlen -= sizeof(struct ether_header);
3138 if (hlen < sizeof(struct ip))
3140 if (ntohs(ip->ip_len) < hlen)
3142 if (ntohs(ip->ip_len) != pktlen)
3144 if (ip->ip_off & htons(IP_MF | IP_OFFMASK))
3145 return; /* can't handle fragmented packet. */
3149 if (pktlen < (hlen + sizeof(struct tcphdr)))
3153 if (pktlen < (hlen + sizeof(struct udphdr)))
3155 uh = (struct udphdr *)((caddr_t)ip + hlen);
3156 if (uh->uh_sum == 0)
3157 return; /* no checksum */
3162 csum = bswap16(sc_if->msk_csum & 0xFFFF);
3163 /* Checksum fixup for IP options. */
3164 len = hlen - sizeof(struct ip);
3166 opts = (uint16_t *)(ip + 1);
3167 for (; len > 0; len -= sizeof(uint16_t), opts++) {
3168 temp32 = csum - *opts;
3169 temp32 = (temp32 >> 16) + (temp32 & 65535);
3170 csum = temp32 & 65535;
3173 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID;
3174 m->m_pkthdr.csum_data = csum;
3178 msk_rxeof(struct msk_if_softc *sc_if, uint32_t status, uint32_t control,
3183 struct msk_rxdesc *rxd;
3186 ifp = sc_if->msk_ifp;
3188 MSK_IF_LOCK_ASSERT(sc_if);
3190 cons = sc_if->msk_cdata.msk_rx_cons;
3192 rxlen = status >> 16;
3193 if ((status & GMR_FS_VLAN) != 0 &&
3194 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
3195 rxlen -= ETHER_VLAN_ENCAP_LEN;
3196 if ((sc_if->msk_flags & MSK_FLAG_NORXCHK) != 0) {
3198 * For controllers that returns bogus status code
3199 * just do minimal check and let upper stack
3200 * handle this frame.
3202 if (len > MSK_MAX_FRAMELEN || len < ETHER_HDR_LEN) {
3203 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
3204 msk_discard_rxbuf(sc_if, cons);
3207 } else if (len > sc_if->msk_framesize ||
3208 ((status & GMR_FS_ANY_ERR) != 0) ||
3209 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) {
3210 /* Don't count flow-control packet as errors. */
3211 if ((status & GMR_FS_GOOD_FC) == 0)
3212 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
3213 msk_discard_rxbuf(sc_if, cons);
3216 #ifdef MSK_64BIT_DMA
3217 rxd = &sc_if->msk_cdata.msk_rxdesc[(cons + 1) %
3220 rxd = &sc_if->msk_cdata.msk_rxdesc[cons];
3223 if (msk_newbuf(sc_if, cons) != 0) {
3224 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
3225 /* Reuse old buffer. */
3226 msk_discard_rxbuf(sc_if, cons);
3229 m->m_pkthdr.rcvif = ifp;
3230 m->m_pkthdr.len = m->m_len = len;
3231 #ifndef __NO_STRICT_ALIGNMENT
3232 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0)
3235 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
3236 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
3237 msk_rxcsum(sc_if, control, m);
3238 /* Check for VLAN tagged packets. */
3239 if ((status & GMR_FS_VLAN) != 0 &&
3240 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) {
3241 m->m_pkthdr.ether_vtag = sc_if->msk_vtag;
3242 m->m_flags |= M_VLANTAG;
3244 MSK_IF_UNLOCK(sc_if);
3245 (*ifp->if_input)(ifp, m);
3249 MSK_RX_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT);
3250 MSK_RX_INC(sc_if->msk_cdata.msk_rx_prod, MSK_RX_RING_CNT);
3254 msk_jumbo_rxeof(struct msk_if_softc *sc_if, uint32_t status, uint32_t control,
3259 struct msk_rxdesc *jrxd;
3262 ifp = sc_if->msk_ifp;
3264 MSK_IF_LOCK_ASSERT(sc_if);
3266 cons = sc_if->msk_cdata.msk_rx_cons;
3268 rxlen = status >> 16;
3269 if ((status & GMR_FS_VLAN) != 0 &&
3270 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
3271 rxlen -= ETHER_VLAN_ENCAP_LEN;
3272 if (len > sc_if->msk_framesize ||
3273 ((status & GMR_FS_ANY_ERR) != 0) ||
3274 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) {
3275 /* Don't count flow-control packet as errors. */
3276 if ((status & GMR_FS_GOOD_FC) == 0)
3277 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
3278 msk_discard_jumbo_rxbuf(sc_if, cons);
3281 #ifdef MSK_64BIT_DMA
3282 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[(cons + 1) %
3283 MSK_JUMBO_RX_RING_CNT];
3285 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[cons];
3288 if (msk_jumbo_newbuf(sc_if, cons) != 0) {
3289 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
3290 /* Reuse old buffer. */
3291 msk_discard_jumbo_rxbuf(sc_if, cons);
3294 m->m_pkthdr.rcvif = ifp;
3295 m->m_pkthdr.len = m->m_len = len;
3296 #ifndef __NO_STRICT_ALIGNMENT
3297 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0)
3300 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
3301 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
3302 msk_rxcsum(sc_if, control, m);
3303 /* Check for VLAN tagged packets. */
3304 if ((status & GMR_FS_VLAN) != 0 &&
3305 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) {
3306 m->m_pkthdr.ether_vtag = sc_if->msk_vtag;
3307 m->m_flags |= M_VLANTAG;
3309 MSK_IF_UNLOCK(sc_if);
3310 (*ifp->if_input)(ifp, m);
3314 MSK_RX_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT);
3315 MSK_RX_INC(sc_if->msk_cdata.msk_rx_prod, MSK_JUMBO_RX_RING_CNT);
3319 msk_txeof(struct msk_if_softc *sc_if, int idx)
3321 struct msk_txdesc *txd;
3322 struct msk_tx_desc *cur_tx;
3327 MSK_IF_LOCK_ASSERT(sc_if);
3329 ifp = sc_if->msk_ifp;
3331 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag,
3332 sc_if->msk_cdata.msk_tx_ring_map,
3333 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
3335 * Go through our tx ring and free mbufs for those
3336 * frames that have been sent.
3338 cons = sc_if->msk_cdata.msk_tx_cons;
3340 for (; cons != idx; MSK_INC(cons, MSK_TX_RING_CNT)) {
3341 if (sc_if->msk_cdata.msk_tx_cnt <= 0)
3344 cur_tx = &sc_if->msk_rdata.msk_tx_ring[cons];
3345 control = le32toh(cur_tx->msk_control);
3346 sc_if->msk_cdata.msk_tx_cnt--;
3347 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3348 if ((control & EOP) == 0)
3350 txd = &sc_if->msk_cdata.msk_txdesc[cons];
3351 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap,
3352 BUS_DMASYNC_POSTWRITE);
3353 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap);
3355 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
3356 KASSERT(txd->tx_m != NULL, ("%s: freeing NULL mbuf!",
3363 sc_if->msk_cdata.msk_tx_cons = cons;
3364 if (sc_if->msk_cdata.msk_tx_cnt == 0)
3365 sc_if->msk_watchdog_timer = 0;
3366 /* No need to sync LEs as we didn't update LEs. */
3371 msk_tick(void *xsc_if)
3373 struct msk_if_softc *sc_if;
3374 struct mii_data *mii;
3378 MSK_IF_LOCK_ASSERT(sc_if);
3380 mii = device_get_softc(sc_if->msk_miibus);
3383 if ((sc_if->msk_flags & MSK_FLAG_LINK) == 0)
3384 msk_miibus_statchg(sc_if->msk_if_dev);
3385 msk_handle_events(sc_if->msk_softc);
3386 msk_watchdog(sc_if);
3387 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if);
3391 msk_intr_phy(struct msk_if_softc *sc_if)
3395 msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT);
3396 status = msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT);
3397 /* Handle FIFO Underrun/Overflow? */
3398 if ((status & PHY_M_IS_FIFO_ERROR))
3399 device_printf(sc_if->msk_if_dev,
3400 "PHY FIFO underrun/overflow.\n");
3404 msk_intr_gmac(struct msk_if_softc *sc_if)
3406 struct msk_softc *sc;
3409 sc = sc_if->msk_softc;
3410 status = CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC));
3412 /* GMAC Rx FIFO overrun. */
3413 if ((status & GM_IS_RX_FF_OR) != 0)
3414 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T),
3416 /* GMAC Tx FIFO underrun. */
3417 if ((status & GM_IS_TX_FF_UR) != 0) {
3418 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
3420 device_printf(sc_if->msk_if_dev, "Tx FIFO underrun!\n");
3423 * In case of Tx underrun, we may need to flush/reset
3424 * Tx MAC but that would also require resynchronization
3425 * with status LEs. Reinitializing status LEs would
3426 * affect other port in dual MAC configuration so it
3427 * should be avoided as possible as we can.
3428 * Due to lack of documentation it's all vague guess but
3429 * it needs more investigation.
3435 msk_handle_hwerr(struct msk_if_softc *sc_if, uint32_t status)
3437 struct msk_softc *sc;
3439 sc = sc_if->msk_softc;
3440 if ((status & Y2_IS_PAR_RD1) != 0) {
3441 device_printf(sc_if->msk_if_dev,
3442 "RAM buffer read parity error\n");
3444 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL),
3447 if ((status & Y2_IS_PAR_WR1) != 0) {
3448 device_printf(sc_if->msk_if_dev,
3449 "RAM buffer write parity error\n");
3451 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL),
3454 if ((status & Y2_IS_PAR_MAC1) != 0) {
3455 device_printf(sc_if->msk_if_dev, "Tx MAC parity error\n");
3457 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
3460 if ((status & Y2_IS_PAR_RX1) != 0) {
3461 device_printf(sc_if->msk_if_dev, "Rx parity error\n");
3463 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_IRQ_PAR);
3465 if ((status & (Y2_IS_TCP_TXS1 | Y2_IS_TCP_TXA1)) != 0) {
3466 device_printf(sc_if->msk_if_dev, "TCP segmentation error\n");
3468 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_IRQ_TCP);
3473 msk_intr_hwerr(struct msk_softc *sc)
3476 uint32_t tlphead[4];
3478 status = CSR_READ_4(sc, B0_HWE_ISRC);
3479 /* Time Stamp timer overflow. */
3480 if ((status & Y2_IS_TIST_OV) != 0)
3481 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3482 if ((status & Y2_IS_PCI_NEXP) != 0) {
3484 * PCI Express Error occurred which is not described in PEX
3486 * This error is also mapped either to Master Abort(
3487 * Y2_IS_MST_ERR) or Target Abort (Y2_IS_IRQ_STAT) bit and
3488 * can only be cleared there.
3490 device_printf(sc->msk_dev,
3491 "PCI Express protocol violation error\n");
3494 if ((status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) != 0) {
3497 if ((status & Y2_IS_MST_ERR) != 0)
3498 device_printf(sc->msk_dev,
3499 "unexpected IRQ Status error\n");
3501 device_printf(sc->msk_dev,
3502 "unexpected IRQ Master error\n");
3503 /* Reset all bits in the PCI status register. */
3504 v16 = pci_read_config(sc->msk_dev, PCIR_STATUS, 2);
3505 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3506 pci_write_config(sc->msk_dev, PCIR_STATUS, v16 |
3507 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT |
3508 PCIM_STATUS_RTABORT | PCIM_STATUS_MDPERR, 2);
3509 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3512 /* Check for PCI Express Uncorrectable Error. */
3513 if ((status & Y2_IS_PCI_EXP) != 0) {
3517 * On PCI Express bus bridges are called root complexes (RC).
3518 * PCI Express errors are recognized by the root complex too,
3519 * which requests the system to handle the problem. After
3520 * error occurrence it may be that no access to the adapter
3521 * may be performed any longer.
3524 v32 = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT);
3525 if ((v32 & PEX_UNSUP_REQ) != 0) {
3526 /* Ignore unsupported request error. */
3527 device_printf(sc->msk_dev,
3528 "Uncorrectable PCI Express error\n");
3530 if ((v32 & (PEX_FATAL_ERRORS | PEX_POIS_TLP)) != 0) {
3533 /* Get TLP header form Log Registers. */
3534 for (i = 0; i < 4; i++)
3535 tlphead[i] = CSR_PCI_READ_4(sc,
3536 PEX_HEADER_LOG + i * 4);
3537 /* Check for vendor defined broadcast message. */
3538 if (!(tlphead[0] == 0x73004001 && tlphead[1] == 0x7f)) {
3539 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP;
3540 CSR_WRITE_4(sc, B0_HWE_IMSK,
3541 sc->msk_intrhwemask);
3542 CSR_READ_4(sc, B0_HWE_IMSK);
3545 /* Clear the interrupt. */
3546 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3547 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff);
3548 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3551 if ((status & Y2_HWE_L1_MASK) != 0 && sc->msk_if[MSK_PORT_A] != NULL)
3552 msk_handle_hwerr(sc->msk_if[MSK_PORT_A], status);
3553 if ((status & Y2_HWE_L2_MASK) != 0 && sc->msk_if[MSK_PORT_B] != NULL)
3554 msk_handle_hwerr(sc->msk_if[MSK_PORT_B], status >> 8);
3557 static __inline void
3558 msk_rxput(struct msk_if_softc *sc_if)
3560 struct msk_softc *sc;
3562 sc = sc_if->msk_softc;
3563 if (sc_if->msk_framesize > (MCLBYTES - MSK_RX_BUF_ALIGN))
3565 sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
3566 sc_if->msk_cdata.msk_jumbo_rx_ring_map,
3567 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3570 sc_if->msk_cdata.msk_rx_ring_tag,
3571 sc_if->msk_cdata.msk_rx_ring_map,
3572 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3573 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq,
3574 PREF_UNIT_PUT_IDX_REG), sc_if->msk_cdata.msk_rx_prod);
3578 msk_handle_events(struct msk_softc *sc)
3580 struct msk_if_softc *sc_if;
3582 struct msk_stat_desc *sd;
3583 uint32_t control, status;
3584 int cons, len, port, rxprog;
3586 if (sc->msk_stat_cons == CSR_READ_2(sc, STAT_PUT_IDX))
3589 /* Sync status LEs. */
3590 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map,
3591 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
3593 rxput[MSK_PORT_A] = rxput[MSK_PORT_B] = 0;
3595 cons = sc->msk_stat_cons;
3597 sd = &sc->msk_stat_ring[cons];
3598 control = le32toh(sd->msk_control);
3599 if ((control & HW_OWNER) == 0)
3601 control &= ~HW_OWNER;
3602 sd->msk_control = htole32(control);
3603 status = le32toh(sd->msk_status);
3604 len = control & STLE_LEN_MASK;
3605 port = (control >> 16) & 0x01;
3606 sc_if = sc->msk_if[port];
3607 if (sc_if == NULL) {
3608 device_printf(sc->msk_dev, "invalid port opcode "
3609 "0x%08x\n", control & STLE_OP_MASK);
3613 switch (control & STLE_OP_MASK) {
3615 sc_if->msk_vtag = ntohs(len);
3618 sc_if->msk_vtag = ntohs(len);
3621 sc_if->msk_csum = status;
3624 if (!(sc_if->msk_ifp->if_drv_flags & IFF_DRV_RUNNING))
3626 if (sc_if->msk_framesize >
3627 (MCLBYTES - MSK_RX_BUF_ALIGN))
3628 msk_jumbo_rxeof(sc_if, status, control, len);
3630 msk_rxeof(sc_if, status, control, len);
3633 * Because there is no way to sync single Rx LE
3634 * put the DMA sync operation off until the end of
3638 /* Update prefetch unit if we've passed water mark. */
3639 if (rxput[port] >= sc_if->msk_cdata.msk_rx_putwm) {
3645 if (sc->msk_if[MSK_PORT_A] != NULL)
3646 msk_txeof(sc->msk_if[MSK_PORT_A],
3647 status & STLE_TXA1_MSKL);
3648 if (sc->msk_if[MSK_PORT_B] != NULL)
3649 msk_txeof(sc->msk_if[MSK_PORT_B],
3650 ((status & STLE_TXA2_MSKL) >>
3652 ((len & STLE_TXA2_MSKH) <<
3656 device_printf(sc->msk_dev, "unhandled opcode 0x%08x\n",
3657 control & STLE_OP_MASK);
3660 MSK_INC(cons, sc->msk_stat_count);
3661 if (rxprog > sc->msk_process_limit)
3665 sc->msk_stat_cons = cons;
3666 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map,
3667 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3669 if (rxput[MSK_PORT_A] > 0)
3670 msk_rxput(sc->msk_if[MSK_PORT_A]);
3671 if (rxput[MSK_PORT_B] > 0)
3672 msk_rxput(sc->msk_if[MSK_PORT_B]);
3674 return (sc->msk_stat_cons != CSR_READ_2(sc, STAT_PUT_IDX));
3680 struct msk_softc *sc;
3681 struct msk_if_softc *sc_if0, *sc_if1;
3682 struct ifnet *ifp0, *ifp1;
3689 /* Reading B0_Y2_SP_ISRC2 masks further interrupts. */
3690 status = CSR_READ_4(sc, B0_Y2_SP_ISRC2);
3691 if (status == 0 || status == 0xffffffff ||
3692 (sc->msk_pflags & MSK_FLAG_SUSPEND) != 0 ||
3693 (status & sc->msk_intrmask) == 0) {
3694 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2);
3699 sc_if0 = sc->msk_if[MSK_PORT_A];
3700 sc_if1 = sc->msk_if[MSK_PORT_B];
3703 ifp0 = sc_if0->msk_ifp;
3705 ifp1 = sc_if1->msk_ifp;
3707 if ((status & Y2_IS_IRQ_PHY1) != 0 && sc_if0 != NULL)
3708 msk_intr_phy(sc_if0);
3709 if ((status & Y2_IS_IRQ_PHY2) != 0 && sc_if1 != NULL)
3710 msk_intr_phy(sc_if1);
3711 if ((status & Y2_IS_IRQ_MAC1) != 0 && sc_if0 != NULL)
3712 msk_intr_gmac(sc_if0);
3713 if ((status & Y2_IS_IRQ_MAC2) != 0 && sc_if1 != NULL)
3714 msk_intr_gmac(sc_if1);
3715 if ((status & (Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2)) != 0) {
3716 device_printf(sc->msk_dev, "Rx descriptor error\n");
3717 sc->msk_intrmask &= ~(Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2);
3718 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask);
3719 CSR_READ_4(sc, B0_IMSK);
3721 if ((status & (Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2)) != 0) {
3722 device_printf(sc->msk_dev, "Tx descriptor error\n");
3723 sc->msk_intrmask &= ~(Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2);
3724 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask);
3725 CSR_READ_4(sc, B0_IMSK);
3727 if ((status & Y2_IS_HW_ERR) != 0)
3730 domore = msk_handle_events(sc);
3731 if ((status & Y2_IS_STAT_BMU) != 0 && domore == 0)
3732 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_CLR_IRQ);
3734 /* Reenable interrupts. */
3735 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2);
3737 if (ifp0 != NULL && (ifp0->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
3738 !IFQ_DRV_IS_EMPTY(&ifp0->if_snd))
3739 msk_start_locked(ifp0);
3740 if (ifp1 != NULL && (ifp1->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
3741 !IFQ_DRV_IS_EMPTY(&ifp1->if_snd))
3742 msk_start_locked(ifp1);
3748 msk_set_tx_stfwd(struct msk_if_softc *sc_if)
3750 struct msk_softc *sc;
3753 ifp = sc_if->msk_ifp;
3754 sc = sc_if->msk_softc;
3755 if ((sc->msk_hw_id == CHIP_ID_YUKON_EX &&
3756 sc->msk_hw_rev != CHIP_REV_YU_EX_A0) ||
3757 sc->msk_hw_id >= CHIP_ID_YUKON_SUPR) {
3758 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
3761 if (ifp->if_mtu > ETHERMTU) {
3762 /* Set Tx GMAC FIFO Almost Empty Threshold. */
3764 MR_ADDR(sc_if->msk_port, TX_GMF_AE_THR),
3765 MSK_ECU_JUMBO_WM << 16 | MSK_ECU_AE_THR);
3766 /* Disable Store & Forward mode for Tx. */
3767 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
3770 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
3779 struct msk_if_softc *sc_if = xsc;
3782 msk_init_locked(sc_if);
3783 MSK_IF_UNLOCK(sc_if);
3787 msk_init_locked(struct msk_if_softc *sc_if)
3789 struct msk_softc *sc;
3791 struct mii_data *mii;
3797 MSK_IF_LOCK_ASSERT(sc_if);
3799 ifp = sc_if->msk_ifp;
3800 sc = sc_if->msk_softc;
3801 mii = device_get_softc(sc_if->msk_miibus);
3803 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
3807 /* Cancel pending I/O and free all Rx/Tx buffers. */
3810 if (ifp->if_mtu < ETHERMTU)
3811 sc_if->msk_framesize = ETHERMTU;
3813 sc_if->msk_framesize = ifp->if_mtu;
3814 sc_if->msk_framesize += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
3815 if (ifp->if_mtu > ETHERMTU &&
3816 (sc_if->msk_flags & MSK_FLAG_JUMBO_NOCSUM) != 0) {
3817 ifp->if_hwassist &= ~(MSK_CSUM_FEATURES | CSUM_TSO);
3818 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TXCSUM);
3821 /* GMAC Control reset. */
3822 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_SET);
3823 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_CLR);
3824 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_F_LOOPB_OFF);
3825 if (sc->msk_hw_id == CHIP_ID_YUKON_EX ||
3826 sc->msk_hw_id == CHIP_ID_YUKON_SUPR)
3827 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL),
3828 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON |
3832 * Initialize GMAC first such that speed/duplex/flow-control
3833 * parameters are renegotiated when interface is brought up.
3835 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, 0);
3837 /* Dummy read the Interrupt Source Register. */
3838 CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC));
3840 /* Clear MIB stats. */
3841 msk_stats_clear(sc_if);
3844 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, GM_RXCR_CRC_DIS);
3846 /* Setup Transmit Control Register. */
3847 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
3849 /* Setup Transmit Flow Control Register. */
3850 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_FLOW_CTRL, 0xffff);
3852 /* Setup Transmit Parameter Register. */
3853 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_PARAM,
3854 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
3855 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) | TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
3857 gmac = DATA_BLIND_VAL(DATA_BLIND_DEF) |
3858 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
3860 if (ifp->if_mtu > ETHERMTU)
3861 gmac |= GM_SMOD_JUMBO_ENA;
3862 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SERIAL_MODE, gmac);
3864 /* Set station address. */
3865 eaddr = IF_LLADDR(ifp);
3866 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1L,
3867 eaddr[0] | (eaddr[1] << 8));
3868 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1M,
3869 eaddr[2] | (eaddr[3] << 8));
3870 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1H,
3871 eaddr[4] | (eaddr[5] << 8));
3872 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2L,
3873 eaddr[0] | (eaddr[1] << 8));
3874 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2M,
3875 eaddr[2] | (eaddr[3] << 8));
3876 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2H,
3877 eaddr[4] | (eaddr[5] << 8));
3879 /* Disable interrupts for counter overflows. */
3880 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_IRQ_MSK, 0);
3881 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_IRQ_MSK, 0);
3882 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TR_IRQ_MSK, 0);
3884 /* Configure Rx MAC FIFO. */
3885 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET);
3886 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_CLR);
3887 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
3888 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P ||
3889 sc->msk_hw_id == CHIP_ID_YUKON_EX)
3890 reg |= GMF_RX_OVER_ON;
3891 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), reg);
3893 /* Set receive filter. */
3894 msk_rxfilter(sc_if);
3896 if (sc->msk_hw_id == CHIP_ID_YUKON_XL) {
3897 /* Clear flush mask - HW bug. */
3898 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK), 0);
3900 /* Flush Rx MAC FIFO on any flow control or error. */
3901 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK),
3906 * Set Rx FIFO flush threshold to 64 bytes + 1 FIFO word
3907 * due to hardware hang on receipt of pause frames.
3909 reg = RX_GMF_FL_THR_DEF + 1;
3910 /* Another magic for Yukon FE+ - From Linux. */
3911 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P &&
3912 sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0)
3914 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_THR), reg);
3916 /* Configure Tx MAC FIFO. */
3917 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET);
3918 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_CLR);
3919 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_OPER_ON);
3921 /* Configure hardware VLAN tag insertion/stripping. */
3922 msk_setvlan(sc_if, ifp);
3924 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) {
3925 /* Set Rx Pause threshold. */
3926 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_LP_THR),
3928 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_UP_THR),
3930 /* Configure store-and-forward for Tx. */
3931 msk_set_tx_stfwd(sc_if);
3934 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P &&
3935 sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) {
3936 /* Disable dynamic watermark - from Linux. */
3937 reg = CSR_READ_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA));
3939 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA), reg);
3943 * Disable Force Sync bit and Alloc bit in Tx RAM interface
3944 * arbiter as we don't use Sync Tx queue.
3946 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL),
3947 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
3948 /* Enable the RAM Interface Arbiter. */
3949 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_ENA_ARB);
3951 /* Setup RAM buffer. */
3952 msk_set_rambuffer(sc_if);
3954 /* Disable Tx sync Queue. */
3955 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txsq, RB_CTRL), RB_RST_SET);
3957 /* Setup Tx Queue Bus Memory Interface. */
3958 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_RESET);
3959 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_OPER_INIT);
3960 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_FIFO_OP_ON);
3961 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_WM), MSK_BMU_TX_WM);
3962 switch (sc->msk_hw_id) {
3963 case CHIP_ID_YUKON_EC_U:
3964 if (sc->msk_hw_rev == CHIP_REV_YU_EC_U_A0) {
3965 /* Fix for Yukon-EC Ultra: set BMU FIFO level */
3966 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_AL),
3970 case CHIP_ID_YUKON_EX:
3972 * Yukon Extreme seems to have silicon bug for
3973 * automatic Tx checksum calculation capability.
3975 if (sc->msk_hw_rev == CHIP_REV_YU_EX_B0)
3976 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_F),
3981 /* Setup Rx Queue Bus Memory Interface. */
3982 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_RESET);
3983 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_OPER_INIT);
3984 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_FIFO_OP_ON);
3985 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_rxq, Q_WM), MSK_BMU_RX_WM);
3986 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U &&
3987 sc->msk_hw_rev >= CHIP_REV_YU_EC_U_A1) {
3988 /* MAC Rx RAM Read is controlled by hardware. */
3989 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_F), F_M_RX_RAM_DIS);
3992 msk_set_prefetch(sc, sc_if->msk_txq,
3993 sc_if->msk_rdata.msk_tx_ring_paddr, MSK_TX_RING_CNT - 1);
3994 msk_init_tx_ring(sc_if);
3996 /* Disable Rx checksum offload and RSS hash. */
3997 reg = BMU_DIS_RX_RSS_HASH;
3998 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 &&
3999 (ifp->if_capenable & IFCAP_RXCSUM) != 0)
4000 reg |= BMU_ENA_RX_CHKSUM;
4002 reg |= BMU_DIS_RX_CHKSUM;
4003 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), reg);
4004 if (sc_if->msk_framesize > (MCLBYTES - MSK_RX_BUF_ALIGN)) {
4005 msk_set_prefetch(sc, sc_if->msk_rxq,
4006 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr,
4007 MSK_JUMBO_RX_RING_CNT - 1);
4008 error = msk_init_jumbo_rx_ring(sc_if);
4010 msk_set_prefetch(sc, sc_if->msk_rxq,
4011 sc_if->msk_rdata.msk_rx_ring_paddr,
4012 MSK_RX_RING_CNT - 1);
4013 error = msk_init_rx_ring(sc_if);
4016 device_printf(sc_if->msk_if_dev,
4017 "initialization failed: no memory for Rx buffers\n");
4021 if (sc->msk_hw_id == CHIP_ID_YUKON_EX ||
4022 sc->msk_hw_id == CHIP_ID_YUKON_SUPR) {
4023 /* Disable flushing of non-ASF packets. */
4024 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T),
4025 GMF_RX_MACSEC_FLUSH_OFF);
4028 /* Configure interrupt handling. */
4029 if (sc_if->msk_port == MSK_PORT_A) {
4030 sc->msk_intrmask |= Y2_IS_PORT_A;
4031 sc->msk_intrhwemask |= Y2_HWE_L1_MASK;
4033 sc->msk_intrmask |= Y2_IS_PORT_B;
4034 sc->msk_intrhwemask |= Y2_HWE_L2_MASK;
4036 /* Configure IRQ moderation mask. */
4037 CSR_WRITE_4(sc, B2_IRQM_MSK, sc->msk_intrmask);
4038 if (sc->msk_int_holdoff > 0) {
4039 /* Configure initial IRQ moderation timer value. */
4040 CSR_WRITE_4(sc, B2_IRQM_INI,
4041 MSK_USECS(sc, sc->msk_int_holdoff));
4042 CSR_WRITE_4(sc, B2_IRQM_VAL,
4043 MSK_USECS(sc, sc->msk_int_holdoff));
4044 /* Start IRQ moderation. */
4045 CSR_WRITE_1(sc, B2_IRQM_CTRL, TIM_START);
4047 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask);
4048 CSR_READ_4(sc, B0_HWE_IMSK);
4049 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask);
4050 CSR_READ_4(sc, B0_IMSK);
4052 ifp->if_drv_flags |= IFF_DRV_RUNNING;
4053 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
4055 sc_if->msk_flags &= ~MSK_FLAG_LINK;
4058 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if);
4062 msk_set_rambuffer(struct msk_if_softc *sc_if)
4064 struct msk_softc *sc;
4067 sc = sc_if->msk_softc;
4068 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0)
4071 /* Setup Rx Queue. */
4072 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_CLR);
4073 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_START),
4074 sc->msk_rxqstart[sc_if->msk_port] / 8);
4075 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_END),
4076 sc->msk_rxqend[sc_if->msk_port] / 8);
4077 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_WP),
4078 sc->msk_rxqstart[sc_if->msk_port] / 8);
4079 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RP),
4080 sc->msk_rxqstart[sc_if->msk_port] / 8);
4082 utpp = (sc->msk_rxqend[sc_if->msk_port] + 1 -
4083 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_ULPP) / 8;
4084 ltpp = (sc->msk_rxqend[sc_if->msk_port] + 1 -
4085 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_LLPP_B) / 8;
4086 if (sc->msk_rxqsize < MSK_MIN_RXQ_SIZE)
4087 ltpp += (MSK_RB_LLPP_B - MSK_RB_LLPP_S) / 8;
4088 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_UTPP), utpp);
4089 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_LTPP), ltpp);
4090 /* Set Rx priority(RB_RX_UTHP/RB_RX_LTHP) thresholds? */
4092 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_ENA_OP_MD);
4093 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL));
4095 /* Setup Tx Queue. */
4096 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_CLR);
4097 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_START),
4098 sc->msk_txqstart[sc_if->msk_port] / 8);
4099 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_END),
4100 sc->msk_txqend[sc_if->msk_port] / 8);
4101 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_WP),
4102 sc->msk_txqstart[sc_if->msk_port] / 8);
4103 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_RP),
4104 sc->msk_txqstart[sc_if->msk_port] / 8);
4105 /* Enable Store & Forward for Tx side. */
4106 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_STFWD);
4107 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_OP_MD);
4108 CSR_READ_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL));
4112 msk_set_prefetch(struct msk_softc *sc, int qaddr, bus_addr_t addr,
4116 /* Reset the prefetch unit. */
4117 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG),
4119 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG),
4121 /* Set LE base address. */
4122 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_LOW_REG),
4124 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_HI_REG),
4126 /* Set the list last index. */
4127 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_LAST_IDX_REG),
4129 /* Turn on prefetch unit. */
4130 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG),
4132 /* Dummy read to ensure write. */
4133 CSR_READ_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG));
4137 msk_stop(struct msk_if_softc *sc_if)
4139 struct msk_softc *sc;
4140 struct msk_txdesc *txd;
4141 struct msk_rxdesc *rxd;
4142 struct msk_rxdesc *jrxd;
4147 MSK_IF_LOCK_ASSERT(sc_if);
4148 sc = sc_if->msk_softc;
4149 ifp = sc_if->msk_ifp;
4151 callout_stop(&sc_if->msk_tick_ch);
4152 sc_if->msk_watchdog_timer = 0;
4154 /* Disable interrupts. */
4155 if (sc_if->msk_port == MSK_PORT_A) {
4156 sc->msk_intrmask &= ~Y2_IS_PORT_A;
4157 sc->msk_intrhwemask &= ~Y2_HWE_L1_MASK;
4159 sc->msk_intrmask &= ~Y2_IS_PORT_B;
4160 sc->msk_intrhwemask &= ~Y2_HWE_L2_MASK;
4162 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask);
4163 CSR_READ_4(sc, B0_HWE_IMSK);
4164 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask);
4165 CSR_READ_4(sc, B0_IMSK);
4167 /* Disable Tx/Rx MAC. */
4168 val = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
4169 val &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
4170 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, val);
4171 /* Read again to ensure writing. */
4172 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
4173 /* Update stats and clear counters. */
4174 msk_stats_update(sc_if);
4177 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_STOP);
4178 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR));
4179 for (i = 0; i < MSK_TIMEOUT; i++) {
4180 if ((val & (BMU_STOP | BMU_IDLE)) == 0) {
4181 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR),
4183 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR));
4188 if (i == MSK_TIMEOUT)
4189 device_printf(sc_if->msk_if_dev, "Tx BMU stop failed\n");
4190 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL),
4191 RB_RST_SET | RB_DIS_OP_MD);
4193 /* Disable all GMAC interrupt. */
4194 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), 0);
4195 /* Disable PHY interrupt. */
4196 msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0);
4198 /* Disable the RAM Interface Arbiter. */
4199 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_DIS_ARB);
4201 /* Reset the PCI FIFO of the async Tx queue */
4202 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR),
4203 BMU_RST_SET | BMU_FIFO_RST);
4205 /* Reset the Tx prefetch units. */
4206 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_CTRL_REG),
4209 /* Reset the RAM Buffer async Tx queue. */
4210 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_SET);
4212 /* Reset Tx MAC FIFO. */
4213 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET);
4214 /* Set Pause Off. */
4215 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_PAUSE_OFF);
4218 * The Rx Stop command will not work for Yukon-2 if the BMU does not
4219 * reach the end of packet and since we can't make sure that we have
4220 * incoming data, we must reset the BMU while it is not during a DMA
4221 * transfer. Since it is possible that the Rx path is still active,
4222 * the Rx RAM buffer will be stopped first, so any possible incoming
4223 * data will not trigger a DMA. After the RAM buffer is stopped, the
4224 * BMU is polled until any DMA in progress is ended and only then it
4228 /* Disable the RAM Buffer receive queue. */
4229 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_DIS_OP_MD);
4230 for (i = 0; i < MSK_TIMEOUT; i++) {
4231 if (CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RSL)) ==
4232 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RL)))
4236 if (i == MSK_TIMEOUT)
4237 device_printf(sc_if->msk_if_dev, "Rx BMU stop failed\n");
4238 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR),
4239 BMU_RST_SET | BMU_FIFO_RST);
4240 /* Reset the Rx prefetch unit. */
4241 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_CTRL_REG),
4243 /* Reset the RAM Buffer receive queue. */
4244 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_SET);
4245 /* Reset Rx MAC FIFO. */
4246 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET);
4248 /* Free Rx and Tx mbufs still in the queues. */
4249 for (i = 0; i < MSK_RX_RING_CNT; i++) {
4250 rxd = &sc_if->msk_cdata.msk_rxdesc[i];
4251 if (rxd->rx_m != NULL) {
4252 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag,
4253 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
4254 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag,
4260 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) {
4261 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i];
4262 if (jrxd->rx_m != NULL) {
4263 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag,
4264 jrxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
4265 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag,
4267 m_freem(jrxd->rx_m);
4271 for (i = 0; i < MSK_TX_RING_CNT; i++) {
4272 txd = &sc_if->msk_cdata.msk_txdesc[i];
4273 if (txd->tx_m != NULL) {
4274 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag,
4275 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
4276 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag,
4284 * Mark the interface down.
4286 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
4287 sc_if->msk_flags &= ~MSK_FLAG_LINK;
4291 * When GM_PAR_MIB_CLR bit of GM_PHY_ADDR is set, reading lower
4292 * counter clears high 16 bits of the counter such that accessing
4293 * lower 16 bits should be the last operation.
4295 #define MSK_READ_MIB32(x, y) \
4296 (((uint32_t)GMAC_READ_2(sc, x, (y) + 4)) << 16) + \
4297 (uint32_t)GMAC_READ_2(sc, x, y)
4298 #define MSK_READ_MIB64(x, y) \
4299 (((uint64_t)MSK_READ_MIB32(x, (y) + 8)) << 32) + \
4300 (uint64_t)MSK_READ_MIB32(x, y)
4303 msk_stats_clear(struct msk_if_softc *sc_if)
4305 struct msk_softc *sc;
4310 MSK_IF_LOCK_ASSERT(sc_if);
4312 sc = sc_if->msk_softc;
4313 /* Set MIB Clear Counter Mode. */
4314 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR);
4315 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR);
4316 /* Read all MIB Counters with Clear Mode set. */
4317 for (i = GM_RXF_UC_OK; i <= GM_TXE_FIFO_UR; i += sizeof(uint32_t))
4318 reg = MSK_READ_MIB32(sc_if->msk_port, i);
4319 /* Clear MIB Clear Counter Mode. */
4320 gmac &= ~GM_PAR_MIB_CLR;
4321 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac);
4325 msk_stats_update(struct msk_if_softc *sc_if)
4327 struct msk_softc *sc;
4329 struct msk_hw_stats *stats;
4333 MSK_IF_LOCK_ASSERT(sc_if);
4335 ifp = sc_if->msk_ifp;
4336 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
4338 sc = sc_if->msk_softc;
4339 stats = &sc_if->msk_stats;
4340 /* Set MIB Clear Counter Mode. */
4341 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR);
4342 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR);
4345 stats->rx_ucast_frames +=
4346 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_UC_OK);
4347 stats->rx_bcast_frames +=
4348 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_BC_OK);
4349 stats->rx_pause_frames +=
4350 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MPAUSE);
4351 stats->rx_mcast_frames +=
4352 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MC_OK);
4353 stats->rx_crc_errs +=
4354 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_FCS_ERR);
4355 reg = MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SPARE1);
4356 stats->rx_good_octets +=
4357 MSK_READ_MIB64(sc_if->msk_port, GM_RXO_OK_LO);
4358 stats->rx_bad_octets +=
4359 MSK_READ_MIB64(sc_if->msk_port, GM_RXO_ERR_LO);
4361 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SHT);
4362 stats->rx_runt_errs +=
4363 MSK_READ_MIB32(sc_if->msk_port, GM_RXE_FRAG);
4364 stats->rx_pkts_64 +=
4365 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_64B);
4366 stats->rx_pkts_65_127 +=
4367 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_127B);
4368 stats->rx_pkts_128_255 +=
4369 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_255B);
4370 stats->rx_pkts_256_511 +=
4371 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_511B);
4372 stats->rx_pkts_512_1023 +=
4373 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_1023B);
4374 stats->rx_pkts_1024_1518 +=
4375 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_1518B);
4376 stats->rx_pkts_1519_max +=
4377 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MAX_SZ);
4378 stats->rx_pkts_too_long +=
4379 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_LNG_ERR);
4380 stats->rx_pkts_jabbers +=
4381 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_JAB_PKT);
4382 reg = MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SPARE2);
4383 stats->rx_fifo_oflows +=
4384 MSK_READ_MIB32(sc_if->msk_port, GM_RXE_FIFO_OV);
4385 reg = MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SPARE3);
4388 stats->tx_ucast_frames +=
4389 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_UC_OK);
4390 stats->tx_bcast_frames +=
4391 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_BC_OK);
4392 stats->tx_pause_frames +=
4393 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MPAUSE);
4394 stats->tx_mcast_frames +=
4395 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MC_OK);
4397 MSK_READ_MIB64(sc_if->msk_port, GM_TXO_OK_LO);
4398 stats->tx_pkts_64 +=
4399 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_64B);
4400 stats->tx_pkts_65_127 +=
4401 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_127B);
4402 stats->tx_pkts_128_255 +=
4403 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_255B);
4404 stats->tx_pkts_256_511 +=
4405 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_511B);
4406 stats->tx_pkts_512_1023 +=
4407 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_1023B);
4408 stats->tx_pkts_1024_1518 +=
4409 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_1518B);
4410 stats->tx_pkts_1519_max +=
4411 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MAX_SZ);
4412 reg = MSK_READ_MIB32(sc_if->msk_port, GM_TXF_SPARE1);
4414 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_COL);
4415 stats->tx_late_colls +=
4416 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_LAT_COL);
4417 stats->tx_excess_colls +=
4418 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_ABO_COL);
4419 stats->tx_multi_colls +=
4420 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MUL_COL);
4421 stats->tx_single_colls +=
4422 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_SNG_COL);
4423 stats->tx_underflows +=
4424 MSK_READ_MIB32(sc_if->msk_port, GM_TXE_FIFO_UR);
4425 /* Clear MIB Clear Counter Mode. */
4426 gmac &= ~GM_PAR_MIB_CLR;
4427 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac);
4431 msk_sysctl_stat32(SYSCTL_HANDLER_ARGS)
4433 struct msk_softc *sc;
4434 struct msk_if_softc *sc_if;
4435 uint32_t result, *stat;
4438 sc_if = (struct msk_if_softc *)arg1;
4439 sc = sc_if->msk_softc;
4441 stat = (uint32_t *)((uint8_t *)&sc_if->msk_stats + off);
4444 result = MSK_READ_MIB32(sc_if->msk_port, GM_MIB_CNT_BASE + off * 2);
4446 MSK_IF_UNLOCK(sc_if);
4448 return (sysctl_handle_int(oidp, &result, 0, req));
4452 msk_sysctl_stat64(SYSCTL_HANDLER_ARGS)
4454 struct msk_softc *sc;
4455 struct msk_if_softc *sc_if;
4456 uint64_t result, *stat;
4459 sc_if = (struct msk_if_softc *)arg1;
4460 sc = sc_if->msk_softc;
4462 stat = (uint64_t *)((uint8_t *)&sc_if->msk_stats + off);
4465 result = MSK_READ_MIB64(sc_if->msk_port, GM_MIB_CNT_BASE + off * 2);
4467 MSK_IF_UNLOCK(sc_if);
4469 return (sysctl_handle_64(oidp, &result, 0, req));
4472 #undef MSK_READ_MIB32
4473 #undef MSK_READ_MIB64
4475 #define MSK_SYSCTL_STAT32(sc, c, o, p, n, d) \
4476 SYSCTL_ADD_PROC(c, p, OID_AUTO, o, CTLTYPE_UINT | CTLFLAG_RD, \
4477 sc, offsetof(struct msk_hw_stats, n), msk_sysctl_stat32, \
4479 #define MSK_SYSCTL_STAT64(sc, c, o, p, n, d) \
4480 SYSCTL_ADD_PROC(c, p, OID_AUTO, o, CTLTYPE_U64 | CTLFLAG_RD, \
4481 sc, offsetof(struct msk_hw_stats, n), msk_sysctl_stat64, \
4485 msk_sysctl_node(struct msk_if_softc *sc_if)
4487 struct sysctl_ctx_list *ctx;
4488 struct sysctl_oid_list *child, *schild;
4489 struct sysctl_oid *tree;
4491 ctx = device_get_sysctl_ctx(sc_if->msk_if_dev);
4492 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc_if->msk_if_dev));
4494 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD,
4495 NULL, "MSK Statistics");
4496 schild = SYSCTL_CHILDREN(tree);
4497 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "rx", CTLFLAG_RD,
4498 NULL, "MSK RX Statistics");
4499 child = SYSCTL_CHILDREN(tree);
4500 MSK_SYSCTL_STAT32(sc_if, ctx, "ucast_frames",
4501 child, rx_ucast_frames, "Good unicast frames");
4502 MSK_SYSCTL_STAT32(sc_if, ctx, "bcast_frames",
4503 child, rx_bcast_frames, "Good broadcast frames");
4504 MSK_SYSCTL_STAT32(sc_if, ctx, "pause_frames",
4505 child, rx_pause_frames, "Pause frames");
4506 MSK_SYSCTL_STAT32(sc_if, ctx, "mcast_frames",
4507 child, rx_mcast_frames, "Multicast frames");
4508 MSK_SYSCTL_STAT32(sc_if, ctx, "crc_errs",
4509 child, rx_crc_errs, "CRC errors");
4510 MSK_SYSCTL_STAT64(sc_if, ctx, "good_octets",
4511 child, rx_good_octets, "Good octets");
4512 MSK_SYSCTL_STAT64(sc_if, ctx, "bad_octets",
4513 child, rx_bad_octets, "Bad octets");
4514 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_64",
4515 child, rx_pkts_64, "64 bytes frames");
4516 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_65_127",
4517 child, rx_pkts_65_127, "65 to 127 bytes frames");
4518 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_128_255",
4519 child, rx_pkts_128_255, "128 to 255 bytes frames");
4520 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_256_511",
4521 child, rx_pkts_256_511, "256 to 511 bytes frames");
4522 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_512_1023",
4523 child, rx_pkts_512_1023, "512 to 1023 bytes frames");
4524 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1024_1518",
4525 child, rx_pkts_1024_1518, "1024 to 1518 bytes frames");
4526 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1519_max",
4527 child, rx_pkts_1519_max, "1519 to max frames");
4528 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_too_long",
4529 child, rx_pkts_too_long, "frames too long");
4530 MSK_SYSCTL_STAT32(sc_if, ctx, "jabbers",
4531 child, rx_pkts_jabbers, "Jabber errors");
4532 MSK_SYSCTL_STAT32(sc_if, ctx, "overflows",
4533 child, rx_fifo_oflows, "FIFO overflows");
4535 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx", CTLFLAG_RD,
4536 NULL, "MSK TX Statistics");
4537 child = SYSCTL_CHILDREN(tree);
4538 MSK_SYSCTL_STAT32(sc_if, ctx, "ucast_frames",
4539 child, tx_ucast_frames, "Unicast frames");
4540 MSK_SYSCTL_STAT32(sc_if, ctx, "bcast_frames",
4541 child, tx_bcast_frames, "Broadcast frames");
4542 MSK_SYSCTL_STAT32(sc_if, ctx, "pause_frames",
4543 child, tx_pause_frames, "Pause frames");
4544 MSK_SYSCTL_STAT32(sc_if, ctx, "mcast_frames",
4545 child, tx_mcast_frames, "Multicast frames");
4546 MSK_SYSCTL_STAT64(sc_if, ctx, "octets",
4547 child, tx_octets, "Octets");
4548 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_64",
4549 child, tx_pkts_64, "64 bytes frames");
4550 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_65_127",
4551 child, tx_pkts_65_127, "65 to 127 bytes frames");
4552 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_128_255",
4553 child, tx_pkts_128_255, "128 to 255 bytes frames");
4554 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_256_511",
4555 child, tx_pkts_256_511, "256 to 511 bytes frames");
4556 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_512_1023",
4557 child, tx_pkts_512_1023, "512 to 1023 bytes frames");
4558 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1024_1518",
4559 child, tx_pkts_1024_1518, "1024 to 1518 bytes frames");
4560 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1519_max",
4561 child, tx_pkts_1519_max, "1519 to max frames");
4562 MSK_SYSCTL_STAT32(sc_if, ctx, "colls",
4563 child, tx_colls, "Collisions");
4564 MSK_SYSCTL_STAT32(sc_if, ctx, "late_colls",
4565 child, tx_late_colls, "Late collisions");
4566 MSK_SYSCTL_STAT32(sc_if, ctx, "excess_colls",
4567 child, tx_excess_colls, "Excessive collisions");
4568 MSK_SYSCTL_STAT32(sc_if, ctx, "multi_colls",
4569 child, tx_multi_colls, "Multiple collisions");
4570 MSK_SYSCTL_STAT32(sc_if, ctx, "single_colls",
4571 child, tx_single_colls, "Single collisions");
4572 MSK_SYSCTL_STAT32(sc_if, ctx, "underflows",
4573 child, tx_underflows, "FIFO underflows");
4576 #undef MSK_SYSCTL_STAT32
4577 #undef MSK_SYSCTL_STAT64
4580 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
4586 value = *(int *)arg1;
4587 error = sysctl_handle_int(oidp, &value, 0, req);
4588 if (error || !req->newptr)
4590 if (value < low || value > high)
4592 *(int *)arg1 = value;
4598 sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS)
4601 return (sysctl_int_range(oidp, arg1, arg2, req, MSK_PROC_MIN,