sys/dev/mthca/mthca_cmd.c

   1 /*
   2  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
   4  * Copyright (c) 2005, 2006 Cisco Systems.  All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  */
  34
  35 #define LINUXKPI_PARAM_PREFIX mthca_
  36
  37 #include <linux/completion.h>
  38 #include <linux/pci.h>
  39 #include <linux/errno.h>
  40 #include <linux/sched.h>
  41 #include <linux/module.h>
  42 #include <linux/slab.h>
  43 #include <linux/page.h>
  44 #include <asm/io.h>
  45 #include <rdma/ib_mad.h>
  46
  47 #include "mthca_dev.h"
  48 #include "mthca_config_reg.h"
  49 #include "mthca_cmd.h"
  50 #include "mthca_memfree.h"
  51
  52 #define CMD_POLL_TOKEN 0xffff
  53
  54 enum {
  55         HCR_IN_PARAM_OFFSET    = 0x00,
  56         HCR_IN_MODIFIER_OFFSET = 0x08,
  57         HCR_OUT_PARAM_OFFSET   = 0x0c,
  58         HCR_TOKEN_OFFSET       = 0x14,
  59         HCR_STATUS_OFFSET      = 0x18,
  60
  61         HCR_OPMOD_SHIFT        = 12,
  62         HCA_E_BIT              = 22,
  63         HCR_GO_BIT             = 23
  64 };
  65
  66 enum {
  67         /* initialization and general commands */
  68         CMD_SYS_EN          = 0x1,
  69         CMD_SYS_DIS         = 0x2,
  70         CMD_MAP_FA          = 0xfff,
  71         CMD_UNMAP_FA        = 0xffe,
  72         CMD_RUN_FW          = 0xff6,
  73         CMD_MOD_STAT_CFG    = 0x34,
  74         CMD_QUERY_DEV_LIM   = 0x3,
  75         CMD_QUERY_FW        = 0x4,
  76         CMD_ENABLE_LAM      = 0xff8,
  77         CMD_DISABLE_LAM     = 0xff7,
  78         CMD_QUERY_DDR       = 0x5,
  79         CMD_QUERY_ADAPTER   = 0x6,
  80         CMD_INIT_HCA        = 0x7,
  81         CMD_CLOSE_HCA       = 0x8,
  82         CMD_INIT_IB         = 0x9,
  83         CMD_CLOSE_IB        = 0xa,
  84         CMD_QUERY_HCA       = 0xb,
  85         CMD_SET_IB          = 0xc,
  86         CMD_ACCESS_DDR      = 0x2e,
  87         CMD_MAP_ICM         = 0xffa,
  88         CMD_UNMAP_ICM       = 0xff9,
  89         CMD_MAP_ICM_AUX     = 0xffc,
  90         CMD_UNMAP_ICM_AUX   = 0xffb,
  91         CMD_SET_ICM_SIZE    = 0xffd,
  92
  93         /* TPT commands */
  94         CMD_SW2HW_MPT       = 0xd,
  95         CMD_QUERY_MPT       = 0xe,
  96         CMD_HW2SW_MPT       = 0xf,
  97         CMD_READ_MTT        = 0x10,
  98         CMD_WRITE_MTT       = 0x11,
  99         CMD_SYNC_TPT        = 0x2f,
 100
 101         /* EQ commands */
 102         CMD_MAP_EQ          = 0x12,
 103         CMD_SW2HW_EQ        = 0x13,
 104         CMD_HW2SW_EQ        = 0x14,
 105         CMD_QUERY_EQ        = 0x15,
 106
 107         /* CQ commands */
 108         CMD_SW2HW_CQ        = 0x16,
 109         CMD_HW2SW_CQ        = 0x17,
 110         CMD_QUERY_CQ        = 0x18,
 111         CMD_RESIZE_CQ       = 0x2c,
 112
 113         /* SRQ commands */
 114         CMD_SW2HW_SRQ       = 0x35,
 115         CMD_HW2SW_SRQ       = 0x36,
 116         CMD_QUERY_SRQ       = 0x37,
 117         CMD_ARM_SRQ         = 0x40,
 118
 119         /* QP/EE commands */
 120         CMD_RST2INIT_QPEE   = 0x19,
 121         CMD_INIT2RTR_QPEE   = 0x1a,
 122         CMD_RTR2RTS_QPEE    = 0x1b,
 123         CMD_RTS2RTS_QPEE    = 0x1c,
 124         CMD_SQERR2RTS_QPEE  = 0x1d,
 125         CMD_2ERR_QPEE       = 0x1e,
 126         CMD_RTS2SQD_QPEE    = 0x1f,
 127         CMD_SQD2SQD_QPEE    = 0x38,
 128         CMD_SQD2RTS_QPEE    = 0x20,
 129         CMD_ERR2RST_QPEE    = 0x21,
 130         CMD_QUERY_QPEE      = 0x22,
 131         CMD_INIT2INIT_QPEE  = 0x2d,
 132         CMD_SUSPEND_QPEE    = 0x32,
 133         CMD_UNSUSPEND_QPEE  = 0x33,
 134         /* special QPs and management commands */
 135         CMD_CONF_SPECIAL_QP = 0x23,
 136         CMD_MAD_IFC         = 0x24,
 137
 138         /* multicast commands */
 139         CMD_READ_MGM        = 0x25,
 140         CMD_WRITE_MGM       = 0x26,
 141         CMD_MGID_HASH       = 0x27,
 142
 143         /* miscellaneous commands */
 144         CMD_DIAG_RPRT       = 0x30,
 145         CMD_NOP             = 0x31,
 146
 147         /* debug commands */
 148         CMD_QUERY_DEBUG_MSG = 0x2a,
 149         CMD_SET_DEBUG_MSG   = 0x2b,
 150 };
 151
 152 /*
 153  * According to Mellanox code, FW may be starved and never complete
 154  * commands.  So we can't use strict timeouts described in PRM -- we
 155  * just arbitrarily select 60 seconds for now.
 156  */
 157 #if 0
 158 /*
 159  * Round up and add 1 to make sure we get the full wait time (since we
 160  * will be starting in the middle of a jiffy)
 161  */
 162 enum {
 163         CMD_TIME_CLASS_A = (HZ + 999) / 1000 + 1,
 164         CMD_TIME_CLASS_B = (HZ +  99) /  100 + 1,
 165         CMD_TIME_CLASS_C = (HZ +   9) /   10 + 1,
 166         CMD_TIME_CLASS_D = 60 * HZ
 167 };
 168 #else
 169 #define CMD_TIME_CLASS_A (60 * HZ)
 170 #define CMD_TIME_CLASS_B (60 * HZ)
 171 #define CMD_TIME_CLASS_C (60 * HZ)
 172 #define CMD_TIME_CLASS_D (60 * HZ)
 173 #endif
 174
 175 #define GO_BIT_TIMEOUT (HZ * 10)
 176
 177 struct mthca_cmd_context {
 178         struct completion done;
 179         int               result;
 180         int               next;
 181         u64               out_param;
 182         u16               token;
 183         u8                status;
 184 };
 185
 186 static int fw_cmd_doorbell = 0;
 187 module_param(fw_cmd_doorbell, int, 0644);
 188 MODULE_PARM_DESC(fw_cmd_doorbell, "post FW commands through doorbell page if nonzero "
 189                  "(and supported by FW)");
 190
 191 static inline int go_bit(struct mthca_dev *dev)
 192 {
 193         return readl(dev->hcr + HCR_STATUS_OFFSET) &
 194                 swab32(1 << HCR_GO_BIT);
 195 }
 196
 197 static void mthca_cmd_post_dbell(struct mthca_dev *dev,
 198                                  u64 in_param,
 199                                  u64 out_param,
 200                                  u32 in_modifier,
 201                                  u8 op_modifier,
 202                                  u16 op,
 203                                  u16 token)
 204 {
 205         void __iomem *ptr = dev->cmd.dbell_map;
 206         u16 *offs = dev->cmd.dbell_offsets;
 207
 208         __raw_writel((__force u32) cpu_to_be32(in_param >> 32),           ptr + offs[0]);
 209         wmb();
 210         __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful),  ptr + offs[1]);
 211         wmb();
 212         __raw_writel((__force u32) cpu_to_be32(in_modifier),              ptr + offs[2]);
 213         wmb();
 214         __raw_writel((__force u32) cpu_to_be32(out_param >> 32),          ptr + offs[3]);
 215         wmb();
 216         __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), ptr + offs[4]);
 217         wmb();
 218         __raw_writel((__force u32) cpu_to_be32(token << 16),              ptr + offs[5]);
 219         wmb();
 220         __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT)                |
 221                                                (1 << HCA_E_BIT)                 |
 222                                                (op_modifier << HCR_OPMOD_SHIFT) |
 223                                                 op),                      ptr + offs[6]);
 224         wmb();
 225         __raw_writel((__force u32) 0,                                     ptr + offs[7]);
 226         wmb();
 227 }
 228
 229 static int mthca_cmd_post_hcr(struct mthca_dev *dev,
 230                               u64 in_param,
 231                               u64 out_param,
 232                               u32 in_modifier,
 233                               u8 op_modifier,
 234                               u16 op,
 235                               u16 token,
 236                               int event)
 237 {
 238         if (event) {
 239                 unsigned long end = jiffies + GO_BIT_TIMEOUT;
 240
 241                 while (go_bit(dev) && time_before(jiffies, end)) {
 242                         set_current_state(TASK_RUNNING);
 243                         schedule();
 244                 }
 245         }
 246
 247         if (go_bit(dev))
 248                 return -EAGAIN;
 249
 250         /*
 251          * We use writel (instead of something like memcpy_toio)
 252          * because writes of less than 32 bits to the HCR don't work
 253          * (and some architectures such as ia64 implement memcpy_toio
 254          * in terms of writeb).
 255          */
 256         __raw_writel((__force u32) cpu_to_be32(in_param >> 32),           dev->hcr + 0 * 4);
 257         __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful),  dev->hcr + 1 * 4);
 258         __raw_writel((__force u32) cpu_to_be32(in_modifier),              dev->hcr + 2 * 4);
 259         __raw_writel((__force u32) cpu_to_be32(out_param >> 32),          dev->hcr + 3 * 4);
 260         __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), dev->hcr + 4 * 4);
 261         __raw_writel((__force u32) cpu_to_be32(token << 16),              dev->hcr + 5 * 4);
 262
 263         /* __raw_writel may not order writes. */
 264         wmb();
 265
 266         __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT)                |
 267                                                (event ? (1 << HCA_E_BIT) : 0)   |
 268                                                (op_modifier << HCR_OPMOD_SHIFT) |
 269                                                op),                       dev->hcr + 6 * 4);
 270
 271         return 0;
 272 }
 273
 274 static int mthca_cmd_post(struct mthca_dev *dev,
 275                           u64 in_param,
 276                           u64 out_param,
 277                           u32 in_modifier,
 278                           u8 op_modifier,
 279                           u16 op,
 280                           u16 token,
 281                           int event)
 282 {
 283         int err = 0;
 284
 285         mutex_lock(&dev->cmd.hcr_mutex);
 286
 287         if (event && dev->cmd.flags & MTHCA_CMD_POST_DOORBELLS && fw_cmd_doorbell)
 288                 mthca_cmd_post_dbell(dev, in_param, out_param, in_modifier,
 289                                            op_modifier, op, token);
 290         else
 291                 err = mthca_cmd_post_hcr(dev, in_param, out_param, in_modifier,
 292                                          op_modifier, op, token, event);
 293
 294         /*
 295          * Make sure that our HCR writes don't get mixed in with
 296          * writes from another CPU starting a FW command.
 297          */
 298         mmiowb();
 299
 300         mutex_unlock(&dev->cmd.hcr_mutex);
 301         return err;
 302 }
 303
 304 static int mthca_status_to_errno(u8 status)
 305 {
 306         static const int trans_table[] = {
 307                 [MTHCA_CMD_STAT_INTERNAL_ERR]   = -EIO,
 308                 [MTHCA_CMD_STAT_BAD_OP]         = -EPERM,
 309                 [MTHCA_CMD_STAT_BAD_PARAM]      = -EINVAL,
 310                 [MTHCA_CMD_STAT_BAD_SYS_STATE]  = -ENXIO,
 311                 [MTHCA_CMD_STAT_BAD_RESOURCE]   = -EBADF,
 312                 [MTHCA_CMD_STAT_RESOURCE_BUSY]  = -EBUSY,
 313                 [MTHCA_CMD_STAT_DDR_MEM_ERR]    = -ENOMEM,
 314                 [MTHCA_CMD_STAT_EXCEED_LIM]     = -ENOMEM,
 315                 [MTHCA_CMD_STAT_BAD_RES_STATE]  = -EBADF,
 316                 [MTHCA_CMD_STAT_BAD_INDEX]      = -EBADF,
 317                 [MTHCA_CMD_STAT_BAD_NVMEM]      = -EFAULT,
 318                 [MTHCA_CMD_STAT_BAD_QPEE_STATE] = -EINVAL,
 319                 [MTHCA_CMD_STAT_BAD_SEG_PARAM]  = -EFAULT,
 320                 [MTHCA_CMD_STAT_REG_BOUND]      = -EBUSY,
 321                 [MTHCA_CMD_STAT_LAM_NOT_PRE]    = -EAGAIN,
 322                 [MTHCA_CMD_STAT_BAD_PKT]        = -EBADMSG,
 323                 [MTHCA_CMD_STAT_BAD_SIZE]       = -ENOMEM,
 324         };
 325
 326         if (status >= ARRAY_SIZE(trans_table) ||
 327                         (status != MTHCA_CMD_STAT_OK
 328                          && trans_table[status] == 0))
 329                 return -EINVAL;
 330
 331         return trans_table[status];
 332 }
 333
 334 static int mthca_cmd_poll(struct mthca_dev *dev,
 335                           u64 in_param,
 336                           u64 *out_param,
 337                           int out_is_imm,
 338                           u32 in_modifier,
 339                           u8 op_modifier,
 340                           u16 op,
 341                           unsigned long timeout)
 342 {
 343         int err = 0;
 344         unsigned long end;
 345         u8 status;
 346
 347         down(&dev->cmd.poll_sem);
 348
 349         err = mthca_cmd_post(dev, in_param,
 350                              out_param ? *out_param : 0,
 351                              in_modifier, op_modifier,
 352                              op, CMD_POLL_TOKEN, 0);
 353         if (err)
 354                 goto out;
 355
 356         end = timeout + jiffies;
 357         while (go_bit(dev) && time_before(jiffies, end)) {
 358                 set_current_state(TASK_RUNNING);
 359                 schedule();
 360         }
 361
 362         if (go_bit(dev)) {
 363                 err = -EBUSY;
 364                 goto out;
 365         }
 366
 367         if (out_is_imm)
 368                 *out_param =
 369                         (u64) be32_to_cpu((__force __be32)
 370                                           __raw_readl(dev->hcr + HCR_OUT_PARAM_OFFSET)) << 32 |
 371                         (u64) be32_to_cpu((__force __be32)
 372                                           __raw_readl(dev->hcr + HCR_OUT_PARAM_OFFSET + 4));
 373
 374         status = be32_to_cpu((__force __be32) __raw_readl(dev->hcr + HCR_STATUS_OFFSET)) >> 24;
 375         if (status) {
 376                 mthca_dbg(dev, "Command %02x completed with status %02x\n",
 377                           op, status);
 378                 err = mthca_status_to_errno(status);
 379         }
 380
 381 out:
 382         up(&dev->cmd.poll_sem);
 383         return err;
 384 }
 385
 386 void mthca_cmd_event(struct mthca_dev *dev,
 387                      u16 token,
 388                      u8  status,
 389                      u64 out_param)
 390 {
 391         struct mthca_cmd_context *context =
 392                 &dev->cmd.context[token & dev->cmd.token_mask];
 393
 394         /* previously timed out command completing at long last */
 395         if (token != context->token)
 396                 return;
 397
 398         context->result    = 0;
 399         context->status    = status;
 400         context->out_param = out_param;
 401
 402         complete(&context->done);
 403 }
 404
 405 static int mthca_cmd_wait(struct mthca_dev *dev,
 406                           u64 in_param,
 407                           u64 *out_param,
 408                           int out_is_imm,
 409                           u32 in_modifier,
 410                           u8 op_modifier,
 411                           u16 op,
 412                           unsigned long timeout)
 413 {
 414         int err = 0;
 415         struct mthca_cmd_context *context;
 416
 417         down(&dev->cmd.event_sem);
 418
 419         spin_lock(&dev->cmd.context_lock);
 420         BUG_ON(dev->cmd.free_head < 0);
 421         context = &dev->cmd.context[dev->cmd.free_head];
 422         context->token += dev->cmd.token_mask + 1;
 423         dev->cmd.free_head = context->next;
 424         spin_unlock(&dev->cmd.context_lock);
 425
 426         init_completion(&context->done);
 427
 428         err = mthca_cmd_post(dev, in_param,
 429                              out_param ? *out_param : 0,
 430                              in_modifier, op_modifier,
 431                              op, context->token, 1);
 432         if (err)
 433                 goto out;
 434
 435         if (!wait_for_completion_timeout(&context->done, timeout)) {
 436                 err = -EBUSY;
 437                 goto out;
 438         }
 439
 440         err = context->result;
 441         if (err)
 442                 goto out;
 443
 444         if (context->status) {
 445                 mthca_dbg(dev, "Command %02x completed with status %02x\n",
 446                           op, context->status);
 447                 err = mthca_status_to_errno(context->status);
 448         }
 449
 450         if (out_is_imm)
 451                 *out_param = context->out_param;
 452
 453 out:
 454         spin_lock(&dev->cmd.context_lock);
 455         context->next = dev->cmd.free_head;
 456         dev->cmd.free_head = context - dev->cmd.context;
 457         spin_unlock(&dev->cmd.context_lock);
 458
 459         up(&dev->cmd.event_sem);
 460         return err;
 461 }
 462
 463 /* Invoke a command with an output mailbox */
 464 static int mthca_cmd_box(struct mthca_dev *dev,
 465                          u64 in_param,
 466                          u64 out_param,
 467                          u32 in_modifier,
 468                          u8 op_modifier,
 469                          u16 op,
 470                          unsigned long timeout)
 471 {
 472         if (dev->cmd.flags & MTHCA_CMD_USE_EVENTS)
 473                 return mthca_cmd_wait(dev, in_param, &out_param, 0,
 474                                       in_modifier, op_modifier, op,
 475                                       timeout);
 476         else
 477                 return mthca_cmd_poll(dev, in_param, &out_param, 0,
 478                                       in_modifier, op_modifier, op,
 479                                       timeout);
 480 }
 481
 482 /* Invoke a command with no output parameter */
 483 static int mthca_cmd(struct mthca_dev *dev,
 484                      u64 in_param,
 485                      u32 in_modifier,
 486                      u8 op_modifier,
 487                      u16 op,
 488                      unsigned long timeout)
 489 {
 490         return mthca_cmd_box(dev, in_param, 0, in_modifier,
 491                              op_modifier, op, timeout);
 492 }
 493
 494 /*
 495  * Invoke a command with an immediate output parameter (and copy the
 496  * output into the caller's out_param pointer after the command
 497  * executes).
 498  */
 499 static int mthca_cmd_imm(struct mthca_dev *dev,
 500                          u64 in_param,
 501                          u64 *out_param,
 502                          u32 in_modifier,
 503                          u8 op_modifier,
 504                          u16 op,
 505                          unsigned long timeout)
 506 {
 507         if (dev->cmd.flags & MTHCA_CMD_USE_EVENTS)
 508                 return mthca_cmd_wait(dev, in_param, out_param, 1,
 509                                       in_modifier, op_modifier, op,
 510                                       timeout);
 511         else
 512                 return mthca_cmd_poll(dev, in_param, out_param, 1,
 513                                       in_modifier, op_modifier, op,
 514                                       timeout);
 515 }
 516
 517 int mthca_cmd_init(struct mthca_dev *dev)
 518 {
 519         mutex_init(&dev->cmd.hcr_mutex);
 520         sema_init(&dev->cmd.poll_sem, 1);
 521         dev->cmd.flags = 0;
 522
 523         dev->hcr = ioremap(pci_resource_start(dev->pdev, 0) + MTHCA_HCR_BASE,
 524                            MTHCA_HCR_SIZE);
 525         if (!dev->hcr) {
 526                 mthca_err(dev, "Couldn't map command register.");
 527                 return -ENOMEM;
 528         }
 529
 530         dev->cmd.pool = pci_pool_create("mthca_cmd", dev->pdev,
 531                                         MTHCA_MAILBOX_SIZE,
 532                                         MTHCA_MAILBOX_SIZE, 0);
 533         if (!dev->cmd.pool) {
 534                 iounmap(dev->hcr);
 535                 return -ENOMEM;
 536         }
 537
 538         return 0;
 539 }
 540
 541 void mthca_cmd_cleanup(struct mthca_dev *dev)
 542 {
 543         pci_pool_destroy(dev->cmd.pool);
 544         iounmap(dev->hcr);
 545         if (dev->cmd.flags & MTHCA_CMD_POST_DOORBELLS)
 546                 iounmap(dev->cmd.dbell_map);
 547 }
 548
 549 /*
 550  * Switch to using events to issue FW commands (should be called after
 551  * event queue to command events has been initialized).
 552  */
 553 int mthca_cmd_use_events(struct mthca_dev *dev)
 554 {
 555         int i;
 556
 557         dev->cmd.context = kmalloc(dev->cmd.max_cmds *
 558                                    sizeof (struct mthca_cmd_context),
 559                                    GFP_KERNEL);
 560         if (!dev->cmd.context)
 561                 return -ENOMEM;
 562
 563         for (i = 0; i < dev->cmd.max_cmds; ++i) {
 564                 dev->cmd.context[i].token = i;
 565                 dev->cmd.context[i].next = i + 1;
 566         }
 567
 568         dev->cmd.context[dev->cmd.max_cmds - 1].next = -1;
 569         dev->cmd.free_head = 0;
 570
 571         sema_init(&dev->cmd.event_sem, dev->cmd.max_cmds);
 572         spin_lock_init(&dev->cmd.context_lock);
 573
 574         for (dev->cmd.token_mask = 1;
 575              dev->cmd.token_mask < dev->cmd.max_cmds;
 576              dev->cmd.token_mask <<= 1)
 577                 ; /* nothing */
 578         --dev->cmd.token_mask;
 579
 580         dev->cmd.flags |= MTHCA_CMD_USE_EVENTS;
 581
 582         down(&dev->cmd.poll_sem);
 583
 584         return 0;
 585 }
 586
 587 /*
 588  * Switch back to polling (used when shutting down the device)
 589  */
 590 void mthca_cmd_use_polling(struct mthca_dev *dev)
 591 {
 592         int i;
 593
 594         dev->cmd.flags &= ~MTHCA_CMD_USE_EVENTS;
 595
 596         for (i = 0; i < dev->cmd.max_cmds; ++i)
 597                 down(&dev->cmd.event_sem);
 598
 599         kfree(dev->cmd.context);
 600
 601         up(&dev->cmd.poll_sem);
 602 }
 603
 604 struct mthca_mailbox *mthca_alloc_mailbox(struct mthca_dev *dev,
 605                                           gfp_t gfp_mask)
 606 {
 607         struct mthca_mailbox *mailbox;
 608
 609         mailbox = kmalloc(sizeof *mailbox, gfp_mask);
 610         if (!mailbox)
 611                 return ERR_PTR(-ENOMEM);
 612
 613         mailbox->buf = pci_pool_alloc(dev->cmd.pool, gfp_mask, &mailbox->dma);
 614         if (!mailbox->buf) {
 615                 kfree(mailbox);
 616                 return ERR_PTR(-ENOMEM);
 617         }
 618
 619         return mailbox;
 620 }
 621
 622 void mthca_free_mailbox(struct mthca_dev *dev, struct mthca_mailbox *mailbox)
 623 {
 624         if (!mailbox)
 625                 return;
 626
 627         pci_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma);
 628         kfree(mailbox);
 629 }
 630
 631 int mthca_SYS_EN(struct mthca_dev *dev)
 632 {
 633         u64 out;
 634         int ret;
 635
 636         ret = mthca_cmd_imm(dev, 0, &out, 0, 0, CMD_SYS_EN, CMD_TIME_CLASS_D);
 637
 638         if (ret == -ENOMEM)
 639                 mthca_warn(dev, "SYS_EN DDR error: syn=%x, sock=%d, "
 640                            "sladdr=%d, SPD source=%s\n",
 641                            (int) (out >> 6) & 0xf, (int) (out >> 4) & 3,
 642                            (int) (out >> 1) & 7, (int) out & 1 ? "NVMEM" : "DIMM");
 643
 644         return ret;
 645 }
 646
 647 int mthca_SYS_DIS(struct mthca_dev *dev)
 648 {
 649         return mthca_cmd(dev, 0, 0, 0, CMD_SYS_DIS, CMD_TIME_CLASS_C);
 650 }
 651
 652 static int mthca_map_cmd(struct mthca_dev *dev, u16 op, struct mthca_icm *icm,
 653                          u64 virt)
 654 {
 655         struct mthca_mailbox *mailbox;
 656         struct mthca_icm_iter iter;
 657         __be64 *pages;
 658         int lg;
 659         int nent = 0;
 660         int i;
 661         int err = 0;
 662         int ts = 0, tc = 0;
 663
 664         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 665         if (IS_ERR(mailbox))
 666                 return PTR_ERR(mailbox);
 667         memset(mailbox->buf, 0, MTHCA_MAILBOX_SIZE);
 668         pages = mailbox->buf;
 669
 670         for (mthca_icm_first(icm, &iter);
 671              !mthca_icm_last(&iter);
 672              mthca_icm_next(&iter)) {
 673                 /*
 674                  * We have to pass pages that are aligned to their
 675                  * size, so find the least significant 1 in the
 676                  * address or size and use that as our log2 size.
 677                  */
 678                 lg = ffs(mthca_icm_addr(&iter) | mthca_icm_size(&iter)) - 1;
 679                 if (lg < MTHCA_ICM_PAGE_SHIFT) {
 680                         mthca_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n",
 681                                    MTHCA_ICM_PAGE_SIZE,
 682                                    (unsigned long long) mthca_icm_addr(&iter),
 683                                    mthca_icm_size(&iter));
 684                         err = -EINVAL;
 685                         goto out;
 686                 }
 687                 for (i = 0; i < mthca_icm_size(&iter) >> lg; ++i) {
 688                         if (virt != -1) {
 689                                 pages[nent * 2] = cpu_to_be64(virt);
 690                                 virt += 1 << lg;
 691                         }
 692
 693                         pages[nent * 2 + 1] =
 694                                 cpu_to_be64((mthca_icm_addr(&iter) + (i << lg)) |
 695                                             (lg - MTHCA_ICM_PAGE_SHIFT));
 696                         ts += 1 << (lg - 10);
 697                         ++tc;
 698
 699                         if (++nent == MTHCA_MAILBOX_SIZE / 16) {
 700                                 err = mthca_cmd(dev, mailbox->dma, nent, 0, op,
 701                                                 CMD_TIME_CLASS_B);
 702                                 if (err)
 703                                         goto out;
 704                                 nent = 0;
 705                         }
 706                 }
 707         }
 708
 709         if (nent)
 710                 err = mthca_cmd(dev, mailbox->dma, nent, 0, op,
 711                                 CMD_TIME_CLASS_B);
 712
 713         switch (op) {
 714         case CMD_MAP_FA:
 715                 mthca_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts);
 716                 break;
 717         case CMD_MAP_ICM_AUX:
 718                 mthca_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts);
 719                 break;
 720         case CMD_MAP_ICM:
 721                 mthca_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n",
 722                           tc, ts, (unsigned long long) virt - (ts << 10));
 723                 break;
 724         }
 725
 726 out:
 727         mthca_free_mailbox(dev, mailbox);
 728         return err;
 729 }
 730
 731 int mthca_MAP_FA(struct mthca_dev *dev, struct mthca_icm *icm)
 732 {
 733         return mthca_map_cmd(dev, CMD_MAP_FA, icm, -1);
 734 }
 735
 736 int mthca_UNMAP_FA(struct mthca_dev *dev)
 737 {
 738         return mthca_cmd(dev, 0, 0, 0, CMD_UNMAP_FA, CMD_TIME_CLASS_B);
 739 }
 740
 741 int mthca_RUN_FW(struct mthca_dev *dev)
 742 {
 743         return mthca_cmd(dev, 0, 0, 0, CMD_RUN_FW, CMD_TIME_CLASS_A);
 744 }
 745
 746 static void mthca_setup_cmd_doorbells(struct mthca_dev *dev, u64 base)
 747 {
 748         phys_addr_t addr;
 749         u16 max_off = 0;
 750         int i;
 751
 752         for (i = 0; i < 8; ++i)
 753                 max_off = max(max_off, dev->cmd.dbell_offsets[i]);
 754
 755         if ((base & PAGE_MASK) != ((base + max_off) & PAGE_MASK)) {
 756                 mthca_warn(dev, "Firmware doorbell region at 0x%016llx, "
 757                            "length 0x%x crosses a page boundary\n",
 758                            (unsigned long long) base, max_off);
 759                 return;
 760         }
 761
 762         addr = pci_resource_start(dev->pdev, 2) +
 763                 ((pci_resource_len(dev->pdev, 2) - 1) & base);
 764         dev->cmd.dbell_map = ioremap(addr, max_off + sizeof(u32));
 765         if (!dev->cmd.dbell_map)
 766                 return;
 767
 768         dev->cmd.flags |= MTHCA_CMD_POST_DOORBELLS;
 769         mthca_dbg(dev, "Mapped doorbell page for posting FW commands\n");
 770 }
 771
 772 int mthca_QUERY_FW(struct mthca_dev *dev)
 773 {
 774         struct mthca_mailbox *mailbox;
 775         u32 *outbox;
 776         u64 base;
 777         u32 tmp;
 778         int err = 0;
 779         u8 lg;
 780         int i;
 781
 782 #define QUERY_FW_OUT_SIZE             0x100
 783 #define QUERY_FW_VER_OFFSET            0x00
 784 #define QUERY_FW_MAX_CMD_OFFSET        0x0f
 785 #define QUERY_FW_ERR_START_OFFSET      0x30
 786 #define QUERY_FW_ERR_SIZE_OFFSET       0x38
 787
 788 #define QUERY_FW_CMD_DB_EN_OFFSET      0x10
 789 #define QUERY_FW_CMD_DB_OFFSET         0x50
 790 #define QUERY_FW_CMD_DB_BASE           0x60
 791
 792 #define QUERY_FW_START_OFFSET          0x20
 793 #define QUERY_FW_END_OFFSET            0x28
 794
 795 #define QUERY_FW_SIZE_OFFSET           0x00
 796 #define QUERY_FW_CLR_INT_BASE_OFFSET   0x20
 797 #define QUERY_FW_EQ_ARM_BASE_OFFSET    0x40
 798 #define QUERY_FW_EQ_SET_CI_BASE_OFFSET 0x48
 799
 800         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 801         if (IS_ERR(mailbox))
 802                 return PTR_ERR(mailbox);
 803         outbox = mailbox->buf;
 804
 805         err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_FW,
 806                             CMD_TIME_CLASS_A);
 807
 808         if (err)
 809                 goto out;
 810
 811         MTHCA_GET(dev->fw_ver,   outbox, QUERY_FW_VER_OFFSET);
 812         /*
 813          * FW subminor version is at more significant bits than minor
 814          * version, so swap here.
 815          */
 816         dev->fw_ver = (dev->fw_ver & 0xffff00000000ull) |
 817                 ((dev->fw_ver & 0xffff0000ull) >> 16) |
 818                 ((dev->fw_ver & 0x0000ffffull) << 16);
 819
 820         MTHCA_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
 821         dev->cmd.max_cmds = 1 << lg;
 822
 823         mthca_dbg(dev, "FW version %012llx, max commands %d\n",
 824                   (unsigned long long) dev->fw_ver, dev->cmd.max_cmds);
 825
 826         MTHCA_GET(dev->catas_err.addr, outbox, QUERY_FW_ERR_START_OFFSET);
 827         MTHCA_GET(dev->catas_err.size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
 828
 829         mthca_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x\n",
 830                   (unsigned long long) dev->catas_err.addr, dev->catas_err.size);
 831
 832         MTHCA_GET(tmp, outbox, QUERY_FW_CMD_DB_EN_OFFSET);
 833         if (tmp & 0x1) {
 834                 mthca_dbg(dev, "FW supports commands through doorbells\n");
 835
 836                 MTHCA_GET(base, outbox, QUERY_FW_CMD_DB_BASE);
 837                 for (i = 0; i < MTHCA_CMD_NUM_DBELL_DWORDS; ++i)
 838                         MTHCA_GET(dev->cmd.dbell_offsets[i], outbox,
 839                                   QUERY_FW_CMD_DB_OFFSET + (i << 1));
 840
 841                 mthca_setup_cmd_doorbells(dev, base);
 842         }
 843
 844         if (mthca_is_memfree(dev)) {
 845                 MTHCA_GET(dev->fw.arbel.fw_pages,       outbox, QUERY_FW_SIZE_OFFSET);
 846                 MTHCA_GET(dev->fw.arbel.clr_int_base,   outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
 847                 MTHCA_GET(dev->fw.arbel.eq_arm_base,    outbox, QUERY_FW_EQ_ARM_BASE_OFFSET);
 848                 MTHCA_GET(dev->fw.arbel.eq_set_ci_base, outbox, QUERY_FW_EQ_SET_CI_BASE_OFFSET);
 849                 mthca_dbg(dev, "FW size %d KB\n", dev->fw.arbel.fw_pages << 2);
 850
 851                 /*
 852                  * Round up number of system pages needed in case
 853                  * MTHCA_ICM_PAGE_SIZE < PAGE_SIZE.
 854                  */
 855                 dev->fw.arbel.fw_pages =
 856                         ALIGN(dev->fw.arbel.fw_pages, PAGE_SIZE / MTHCA_ICM_PAGE_SIZE) >>
 857                                 (PAGE_SHIFT - MTHCA_ICM_PAGE_SHIFT);
 858
 859                 mthca_dbg(dev, "Clear int @ %llx, EQ arm @ %llx, EQ set CI @ %llx\n",
 860                           (unsigned long long) dev->fw.arbel.clr_int_base,
 861                           (unsigned long long) dev->fw.arbel.eq_arm_base,
 862                           (unsigned long long) dev->fw.arbel.eq_set_ci_base);
 863         } else {
 864                 MTHCA_GET(dev->fw.tavor.fw_start, outbox, QUERY_FW_START_OFFSET);
 865                 MTHCA_GET(dev->fw.tavor.fw_end,   outbox, QUERY_FW_END_OFFSET);
 866
 867                 mthca_dbg(dev, "FW size %d KB (start %llx, end %llx)\n",
 868                           (int) ((dev->fw.tavor.fw_end - dev->fw.tavor.fw_start) >> 10),
 869                           (unsigned long long) dev->fw.tavor.fw_start,
 870                           (unsigned long long) dev->fw.tavor.fw_end);
 871         }
 872
 873 out:
 874         mthca_free_mailbox(dev, mailbox);
 875         return err;
 876 }
 877
 878 int mthca_ENABLE_LAM(struct mthca_dev *dev)
 879 {
 880         struct mthca_mailbox *mailbox;
 881         u8 info;
 882         u32 *outbox;
 883         int err = 0;
 884
 885 #define ENABLE_LAM_OUT_SIZE         0x100
 886 #define ENABLE_LAM_START_OFFSET     0x00
 887 #define ENABLE_LAM_END_OFFSET       0x08
 888 #define ENABLE_LAM_INFO_OFFSET      0x13
 889
 890 #define ENABLE_LAM_INFO_HIDDEN_FLAG (1 << 4)
 891 #define ENABLE_LAM_INFO_ECC_MASK    0x3
 892
 893         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 894         if (IS_ERR(mailbox))
 895                 return PTR_ERR(mailbox);
 896         outbox = mailbox->buf;
 897
 898         err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_ENABLE_LAM,
 899                             CMD_TIME_CLASS_C);
 900
 901         if (err)
 902                 goto out;
 903
 904         MTHCA_GET(dev->ddr_start, outbox, ENABLE_LAM_START_OFFSET);
 905         MTHCA_GET(dev->ddr_end,   outbox, ENABLE_LAM_END_OFFSET);
 906         MTHCA_GET(info,           outbox, ENABLE_LAM_INFO_OFFSET);
 907
 908         if (!!(info & ENABLE_LAM_INFO_HIDDEN_FLAG) !=
 909             !!(dev->mthca_flags & MTHCA_FLAG_DDR_HIDDEN)) {
 910                 mthca_info(dev, "FW reports that HCA-attached memory "
 911                            "is %s hidden; does not match PCI config\n",
 912                            (info & ENABLE_LAM_INFO_HIDDEN_FLAG) ?
 913                            "" : "not");
 914         }
 915         if (info & ENABLE_LAM_INFO_HIDDEN_FLAG)
 916                 mthca_dbg(dev, "HCA-attached memory is hidden.\n");
 917
 918         mthca_dbg(dev, "HCA memory size %d KB (start %llx, end %llx)\n",
 919                   (int) ((dev->ddr_end - dev->ddr_start) >> 10),
 920                   (unsigned long long) dev->ddr_start,
 921                   (unsigned long long) dev->ddr_end);
 922
 923 out:
 924         mthca_free_mailbox(dev, mailbox);
 925         return err;
 926 }
 927
 928 int mthca_DISABLE_LAM(struct mthca_dev *dev)
 929 {
 930         return mthca_cmd(dev, 0, 0, 0, CMD_SYS_DIS, CMD_TIME_CLASS_C);
 931 }
 932
 933 int mthca_QUERY_DDR(struct mthca_dev *dev)
 934 {
 935         struct mthca_mailbox *mailbox;
 936         u8 info;
 937         u32 *outbox;
 938         int err = 0;
 939
 940 #define QUERY_DDR_OUT_SIZE         0x100
 941 #define QUERY_DDR_START_OFFSET     0x00
 942 #define QUERY_DDR_END_OFFSET       0x08
 943 #define QUERY_DDR_INFO_OFFSET      0x13
 944
 945 #define QUERY_DDR_INFO_HIDDEN_FLAG (1 << 4)
 946 #define QUERY_DDR_INFO_ECC_MASK    0x3
 947
 948         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 949         if (IS_ERR(mailbox))
 950                 return PTR_ERR(mailbox);
 951         outbox = mailbox->buf;
 952
 953         err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_DDR,
 954                             CMD_TIME_CLASS_A);
 955
 956         if (err)
 957                 goto out;
 958
 959         MTHCA_GET(dev->ddr_start, outbox, QUERY_DDR_START_OFFSET);
 960         MTHCA_GET(dev->ddr_end,   outbox, QUERY_DDR_END_OFFSET);
 961         MTHCA_GET(info,           outbox, QUERY_DDR_INFO_OFFSET);
 962
 963         if (!!(info & QUERY_DDR_INFO_HIDDEN_FLAG) !=
 964             !!(dev->mthca_flags & MTHCA_FLAG_DDR_HIDDEN)) {
 965                 mthca_info(dev, "FW reports that HCA-attached memory "
 966                            "is %s hidden; does not match PCI config\n",
 967                            (info & QUERY_DDR_INFO_HIDDEN_FLAG) ?
 968                            "" : "not");
 969         }
 970         if (info & QUERY_DDR_INFO_HIDDEN_FLAG)
 971                 mthca_dbg(dev, "HCA-attached memory is hidden.\n");
 972
 973         mthca_dbg(dev, "HCA memory size %d KB (start %llx, end %llx)\n",
 974                   (int) ((dev->ddr_end - dev->ddr_start) >> 10),
 975                   (unsigned long long) dev->ddr_start,
 976                   (unsigned long long) dev->ddr_end);
 977
 978 out:
 979         mthca_free_mailbox(dev, mailbox);
 980         return err;
 981 }
 982
 983 int mthca_QUERY_DEV_LIM(struct mthca_dev *dev,
 984                         struct mthca_dev_lim *dev_lim)
 985 {
 986         struct mthca_mailbox *mailbox;
 987         u32 *outbox;
 988         u8 field;
 989         u16 size;
 990         u16 stat_rate;
 991         int err;
 992
 993 #define QUERY_DEV_LIM_OUT_SIZE             0x100
 994 #define QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET     0x10
 995 #define QUERY_DEV_LIM_MAX_QP_SZ_OFFSET      0x11
 996 #define QUERY_DEV_LIM_RSVD_QP_OFFSET        0x12
 997 #define QUERY_DEV_LIM_MAX_QP_OFFSET         0x13
 998 #define QUERY_DEV_LIM_RSVD_SRQ_OFFSET       0x14
 999 #define QUERY_DEV_LIM_MAX_SRQ_OFFSET        0x15
1000 #define QUERY_DEV_LIM_RSVD_EEC_OFFSET       0x16
1001 #define QUERY_DEV_LIM_MAX_EEC_OFFSET        0x17
1002 #define QUERY_DEV_LIM_MAX_CQ_SZ_OFFSET      0x19
1003 #define QUERY_DEV_LIM_RSVD_CQ_OFFSET        0x1a
1004 #define QUERY_DEV_LIM_MAX_CQ_OFFSET         0x1b
1005 #define QUERY_DEV_LIM_MAX_MPT_OFFSET        0x1d
1006 #define QUERY_DEV_LIM_RSVD_EQ_OFFSET        0x1e
1007 #define QUERY_DEV_LIM_MAX_EQ_OFFSET         0x1f
1008 #define QUERY_DEV_LIM_RSVD_MTT_OFFSET       0x20
1009 #define QUERY_DEV_LIM_MAX_MRW_SZ_OFFSET     0x21
1010 #define QUERY_DEV_LIM_RSVD_MRW_OFFSET       0x22
1011 #define QUERY_DEV_LIM_MAX_MTT_SEG_OFFSET    0x23
1012 #define QUERY_DEV_LIM_MAX_AV_OFFSET         0x27
1013 #define QUERY_DEV_LIM_MAX_REQ_QP_OFFSET     0x29
1014 #define QUERY_DEV_LIM_MAX_RES_QP_OFFSET     0x2b
1015 #define QUERY_DEV_LIM_MAX_RDMA_OFFSET       0x2f
1016 #define QUERY_DEV_LIM_RSZ_SRQ_OFFSET        0x33
1017 #define QUERY_DEV_LIM_ACK_DELAY_OFFSET      0x35
1018 #define QUERY_DEV_LIM_MTU_WIDTH_OFFSET      0x36
1019 #define QUERY_DEV_LIM_VL_PORT_OFFSET        0x37
1020 #define QUERY_DEV_LIM_MAX_GID_OFFSET        0x3b
1021 #define QUERY_DEV_LIM_RATE_SUPPORT_OFFSET   0x3c
1022 #define QUERY_DEV_LIM_MAX_PKEY_OFFSET       0x3f
1023 #define QUERY_DEV_LIM_FLAGS_OFFSET          0x44
1024 #define QUERY_DEV_LIM_RSVD_UAR_OFFSET       0x48
1025 #define QUERY_DEV_LIM_UAR_SZ_OFFSET         0x49
1026 #define QUERY_DEV_LIM_PAGE_SZ_OFFSET        0x4b
1027 #define QUERY_DEV_LIM_MAX_SG_OFFSET         0x51
1028 #define QUERY_DEV_LIM_MAX_DESC_SZ_OFFSET    0x52
1029 #define QUERY_DEV_LIM_MAX_SG_RQ_OFFSET      0x55
1030 #define QUERY_DEV_LIM_MAX_DESC_SZ_RQ_OFFSET 0x56
1031 #define QUERY_DEV_LIM_MAX_QP_MCG_OFFSET     0x61
1032 #define QUERY_DEV_LIM_RSVD_MCG_OFFSET       0x62
1033 #define QUERY_DEV_LIM_MAX_MCG_OFFSET        0x63
1034 #define QUERY_DEV_LIM_RSVD_PD_OFFSET        0x64
1035 #define QUERY_DEV_LIM_MAX_PD_OFFSET         0x65
1036 #define QUERY_DEV_LIM_RSVD_RDD_OFFSET       0x66
1037 #define QUERY_DEV_LIM_MAX_RDD_OFFSET        0x67
1038 #define QUERY_DEV_LIM_EEC_ENTRY_SZ_OFFSET   0x80
1039 #define QUERY_DEV_LIM_QPC_ENTRY_SZ_OFFSET   0x82
1040 #define QUERY_DEV_LIM_EEEC_ENTRY_SZ_OFFSET  0x84
1041 #define QUERY_DEV_LIM_EQPC_ENTRY_SZ_OFFSET  0x86
1042 #define QUERY_DEV_LIM_EQC_ENTRY_SZ_OFFSET   0x88
1043 #define QUERY_DEV_LIM_CQC_ENTRY_SZ_OFFSET   0x8a
1044 #define QUERY_DEV_LIM_SRQ_ENTRY_SZ_OFFSET   0x8c
1045 #define QUERY_DEV_LIM_UAR_ENTRY_SZ_OFFSET   0x8e
1046 #define QUERY_DEV_LIM_MTT_ENTRY_SZ_OFFSET   0x90
1047 #define QUERY_DEV_LIM_MPT_ENTRY_SZ_OFFSET   0x92
1048 #define QUERY_DEV_LIM_PBL_SZ_OFFSET         0x96
1049 #define QUERY_DEV_LIM_BMME_FLAGS_OFFSET     0x97
1050 #define QUERY_DEV_LIM_RSVD_LKEY_OFFSET      0x98
1051 #define QUERY_DEV_LIM_LAMR_OFFSET           0x9f
1052 #define QUERY_DEV_LIM_MAX_ICM_SZ_OFFSET     0xa0
1053
1054         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1055         if (IS_ERR(mailbox))
1056                 return PTR_ERR(mailbox);
1057         outbox = mailbox->buf;
1058
1059         err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_DEV_LIM,
1060                             CMD_TIME_CLASS_A);
1061
1062         if (err)
1063                 goto out;
1064
1065         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_QP_OFFSET);
1066         dev_lim->reserved_qps = 1 << (field & 0xf);
1067         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_OFFSET);
1068         dev_lim->max_qps = 1 << (field & 0x1f);
1069         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_SRQ_OFFSET);
1070         dev_lim->reserved_srqs = 1 << (field >> 4);
1071         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_OFFSET);
1072         dev_lim->max_srqs = 1 << (field & 0x1f);
1073         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_EEC_OFFSET);
1074         dev_lim->reserved_eecs = 1 << (field & 0xf);
1075         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_EEC_OFFSET);
1076         dev_lim->max_eecs = 1 << (field & 0x1f);
1077         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_CQ_SZ_OFFSET);
1078         dev_lim->max_cq_sz = 1 << field;
1079         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_CQ_OFFSET);
1080         dev_lim->reserved_cqs = 1 << (field & 0xf);
1081         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_CQ_OFFSET);
1082         dev_lim->max_cqs = 1 << (field & 0x1f);
1083         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MPT_OFFSET);
1084         dev_lim->max_mpts = 1 << (field & 0x3f);
1085         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_EQ_OFFSET);
1086         dev_lim->reserved_eqs = 1 << (field & 0xf);
1087         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_EQ_OFFSET);
1088         dev_lim->max_eqs = 1 << (field & 0x7);
1089         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MTT_OFFSET);
1090         if (mthca_is_memfree(dev))
1091                 dev_lim->reserved_mtts = ALIGN((1 << (field >> 4)) * sizeof(u64),
1092                                                dev->limits.mtt_seg_size) / dev->limits.mtt_seg_size;
1093         else
1094                 dev_lim->reserved_mtts = 1 << (field >> 4);
1095         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MRW_SZ_OFFSET);
1096         dev_lim->max_mrw_sz = 1 << field;
1097         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MRW_OFFSET);
1098         dev_lim->reserved_mrws = 1 << (field & 0xf);
1099         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MTT_SEG_OFFSET);
1100         dev_lim->max_mtt_seg = 1 << (field & 0x3f);
1101         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_REQ_QP_OFFSET);
1102         dev_lim->max_requester_per_qp = 1 << (field & 0x3f);
1103         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RES_QP_OFFSET);
1104         dev_lim->max_responder_per_qp = 1 << (field & 0x3f);
1105         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RDMA_OFFSET);
1106         dev_lim->max_rdma_global = 1 << (field & 0x3f);
1107         MTHCA_GET(field, outbox, QUERY_DEV_LIM_ACK_DELAY_OFFSET);
1108         dev_lim->local_ca_ack_delay = field & 0x1f;
1109         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MTU_WIDTH_OFFSET);
1110         dev_lim->max_mtu        = field >> 4;
1111         dev_lim->max_port_width = field & 0xf;
1112         MTHCA_GET(field, outbox, QUERY_DEV_LIM_VL_PORT_OFFSET);
1113         dev_lim->max_vl    = field >> 4;
1114         dev_lim->num_ports = field & 0xf;
1115         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_GID_OFFSET);
1116         dev_lim->max_gids = 1 << (field & 0xf);
1117         MTHCA_GET(stat_rate, outbox, QUERY_DEV_LIM_RATE_SUPPORT_OFFSET);
1118         dev_lim->stat_rate_support = stat_rate;
1119         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_PKEY_OFFSET);
1120         dev_lim->max_pkeys = 1 << (field & 0xf);
1121         MTHCA_GET(dev_lim->flags, outbox, QUERY_DEV_LIM_FLAGS_OFFSET);
1122         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_UAR_OFFSET);
1123         dev_lim->reserved_uars = field >> 4;
1124         MTHCA_GET(field, outbox, QUERY_DEV_LIM_UAR_SZ_OFFSET);
1125         dev_lim->uar_size = 1 << ((field & 0x3f) + 20);
1126         MTHCA_GET(field, outbox, QUERY_DEV_LIM_PAGE_SZ_OFFSET);
1127         dev_lim->min_page_sz = 1 << field;
1128         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SG_OFFSET);
1129         dev_lim->max_sg = field;
1130
1131         MTHCA_GET(size, outbox, QUERY_DEV_LIM_MAX_DESC_SZ_OFFSET);
1132         dev_lim->max_desc_sz = size;
1133
1134         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_MCG_OFFSET);
1135         dev_lim->max_qp_per_mcg = 1 << field;
1136         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MCG_OFFSET);
1137         dev_lim->reserved_mgms = field & 0xf;
1138         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MCG_OFFSET);
1139         dev_lim->max_mcgs = 1 << field;
1140         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_PD_OFFSET);
1141         dev_lim->reserved_pds = field >> 4;
1142         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_PD_OFFSET);
1143         dev_lim->max_pds = 1 << (field & 0x3f);
1144         MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_RDD_OFFSET);
1145         dev_lim->reserved_rdds = field >> 4;
1146         MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RDD_OFFSET);
1147         dev_lim->max_rdds = 1 << (field & 0x3f);
1148
1149         MTHCA_GET(size, outbox, QUERY_DEV_LIM_EEC_ENTRY_SZ_OFFSET);
1150         dev_lim->eec_entry_sz = size;
1151         MTHCA_GET(size, outbox, QUERY_DEV_LIM_QPC_ENTRY_SZ_OFFSET);
1152         dev_lim->qpc_entry_sz = size;
1153         MTHCA_GET(size, outbox, QUERY_DEV_LIM_EEEC_ENTRY_SZ_OFFSET);
1154         dev_lim->eeec_entry_sz = size;
1155         MTHCA_GET(size, outbox, QUERY_DEV_LIM_EQPC_ENTRY_SZ_OFFSET);
1156         dev_lim->eqpc_entry_sz = size;
1157         MTHCA_GET(size, outbox, QUERY_DEV_LIM_EQC_ENTRY_SZ_OFFSET);
1158         dev_lim->eqc_entry_sz = size;
1159         MTHCA_GET(size, outbox, QUERY_DEV_LIM_CQC_ENTRY_SZ_OFFSET);
1160         dev_lim->cqc_entry_sz = size;
1161         MTHCA_GET(size, outbox, QUERY_DEV_LIM_SRQ_ENTRY_SZ_OFFSET);
1162         dev_lim->srq_entry_sz = size;
1163         MTHCA_GET(size, outbox, QUERY_DEV_LIM_UAR_ENTRY_SZ_OFFSET);
1164         dev_lim->uar_scratch_entry_sz = size;
1165
1166         if (mthca_is_memfree(dev)) {
1167                 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET);
1168                 dev_lim->max_srq_sz = 1 << field;
1169                 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_SZ_OFFSET);
1170                 dev_lim->max_qp_sz = 1 << field;
1171                 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSZ_SRQ_OFFSET);
1172                 dev_lim->hca.arbel.resize_srq = field & 1;
1173                 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SG_RQ_OFFSET);
1174                 dev_lim->max_sg = min_t(int, field, dev_lim->max_sg);
1175                 MTHCA_GET(size, outbox, QUERY_DEV_LIM_MAX_DESC_SZ_RQ_OFFSET);
1176                 dev_lim->max_desc_sz = min_t(int, size, dev_lim->max_desc_sz);
1177                 MTHCA_GET(size, outbox, QUERY_DEV_LIM_MPT_ENTRY_SZ_OFFSET);
1178                 dev_lim->mpt_entry_sz = size;
1179                 MTHCA_GET(field, outbox, QUERY_DEV_LIM_PBL_SZ_OFFSET);
1180                 dev_lim->hca.arbel.max_pbl_sz = 1 << (field & 0x3f);
1181                 MTHCA_GET(dev_lim->hca.arbel.bmme_flags, outbox,
1182                           QUERY_DEV_LIM_BMME_FLAGS_OFFSET);
1183                 MTHCA_GET(dev_lim->hca.arbel.reserved_lkey, outbox,
1184                           QUERY_DEV_LIM_RSVD_LKEY_OFFSET);
1185                 MTHCA_GET(field, outbox, QUERY_DEV_LIM_LAMR_OFFSET);
1186                 dev_lim->hca.arbel.lam_required = field & 1;
1187                 MTHCA_GET(dev_lim->hca.arbel.max_icm_sz, outbox,
1188                           QUERY_DEV_LIM_MAX_ICM_SZ_OFFSET);
1189
1190                 if (dev_lim->hca.arbel.bmme_flags & 1)
1191                         mthca_dbg(dev, "Base MM extensions: yes "
1192                                   "(flags %d, max PBL %d, rsvd L_Key %08x)\n",
1193                                   dev_lim->hca.arbel.bmme_flags,
1194                                   dev_lim->hca.arbel.max_pbl_sz,
1195                                   dev_lim->hca.arbel.reserved_lkey);
1196                 else
1197                         mthca_dbg(dev, "Base MM extensions: no\n");
1198
1199                 mthca_dbg(dev, "Max ICM size %lld MB\n",
1200                           (unsigned long long) dev_lim->hca.arbel.max_icm_sz >> 20);
1201         } else {
1202                 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET);
1203                 dev_lim->max_srq_sz = (1 << field) - 1;
1204                 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_SZ_OFFSET);
1205                 dev_lim->max_qp_sz = (1 << field) - 1;
1206                 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_AV_OFFSET);
1207                 dev_lim->hca.tavor.max_avs = 1 << (field & 0x3f);
1208                 dev_lim->mpt_entry_sz = MTHCA_MPT_ENTRY_SIZE;
1209         }
1210
1211         mthca_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
1212                   dev_lim->max_qps, dev_lim->reserved_qps, dev_lim->qpc_entry_sz);
1213         mthca_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
1214                   dev_lim->max_srqs, dev_lim->reserved_srqs, dev_lim->srq_entry_sz);
1215         mthca_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
1216                   dev_lim->max_cqs, dev_lim->reserved_cqs, dev_lim->cqc_entry_sz);
1217         mthca_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",
1218                   dev_lim->max_eqs, dev_lim->reserved_eqs, dev_lim->eqc_entry_sz);
1219         mthca_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
1220                   dev_lim->reserved_mrws, dev_lim->reserved_mtts);
1221         mthca_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
1222                   dev_lim->max_pds, dev_lim->reserved_pds, dev_lim->reserved_uars);
1223         mthca_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
1224                   dev_lim->max_pds, dev_lim->reserved_mgms);
1225         mthca_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
1226                   dev_lim->max_cq_sz, dev_lim->max_qp_sz, dev_lim->max_srq_sz);
1227
1228         mthca_dbg(dev, "Flags: %08x\n", dev_lim->flags);
1229
1230 out:
1231         mthca_free_mailbox(dev, mailbox);
1232         return err;
1233 }
1234
1235 static void get_board_id(void *vsd, char *board_id)
1236 {
1237         int i;
1238
1239 #define VSD_OFFSET_SIG1         0x00
1240 #define VSD_OFFSET_SIG2         0xde
1241 #define VSD_OFFSET_MLX_BOARD_ID 0xd0
1242 #define VSD_OFFSET_TS_BOARD_ID  0x20
1243
1244 #define VSD_SIGNATURE_TOPSPIN   0x5ad
1245
1246         memset(board_id, 0, MTHCA_BOARD_ID_LEN);
1247
1248         if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
1249             be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
1250                 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MTHCA_BOARD_ID_LEN);
1251         } else {
1252                 /*
1253                  * The board ID is a string but the firmware byte
1254                  * swaps each 4-byte word before passing it back to
1255                  * us.  Therefore we need to swab it before printing.
1256                  */
1257                 for (i = 0; i < 4; ++i)
1258                         ((u32 *) board_id)[i] =
1259                                 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4));
1260         }
1261 }
1262
1263 int mthca_QUERY_ADAPTER(struct mthca_dev *dev,
1264                         struct mthca_adapter *adapter)
1265 {
1266         struct mthca_mailbox *mailbox;
1267         u32 *outbox;
1268         int err;
1269
1270 #define QUERY_ADAPTER_OUT_SIZE             0x100
1271 #define QUERY_ADAPTER_VENDOR_ID_OFFSET     0x00
1272 #define QUERY_ADAPTER_DEVICE_ID_OFFSET     0x04
1273 #define QUERY_ADAPTER_REVISION_ID_OFFSET   0x08
1274 #define QUERY_ADAPTER_INTA_PIN_OFFSET      0x10
1275 #define QUERY_ADAPTER_VSD_OFFSET           0x20
1276
1277         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1278         if (IS_ERR(mailbox))
1279                 return PTR_ERR(mailbox);
1280         outbox = mailbox->buf;
1281
1282         err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_ADAPTER,
1283                             CMD_TIME_CLASS_A);
1284
1285         if (err)
1286                 goto out;
1287
1288         if (!mthca_is_memfree(dev)) {
1289                 MTHCA_GET(adapter->vendor_id, outbox,
1290                           QUERY_ADAPTER_VENDOR_ID_OFFSET);
1291                 MTHCA_GET(adapter->device_id, outbox,
1292                           QUERY_ADAPTER_DEVICE_ID_OFFSET);
1293                 MTHCA_GET(adapter->revision_id, outbox,
1294                           QUERY_ADAPTER_REVISION_ID_OFFSET);
1295         }
1296         MTHCA_GET(adapter->inta_pin, outbox,    QUERY_ADAPTER_INTA_PIN_OFFSET);
1297
1298         get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
1299                      adapter->board_id);
1300
1301 out:
1302         mthca_free_mailbox(dev, mailbox);
1303         return err;
1304 }
1305
1306 int mthca_INIT_HCA(struct mthca_dev *dev,
1307                    struct mthca_init_hca_param *param)
1308 {
1309         struct mthca_mailbox *mailbox;
1310         __be32 *inbox;
1311         int err;
1312
1313 #define INIT_HCA_IN_SIZE                 0x200
1314 #define INIT_HCA_FLAGS1_OFFSET           0x00c
1315 #define INIT_HCA_FLAGS2_OFFSET           0x014
1316 #define INIT_HCA_QPC_OFFSET              0x020
1317 #define  INIT_HCA_QPC_BASE_OFFSET        (INIT_HCA_QPC_OFFSET + 0x10)
1318 #define  INIT_HCA_LOG_QP_OFFSET          (INIT_HCA_QPC_OFFSET + 0x17)
1319 #define  INIT_HCA_EEC_BASE_OFFSET        (INIT_HCA_QPC_OFFSET + 0x20)
1320 #define  INIT_HCA_LOG_EEC_OFFSET         (INIT_HCA_QPC_OFFSET + 0x27)
1321 #define  INIT_HCA_SRQC_BASE_OFFSET       (INIT_HCA_QPC_OFFSET + 0x28)
1322 #define  INIT_HCA_LOG_SRQ_OFFSET         (INIT_HCA_QPC_OFFSET + 0x2f)
1323 #define  INIT_HCA_CQC_BASE_OFFSET        (INIT_HCA_QPC_OFFSET + 0x30)
1324 #define  INIT_HCA_LOG_CQ_OFFSET          (INIT_HCA_QPC_OFFSET + 0x37)
1325 #define  INIT_HCA_EQPC_BASE_OFFSET       (INIT_HCA_QPC_OFFSET + 0x40)
1326 #define  INIT_HCA_EEEC_BASE_OFFSET       (INIT_HCA_QPC_OFFSET + 0x50)
1327 #define  INIT_HCA_EQC_BASE_OFFSET        (INIT_HCA_QPC_OFFSET + 0x60)
1328 #define  INIT_HCA_LOG_EQ_OFFSET          (INIT_HCA_QPC_OFFSET + 0x67)
1329 #define  INIT_HCA_RDB_BASE_OFFSET        (INIT_HCA_QPC_OFFSET + 0x70)
1330 #define INIT_HCA_UDAV_OFFSET             0x0b0
1331 #define  INIT_HCA_UDAV_LKEY_OFFSET       (INIT_HCA_UDAV_OFFSET + 0x0)
1332 #define  INIT_HCA_UDAV_PD_OFFSET         (INIT_HCA_UDAV_OFFSET + 0x4)
1333 #define INIT_HCA_MCAST_OFFSET            0x0c0
1334 #define  INIT_HCA_MC_BASE_OFFSET         (INIT_HCA_MCAST_OFFSET + 0x00)
1335 #define  INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
1336 #define  INIT_HCA_MC_HASH_SZ_OFFSET      (INIT_HCA_MCAST_OFFSET + 0x16)
1337 #define  INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
1338 #define INIT_HCA_TPT_OFFSET              0x0f0
1339 #define  INIT_HCA_MPT_BASE_OFFSET        (INIT_HCA_TPT_OFFSET + 0x00)
1340 #define  INIT_HCA_MTT_SEG_SZ_OFFSET      (INIT_HCA_TPT_OFFSET + 0x09)
1341 #define  INIT_HCA_LOG_MPT_SZ_OFFSET      (INIT_HCA_TPT_OFFSET + 0x0b)
1342 #define  INIT_HCA_MTT_BASE_OFFSET        (INIT_HCA_TPT_OFFSET + 0x10)
1343 #define INIT_HCA_UAR_OFFSET              0x120
1344 #define  INIT_HCA_UAR_BASE_OFFSET        (INIT_HCA_UAR_OFFSET + 0x00)
1345 #define  INIT_HCA_UARC_SZ_OFFSET         (INIT_HCA_UAR_OFFSET + 0x09)
1346 #define  INIT_HCA_LOG_UAR_SZ_OFFSET      (INIT_HCA_UAR_OFFSET + 0x0a)
1347 #define  INIT_HCA_UAR_PAGE_SZ_OFFSET     (INIT_HCA_UAR_OFFSET + 0x0b)
1348 #define  INIT_HCA_UAR_SCATCH_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x10)
1349 #define  INIT_HCA_UAR_CTX_BASE_OFFSET    (INIT_HCA_UAR_OFFSET + 0x18)
1350
1351         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1352         if (IS_ERR(mailbox))
1353                 return PTR_ERR(mailbox);
1354         inbox = mailbox->buf;
1355
1356         memset(inbox, 0, INIT_HCA_IN_SIZE);
1357
1358         if (dev->mthca_flags & MTHCA_FLAG_SINAI_OPT)
1359                 MTHCA_PUT(inbox, 0x1, INIT_HCA_FLAGS1_OFFSET);
1360
1361 #if defined(__LITTLE_ENDIAN)
1362         *(inbox + INIT_HCA_FLAGS2_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
1363 #elif defined(__BIG_ENDIAN)
1364         *(inbox + INIT_HCA_FLAGS2_OFFSET / 4) |= cpu_to_be32(1 << 1);
1365 #else
1366 #error Host endianness not defined
1367 #endif
1368         /* Check port for UD address vector: */
1369         *(inbox + INIT_HCA_FLAGS2_OFFSET / 4) |= cpu_to_be32(1);
1370
1371         /* Enable IPoIB checksumming if we can: */
1372         if (dev->device_cap_flags & IB_DEVICE_UD_IP_CSUM)
1373                 *(inbox + INIT_HCA_FLAGS2_OFFSET / 4) |= cpu_to_be32(7 << 3);
1374
1375         /* We leave wqe_quota, responder_exu, etc as 0 (default) */
1376
1377         /* QPC/EEC/CQC/EQC/RDB attributes */
1378
1379         MTHCA_PUT(inbox, param->qpc_base,     INIT_HCA_QPC_BASE_OFFSET);
1380         MTHCA_PUT(inbox, param->log_num_qps,  INIT_HCA_LOG_QP_OFFSET);
1381         MTHCA_PUT(inbox, param->eec_base,     INIT_HCA_EEC_BASE_OFFSET);
1382         MTHCA_PUT(inbox, param->log_num_eecs, INIT_HCA_LOG_EEC_OFFSET);
1383         MTHCA_PUT(inbox, param->srqc_base,    INIT_HCA_SRQC_BASE_OFFSET);
1384         MTHCA_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
1385         MTHCA_PUT(inbox, param->cqc_base,     INIT_HCA_CQC_BASE_OFFSET);
1386         MTHCA_PUT(inbox, param->log_num_cqs,  INIT_HCA_LOG_CQ_OFFSET);
1387         MTHCA_PUT(inbox, param->eqpc_base,    INIT_HCA_EQPC_BASE_OFFSET);
1388         MTHCA_PUT(inbox, param->eeec_base,    INIT_HCA_EEEC_BASE_OFFSET);
1389         MTHCA_PUT(inbox, param->eqc_base,     INIT_HCA_EQC_BASE_OFFSET);
1390         MTHCA_PUT(inbox, param->log_num_eqs,  INIT_HCA_LOG_EQ_OFFSET);
1391         MTHCA_PUT(inbox, param->rdb_base,     INIT_HCA_RDB_BASE_OFFSET);
1392
1393         /* UD AV attributes */
1394
1395         /* multicast attributes */
1396
1397         MTHCA_PUT(inbox, param->mc_base,         INIT_HCA_MC_BASE_OFFSET);
1398         MTHCA_PUT(inbox, param->log_mc_entry_sz, INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1399         MTHCA_PUT(inbox, param->mc_hash_sz,      INIT_HCA_MC_HASH_SZ_OFFSET);
1400         MTHCA_PUT(inbox, param->log_mc_table_sz, INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1401
1402         /* TPT attributes */
1403
1404         MTHCA_PUT(inbox, param->mpt_base,   INIT_HCA_MPT_BASE_OFFSET);
1405         if (!mthca_is_memfree(dev))
1406                 MTHCA_PUT(inbox, param->mtt_seg_sz, INIT_HCA_MTT_SEG_SZ_OFFSET);
1407         MTHCA_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
1408         MTHCA_PUT(inbox, param->mtt_base,   INIT_HCA_MTT_BASE_OFFSET);
1409
1410         /* UAR attributes */
1411         {
1412                 u8 uar_page_sz = PAGE_SHIFT - 12;
1413                 MTHCA_PUT(inbox, uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET);
1414         }
1415
1416         MTHCA_PUT(inbox, param->uar_scratch_base, INIT_HCA_UAR_SCATCH_BASE_OFFSET);
1417
1418         if (mthca_is_memfree(dev)) {
1419                 MTHCA_PUT(inbox, param->log_uarc_sz, INIT_HCA_UARC_SZ_OFFSET);
1420                 MTHCA_PUT(inbox, param->log_uar_sz,  INIT_HCA_LOG_UAR_SZ_OFFSET);
1421                 MTHCA_PUT(inbox, param->uarc_base,   INIT_HCA_UAR_CTX_BASE_OFFSET);
1422         }
1423
1424         err = mthca_cmd(dev, mailbox->dma, 0, 0,
1425                         CMD_INIT_HCA, CMD_TIME_CLASS_D);
1426
1427         mthca_free_mailbox(dev, mailbox);
1428         return err;
1429 }
1430
1431 int mthca_INIT_IB(struct mthca_dev *dev,
1432                   struct mthca_init_ib_param *param,
1433                   int port)
1434 {
1435         struct mthca_mailbox *mailbox;
1436         u32 *inbox;
1437         int err;
1438         u32 flags;
1439
1440 #define INIT_IB_IN_SIZE          56
1441 #define INIT_IB_FLAGS_OFFSET     0x00
1442 #define INIT_IB_FLAG_SIG         (1 << 18)
1443 #define INIT_IB_FLAG_NG          (1 << 17)
1444 #define INIT_IB_FLAG_G0          (1 << 16)
1445 #define INIT_IB_VL_SHIFT         4
1446 #define INIT_IB_PORT_WIDTH_SHIFT 8
1447 #define INIT_IB_MTU_SHIFT        12
1448 #define INIT_IB_MAX_GID_OFFSET   0x06
1449 #define INIT_IB_MAX_PKEY_OFFSET  0x0a
1450 #define INIT_IB_GUID0_OFFSET     0x10
1451 #define INIT_IB_NODE_GUID_OFFSET 0x18
1452 #define INIT_IB_SI_GUID_OFFSET   0x20
1453
1454         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1455         if (IS_ERR(mailbox))
1456                 return PTR_ERR(mailbox);
1457         inbox = mailbox->buf;
1458
1459         memset(inbox, 0, INIT_IB_IN_SIZE);
1460
1461         flags = 0;
1462         flags |= param->set_guid0     ? INIT_IB_FLAG_G0  : 0;
1463         flags |= param->set_node_guid ? INIT_IB_FLAG_NG  : 0;
1464         flags |= param->set_si_guid   ? INIT_IB_FLAG_SIG : 0;
1465         flags |= param->vl_cap << INIT_IB_VL_SHIFT;
1466         flags |= param->port_width << INIT_IB_PORT_WIDTH_SHIFT;
1467         flags |= param->mtu_cap << INIT_IB_MTU_SHIFT;
1468         MTHCA_PUT(inbox, flags, INIT_IB_FLAGS_OFFSET);
1469
1470         MTHCA_PUT(inbox, param->gid_cap,   INIT_IB_MAX_GID_OFFSET);
1471         MTHCA_PUT(inbox, param->pkey_cap,  INIT_IB_MAX_PKEY_OFFSET);
1472         MTHCA_PUT(inbox, param->guid0,     INIT_IB_GUID0_OFFSET);
1473         MTHCA_PUT(inbox, param->node_guid, INIT_IB_NODE_GUID_OFFSET);
1474         MTHCA_PUT(inbox, param->si_guid,   INIT_IB_SI_GUID_OFFSET);
1475
1476         err = mthca_cmd(dev, mailbox->dma, port, 0, CMD_INIT_IB,
1477                         CMD_TIME_CLASS_A);
1478
1479         mthca_free_mailbox(dev, mailbox);
1480         return err;
1481 }
1482
1483 int mthca_CLOSE_IB(struct mthca_dev *dev, int port)
1484 {
1485         return mthca_cmd(dev, 0, port, 0, CMD_CLOSE_IB, CMD_TIME_CLASS_A);
1486 }
1487
1488 int mthca_CLOSE_HCA(struct mthca_dev *dev, int panic)
1489 {
1490         return mthca_cmd(dev, 0, 0, panic, CMD_CLOSE_HCA, CMD_TIME_CLASS_C);
1491 }
1492
1493 int mthca_SET_IB(struct mthca_dev *dev, struct mthca_set_ib_param *param,
1494                  int port)
1495 {
1496         struct mthca_mailbox *mailbox;
1497         u32 *inbox;
1498         int err;
1499         u32 flags = 0;
1500
1501 #define SET_IB_IN_SIZE         0x40
1502 #define SET_IB_FLAGS_OFFSET    0x00
1503 #define SET_IB_FLAG_SIG        (1 << 18)
1504 #define SET_IB_FLAG_RQK        (1 <<  0)
1505 #define SET_IB_CAP_MASK_OFFSET 0x04
1506 #define SET_IB_SI_GUID_OFFSET  0x08
1507
1508         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1509         if (IS_ERR(mailbox))
1510                 return PTR_ERR(mailbox);
1511         inbox = mailbox->buf;
1512
1513         memset(inbox, 0, SET_IB_IN_SIZE);
1514
1515         flags |= param->set_si_guid     ? SET_IB_FLAG_SIG : 0;
1516         flags |= param->reset_qkey_viol ? SET_IB_FLAG_RQK : 0;
1517         MTHCA_PUT(inbox, flags, SET_IB_FLAGS_OFFSET);
1518
1519         MTHCA_PUT(inbox, param->cap_mask, SET_IB_CAP_MASK_OFFSET);
1520         MTHCA_PUT(inbox, param->si_guid,  SET_IB_SI_GUID_OFFSET);
1521
1522         err = mthca_cmd(dev, mailbox->dma, port, 0, CMD_SET_IB,
1523                         CMD_TIME_CLASS_B);
1524
1525         mthca_free_mailbox(dev, mailbox);
1526         return err;
1527 }
1528
1529 int mthca_MAP_ICM(struct mthca_dev *dev, struct mthca_icm *icm, u64 virt)
1530 {
1531         return mthca_map_cmd(dev, CMD_MAP_ICM, icm, virt);
1532 }
1533
1534 int mthca_MAP_ICM_page(struct mthca_dev *dev, u64 dma_addr, u64 virt)
1535 {
1536         struct mthca_mailbox *mailbox;
1537         __be64 *inbox;
1538         int err;
1539
1540         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1541         if (IS_ERR(mailbox))
1542                 return PTR_ERR(mailbox);
1543         inbox = mailbox->buf;
1544
1545         inbox[0] = cpu_to_be64(virt);
1546         inbox[1] = cpu_to_be64(dma_addr);
1547
1548         err = mthca_cmd(dev, mailbox->dma, 1, 0, CMD_MAP_ICM,
1549                         CMD_TIME_CLASS_B);
1550
1551         mthca_free_mailbox(dev, mailbox);
1552
1553         if (!err)
1554                 mthca_dbg(dev, "Mapped page at %llx to %llx for ICM.\n",
1555                           (unsigned long long) dma_addr, (unsigned long long) virt);
1556
1557         return err;
1558 }
1559
1560 int mthca_UNMAP_ICM(struct mthca_dev *dev, u64 virt, u32 page_count)
1561 {
1562         mthca_dbg(dev, "Unmapping %d pages at %llx from ICM.\n",
1563                   page_count, (unsigned long long) virt);
1564
1565         return mthca_cmd(dev, virt, page_count, 0,
1566                         CMD_UNMAP_ICM, CMD_TIME_CLASS_B);
1567 }
1568
1569 int mthca_MAP_ICM_AUX(struct mthca_dev *dev, struct mthca_icm *icm)
1570 {
1571         return mthca_map_cmd(dev, CMD_MAP_ICM_AUX, icm, -1);
1572 }
1573
1574 int mthca_UNMAP_ICM_AUX(struct mthca_dev *dev)
1575 {
1576         return mthca_cmd(dev, 0, 0, 0, CMD_UNMAP_ICM_AUX, CMD_TIME_CLASS_B);
1577 }
1578
1579 int mthca_SET_ICM_SIZE(struct mthca_dev *dev, u64 icm_size, u64 *aux_pages)
1580 {
1581         int ret = mthca_cmd_imm(dev, icm_size, aux_pages, 0,
1582                         0, CMD_SET_ICM_SIZE, CMD_TIME_CLASS_A);
1583
1584         if (ret)
1585                 return ret;
1586
1587         /*
1588          * Round up number of system pages needed in case
1589          * MTHCA_ICM_PAGE_SIZE < PAGE_SIZE.
1590          */
1591         *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MTHCA_ICM_PAGE_SIZE) >>
1592                 (PAGE_SHIFT - MTHCA_ICM_PAGE_SHIFT);
1593
1594         return 0;
1595 }
1596
1597 int mthca_SW2HW_MPT(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1598                     int mpt_index)
1599 {
1600         return mthca_cmd(dev, mailbox->dma, mpt_index, 0, CMD_SW2HW_MPT,
1601                          CMD_TIME_CLASS_B);
1602 }
1603
1604 int mthca_HW2SW_MPT(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1605                     int mpt_index)
1606 {
1607         return mthca_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, mpt_index,
1608                              !mailbox, CMD_HW2SW_MPT,
1609                              CMD_TIME_CLASS_B);
1610 }
1611
1612 int mthca_WRITE_MTT(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1613                     int num_mtt)
1614 {
1615         return mthca_cmd(dev, mailbox->dma, num_mtt, 0, CMD_WRITE_MTT,
1616                          CMD_TIME_CLASS_B);
1617 }
1618
1619 int mthca_SYNC_TPT(struct mthca_dev *dev)
1620 {
1621         return mthca_cmd(dev, 0, 0, 0, CMD_SYNC_TPT, CMD_TIME_CLASS_B);
1622 }
1623
1624 int mthca_MAP_EQ(struct mthca_dev *dev, u64 event_mask, int unmap,
1625                  int eq_num)
1626 {
1627         mthca_dbg(dev, "%s mask %016llx for eqn %d\n",
1628                   unmap ? "Clearing" : "Setting",
1629                   (unsigned long long) event_mask, eq_num);
1630         return mthca_cmd(dev, event_mask, (unmap << 31) | eq_num,
1631                          0, CMD_MAP_EQ, CMD_TIME_CLASS_B);
1632 }
1633
1634 int mthca_SW2HW_EQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1635                    int eq_num)
1636 {
1637         return mthca_cmd(dev, mailbox->dma, eq_num, 0, CMD_SW2HW_EQ,
1638                          CMD_TIME_CLASS_A);
1639 }
1640
1641 int mthca_HW2SW_EQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1642                    int eq_num)
1643 {
1644         return mthca_cmd_box(dev, 0, mailbox->dma, eq_num, 0,
1645                              CMD_HW2SW_EQ,
1646                              CMD_TIME_CLASS_A);
1647 }
1648
1649 int mthca_SW2HW_CQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1650                    int cq_num)
1651 {
1652         return mthca_cmd(dev, mailbox->dma, cq_num, 0, CMD_SW2HW_CQ,
1653                         CMD_TIME_CLASS_A);
1654 }
1655
1656 int mthca_HW2SW_CQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1657                    int cq_num)
1658 {
1659         return mthca_cmd_box(dev, 0, mailbox->dma, cq_num, 0,
1660                              CMD_HW2SW_CQ,
1661                              CMD_TIME_CLASS_A);
1662 }
1663
1664 int mthca_RESIZE_CQ(struct mthca_dev *dev, int cq_num, u32 lkey, u8 log_size)
1665 {
1666         struct mthca_mailbox *mailbox;
1667         __be32 *inbox;
1668         int err;
1669
1670 #define RESIZE_CQ_IN_SIZE               0x40
1671 #define RESIZE_CQ_LOG_SIZE_OFFSET       0x0c
1672 #define RESIZE_CQ_LKEY_OFFSET           0x1c
1673
1674         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1675         if (IS_ERR(mailbox))
1676                 return PTR_ERR(mailbox);
1677         inbox = mailbox->buf;
1678
1679         memset(inbox, 0, RESIZE_CQ_IN_SIZE);
1680         /*
1681          * Leave start address fields zeroed out -- mthca assumes that
1682          * MRs for CQs always start at virtual address 0.
1683          */
1684         MTHCA_PUT(inbox, log_size, RESIZE_CQ_LOG_SIZE_OFFSET);
1685         MTHCA_PUT(inbox, lkey,     RESIZE_CQ_LKEY_OFFSET);
1686
1687         err = mthca_cmd(dev, mailbox->dma, cq_num, 1, CMD_RESIZE_CQ,
1688                         CMD_TIME_CLASS_B);
1689
1690         mthca_free_mailbox(dev, mailbox);
1691         return err;
1692 }
1693
1694 int mthca_SW2HW_SRQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1695                     int srq_num)
1696 {
1697         return mthca_cmd(dev, mailbox->dma, srq_num, 0, CMD_SW2HW_SRQ,
1698                         CMD_TIME_CLASS_A);
1699 }
1700
1701 int mthca_HW2SW_SRQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1702                     int srq_num)
1703 {
1704         return mthca_cmd_box(dev, 0, mailbox->dma, srq_num, 0,
1705                              CMD_HW2SW_SRQ,
1706                              CMD_TIME_CLASS_A);
1707 }
1708
1709 int mthca_QUERY_SRQ(struct mthca_dev *dev, u32 num,
1710                     struct mthca_mailbox *mailbox)
1711 {
1712         return mthca_cmd_box(dev, 0, mailbox->dma, num, 0,
1713                              CMD_QUERY_SRQ, CMD_TIME_CLASS_A);
1714 }
1715
1716 int mthca_ARM_SRQ(struct mthca_dev *dev, int srq_num, int limit)
1717 {
1718         return mthca_cmd(dev, limit, srq_num, 0, CMD_ARM_SRQ,
1719                          CMD_TIME_CLASS_B);
1720 }
1721
1722 int mthca_MODIFY_QP(struct mthca_dev *dev, enum ib_qp_state cur,
1723                     enum ib_qp_state next, u32 num, int is_ee,
1724                     struct mthca_mailbox *mailbox, u32 optmask)
1725 {
1726         static const u16 op[IB_QPS_ERR + 1][IB_QPS_ERR + 1] = {
1727                 [IB_QPS_RESET] = {
1728                         [IB_QPS_RESET]  = CMD_ERR2RST_QPEE,
1729                         [IB_QPS_ERR]    = CMD_2ERR_QPEE,
1730                         [IB_QPS_INIT]   = CMD_RST2INIT_QPEE,
1731                 },
1732                 [IB_QPS_INIT]  = {
1733                         [IB_QPS_RESET]  = CMD_ERR2RST_QPEE,
1734                         [IB_QPS_ERR]    = CMD_2ERR_QPEE,
1735                         [IB_QPS_INIT]   = CMD_INIT2INIT_QPEE,
1736                         [IB_QPS_RTR]    = CMD_INIT2RTR_QPEE,
1737                 },
1738                 [IB_QPS_RTR]   = {
1739                         [IB_QPS_RESET]  = CMD_ERR2RST_QPEE,
1740                         [IB_QPS_ERR]    = CMD_2ERR_QPEE,
1741                         [IB_QPS_RTS]    = CMD_RTR2RTS_QPEE,
1742                 },
1743                 [IB_QPS_RTS]   = {
1744                         [IB_QPS_RESET]  = CMD_ERR2RST_QPEE,
1745                         [IB_QPS_ERR]    = CMD_2ERR_QPEE,
1746                         [IB_QPS_RTS]    = CMD_RTS2RTS_QPEE,
1747                         [IB_QPS_SQD]    = CMD_RTS2SQD_QPEE,
1748                 },
1749                 [IB_QPS_SQD] = {
1750                         [IB_QPS_RESET]  = CMD_ERR2RST_QPEE,
1751                         [IB_QPS_ERR]    = CMD_2ERR_QPEE,
1752                         [IB_QPS_RTS]    = CMD_SQD2RTS_QPEE,
1753                         [IB_QPS_SQD]    = CMD_SQD2SQD_QPEE,
1754                 },
1755                 [IB_QPS_SQE] = {
1756                         [IB_QPS_RESET]  = CMD_ERR2RST_QPEE,
1757                         [IB_QPS_ERR]    = CMD_2ERR_QPEE,
1758                         [IB_QPS_RTS]    = CMD_SQERR2RTS_QPEE,
1759                 },
1760                 [IB_QPS_ERR] = {
1761                         [IB_QPS_RESET]  = CMD_ERR2RST_QPEE,
1762                         [IB_QPS_ERR]    = CMD_2ERR_QPEE,
1763                 }
1764         };
1765
1766         u8 op_mod = 0;
1767         int my_mailbox = 0;
1768         int err;
1769
1770         if (op[cur][next] == CMD_ERR2RST_QPEE) {
1771                 op_mod = 3;     /* don't write outbox, any->reset */
1772
1773                 /* For debugging */
1774                 if (!mailbox) {
1775                         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1776                         if (!IS_ERR(mailbox)) {
1777                                 my_mailbox = 1;
1778                                 op_mod     = 2; /* write outbox, any->reset */
1779                         } else
1780                                 mailbox = NULL;
1781                 }
1782
1783                 err = mthca_cmd_box(dev, 0, mailbox ? mailbox->dma : 0,
1784                                     (!!is_ee << 24) | num, op_mod,
1785                                     op[cur][next], CMD_TIME_CLASS_C);
1786
1787                 if (0 && mailbox) {
1788                         int i;
1789                         mthca_dbg(dev, "Dumping QP context:\n");
1790                         printk(" %08x\n", be32_to_cpup(mailbox->buf));
1791                         for (i = 0; i < 0x100 / 4; ++i) {
1792                                 if (i % 8 == 0)
1793                                         printk("[%02x] ", i * 4);
1794                                 printk(" %08x",
1795                                        be32_to_cpu(((__be32 *) mailbox->buf)[i + 2]));
1796                                 if ((i + 1) % 8 == 0)
1797                                         printk("\n");
1798                         }
1799                 }
1800
1801                 if (my_mailbox)
1802                         mthca_free_mailbox(dev, mailbox);
1803         } else {
1804                 if (0) {
1805                         int i;
1806                         mthca_dbg(dev, "Dumping QP context:\n");
1807                         printk("  opt param mask: %08x\n", be32_to_cpup(mailbox->buf));
1808                         for (i = 0; i < 0x100 / 4; ++i) {
1809                                 if (i % 8 == 0)
1810                                         printk("  [%02x] ", i * 4);
1811                                 printk(" %08x",
1812                                        be32_to_cpu(((__be32 *) mailbox->buf)[i + 2]));
1813                                 if ((i + 1) % 8 == 0)
1814                                         printk("\n");
1815                         }
1816                 }
1817
1818                 err = mthca_cmd(dev, mailbox->dma, optmask | (!!is_ee << 24) | num,
1819                                 op_mod, op[cur][next], CMD_TIME_CLASS_C);
1820         }
1821
1822         return err;
1823 }
1824
1825 int mthca_QUERY_QP(struct mthca_dev *dev, u32 num, int is_ee,
1826                    struct mthca_mailbox *mailbox)
1827 {
1828         return mthca_cmd_box(dev, 0, mailbox->dma, (!!is_ee << 24) | num, 0,
1829                              CMD_QUERY_QPEE, CMD_TIME_CLASS_A);
1830 }
1831
1832 int mthca_CONF_SPECIAL_QP(struct mthca_dev *dev, int type, u32 qpn)
1833 {
1834         u8 op_mod;
1835
1836         switch (type) {
1837         case IB_QPT_SMI:
1838                 op_mod = 0;
1839                 break;
1840         case IB_QPT_GSI:
1841                 op_mod = 1;
1842                 break;
1843         case IB_QPT_RAW_IPV6:
1844                 op_mod = 2;
1845                 break;
1846         case IB_QPT_RAW_ETHERTYPE:
1847                 op_mod = 3;
1848                 break;
1849         default:
1850                 return -EINVAL;
1851         }
1852
1853         return mthca_cmd(dev, 0, qpn, op_mod, CMD_CONF_SPECIAL_QP,
1854                          CMD_TIME_CLASS_B);
1855 }
1856
1857 int mthca_MAD_IFC(struct mthca_dev *dev, int ignore_mkey, int ignore_bkey,
1858                   int port, const struct ib_wc *in_wc, const struct ib_grh *in_grh,
1859                   const void *in_mad, void *response_mad)
1860 {
1861         struct mthca_mailbox *inmailbox, *outmailbox;
1862         void *inbox;
1863         int err;
1864         u32 in_modifier = port;
1865         u8 op_modifier = 0;
1866
1867 #define MAD_IFC_BOX_SIZE      0x400
1868 #define MAD_IFC_MY_QPN_OFFSET 0x100
1869 #define MAD_IFC_RQPN_OFFSET   0x108
1870 #define MAD_IFC_SL_OFFSET     0x10c
1871 #define MAD_IFC_G_PATH_OFFSET 0x10d
1872 #define MAD_IFC_RLID_OFFSET   0x10e
1873 #define MAD_IFC_PKEY_OFFSET   0x112
1874 #define MAD_IFC_GRH_OFFSET    0x140
1875
1876         inmailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1877         if (IS_ERR(inmailbox))
1878                 return PTR_ERR(inmailbox);
1879         inbox = inmailbox->buf;
1880
1881         outmailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1882         if (IS_ERR(outmailbox)) {
1883                 mthca_free_mailbox(dev, inmailbox);
1884                 return PTR_ERR(outmailbox);
1885         }
1886
1887         memcpy(inbox, in_mad, 256);
1888
1889         /*
1890          * Key check traps can't be generated unless we have in_wc to
1891          * tell us where to send the trap.
1892          */
1893         if (ignore_mkey || !in_wc)
1894                 op_modifier |= 0x1;
1895         if (ignore_bkey || !in_wc)
1896                 op_modifier |= 0x2;
1897
1898         if (in_wc) {
1899                 u8 val;
1900
1901                 memset(inbox + 256, 0, 256);
1902
1903                 MTHCA_PUT(inbox, in_wc->qp->qp_num, MAD_IFC_MY_QPN_OFFSET);
1904                 MTHCA_PUT(inbox, in_wc->src_qp,     MAD_IFC_RQPN_OFFSET);
1905
1906                 val = in_wc->sl << 4;
1907                 MTHCA_PUT(inbox, val,               MAD_IFC_SL_OFFSET);
1908
1909                 val = in_wc->dlid_path_bits |
1910                         (in_wc->wc_flags & IB_WC_GRH ? 0x80 : 0);
1911                 MTHCA_PUT(inbox, val,               MAD_IFC_G_PATH_OFFSET);
1912
1913                 MTHCA_PUT(inbox, in_wc->slid,       MAD_IFC_RLID_OFFSET);
1914                 MTHCA_PUT(inbox, in_wc->pkey_index, MAD_IFC_PKEY_OFFSET);
1915
1916                 if (in_grh)
1917                         memcpy(inbox + MAD_IFC_GRH_OFFSET, in_grh, 40);
1918
1919                 op_modifier |= 0x4;
1920
1921                 in_modifier |= in_wc->slid << 16;
1922         }
1923
1924         err = mthca_cmd_box(dev, inmailbox->dma, outmailbox->dma,
1925                             in_modifier, op_modifier,
1926                             CMD_MAD_IFC, CMD_TIME_CLASS_C);
1927
1928         if (!err)
1929                 memcpy(response_mad, outmailbox->buf, 256);
1930
1931         mthca_free_mailbox(dev, inmailbox);
1932         mthca_free_mailbox(dev, outmailbox);
1933         return err;
1934 }
1935
1936 int mthca_READ_MGM(struct mthca_dev *dev, int index,
1937                    struct mthca_mailbox *mailbox)
1938 {
1939         return mthca_cmd_box(dev, 0, mailbox->dma, index, 0,
1940                              CMD_READ_MGM, CMD_TIME_CLASS_A);
1941 }
1942
1943 int mthca_WRITE_MGM(struct mthca_dev *dev, int index,
1944                     struct mthca_mailbox *mailbox)
1945 {
1946         return mthca_cmd(dev, mailbox->dma, index, 0, CMD_WRITE_MGM,
1947                          CMD_TIME_CLASS_A);
1948 }
1949
1950 int mthca_MGID_HASH(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1951                     u16 *hash)
1952 {
1953         u64 imm;
1954         int err;
1955
1956         err = mthca_cmd_imm(dev, mailbox->dma, &imm, 0, 0, CMD_MGID_HASH,
1957                             CMD_TIME_CLASS_A);
1958
1959         *hash = imm;
1960         return err;
1961 }
1962
1963 int mthca_NOP(struct mthca_dev *dev)
1964 {
1965         return mthca_cmd(dev, 0, 0x1f, 0, CMD_NOP, msecs_to_jiffies(100));
1966 }