sys/dev/mthca/mthca_qp.c

   1 /*
   2  * Copyright (c) 2004 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005 Cisco Systems. All rights reserved.
   4  * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
   5  * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
   6  *
   7  * This software is available to you under a choice of one of two
   8  * licenses.  You may choose to be licensed under the terms of the GNU
   9  * General Public License (GPL) Version 2, available from the file
  10  * COPYING in the main directory of this source tree, or the
  11  * OpenIB.org BSD license below:
  12  *
  13  *     Redistribution and use in source and binary forms, with or
  14  *     without modification, are permitted provided that the following
  15  *     conditions are met:
  16  *
  17  *      - Redistributions of source code must retain the above
  18  *        copyright notice, this list of conditions and the following
  19  *        disclaimer.
  20  *
  21  *      - Redistributions in binary form must reproduce the above
  22  *        copyright notice, this list of conditions and the following
  23  *        disclaimer in the documentation and/or other materials
  24  *        provided with the distribution.
  25  *
  26  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  27  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  28  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  29  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  30  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  31  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  32  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  33  * SOFTWARE.
  34  */
  35
  36 #include <linux/string.h>
  37 #include <linux/slab.h>
  38 #include <linux/sched.h>
  39
  40 #include <asm/io.h>
  41
  42 #include <rdma/ib_verbs.h>
  43 #include <rdma/ib_cache.h>
  44 #include <rdma/ib_pack.h>
  45 #include <rdma/uverbs_ioctl.h>
  46
  47 #include "mthca_dev.h"
  48 #include "mthca_cmd.h"
  49 #include "mthca_memfree.h"
  50 #include "mthca_wqe.h"
  51
  52 enum {
  53         MTHCA_MAX_DIRECT_QP_SIZE = 4 * PAGE_SIZE,
  54         MTHCA_ACK_REQ_FREQ       = 10,
  55         MTHCA_FLIGHT_LIMIT       = 9,
  56         MTHCA_UD_HEADER_SIZE     = 72, /* largest UD header possible */
  57         MTHCA_INLINE_HEADER_SIZE = 4,  /* data segment overhead for inline */
  58         MTHCA_INLINE_CHUNK_SIZE  = 16  /* inline data segment chunk */
  59 };
  60
  61 enum {
  62         MTHCA_QP_STATE_RST  = 0,
  63         MTHCA_QP_STATE_INIT = 1,
  64         MTHCA_QP_STATE_RTR  = 2,
  65         MTHCA_QP_STATE_RTS  = 3,
  66         MTHCA_QP_STATE_SQE  = 4,
  67         MTHCA_QP_STATE_SQD  = 5,
  68         MTHCA_QP_STATE_ERR  = 6,
  69         MTHCA_QP_STATE_DRAINING = 7
  70 };
  71
  72 enum {
  73         MTHCA_QP_ST_RC  = 0x0,
  74         MTHCA_QP_ST_UC  = 0x1,
  75         MTHCA_QP_ST_RD  = 0x2,
  76         MTHCA_QP_ST_UD  = 0x3,
  77         MTHCA_QP_ST_MLX = 0x7
  78 };
  79
  80 enum {
  81         MTHCA_QP_PM_MIGRATED = 0x3,
  82         MTHCA_QP_PM_ARMED    = 0x0,
  83         MTHCA_QP_PM_REARM    = 0x1
  84 };
  85
  86 enum {
  87         /* qp_context flags */
  88         MTHCA_QP_BIT_DE  = 1 <<  8,
  89         /* params1 */
  90         MTHCA_QP_BIT_SRE = 1 << 15,
  91         MTHCA_QP_BIT_SWE = 1 << 14,
  92         MTHCA_QP_BIT_SAE = 1 << 13,
  93         MTHCA_QP_BIT_SIC = 1 <<  4,
  94         MTHCA_QP_BIT_SSC = 1 <<  3,
  95         /* params2 */
  96         MTHCA_QP_BIT_RRE = 1 << 15,
  97         MTHCA_QP_BIT_RWE = 1 << 14,
  98         MTHCA_QP_BIT_RAE = 1 << 13,
  99         MTHCA_QP_BIT_RIC = 1 <<  4,
 100         MTHCA_QP_BIT_RSC = 1 <<  3
 101 };
 102
 103 enum {
 104         MTHCA_SEND_DOORBELL_FENCE = 1 << 5
 105 };
 106
 107 struct mthca_qp_path {
 108         __be32 port_pkey;
 109         u8     rnr_retry;
 110         u8     g_mylmc;
 111         __be16 rlid;
 112         u8     ackto;
 113         u8     mgid_index;
 114         u8     static_rate;
 115         u8     hop_limit;
 116         __be32 sl_tclass_flowlabel;
 117         u8     rgid[16];
 118 } __attribute__((packed));
 119
 120 struct mthca_qp_context {
 121         __be32 flags;
 122         __be32 tavor_sched_queue; /* Reserved on Arbel */
 123         u8     mtu_msgmax;
 124         u8     rq_size_stride;  /* Reserved on Tavor */
 125         u8     sq_size_stride;  /* Reserved on Tavor */
 126         u8     rlkey_arbel_sched_queue; /* Reserved on Tavor */
 127         __be32 usr_page;
 128         __be32 local_qpn;
 129         __be32 remote_qpn;
 130         u32    reserved1[2];
 131         struct mthca_qp_path pri_path;
 132         struct mthca_qp_path alt_path;
 133         __be32 rdd;
 134         __be32 pd;
 135         __be32 wqe_base;
 136         __be32 wqe_lkey;
 137         __be32 params1;
 138         __be32 reserved2;
 139         __be32 next_send_psn;
 140         __be32 cqn_snd;
 141         __be32 snd_wqe_base_l;  /* Next send WQE on Tavor */
 142         __be32 snd_db_index;    /* (debugging only entries) */
 143         __be32 last_acked_psn;
 144         __be32 ssn;
 145         __be32 params2;
 146         __be32 rnr_nextrecvpsn;
 147         __be32 ra_buff_indx;
 148         __be32 cqn_rcv;
 149         __be32 rcv_wqe_base_l;  /* Next recv WQE on Tavor */
 150         __be32 rcv_db_index;    /* (debugging only entries) */
 151         __be32 qkey;
 152         __be32 srqn;
 153         __be32 rmsn;
 154         __be16 rq_wqe_counter;  /* reserved on Tavor */
 155         __be16 sq_wqe_counter;  /* reserved on Tavor */
 156         u32    reserved3[18];
 157 } __attribute__((packed));
 158
 159 struct mthca_qp_param {
 160         __be32 opt_param_mask;
 161         u32    reserved1;
 162         struct mthca_qp_context context;
 163         u32    reserved2[62];
 164 } __attribute__((packed));
 165
 166 enum {
 167         MTHCA_QP_OPTPAR_ALT_ADDR_PATH     = 1 << 0,
 168         MTHCA_QP_OPTPAR_RRE               = 1 << 1,
 169         MTHCA_QP_OPTPAR_RAE               = 1 << 2,
 170         MTHCA_QP_OPTPAR_RWE               = 1 << 3,
 171         MTHCA_QP_OPTPAR_PKEY_INDEX        = 1 << 4,
 172         MTHCA_QP_OPTPAR_Q_KEY             = 1 << 5,
 173         MTHCA_QP_OPTPAR_RNR_TIMEOUT       = 1 << 6,
 174         MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
 175         MTHCA_QP_OPTPAR_SRA_MAX           = 1 << 8,
 176         MTHCA_QP_OPTPAR_RRA_MAX           = 1 << 9,
 177         MTHCA_QP_OPTPAR_PM_STATE          = 1 << 10,
 178         MTHCA_QP_OPTPAR_PORT_NUM          = 1 << 11,
 179         MTHCA_QP_OPTPAR_RETRY_COUNT       = 1 << 12,
 180         MTHCA_QP_OPTPAR_ALT_RNR_RETRY     = 1 << 13,
 181         MTHCA_QP_OPTPAR_ACK_TIMEOUT       = 1 << 14,
 182         MTHCA_QP_OPTPAR_RNR_RETRY         = 1 << 15,
 183         MTHCA_QP_OPTPAR_SCHED_QUEUE       = 1 << 16
 184 };
 185
 186 static const u8 mthca_opcode[] = {
 187         [IB_WR_SEND]                 = MTHCA_OPCODE_SEND,
 188         [IB_WR_SEND_WITH_IMM]        = MTHCA_OPCODE_SEND_IMM,
 189         [IB_WR_RDMA_WRITE]           = MTHCA_OPCODE_RDMA_WRITE,
 190         [IB_WR_RDMA_WRITE_WITH_IMM]  = MTHCA_OPCODE_RDMA_WRITE_IMM,
 191         [IB_WR_RDMA_READ]            = MTHCA_OPCODE_RDMA_READ,
 192         [IB_WR_ATOMIC_CMP_AND_SWP]   = MTHCA_OPCODE_ATOMIC_CS,
 193         [IB_WR_ATOMIC_FETCH_AND_ADD] = MTHCA_OPCODE_ATOMIC_FA,
 194 };
 195
 196 static int is_sqp(struct mthca_dev *dev, struct mthca_qp *qp)
 197 {
 198         return qp->qpn >= dev->qp_table.sqp_start &&
 199                 qp->qpn <= dev->qp_table.sqp_start + 3;
 200 }
 201
 202 static int is_qp0(struct mthca_dev *dev, struct mthca_qp *qp)
 203 {
 204         return qp->qpn >= dev->qp_table.sqp_start &&
 205                 qp->qpn <= dev->qp_table.sqp_start + 1;
 206 }
 207
 208 static void *get_recv_wqe(struct mthca_qp *qp, int n)
 209 {
 210         if (qp->is_direct)
 211                 return qp->queue.direct.buf + (n << qp->rq.wqe_shift);
 212         else
 213                 return qp->queue.page_list[(n << qp->rq.wqe_shift) >> PAGE_SHIFT].buf +
 214                         ((n << qp->rq.wqe_shift) & (PAGE_SIZE - 1));
 215 }
 216
 217 static void *get_send_wqe(struct mthca_qp *qp, int n)
 218 {
 219         if (qp->is_direct)
 220                 return qp->queue.direct.buf + qp->send_wqe_offset +
 221                         (n << qp->sq.wqe_shift);
 222         else
 223                 return qp->queue.page_list[(qp->send_wqe_offset +
 224                                             (n << qp->sq.wqe_shift)) >>
 225                                            PAGE_SHIFT].buf +
 226                         ((qp->send_wqe_offset + (n << qp->sq.wqe_shift)) &
 227                          (PAGE_SIZE - 1));
 228 }
 229
 230 static void mthca_wq_reset(struct mthca_wq *wq)
 231 {
 232         wq->next_ind  = 0;
 233         wq->last_comp = wq->max - 1;
 234         wq->head      = 0;
 235         wq->tail      = 0;
 236 }
 237
 238 void mthca_qp_event(struct mthca_dev *dev, u32 qpn,
 239                     enum ib_event_type event_type)
 240 {
 241         struct mthca_qp *qp;
 242         struct ib_event event;
 243
 244         spin_lock(&dev->qp_table.lock);
 245         qp = mthca_array_get(&dev->qp_table.qp, qpn & (dev->limits.num_qps - 1));
 246         if (qp)
 247                 ++qp->refcount;
 248         spin_unlock(&dev->qp_table.lock);
 249
 250         if (!qp) {
 251                 mthca_warn(dev, "Async event %d for bogus QP %08x\n",
 252                            event_type, qpn);
 253                 return;
 254         }
 255
 256         if (event_type == IB_EVENT_PATH_MIG)
 257                 qp->port = qp->alt_port;
 258
 259         event.device      = &dev->ib_dev;
 260         event.event       = event_type;
 261         event.element.qp  = &qp->ibqp;
 262         if (qp->ibqp.event_handler)
 263                 qp->ibqp.event_handler(&event, qp->ibqp.qp_context);
 264
 265         spin_lock(&dev->qp_table.lock);
 266         if (!--qp->refcount)
 267                 wake_up(&qp->wait);
 268         spin_unlock(&dev->qp_table.lock);
 269 }
 270
 271 static int to_mthca_state(enum ib_qp_state ib_state)
 272 {
 273         switch (ib_state) {
 274         case IB_QPS_RESET: return MTHCA_QP_STATE_RST;
 275         case IB_QPS_INIT:  return MTHCA_QP_STATE_INIT;
 276         case IB_QPS_RTR:   return MTHCA_QP_STATE_RTR;
 277         case IB_QPS_RTS:   return MTHCA_QP_STATE_RTS;
 278         case IB_QPS_SQD:   return MTHCA_QP_STATE_SQD;
 279         case IB_QPS_SQE:   return MTHCA_QP_STATE_SQE;
 280         case IB_QPS_ERR:   return MTHCA_QP_STATE_ERR;
 281         default:                return -1;
 282         }
 283 }
 284
 285 enum { RC, UC, UD, RD, RDEE, MLX, NUM_TRANS };
 286
 287 static int to_mthca_st(int transport)
 288 {
 289         switch (transport) {
 290         case RC:  return MTHCA_QP_ST_RC;
 291         case UC:  return MTHCA_QP_ST_UC;
 292         case UD:  return MTHCA_QP_ST_UD;
 293         case RD:  return MTHCA_QP_ST_RD;
 294         case MLX: return MTHCA_QP_ST_MLX;
 295         default:  return -1;
 296         }
 297 }
 298
 299 static void store_attrs(struct mthca_sqp *sqp, const struct ib_qp_attr *attr,
 300                         int attr_mask)
 301 {
 302         if (attr_mask & IB_QP_PKEY_INDEX)
 303                 sqp->pkey_index = attr->pkey_index;
 304         if (attr_mask & IB_QP_QKEY)
 305                 sqp->qkey = attr->qkey;
 306         if (attr_mask & IB_QP_SQ_PSN)
 307                 sqp->send_psn = attr->sq_psn;
 308 }
 309
 310 static void init_port(struct mthca_dev *dev, int port)
 311 {
 312         int err;
 313         struct mthca_init_ib_param param;
 314
 315         memset(&param, 0, sizeof param);
 316
 317         param.port_width = dev->limits.port_width_cap;
 318         param.vl_cap     = dev->limits.vl_cap;
 319         param.mtu_cap    = dev->limits.mtu_cap;
 320         param.gid_cap    = dev->limits.gid_table_len;
 321         param.pkey_cap   = dev->limits.pkey_table_len;
 322
 323         err = mthca_INIT_IB(dev, &param, port);
 324         if (err)
 325                 mthca_warn(dev, "INIT_IB failed, return code %d.\n", err);
 326 }
 327
 328 static __be32 get_hw_access_flags(struct mthca_qp *qp, const struct ib_qp_attr *attr,
 329                                   int attr_mask)
 330 {
 331         u8 dest_rd_atomic;
 332         u32 access_flags;
 333         u32 hw_access_flags = 0;
 334
 335         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
 336                 dest_rd_atomic = attr->max_dest_rd_atomic;
 337         else
 338                 dest_rd_atomic = qp->resp_depth;
 339
 340         if (attr_mask & IB_QP_ACCESS_FLAGS)
 341                 access_flags = attr->qp_access_flags;
 342         else
 343                 access_flags = qp->atomic_rd_en;
 344
 345         if (!dest_rd_atomic)
 346                 access_flags &= IB_ACCESS_REMOTE_WRITE;
 347
 348         if (access_flags & IB_ACCESS_REMOTE_READ)
 349                 hw_access_flags |= MTHCA_QP_BIT_RRE;
 350         if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
 351                 hw_access_flags |= MTHCA_QP_BIT_RAE;
 352         if (access_flags & IB_ACCESS_REMOTE_WRITE)
 353                 hw_access_flags |= MTHCA_QP_BIT_RWE;
 354
 355         return cpu_to_be32(hw_access_flags);
 356 }
 357
 358 static inline enum ib_qp_state to_ib_qp_state(int mthca_state)
 359 {
 360         switch (mthca_state) {
 361         case MTHCA_QP_STATE_RST:      return IB_QPS_RESET;
 362         case MTHCA_QP_STATE_INIT:     return IB_QPS_INIT;
 363         case MTHCA_QP_STATE_RTR:      return IB_QPS_RTR;
 364         case MTHCA_QP_STATE_RTS:      return IB_QPS_RTS;
 365         case MTHCA_QP_STATE_DRAINING:
 366         case MTHCA_QP_STATE_SQD:      return IB_QPS_SQD;
 367         case MTHCA_QP_STATE_SQE:      return IB_QPS_SQE;
 368         case MTHCA_QP_STATE_ERR:      return IB_QPS_ERR;
 369         default:                      return -1;
 370         }
 371 }
 372
 373 static inline enum ib_mig_state to_ib_mig_state(int mthca_mig_state)
 374 {
 375         switch (mthca_mig_state) {
 376         case 0:  return IB_MIG_ARMED;
 377         case 1:  return IB_MIG_REARM;
 378         case 3:  return IB_MIG_MIGRATED;
 379         default: return -1;
 380         }
 381 }
 382
 383 static int to_ib_qp_access_flags(int mthca_flags)
 384 {
 385         int ib_flags = 0;
 386
 387         if (mthca_flags & MTHCA_QP_BIT_RRE)
 388                 ib_flags |= IB_ACCESS_REMOTE_READ;
 389         if (mthca_flags & MTHCA_QP_BIT_RWE)
 390                 ib_flags |= IB_ACCESS_REMOTE_WRITE;
 391         if (mthca_flags & MTHCA_QP_BIT_RAE)
 392                 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
 393
 394         return ib_flags;
 395 }
 396
 397 static void to_ib_ah_attr(struct mthca_dev *dev, struct ib_ah_attr *ib_ah_attr,
 398                                 struct mthca_qp_path *path)
 399 {
 400         memset(ib_ah_attr, 0, sizeof *ib_ah_attr);
 401         ib_ah_attr->port_num      = (be32_to_cpu(path->port_pkey) >> 24) & 0x3;
 402
 403         if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->limits.num_ports)
 404                 return;
 405
 406         ib_ah_attr->dlid          = be16_to_cpu(path->rlid);
 407         ib_ah_attr->sl            = be32_to_cpu(path->sl_tclass_flowlabel) >> 28;
 408         ib_ah_attr->src_path_bits = path->g_mylmc & 0x7f;
 409         ib_ah_attr->static_rate   = mthca_rate_to_ib(dev,
 410                                                      path->static_rate & 0xf,
 411                                                      ib_ah_attr->port_num);
 412         ib_ah_attr->ah_flags      = (path->g_mylmc & (1 << 7)) ? IB_AH_GRH : 0;
 413         if (ib_ah_attr->ah_flags) {
 414                 ib_ah_attr->grh.sgid_index = path->mgid_index & (dev->limits.gid_table_len - 1);
 415                 ib_ah_attr->grh.hop_limit  = path->hop_limit;
 416                 ib_ah_attr->grh.traffic_class =
 417                         (be32_to_cpu(path->sl_tclass_flowlabel) >> 20) & 0xff;
 418                 ib_ah_attr->grh.flow_label =
 419                         be32_to_cpu(path->sl_tclass_flowlabel) & 0xfffff;
 420                 memcpy(ib_ah_attr->grh.dgid.raw,
 421                         path->rgid, sizeof ib_ah_attr->grh.dgid.raw);
 422         }
 423 }
 424
 425 int mthca_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
 426                    struct ib_qp_init_attr *qp_init_attr)
 427 {
 428         struct mthca_dev *dev = to_mdev(ibqp->device);
 429         struct mthca_qp *qp = to_mqp(ibqp);
 430         int err = 0;
 431         struct mthca_mailbox *mailbox = NULL;
 432         struct mthca_qp_param *qp_param;
 433         struct mthca_qp_context *context;
 434         int mthca_state;
 435
 436         mutex_lock(&qp->mutex);
 437
 438         if (qp->state == IB_QPS_RESET) {
 439                 qp_attr->qp_state = IB_QPS_RESET;
 440                 goto done;
 441         }
 442
 443         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 444         if (IS_ERR(mailbox)) {
 445                 err = PTR_ERR(mailbox);
 446                 goto out;
 447         }
 448
 449         err = mthca_QUERY_QP(dev, qp->qpn, 0, mailbox);
 450         if (err) {
 451                 mthca_warn(dev, "QUERY_QP failed (%d)\n", err);
 452                 goto out_mailbox;
 453         }
 454
 455         qp_param    = mailbox->buf;
 456         context     = &qp_param->context;
 457         mthca_state = be32_to_cpu(context->flags) >> 28;
 458
 459         qp->state                    = to_ib_qp_state(mthca_state);
 460         qp_attr->qp_state            = qp->state;
 461         qp_attr->path_mtu            = context->mtu_msgmax >> 5;
 462         qp_attr->path_mig_state      =
 463                 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
 464         qp_attr->qkey                = be32_to_cpu(context->qkey);
 465         qp_attr->rq_psn              = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
 466         qp_attr->sq_psn              = be32_to_cpu(context->next_send_psn) & 0xffffff;
 467         qp_attr->dest_qp_num         = be32_to_cpu(context->remote_qpn) & 0xffffff;
 468         qp_attr->qp_access_flags     =
 469                 to_ib_qp_access_flags(be32_to_cpu(context->params2));
 470
 471         if (qp->transport == RC || qp->transport == UC) {
 472                 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
 473                 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
 474                 qp_attr->alt_pkey_index =
 475                         be32_to_cpu(context->alt_path.port_pkey) & 0x7f;
 476                 qp_attr->alt_port_num   = qp_attr->alt_ah_attr.port_num;
 477         }
 478
 479         qp_attr->pkey_index = be32_to_cpu(context->pri_path.port_pkey) & 0x7f;
 480         qp_attr->port_num   =
 481                 (be32_to_cpu(context->pri_path.port_pkey) >> 24) & 0x3;
 482
 483         /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
 484         qp_attr->sq_draining = mthca_state == MTHCA_QP_STATE_DRAINING;
 485
 486         qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
 487
 488         qp_attr->max_dest_rd_atomic =
 489                 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
 490         qp_attr->min_rnr_timer      =
 491                 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
 492         qp_attr->timeout            = context->pri_path.ackto >> 3;
 493         qp_attr->retry_cnt          = (be32_to_cpu(context->params1) >> 16) & 0x7;
 494         qp_attr->rnr_retry          = context->pri_path.rnr_retry >> 5;
 495         qp_attr->alt_timeout        = context->alt_path.ackto >> 3;
 496
 497 done:
 498         qp_attr->cur_qp_state        = qp_attr->qp_state;
 499         qp_attr->cap.max_send_wr     = qp->sq.max;
 500         qp_attr->cap.max_recv_wr     = qp->rq.max;
 501         qp_attr->cap.max_send_sge    = qp->sq.max_gs;
 502         qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
 503         qp_attr->cap.max_inline_data = qp->max_inline_data;
 504
 505         qp_init_attr->cap            = qp_attr->cap;
 506         qp_init_attr->sq_sig_type    = qp->sq_policy;
 507
 508 out_mailbox:
 509         mthca_free_mailbox(dev, mailbox);
 510
 511 out:
 512         mutex_unlock(&qp->mutex);
 513         return err;
 514 }
 515
 516 static int mthca_path_set(struct mthca_dev *dev, const struct ib_ah_attr *ah,
 517                           struct mthca_qp_path *path, u8 port)
 518 {
 519         path->g_mylmc     = ah->src_path_bits & 0x7f;
 520         path->rlid        = cpu_to_be16(ah->dlid);
 521         path->static_rate = mthca_get_rate(dev, ah->static_rate, port);
 522
 523         if (ah->ah_flags & IB_AH_GRH) {
 524                 if (ah->grh.sgid_index >= dev->limits.gid_table_len) {
 525                         mthca_dbg(dev, "sgid_index (%u) too large. max is %d\n",
 526                                   ah->grh.sgid_index, dev->limits.gid_table_len-1);
 527                         return -1;
 528                 }
 529
 530                 path->g_mylmc   |= 1 << 7;
 531                 path->mgid_index = ah->grh.sgid_index;
 532                 path->hop_limit  = ah->grh.hop_limit;
 533                 path->sl_tclass_flowlabel =
 534                         cpu_to_be32((ah->sl << 28)                |
 535                                     (ah->grh.traffic_class << 20) |
 536                                     (ah->grh.flow_label));
 537                 memcpy(path->rgid, ah->grh.dgid.raw, 16);
 538         } else
 539                 path->sl_tclass_flowlabel = cpu_to_be32(ah->sl << 28);
 540
 541         return 0;
 542 }
 543
 544 static int __mthca_modify_qp(struct ib_qp *ibqp,
 545                              const struct ib_qp_attr *attr, int attr_mask,
 546                              enum ib_qp_state cur_state,
 547                              enum ib_qp_state new_state,
 548                              struct ib_udata *udata)
 549 {
 550         struct mthca_dev *dev = to_mdev(ibqp->device);
 551         struct mthca_qp *qp = to_mqp(ibqp);
 552         struct mthca_ucontext *context = rdma_udata_to_drv_context(
 553                 udata, struct mthca_ucontext, ibucontext);
 554         struct mthca_mailbox *mailbox;
 555         struct mthca_qp_param *qp_param;
 556         struct mthca_qp_context *qp_context;
 557         u32 sqd_event = 0;
 558         int err = -EINVAL;
 559
 560         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 561         if (IS_ERR(mailbox)) {
 562                 err = PTR_ERR(mailbox);
 563                 goto out;
 564         }
 565         qp_param = mailbox->buf;
 566         qp_context = &qp_param->context;
 567         memset(qp_param, 0, sizeof *qp_param);
 568
 569         qp_context->flags      = cpu_to_be32((to_mthca_state(new_state) << 28) |
 570                                              (to_mthca_st(qp->transport) << 16));
 571         qp_context->flags     |= cpu_to_be32(MTHCA_QP_BIT_DE);
 572         if (!(attr_mask & IB_QP_PATH_MIG_STATE))
 573                 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
 574         else {
 575                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PM_STATE);
 576                 switch (attr->path_mig_state) {
 577                 case IB_MIG_MIGRATED:
 578                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
 579                         break;
 580                 case IB_MIG_REARM:
 581                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_REARM << 11);
 582                         break;
 583                 case IB_MIG_ARMED:
 584                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_ARMED << 11);
 585                         break;
 586                 }
 587         }
 588
 589         /* leave tavor_sched_queue as 0 */
 590
 591         if (qp->transport == MLX || qp->transport == UD)
 592                 qp_context->mtu_msgmax = (IB_MTU_2048 << 5) | 11;
 593         else if (attr_mask & IB_QP_PATH_MTU) {
 594                 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_2048) {
 595                         mthca_dbg(dev, "path MTU (%u) is invalid\n",
 596                                   attr->path_mtu);
 597                         goto out_mailbox;
 598                 }
 599                 qp_context->mtu_msgmax = (attr->path_mtu << 5) | 31;
 600         }
 601
 602         if (mthca_is_memfree(dev)) {
 603                 if (qp->rq.max)
 604                         qp_context->rq_size_stride = ilog2(qp->rq.max) << 3;
 605                 qp_context->rq_size_stride |= qp->rq.wqe_shift - 4;
 606
 607                 if (qp->sq.max)
 608                         qp_context->sq_size_stride = ilog2(qp->sq.max) << 3;
 609                 qp_context->sq_size_stride |= qp->sq.wqe_shift - 4;
 610         }
 611
 612         /* leave arbel_sched_queue as 0 */
 613
 614         if (qp->ibqp.uobject)
 615                 qp_context->usr_page = cpu_to_be32(context->uar.index);
 616         else
 617                 qp_context->usr_page = cpu_to_be32(dev->driver_uar.index);
 618         qp_context->local_qpn  = cpu_to_be32(qp->qpn);
 619         if (attr_mask & IB_QP_DEST_QPN) {
 620                 qp_context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
 621         }
 622
 623         if (qp->transport == MLX)
 624                 qp_context->pri_path.port_pkey |=
 625                         cpu_to_be32(qp->port << 24);
 626         else {
 627                 if (attr_mask & IB_QP_PORT) {
 628                         qp_context->pri_path.port_pkey |=
 629                                 cpu_to_be32(attr->port_num << 24);
 630                         qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PORT_NUM);
 631                 }
 632         }
 633
 634         if (attr_mask & IB_QP_PKEY_INDEX) {
 635                 qp_context->pri_path.port_pkey |=
 636                         cpu_to_be32(attr->pkey_index);
 637                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PKEY_INDEX);
 638         }
 639
 640         if (attr_mask & IB_QP_RNR_RETRY) {
 641                 qp_context->alt_path.rnr_retry = qp_context->pri_path.rnr_retry =
 642                         attr->rnr_retry << 5;
 643                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_RETRY |
 644                                                         MTHCA_QP_OPTPAR_ALT_RNR_RETRY);
 645         }
 646
 647         if (attr_mask & IB_QP_AV) {
 648                 if (mthca_path_set(dev, &attr->ah_attr, &qp_context->pri_path,
 649                                    attr_mask & IB_QP_PORT ? attr->port_num : qp->port))
 650                         goto out_mailbox;
 651
 652                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH);
 653         }
 654
 655         if (ibqp->qp_type == IB_QPT_RC &&
 656             cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
 657                 u8 sched_queue = ibqp->uobject ? 0x2 : 0x1;
 658
 659                 if (mthca_is_memfree(dev))
 660                         qp_context->rlkey_arbel_sched_queue |= sched_queue;
 661                 else
 662                         qp_context->tavor_sched_queue |= cpu_to_be32(sched_queue);
 663
 664                 qp_param->opt_param_mask |=
 665                         cpu_to_be32(MTHCA_QP_OPTPAR_SCHED_QUEUE);
 666         }
 667
 668         if (attr_mask & IB_QP_TIMEOUT) {
 669                 qp_context->pri_path.ackto = attr->timeout << 3;
 670                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ACK_TIMEOUT);
 671         }
 672
 673         if (attr_mask & IB_QP_ALT_PATH) {
 674                 if (attr->alt_pkey_index >= dev->limits.pkey_table_len) {
 675                         mthca_dbg(dev, "Alternate P_Key index (%u) too large. max is %d\n",
 676                                   attr->alt_pkey_index, dev->limits.pkey_table_len-1);
 677                         goto out_mailbox;
 678                 }
 679
 680                 if (attr->alt_port_num == 0 || attr->alt_port_num > dev->limits.num_ports) {
 681                         mthca_dbg(dev, "Alternate port number (%u) is invalid\n",
 682                                 attr->alt_port_num);
 683                         goto out_mailbox;
 684                 }
 685
 686                 if (mthca_path_set(dev, &attr->alt_ah_attr, &qp_context->alt_path,
 687                                    attr->alt_ah_attr.port_num))
 688                         goto out_mailbox;
 689
 690                 qp_context->alt_path.port_pkey |= cpu_to_be32(attr->alt_pkey_index |
 691                                                               attr->alt_port_num << 24);
 692                 qp_context->alt_path.ackto = attr->alt_timeout << 3;
 693                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ALT_ADDR_PATH);
 694         }
 695
 696         /* leave rdd as 0 */
 697         qp_context->pd         = cpu_to_be32(to_mpd(ibqp->pd)->pd_num);
 698         /* leave wqe_base as 0 (we always create an MR based at 0 for WQs) */
 699         qp_context->wqe_lkey   = cpu_to_be32(qp->mr.ibmr.lkey);
 700         qp_context->params1    = cpu_to_be32((MTHCA_ACK_REQ_FREQ << 28) |
 701                                              (MTHCA_FLIGHT_LIMIT << 24) |
 702                                              MTHCA_QP_BIT_SWE);
 703         if (qp->sq_policy == IB_SIGNAL_ALL_WR)
 704                 qp_context->params1 |= cpu_to_be32(MTHCA_QP_BIT_SSC);
 705         if (attr_mask & IB_QP_RETRY_CNT) {
 706                 qp_context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
 707                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RETRY_COUNT);
 708         }
 709
 710         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
 711                 if (attr->max_rd_atomic) {
 712                         qp_context->params1 |=
 713                                 cpu_to_be32(MTHCA_QP_BIT_SRE |
 714                                             MTHCA_QP_BIT_SAE);
 715                         qp_context->params1 |=
 716                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
 717                 }
 718                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_SRA_MAX);
 719         }
 720
 721         if (attr_mask & IB_QP_SQ_PSN)
 722                 qp_context->next_send_psn = cpu_to_be32(attr->sq_psn);
 723         qp_context->cqn_snd = cpu_to_be32(to_mcq(ibqp->send_cq)->cqn);
 724
 725         if (mthca_is_memfree(dev)) {
 726                 qp_context->snd_wqe_base_l = cpu_to_be32(qp->send_wqe_offset);
 727                 qp_context->snd_db_index   = cpu_to_be32(qp->sq.db_index);
 728         }
 729
 730         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
 731                 if (attr->max_dest_rd_atomic)
 732                         qp_context->params2 |=
 733                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
 734
 735                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RRA_MAX);
 736         }
 737
 738         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
 739                 qp_context->params2      |= get_hw_access_flags(qp, attr, attr_mask);
 740                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RWE |
 741                                                         MTHCA_QP_OPTPAR_RRE |
 742                                                         MTHCA_QP_OPTPAR_RAE);
 743         }
 744
 745         qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RSC);
 746
 747         if (ibqp->srq)
 748                 qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RIC);
 749
 750         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
 751                 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
 752                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_TIMEOUT);
 753         }
 754         if (attr_mask & IB_QP_RQ_PSN)
 755                 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
 756
 757         qp_context->ra_buff_indx =
 758                 cpu_to_be32(dev->qp_table.rdb_base +
 759                             ((qp->qpn & (dev->limits.num_qps - 1)) * MTHCA_RDB_ENTRY_SIZE <<
 760                              dev->qp_table.rdb_shift));
 761
 762         qp_context->cqn_rcv = cpu_to_be32(to_mcq(ibqp->recv_cq)->cqn);
 763
 764         if (mthca_is_memfree(dev))
 765                 qp_context->rcv_db_index   = cpu_to_be32(qp->rq.db_index);
 766
 767         if (attr_mask & IB_QP_QKEY) {
 768                 qp_context->qkey = cpu_to_be32(attr->qkey);
 769                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_Q_KEY);
 770         }
 771
 772         if (ibqp->srq)
 773                 qp_context->srqn = cpu_to_be32(1 << 24 |
 774                                                to_msrq(ibqp->srq)->srqn);
 775
 776         if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD  &&
 777             attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY               &&
 778             attr->en_sqd_async_notify)
 779                 sqd_event = 1 << 31;
 780
 781         err = mthca_MODIFY_QP(dev, cur_state, new_state, qp->qpn, 0,
 782                               mailbox, sqd_event);
 783         if (err) {
 784                 mthca_warn(dev, "modify QP %d->%d returned %d.\n",
 785                            cur_state, new_state, err);
 786                 goto out_mailbox;
 787         }
 788
 789         qp->state = new_state;
 790         if (attr_mask & IB_QP_ACCESS_FLAGS)
 791                 qp->atomic_rd_en = attr->qp_access_flags;
 792         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
 793                 qp->resp_depth = attr->max_dest_rd_atomic;
 794         if (attr_mask & IB_QP_PORT)
 795                 qp->port = attr->port_num;
 796         if (attr_mask & IB_QP_ALT_PATH)
 797                 qp->alt_port = attr->alt_port_num;
 798
 799         if (is_sqp(dev, qp))
 800                 store_attrs(to_msqp(qp), attr, attr_mask);
 801
 802         /*
 803          * If we moved QP0 to RTR, bring the IB link up; if we moved
 804          * QP0 to RESET or ERROR, bring the link back down.
 805          */
 806         if (is_qp0(dev, qp)) {
 807                 if (cur_state != IB_QPS_RTR &&
 808                     new_state == IB_QPS_RTR)
 809                         init_port(dev, qp->port);
 810
 811                 if (cur_state != IB_QPS_RESET &&
 812                     cur_state != IB_QPS_ERR &&
 813                     (new_state == IB_QPS_RESET ||
 814                      new_state == IB_QPS_ERR))
 815                         mthca_CLOSE_IB(dev, qp->port);
 816         }
 817
 818         /*
 819          * If we moved a kernel QP to RESET, clean up all old CQ
 820          * entries and reinitialize the QP.
 821          */
 822         if (new_state == IB_QPS_RESET && !qp->ibqp.uobject) {
 823                 mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq), qp->qpn,
 824                                qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
 825                 if (qp->ibqp.send_cq != qp->ibqp.recv_cq)
 826                         mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq), qp->qpn, NULL);
 827
 828                 mthca_wq_reset(&qp->sq);
 829                 qp->sq.last = get_send_wqe(qp, qp->sq.max - 1);
 830
 831                 mthca_wq_reset(&qp->rq);
 832                 qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1);
 833
 834                 if (mthca_is_memfree(dev)) {
 835                         *qp->sq.db = 0;
 836                         *qp->rq.db = 0;
 837                 }
 838         }
 839
 840 out_mailbox:
 841         mthca_free_mailbox(dev, mailbox);
 842 out:
 843         return err;
 844 }
 845
 846 int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask,
 847                     struct ib_udata *udata)
 848 {
 849         struct mthca_dev *dev = to_mdev(ibqp->device);
 850         struct mthca_qp *qp = to_mqp(ibqp);
 851         enum ib_qp_state cur_state, new_state;
 852         int err = -EINVAL;
 853
 854         mutex_lock(&qp->mutex);
 855         if (attr_mask & IB_QP_CUR_STATE) {
 856                 cur_state = attr->cur_qp_state;
 857         } else {
 858                 spin_lock_irq(&qp->sq.lock);
 859                 spin_lock(&qp->rq.lock);
 860                 cur_state = qp->state;
 861                 spin_unlock(&qp->rq.lock);
 862                 spin_unlock_irq(&qp->sq.lock);
 863         }
 864
 865         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
 866
 867         if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask)) {
 868                 mthca_dbg(dev, "Bad QP transition (transport %d) "
 869                           "%d->%d with attr 0x%08x\n",
 870                           qp->transport, cur_state, new_state,
 871                           attr_mask);
 872                 goto out;
 873         }
 874
 875         if ((attr_mask & IB_QP_PKEY_INDEX) &&
 876              attr->pkey_index >= dev->limits.pkey_table_len) {
 877                 mthca_dbg(dev, "P_Key index (%u) too large. max is %d\n",
 878                           attr->pkey_index, dev->limits.pkey_table_len-1);
 879                 goto out;
 880         }
 881
 882         if ((attr_mask & IB_QP_PORT) &&
 883             (attr->port_num == 0 || attr->port_num > dev->limits.num_ports)) {
 884                 mthca_dbg(dev, "Port number (%u) is invalid\n", attr->port_num);
 885                 goto out;
 886         }
 887
 888         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
 889             attr->max_rd_atomic > dev->limits.max_qp_init_rdma) {
 890                 mthca_dbg(dev, "Max rdma_atomic as initiator %u too large (max is %d)\n",
 891                           attr->max_rd_atomic, dev->limits.max_qp_init_rdma);
 892                 goto out;
 893         }
 894
 895         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
 896             attr->max_dest_rd_atomic > 1 << dev->qp_table.rdb_shift) {
 897                 mthca_dbg(dev, "Max rdma_atomic as responder %u too large (max %d)\n",
 898                           attr->max_dest_rd_atomic, 1 << dev->qp_table.rdb_shift);
 899                 goto out;
 900         }
 901
 902         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
 903                 err = 0;
 904                 goto out;
 905         }
 906
 907         err = __mthca_modify_qp(ibqp, attr, attr_mask, cur_state, new_state,
 908                                 udata);
 909
 910 out:
 911         mutex_unlock(&qp->mutex);
 912         return err;
 913 }
 914
 915 static int mthca_max_data_size(struct mthca_dev *dev, struct mthca_qp *qp, int desc_sz)
 916 {
 917         /*
 918          * Calculate the maximum size of WQE s/g segments, excluding
 919          * the next segment and other non-data segments.
 920          */
 921         int max_data_size = desc_sz - sizeof (struct mthca_next_seg);
 922
 923         switch (qp->transport) {
 924         case MLX:
 925                 max_data_size -= 2 * sizeof (struct mthca_data_seg);
 926                 break;
 927
 928         case UD:
 929                 if (mthca_is_memfree(dev))
 930                         max_data_size -= sizeof (struct mthca_arbel_ud_seg);
 931                 else
 932                         max_data_size -= sizeof (struct mthca_tavor_ud_seg);
 933                 break;
 934
 935         default:
 936                 max_data_size -= sizeof (struct mthca_raddr_seg);
 937                 break;
 938         }
 939
 940         return max_data_size;
 941 }
 942
 943 static inline int mthca_max_inline_data(struct mthca_pd *pd, int max_data_size)
 944 {
 945         /* We don't support inline data for kernel QPs (yet). */
 946         return pd->ibpd.uobject ? max_data_size - MTHCA_INLINE_HEADER_SIZE : 0;
 947 }
 948
 949 static void mthca_adjust_qp_caps(struct mthca_dev *dev,
 950                                  struct mthca_pd *pd,
 951                                  struct mthca_qp *qp)
 952 {
 953         int max_data_size = mthca_max_data_size(dev, qp,
 954                                                 min(dev->limits.max_desc_sz,
 955                                                     1 << qp->sq.wqe_shift));
 956
 957         qp->max_inline_data = mthca_max_inline_data(pd, max_data_size);
 958
 959         qp->sq.max_gs = min_t(int, dev->limits.max_sg,
 960                               max_data_size / sizeof (struct mthca_data_seg));
 961         qp->rq.max_gs = min_t(int, dev->limits.max_sg,
 962                                (min(dev->limits.max_desc_sz, 1 << qp->rq.wqe_shift) -
 963                                 sizeof (struct mthca_next_seg)) /
 964                                sizeof (struct mthca_data_seg));
 965 }
 966
 967 /*
 968  * Allocate and register buffer for WQEs.  qp->rq.max, sq.max,
 969  * rq.max_gs and sq.max_gs must all be assigned.
 970  * mthca_alloc_wqe_buf will calculate rq.wqe_shift and
 971  * sq.wqe_shift (as well as send_wqe_offset, is_direct, and
 972  * queue)
 973  */
 974 static int mthca_alloc_wqe_buf(struct mthca_dev *dev,
 975                                struct mthca_pd *pd,
 976                                struct mthca_qp *qp,
 977                                struct ib_udata *udata)
 978 {
 979         int size;
 980         int err = -ENOMEM;
 981
 982         size = sizeof (struct mthca_next_seg) +
 983                 qp->rq.max_gs * sizeof (struct mthca_data_seg);
 984
 985         if (size > dev->limits.max_desc_sz)
 986                 return -EINVAL;
 987
 988         for (qp->rq.wqe_shift = 6; 1 << qp->rq.wqe_shift < size;
 989              qp->rq.wqe_shift++)
 990                 ; /* nothing */
 991
 992         size = qp->sq.max_gs * sizeof (struct mthca_data_seg);
 993         switch (qp->transport) {
 994         case MLX:
 995                 size += 2 * sizeof (struct mthca_data_seg);
 996                 break;
 997
 998         case UD:
 999                 size += mthca_is_memfree(dev) ?
1000                         sizeof (struct mthca_arbel_ud_seg) :
1001                         sizeof (struct mthca_tavor_ud_seg);
1002                 break;
1003
1004         case UC:
1005                 size += sizeof (struct mthca_raddr_seg);
1006                 break;
1007
1008         case RC:
1009                 size += sizeof (struct mthca_raddr_seg);
1010                 /*
1011                  * An atomic op will require an atomic segment, a
1012                  * remote address segment and one scatter entry.
1013                  */
1014                 size = max_t(int, size,
1015                              sizeof (struct mthca_atomic_seg) +
1016                              sizeof (struct mthca_raddr_seg) +
1017                              sizeof (struct mthca_data_seg));
1018                 break;
1019
1020         default:
1021                 break;
1022         }
1023
1024         /* Make sure that we have enough space for a bind request */
1025         size = max_t(int, size, sizeof (struct mthca_bind_seg));
1026
1027         size += sizeof (struct mthca_next_seg);
1028
1029         if (size > dev->limits.max_desc_sz)
1030                 return -EINVAL;
1031
1032         for (qp->sq.wqe_shift = 6; 1 << qp->sq.wqe_shift < size;
1033              qp->sq.wqe_shift++)
1034                 ; /* nothing */
1035
1036         qp->send_wqe_offset = ALIGN(qp->rq.max << qp->rq.wqe_shift,
1037                                     1 << qp->sq.wqe_shift);
1038
1039         /*
1040          * If this is a userspace QP, we don't actually have to
1041          * allocate anything.  All we need is to calculate the WQE
1042          * sizes and the send_wqe_offset, so we're done now.
1043          */
1044         if (udata)
1045                 return 0;
1046
1047         size = PAGE_ALIGN(qp->send_wqe_offset +
1048                           (qp->sq.max << qp->sq.wqe_shift));
1049
1050         qp->wrid = kmalloc((qp->rq.max + qp->sq.max) * sizeof (u64),
1051                            GFP_KERNEL);
1052         if (!qp->wrid)
1053                 goto err_out;
1054
1055         err = mthca_buf_alloc(dev, size, MTHCA_MAX_DIRECT_QP_SIZE,
1056                               &qp->queue, &qp->is_direct, pd, 0, &qp->mr);
1057         if (err)
1058                 goto err_out;
1059
1060         return 0;
1061
1062 err_out:
1063         kfree(qp->wrid);
1064         return err;
1065 }
1066
1067 static void mthca_free_wqe_buf(struct mthca_dev *dev,
1068                                struct mthca_qp *qp)
1069 {
1070         mthca_buf_free(dev, PAGE_ALIGN(qp->send_wqe_offset +
1071                                        (qp->sq.max << qp->sq.wqe_shift)),
1072                        &qp->queue, qp->is_direct, &qp->mr);
1073         kfree(qp->wrid);
1074 }
1075
1076 static int mthca_map_memfree(struct mthca_dev *dev,
1077                              struct mthca_qp *qp)
1078 {
1079         int ret;
1080
1081         if (mthca_is_memfree(dev)) {
1082                 ret = mthca_table_get(dev, dev->qp_table.qp_table, qp->qpn);
1083                 if (ret)
1084                         return ret;
1085
1086                 ret = mthca_table_get(dev, dev->qp_table.eqp_table, qp->qpn);
1087                 if (ret)
1088                         goto err_qpc;
1089
1090                 ret = mthca_table_get(dev, dev->qp_table.rdb_table,
1091                                       qp->qpn << dev->qp_table.rdb_shift);
1092                 if (ret)
1093                         goto err_eqpc;
1094         }
1095
1096         return 0;
1097
1098 err_eqpc:
1099         mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1100
1101 err_qpc:
1102         mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1103
1104         return ret;
1105 }
1106
1107 static void mthca_unmap_memfree(struct mthca_dev *dev,
1108                                 struct mthca_qp *qp)
1109 {
1110         mthca_table_put(dev, dev->qp_table.rdb_table,
1111                         qp->qpn << dev->qp_table.rdb_shift);
1112         mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1113         mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1114 }
1115
1116 static int mthca_alloc_memfree(struct mthca_dev *dev,
1117                                struct mthca_qp *qp)
1118 {
1119         if (mthca_is_memfree(dev)) {
1120                 qp->rq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_RQ,
1121                                                  qp->qpn, &qp->rq.db);
1122                 if (qp->rq.db_index < 0)
1123                         return -ENOMEM;
1124
1125                 qp->sq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_SQ,
1126                                                  qp->qpn, &qp->sq.db);
1127                 if (qp->sq.db_index < 0) {
1128                         mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1129                         return -ENOMEM;
1130                 }
1131         }
1132
1133         return 0;
1134 }
1135
1136 static void mthca_free_memfree(struct mthca_dev *dev,
1137                                struct mthca_qp *qp)
1138 {
1139         if (mthca_is_memfree(dev)) {
1140                 mthca_free_db(dev, MTHCA_DB_TYPE_SQ, qp->sq.db_index);
1141                 mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1142         }
1143 }
1144
1145 static int mthca_alloc_qp_common(struct mthca_dev *dev,
1146                                  struct mthca_pd *pd,
1147                                  struct mthca_cq *send_cq,
1148                                  struct mthca_cq *recv_cq,
1149                                  enum ib_sig_type send_policy,
1150                                  struct mthca_qp *qp,
1151                                  struct ib_udata *udata)
1152 {
1153         int ret;
1154         int i;
1155         struct mthca_next_seg *next;
1156
1157         qp->refcount = 1;
1158         init_waitqueue_head(&qp->wait);
1159         mutex_init(&qp->mutex);
1160         qp->state        = IB_QPS_RESET;
1161         qp->atomic_rd_en = 0;
1162         qp->resp_depth   = 0;
1163         qp->sq_policy    = send_policy;
1164         mthca_wq_reset(&qp->sq);
1165         mthca_wq_reset(&qp->rq);
1166
1167         spin_lock_init(&qp->sq.lock);
1168         spin_lock_init(&qp->rq.lock);
1169
1170         ret = mthca_map_memfree(dev, qp);
1171         if (ret)
1172                 return ret;
1173
1174         ret = mthca_alloc_wqe_buf(dev, pd, qp, udata);
1175         if (ret) {
1176                 mthca_unmap_memfree(dev, qp);
1177                 return ret;
1178         }
1179
1180         mthca_adjust_qp_caps(dev, pd, qp);
1181
1182         /*
1183          * If this is a userspace QP, we're done now.  The doorbells
1184          * will be allocated and buffers will be initialized in
1185          * userspace.
1186          */
1187         if (udata)
1188                 return 0;
1189
1190         ret = mthca_alloc_memfree(dev, qp);
1191         if (ret) {
1192                 mthca_free_wqe_buf(dev, qp);
1193                 mthca_unmap_memfree(dev, qp);
1194                 return ret;
1195         }
1196
1197         if (mthca_is_memfree(dev)) {
1198                 struct mthca_data_seg *scatter;
1199                 int size = (sizeof (struct mthca_next_seg) +
1200                             qp->rq.max_gs * sizeof (struct mthca_data_seg)) / 16;
1201
1202                 for (i = 0; i < qp->rq.max; ++i) {
1203                         next = get_recv_wqe(qp, i);
1204                         next->nda_op = cpu_to_be32(((i + 1) & (qp->rq.max - 1)) <<
1205                                                    qp->rq.wqe_shift);
1206                         next->ee_nds = cpu_to_be32(size);
1207
1208                         for (scatter = (void *) (next + 1);
1209                              (void *) scatter < (void *) next + (1 << qp->rq.wqe_shift);
1210                              ++scatter)
1211                                 scatter->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
1212                 }
1213
1214                 for (i = 0; i < qp->sq.max; ++i) {
1215                         next = get_send_wqe(qp, i);
1216                         next->nda_op = cpu_to_be32((((i + 1) & (qp->sq.max - 1)) <<
1217                                                     qp->sq.wqe_shift) +
1218                                                    qp->send_wqe_offset);
1219                 }
1220         } else {
1221                 for (i = 0; i < qp->rq.max; ++i) {
1222                         next = get_recv_wqe(qp, i);
1223                         next->nda_op = htonl((((i + 1) % qp->rq.max) <<
1224                                               qp->rq.wqe_shift) | 1);
1225                 }
1226         }
1227
1228         qp->sq.last = get_send_wqe(qp, qp->sq.max - 1);
1229         qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1);
1230
1231         return 0;
1232 }
1233
1234 static int mthca_set_qp_size(struct mthca_dev *dev, struct ib_qp_cap *cap,
1235                              struct mthca_pd *pd, struct mthca_qp *qp)
1236 {
1237         int max_data_size = mthca_max_data_size(dev, qp, dev->limits.max_desc_sz);
1238
1239         /* Sanity check QP size before proceeding */
1240         if (cap->max_send_wr     > dev->limits.max_wqes ||
1241             cap->max_recv_wr     > dev->limits.max_wqes ||
1242             cap->max_send_sge    > dev->limits.max_sg   ||
1243             cap->max_recv_sge    > dev->limits.max_sg   ||
1244             cap->max_inline_data > mthca_max_inline_data(pd, max_data_size))
1245                 return -EINVAL;
1246
1247         /*
1248          * For MLX transport we need 2 extra send gather entries:
1249          * one for the header and one for the checksum at the end
1250          */
1251         if (qp->transport == MLX && cap->max_send_sge + 2 > dev->limits.max_sg)
1252                 return -EINVAL;
1253
1254         if (mthca_is_memfree(dev)) {
1255                 qp->rq.max = cap->max_recv_wr ?
1256                         roundup_pow_of_two(cap->max_recv_wr) : 0;
1257                 qp->sq.max = cap->max_send_wr ?
1258                         roundup_pow_of_two(cap->max_send_wr) : 0;
1259         } else {
1260                 qp->rq.max = cap->max_recv_wr;
1261                 qp->sq.max = cap->max_send_wr;
1262         }
1263
1264         qp->rq.max_gs = cap->max_recv_sge;
1265         qp->sq.max_gs = max_t(int, cap->max_send_sge,
1266                               ALIGN(cap->max_inline_data + MTHCA_INLINE_HEADER_SIZE,
1267                                     MTHCA_INLINE_CHUNK_SIZE) /
1268                               sizeof (struct mthca_data_seg));
1269
1270         return 0;
1271 }
1272
1273 int mthca_alloc_qp(struct mthca_dev *dev,
1274                    struct mthca_pd *pd,
1275                    struct mthca_cq *send_cq,
1276                    struct mthca_cq *recv_cq,
1277                    enum ib_qp_type type,
1278                    enum ib_sig_type send_policy,
1279                    struct ib_qp_cap *cap,
1280                    struct mthca_qp *qp,
1281                    struct ib_udata *udata)
1282 {
1283         int err;
1284
1285         switch (type) {
1286         case IB_QPT_RC: qp->transport = RC; break;
1287         case IB_QPT_UC: qp->transport = UC; break;
1288         case IB_QPT_UD: qp->transport = UD; break;
1289         default: return -EINVAL;
1290         }
1291
1292         err = mthca_set_qp_size(dev, cap, pd, qp);
1293         if (err)
1294                 return err;
1295
1296         qp->qpn = mthca_alloc(&dev->qp_table.alloc);
1297         if (qp->qpn == -1)
1298                 return -ENOMEM;
1299
1300         /* initialize port to zero for error-catching. */
1301         qp->port = 0;
1302
1303         err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1304                                     send_policy, qp, udata);
1305         if (err) {
1306                 mthca_free(&dev->qp_table.alloc, qp->qpn);
1307                 return err;
1308         }
1309
1310         spin_lock_irq(&dev->qp_table.lock);
1311         mthca_array_set(&dev->qp_table.qp,
1312                         qp->qpn & (dev->limits.num_qps - 1), qp);
1313         spin_unlock_irq(&dev->qp_table.lock);
1314
1315         return 0;
1316 }
1317
1318 static void mthca_lock_cqs(struct mthca_cq *send_cq, struct mthca_cq *recv_cq)
1319         __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1320 {
1321         if (send_cq == recv_cq) {
1322                 spin_lock_irq(&send_cq->lock);
1323                 __acquire(&recv_cq->lock);
1324         } else if (send_cq->cqn < recv_cq->cqn) {
1325                 spin_lock_irq(&send_cq->lock);
1326                 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
1327         } else {
1328                 spin_lock_irq(&recv_cq->lock);
1329                 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
1330         }
1331 }
1332
1333 static void mthca_unlock_cqs(struct mthca_cq *send_cq, struct mthca_cq *recv_cq)
1334         __releases(&send_cq->lock) __releases(&recv_cq->lock)
1335 {
1336         if (send_cq == recv_cq) {
1337                 __release(&recv_cq->lock);
1338                 spin_unlock_irq(&send_cq->lock);
1339         } else if (send_cq->cqn < recv_cq->cqn) {
1340                 spin_unlock(&recv_cq->lock);
1341                 spin_unlock_irq(&send_cq->lock);
1342         } else {
1343                 spin_unlock(&send_cq->lock);
1344                 spin_unlock_irq(&recv_cq->lock);
1345         }
1346 }
1347
1348 int mthca_alloc_sqp(struct mthca_dev *dev,
1349                     struct mthca_pd *pd,
1350                     struct mthca_cq *send_cq,
1351                     struct mthca_cq *recv_cq,
1352                     enum ib_sig_type send_policy,
1353                     struct ib_qp_cap *cap,
1354                     int qpn,
1355                     int port,
1356                     struct mthca_sqp *sqp,
1357                     struct ib_udata *udata)
1358 {
1359         u32 mqpn = qpn * 2 + dev->qp_table.sqp_start + port - 1;
1360         int err;
1361
1362         sqp->qp.transport = MLX;
1363         err = mthca_set_qp_size(dev, cap, pd, &sqp->qp);
1364         if (err)
1365                 return err;
1366
1367         sqp->header_buf_size = sqp->qp.sq.max * MTHCA_UD_HEADER_SIZE;
1368         sqp->header_buf = dma_alloc_coherent(&dev->pdev->dev, sqp->header_buf_size,
1369                                              &sqp->header_dma, GFP_KERNEL);
1370         if (!sqp->header_buf)
1371                 return -ENOMEM;
1372
1373         spin_lock_irq(&dev->qp_table.lock);
1374         if (mthca_array_get(&dev->qp_table.qp, mqpn))
1375                 err = -EBUSY;
1376         else
1377                 mthca_array_set(&dev->qp_table.qp, mqpn, sqp);
1378         spin_unlock_irq(&dev->qp_table.lock);
1379
1380         if (err)
1381                 goto err_out;
1382
1383         sqp->qp.port      = port;
1384         sqp->qp.qpn       = mqpn;
1385         sqp->qp.transport = MLX;
1386
1387         err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1388                                     send_policy, &sqp->qp, udata);
1389         if (err)
1390                 goto err_out_free;
1391
1392         atomic_inc(&pd->sqp_count);
1393
1394         return 0;
1395
1396  err_out_free:
1397         /*
1398          * Lock CQs here, so that CQ polling code can do QP lookup
1399          * without taking a lock.
1400          */
1401         mthca_lock_cqs(send_cq, recv_cq);
1402
1403         spin_lock(&dev->qp_table.lock);
1404         mthca_array_clear(&dev->qp_table.qp, mqpn);
1405         spin_unlock(&dev->qp_table.lock);
1406
1407         mthca_unlock_cqs(send_cq, recv_cq);
1408
1409  err_out:
1410         dma_free_coherent(&dev->pdev->dev, sqp->header_buf_size,
1411                           sqp->header_buf, sqp->header_dma);
1412
1413         return err;
1414 }
1415
1416 static inline int get_qp_refcount(struct mthca_dev *dev, struct mthca_qp *qp)
1417 {
1418         int c;
1419
1420         spin_lock_irq(&dev->qp_table.lock);
1421         c = qp->refcount;
1422         spin_unlock_irq(&dev->qp_table.lock);
1423
1424         return c;
1425 }
1426
1427 void mthca_free_qp(struct mthca_dev *dev,
1428                    struct mthca_qp *qp)
1429 {
1430         struct mthca_cq *send_cq;
1431         struct mthca_cq *recv_cq;
1432
1433         send_cq = to_mcq(qp->ibqp.send_cq);
1434         recv_cq = to_mcq(qp->ibqp.recv_cq);
1435
1436         /*
1437          * Lock CQs here, so that CQ polling code can do QP lookup
1438          * without taking a lock.
1439          */
1440         mthca_lock_cqs(send_cq, recv_cq);
1441
1442         spin_lock(&dev->qp_table.lock);
1443         mthca_array_clear(&dev->qp_table.qp,
1444                           qp->qpn & (dev->limits.num_qps - 1));
1445         --qp->refcount;
1446         spin_unlock(&dev->qp_table.lock);
1447
1448         mthca_unlock_cqs(send_cq, recv_cq);
1449
1450         wait_event(qp->wait, !get_qp_refcount(dev, qp));
1451
1452         if (qp->state != IB_QPS_RESET)
1453                 mthca_MODIFY_QP(dev, qp->state, IB_QPS_RESET, qp->qpn, 0,
1454                                 NULL, 0);
1455
1456         /*
1457          * If this is a userspace QP, the buffers, MR, CQs and so on
1458          * will be cleaned up in userspace, so all we have to do is
1459          * unref the mem-free tables and free the QPN in our table.
1460          */
1461         if (!qp->ibqp.uobject) {
1462                 mthca_cq_clean(dev, recv_cq, qp->qpn,
1463                                qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1464                 if (send_cq != recv_cq)
1465                         mthca_cq_clean(dev, send_cq, qp->qpn, NULL);
1466
1467                 mthca_free_memfree(dev, qp);
1468                 mthca_free_wqe_buf(dev, qp);
1469         }
1470
1471         mthca_unmap_memfree(dev, qp);
1472
1473         if (is_sqp(dev, qp)) {
1474                 atomic_dec(&(to_mpd(qp->ibqp.pd)->sqp_count));
1475                 dma_free_coherent(&dev->pdev->dev,
1476                                   to_msqp(qp)->header_buf_size,
1477                                   to_msqp(qp)->header_buf,
1478                                   to_msqp(qp)->header_dma);
1479         } else
1480                 mthca_free(&dev->qp_table.alloc, qp->qpn);
1481 }
1482
1483 /* Create UD header for an MLX send and build a data segment for it */
1484 static int build_mlx_header(struct mthca_dev *dev, struct mthca_sqp *sqp,
1485                             int ind, const struct ib_ud_wr *wr,
1486                             struct mthca_mlx_seg *mlx,
1487                             struct mthca_data_seg *data)
1488 {
1489         int header_size;
1490         int err;
1491         u16 pkey;
1492
1493         ib_ud_header_init(256, /* assume a MAD */ 1, 0, 0,
1494                           mthca_ah_grh_present(to_mah(wr->ah)), 0, 0, 0,
1495                           &sqp->ud_header);
1496
1497         err = mthca_read_ah(dev, to_mah(wr->ah), &sqp->ud_header);
1498         if (err)
1499                 return err;
1500         mlx->flags &= ~cpu_to_be32(MTHCA_NEXT_SOLICIT | 1);
1501         mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MTHCA_MLX_VL15 : 0) |
1502                                   (sqp->ud_header.lrh.destination_lid ==
1503                                    IB_LID_PERMISSIVE ? MTHCA_MLX_SLR : 0) |
1504                                   (sqp->ud_header.lrh.service_level << 8));
1505         mlx->rlid = sqp->ud_header.lrh.destination_lid;
1506         mlx->vcrc = 0;
1507
1508         switch (wr->wr.opcode) {
1509         case IB_WR_SEND:
1510                 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
1511                 sqp->ud_header.immediate_present = 0;
1512                 break;
1513         case IB_WR_SEND_WITH_IMM:
1514                 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1515                 sqp->ud_header.immediate_present = 1;
1516                 sqp->ud_header.immediate_data = wr->wr.ex.imm_data;
1517                 break;
1518         default:
1519                 return -EINVAL;
1520         }
1521
1522         sqp->ud_header.lrh.virtual_lane    = !sqp->qp.ibqp.qp_num ? 15 : 0;
1523         if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
1524                 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
1525         sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
1526         if (!sqp->qp.ibqp.qp_num)
1527                 ib_get_cached_pkey(&dev->ib_dev, sqp->qp.port,
1528                                    sqp->pkey_index, &pkey);
1529         else
1530                 ib_get_cached_pkey(&dev->ib_dev, sqp->qp.port,
1531                                    wr->pkey_index, &pkey);
1532         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
1533         sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
1534         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1535         sqp->ud_header.deth.qkey = cpu_to_be32(wr->remote_qkey & 0x80000000 ?
1536                                                sqp->qkey : wr->remote_qkey);
1537         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
1538
1539         header_size = ib_ud_header_pack(&sqp->ud_header,
1540                                         sqp->header_buf +
1541                                         ind * MTHCA_UD_HEADER_SIZE);
1542
1543         data->byte_count = cpu_to_be32(header_size);
1544         data->lkey       = cpu_to_be32(to_mpd(sqp->qp.ibqp.pd)->ntmr.ibmr.lkey);
1545         data->addr       = cpu_to_be64(sqp->header_dma +
1546                                        ind * MTHCA_UD_HEADER_SIZE);
1547
1548         return 0;
1549 }
1550
1551 static inline int mthca_wq_overflow(struct mthca_wq *wq, int nreq,
1552                                     struct ib_cq *ib_cq)
1553 {
1554         unsigned cur;
1555         struct mthca_cq *cq;
1556
1557         cur = wq->head - wq->tail;
1558         if (likely(cur + nreq < wq->max))
1559                 return 0;
1560
1561         cq = to_mcq(ib_cq);
1562         spin_lock(&cq->lock);
1563         cur = wq->head - wq->tail;
1564         spin_unlock(&cq->lock);
1565
1566         return cur + nreq >= wq->max;
1567 }
1568
1569 static __always_inline void set_raddr_seg(struct mthca_raddr_seg *rseg,
1570                                           u64 remote_addr, u32 rkey)
1571 {
1572         rseg->raddr    = cpu_to_be64(remote_addr);
1573         rseg->rkey     = cpu_to_be32(rkey);
1574         rseg->reserved = 0;
1575 }
1576
1577 static __always_inline void set_atomic_seg(struct mthca_atomic_seg *aseg,
1578                                            const struct ib_atomic_wr *wr)
1579 {
1580         if (wr->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1581                 aseg->swap_add = cpu_to_be64(wr->swap);
1582                 aseg->compare  = cpu_to_be64(wr->compare_add);
1583         } else {
1584                 aseg->swap_add = cpu_to_be64(wr->compare_add);
1585                 aseg->compare  = 0;
1586         }
1587
1588 }
1589
1590 static void set_tavor_ud_seg(struct mthca_tavor_ud_seg *useg,
1591                              const struct ib_ud_wr *wr)
1592 {
1593         useg->lkey    = cpu_to_be32(to_mah(wr->ah)->key);
1594         useg->av_addr = cpu_to_be64(to_mah(wr->ah)->avdma);
1595         useg->dqpn    = cpu_to_be32(wr->remote_qpn);
1596         useg->qkey    = cpu_to_be32(wr->remote_qkey);
1597
1598 }
1599
1600 static void set_arbel_ud_seg(struct mthca_arbel_ud_seg *useg,
1601                              const struct ib_ud_wr *wr)
1602 {
1603         memcpy(useg->av, to_mah(wr->ah)->av, MTHCA_AV_SIZE);
1604         useg->dqpn = cpu_to_be32(wr->remote_qpn);
1605         useg->qkey = cpu_to_be32(wr->remote_qkey);
1606 }
1607
1608 int mthca_tavor_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
1609                           const struct ib_send_wr **bad_wr)
1610 {
1611         struct mthca_dev *dev = to_mdev(ibqp->device);
1612         struct mthca_qp *qp = to_mqp(ibqp);
1613         void *wqe;
1614         void *prev_wqe;
1615         unsigned long flags;
1616         int err = 0;
1617         int nreq;
1618         int i;
1619         int size;
1620         /*
1621          * f0 and size0 are only used if nreq != 0, and they will
1622          * always be initialized the first time through the main loop
1623          * before nreq is incremented.  So nreq cannot become non-zero
1624          * without initializing f0 and size0, and they are in fact
1625          * never used uninitialized.
1626          */
1627         int uninitialized_var(size0);
1628         u32 uninitialized_var(f0);
1629         int ind;
1630         u8 op0 = 0;
1631
1632         spin_lock_irqsave(&qp->sq.lock, flags);
1633
1634         /* XXX check that state is OK to post send */
1635
1636         ind = qp->sq.next_ind;
1637
1638         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1639                 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1640                         mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1641                                         " %d max, %d nreq)\n", qp->qpn,
1642                                         qp->sq.head, qp->sq.tail,
1643                                         qp->sq.max, nreq);
1644                         err = -ENOMEM;
1645                         *bad_wr = wr;
1646                         goto out;
1647                 }
1648
1649                 wqe = get_send_wqe(qp, ind);
1650                 prev_wqe = qp->sq.last;
1651                 qp->sq.last = wqe;
1652
1653                 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1654                 ((struct mthca_next_seg *) wqe)->ee_nds = 0;
1655                 ((struct mthca_next_seg *) wqe)->flags =
1656                         ((wr->send_flags & IB_SEND_SIGNALED) ?
1657                          cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1658                         ((wr->send_flags & IB_SEND_SOLICITED) ?
1659                          cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0)   |
1660                         cpu_to_be32(1);
1661                 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1662                     wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1663                         ((struct mthca_next_seg *) wqe)->imm = wr->ex.imm_data;
1664
1665                 wqe += sizeof (struct mthca_next_seg);
1666                 size = sizeof (struct mthca_next_seg) / 16;
1667
1668                 switch (qp->transport) {
1669                 case RC:
1670                         switch (wr->opcode) {
1671                         case IB_WR_ATOMIC_CMP_AND_SWP:
1672                         case IB_WR_ATOMIC_FETCH_AND_ADD:
1673                                 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
1674                                               atomic_wr(wr)->rkey);
1675                                 wqe += sizeof (struct mthca_raddr_seg);
1676
1677                                 set_atomic_seg(wqe, atomic_wr(wr));
1678                                 wqe += sizeof (struct mthca_atomic_seg);
1679                                 size += (sizeof (struct mthca_raddr_seg) +
1680                                          sizeof (struct mthca_atomic_seg)) / 16;
1681                                 break;
1682
1683                         case IB_WR_RDMA_WRITE:
1684                         case IB_WR_RDMA_WRITE_WITH_IMM:
1685                         case IB_WR_RDMA_READ:
1686                                 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
1687                                               rdma_wr(wr)->rkey);
1688                                 wqe  += sizeof (struct mthca_raddr_seg);
1689                                 size += sizeof (struct mthca_raddr_seg) / 16;
1690                                 break;
1691
1692                         default:
1693                                 /* No extra segments required for sends */
1694                                 break;
1695                         }
1696
1697                         break;
1698
1699                 case UC:
1700                         switch (wr->opcode) {
1701                         case IB_WR_RDMA_WRITE:
1702                         case IB_WR_RDMA_WRITE_WITH_IMM:
1703                                 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
1704                                               rdma_wr(wr)->rkey);
1705                                 wqe  += sizeof (struct mthca_raddr_seg);
1706                                 size += sizeof (struct mthca_raddr_seg) / 16;
1707                                 break;
1708
1709                         default:
1710                                 /* No extra segments required for sends */
1711                                 break;
1712                         }
1713
1714                         break;
1715
1716                 case UD:
1717                         set_tavor_ud_seg(wqe, ud_wr(wr));
1718                         wqe  += sizeof (struct mthca_tavor_ud_seg);
1719                         size += sizeof (struct mthca_tavor_ud_seg) / 16;
1720                         break;
1721
1722                 case MLX:
1723                         err = build_mlx_header(dev, to_msqp(qp), ind, ud_wr(wr),
1724                                                wqe - sizeof (struct mthca_next_seg),
1725                                                wqe);
1726                         if (err) {
1727                                 *bad_wr = wr;
1728                                 goto out;
1729                         }
1730                         wqe += sizeof (struct mthca_data_seg);
1731                         size += sizeof (struct mthca_data_seg) / 16;
1732                         break;
1733                 }
1734
1735                 if (wr->num_sge > qp->sq.max_gs) {
1736                         mthca_err(dev, "too many gathers\n");
1737                         err = -EINVAL;
1738                         *bad_wr = wr;
1739                         goto out;
1740                 }
1741
1742                 for (i = 0; i < wr->num_sge; ++i) {
1743                         mthca_set_data_seg(wqe, wr->sg_list + i);
1744                         wqe  += sizeof (struct mthca_data_seg);
1745                         size += sizeof (struct mthca_data_seg) / 16;
1746                 }
1747
1748                 /* Add one more inline data segment for ICRC */
1749                 if (qp->transport == MLX) {
1750                         ((struct mthca_data_seg *) wqe)->byte_count =
1751                                 cpu_to_be32((1 << 31) | 4);
1752                         ((u32 *) wqe)[1] = 0;
1753                         wqe += sizeof (struct mthca_data_seg);
1754                         size += sizeof (struct mthca_data_seg) / 16;
1755                 }
1756
1757                 qp->wrid[ind + qp->rq.max] = wr->wr_id;
1758
1759                 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
1760                         mthca_err(dev, "opcode invalid\n");
1761                         err = -EINVAL;
1762                         *bad_wr = wr;
1763                         goto out;
1764                 }
1765
1766                 ((struct mthca_next_seg *) prev_wqe)->nda_op =
1767                         cpu_to_be32(((ind << qp->sq.wqe_shift) +
1768                                      qp->send_wqe_offset) |
1769                                     mthca_opcode[wr->opcode]);
1770                 wmb();
1771                 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1772                         cpu_to_be32((nreq ? 0 : MTHCA_NEXT_DBD) | size |
1773                                     ((wr->send_flags & IB_SEND_FENCE) ?
1774                                     MTHCA_NEXT_FENCE : 0));
1775
1776                 if (!nreq) {
1777                         size0 = size;
1778                         op0   = mthca_opcode[wr->opcode];
1779                         f0    = wr->send_flags & IB_SEND_FENCE ?
1780                                 MTHCA_SEND_DOORBELL_FENCE : 0;
1781                 }
1782
1783                 ++ind;
1784                 if (unlikely(ind >= qp->sq.max))
1785                         ind -= qp->sq.max;
1786         }
1787
1788 out:
1789         if (likely(nreq)) {
1790                 wmb();
1791
1792                 mthca_write64(((qp->sq.next_ind << qp->sq.wqe_shift) +
1793                                qp->send_wqe_offset) | f0 | op0,
1794                               (qp->qpn << 8) | size0,
1795                               dev->kar + MTHCA_SEND_DOORBELL,
1796                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1797                 /*
1798                  * Make sure doorbells don't leak out of SQ spinlock
1799                  * and reach the HCA out of order:
1800                  */
1801                 mmiowb();
1802         }
1803
1804         qp->sq.next_ind = ind;
1805         qp->sq.head    += nreq;
1806
1807         spin_unlock_irqrestore(&qp->sq.lock, flags);
1808         return err;
1809 }
1810
1811 int mthca_tavor_post_receive(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
1812                              const struct ib_recv_wr **bad_wr)
1813 {
1814         struct mthca_dev *dev = to_mdev(ibqp->device);
1815         struct mthca_qp *qp = to_mqp(ibqp);
1816         unsigned long flags;
1817         int err = 0;
1818         int nreq;
1819         int i;
1820         int size;
1821         /*
1822          * size0 is only used if nreq != 0, and it will always be
1823          * initialized the first time through the main loop before
1824          * nreq is incremented.  So nreq cannot become non-zero
1825          * without initializing size0, and it is in fact never used
1826          * uninitialized.
1827          */
1828         int uninitialized_var(size0);
1829         int ind;
1830         void *wqe;
1831         void *prev_wqe;
1832
1833         spin_lock_irqsave(&qp->rq.lock, flags);
1834
1835         /* XXX check that state is OK to post receive */
1836
1837         ind = qp->rq.next_ind;
1838
1839         for (nreq = 0; wr; wr = wr->next) {
1840                 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
1841                         mthca_err(dev, "RQ %06x full (%u head, %u tail,"
1842                                         " %d max, %d nreq)\n", qp->qpn,
1843                                         qp->rq.head, qp->rq.tail,
1844                                         qp->rq.max, nreq);
1845                         err = -ENOMEM;
1846                         *bad_wr = wr;
1847                         goto out;
1848                 }
1849
1850                 wqe = get_recv_wqe(qp, ind);
1851                 prev_wqe = qp->rq.last;
1852                 qp->rq.last = wqe;
1853
1854                 ((struct mthca_next_seg *) wqe)->ee_nds =
1855                         cpu_to_be32(MTHCA_NEXT_DBD);
1856                 ((struct mthca_next_seg *) wqe)->flags = 0;
1857
1858                 wqe += sizeof (struct mthca_next_seg);
1859                 size = sizeof (struct mthca_next_seg) / 16;
1860
1861                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1862                         err = -EINVAL;
1863                         *bad_wr = wr;
1864                         goto out;
1865                 }
1866
1867                 for (i = 0; i < wr->num_sge; ++i) {
1868                         mthca_set_data_seg(wqe, wr->sg_list + i);
1869                         wqe  += sizeof (struct mthca_data_seg);
1870                         size += sizeof (struct mthca_data_seg) / 16;
1871                 }
1872
1873                 qp->wrid[ind] = wr->wr_id;
1874
1875                 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1876                         cpu_to_be32(MTHCA_NEXT_DBD | size);
1877
1878                 if (!nreq)
1879                         size0 = size;
1880
1881                 ++ind;
1882                 if (unlikely(ind >= qp->rq.max))
1883                         ind -= qp->rq.max;
1884
1885                 ++nreq;
1886                 if (unlikely(nreq == MTHCA_TAVOR_MAX_WQES_PER_RECV_DB)) {
1887                         nreq = 0;
1888
1889                         wmb();
1890
1891                         mthca_write64((qp->rq.next_ind << qp->rq.wqe_shift) | size0,
1892                                       qp->qpn << 8, dev->kar + MTHCA_RECEIVE_DOORBELL,
1893                                       MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1894
1895                         qp->rq.next_ind = ind;
1896                         qp->rq.head += MTHCA_TAVOR_MAX_WQES_PER_RECV_DB;
1897                 }
1898         }
1899
1900 out:
1901         if (likely(nreq)) {
1902                 wmb();
1903
1904                 mthca_write64((qp->rq.next_ind << qp->rq.wqe_shift) | size0,
1905                               qp->qpn << 8 | nreq, dev->kar + MTHCA_RECEIVE_DOORBELL,
1906                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1907         }
1908
1909         qp->rq.next_ind = ind;
1910         qp->rq.head    += nreq;
1911
1912         /*
1913          * Make sure doorbells don't leak out of RQ spinlock and reach
1914          * the HCA out of order:
1915          */
1916         mmiowb();
1917
1918         spin_unlock_irqrestore(&qp->rq.lock, flags);
1919         return err;
1920 }
1921
1922 int mthca_arbel_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
1923                           const struct ib_send_wr **bad_wr)
1924 {
1925         struct mthca_dev *dev = to_mdev(ibqp->device);
1926         struct mthca_qp *qp = to_mqp(ibqp);
1927         u32 dbhi;
1928         void *wqe;
1929         void *prev_wqe;
1930         unsigned long flags;
1931         int err = 0;
1932         int nreq;
1933         int i;
1934         int size;
1935         /*
1936          * f0 and size0 are only used if nreq != 0, and they will
1937          * always be initialized the first time through the main loop
1938          * before nreq is incremented.  So nreq cannot become non-zero
1939          * without initializing f0 and size0, and they are in fact
1940          * never used uninitialized.
1941          */
1942         int uninitialized_var(size0);
1943         u32 uninitialized_var(f0);
1944         int ind;
1945         u8 op0 = 0;
1946
1947         spin_lock_irqsave(&qp->sq.lock, flags);
1948
1949         /* XXX check that state is OK to post send */
1950
1951         ind = qp->sq.head & (qp->sq.max - 1);
1952
1953         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1954                 if (unlikely(nreq == MTHCA_ARBEL_MAX_WQES_PER_SEND_DB)) {
1955                         nreq = 0;
1956
1957                         dbhi = (MTHCA_ARBEL_MAX_WQES_PER_SEND_DB << 24) |
1958                                 ((qp->sq.head & 0xffff) << 8) | f0 | op0;
1959
1960                         qp->sq.head += MTHCA_ARBEL_MAX_WQES_PER_SEND_DB;
1961
1962                         /*
1963                          * Make sure that descriptors are written before
1964                          * doorbell record.
1965                          */
1966                         wmb();
1967                         *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
1968
1969                         /*
1970                          * Make sure doorbell record is written before we
1971                          * write MMIO send doorbell.
1972                          */
1973                         wmb();
1974
1975                         mthca_write64(dbhi, (qp->qpn << 8) | size0,
1976                                       dev->kar + MTHCA_SEND_DOORBELL,
1977                                       MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1978                 }
1979
1980                 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1981                         mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1982                                         " %d max, %d nreq)\n", qp->qpn,
1983                                         qp->sq.head, qp->sq.tail,
1984                                         qp->sq.max, nreq);
1985                         err = -ENOMEM;
1986                         *bad_wr = wr;
1987                         goto out;
1988                 }
1989
1990                 wqe = get_send_wqe(qp, ind);
1991                 prev_wqe = qp->sq.last;
1992                 qp->sq.last = wqe;
1993
1994                 ((struct mthca_next_seg *) wqe)->flags =
1995                         ((wr->send_flags & IB_SEND_SIGNALED) ?
1996                          cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1997                         ((wr->send_flags & IB_SEND_SOLICITED) ?
1998                          cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0)   |
1999                         ((wr->send_flags & IB_SEND_IP_CSUM) ?
2000                          cpu_to_be32(MTHCA_NEXT_IP_CSUM | MTHCA_NEXT_TCP_UDP_CSUM) : 0) |
2001                         cpu_to_be32(1);
2002                 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
2003                     wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
2004                         ((struct mthca_next_seg *) wqe)->imm = wr->ex.imm_data;
2005
2006                 wqe += sizeof (struct mthca_next_seg);
2007                 size = sizeof (struct mthca_next_seg) / 16;
2008
2009                 switch (qp->transport) {
2010                 case RC:
2011                         switch (wr->opcode) {
2012                         case IB_WR_ATOMIC_CMP_AND_SWP:
2013                         case IB_WR_ATOMIC_FETCH_AND_ADD:
2014                                 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
2015                                               atomic_wr(wr)->rkey);
2016                                 wqe += sizeof (struct mthca_raddr_seg);
2017
2018                                 set_atomic_seg(wqe, atomic_wr(wr));
2019                                 wqe  += sizeof (struct mthca_atomic_seg);
2020                                 size += (sizeof (struct mthca_raddr_seg) +
2021                                          sizeof (struct mthca_atomic_seg)) / 16;
2022                                 break;
2023
2024                         case IB_WR_RDMA_READ:
2025                         case IB_WR_RDMA_WRITE:
2026                         case IB_WR_RDMA_WRITE_WITH_IMM:
2027                                 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
2028                                               rdma_wr(wr)->rkey);
2029                                 wqe  += sizeof (struct mthca_raddr_seg);
2030                                 size += sizeof (struct mthca_raddr_seg) / 16;
2031                                 break;
2032
2033                         default:
2034                                 /* No extra segments required for sends */
2035                                 break;
2036                         }
2037
2038                         break;
2039
2040                 case UC:
2041                         switch (wr->opcode) {
2042                         case IB_WR_RDMA_WRITE:
2043                         case IB_WR_RDMA_WRITE_WITH_IMM:
2044                                 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
2045                                               rdma_wr(wr)->rkey);
2046                                 wqe  += sizeof (struct mthca_raddr_seg);
2047                                 size += sizeof (struct mthca_raddr_seg) / 16;
2048                                 break;
2049
2050                         default:
2051                                 /* No extra segments required for sends */
2052                                 break;
2053                         }
2054
2055                         break;
2056
2057                 case UD:
2058                         set_arbel_ud_seg(wqe, ud_wr(wr));
2059                         wqe  += sizeof (struct mthca_arbel_ud_seg);
2060                         size += sizeof (struct mthca_arbel_ud_seg) / 16;
2061                         break;
2062
2063                 case MLX:
2064                         err = build_mlx_header(dev, to_msqp(qp), ind, ud_wr(wr),
2065                                                wqe - sizeof (struct mthca_next_seg),
2066                                                wqe);
2067                         if (err) {
2068                                 *bad_wr = wr;
2069                                 goto out;
2070                         }
2071                         wqe += sizeof (struct mthca_data_seg);
2072                         size += sizeof (struct mthca_data_seg) / 16;
2073                         break;
2074                 }
2075
2076                 if (wr->num_sge > qp->sq.max_gs) {
2077                         mthca_err(dev, "too many gathers\n");
2078                         err = -EINVAL;
2079                         *bad_wr = wr;
2080                         goto out;
2081                 }
2082
2083                 for (i = 0; i < wr->num_sge; ++i) {
2084                         mthca_set_data_seg(wqe, wr->sg_list + i);
2085                         wqe  += sizeof (struct mthca_data_seg);
2086                         size += sizeof (struct mthca_data_seg) / 16;
2087                 }
2088
2089                 /* Add one more inline data segment for ICRC */
2090                 if (qp->transport == MLX) {
2091                         ((struct mthca_data_seg *) wqe)->byte_count =
2092                                 cpu_to_be32((1 << 31) | 4);
2093                         ((u32 *) wqe)[1] = 0;
2094                         wqe += sizeof (struct mthca_data_seg);
2095                         size += sizeof (struct mthca_data_seg) / 16;
2096                 }
2097
2098                 qp->wrid[ind + qp->rq.max] = wr->wr_id;
2099
2100                 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
2101                         mthca_err(dev, "opcode invalid\n");
2102                         err = -EINVAL;
2103                         *bad_wr = wr;
2104                         goto out;
2105                 }
2106
2107                 ((struct mthca_next_seg *) prev_wqe)->nda_op =
2108                         cpu_to_be32(((ind << qp->sq.wqe_shift) +
2109                                      qp->send_wqe_offset) |
2110                                     mthca_opcode[wr->opcode]);
2111                 wmb();
2112                 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
2113                         cpu_to_be32(MTHCA_NEXT_DBD | size |
2114                                     ((wr->send_flags & IB_SEND_FENCE) ?
2115                                      MTHCA_NEXT_FENCE : 0));
2116
2117                 if (!nreq) {
2118                         size0 = size;
2119                         op0   = mthca_opcode[wr->opcode];
2120                         f0    = wr->send_flags & IB_SEND_FENCE ?
2121                                 MTHCA_SEND_DOORBELL_FENCE : 0;
2122                 }
2123
2124                 ++ind;
2125                 if (unlikely(ind >= qp->sq.max))
2126                         ind -= qp->sq.max;
2127         }
2128
2129 out:
2130         if (likely(nreq)) {
2131                 dbhi = (nreq << 24) | ((qp->sq.head & 0xffff) << 8) | f0 | op0;
2132
2133                 qp->sq.head += nreq;
2134
2135                 /*
2136                  * Make sure that descriptors are written before
2137                  * doorbell record.
2138                  */
2139                 wmb();
2140                 *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
2141
2142                 /*
2143                  * Make sure doorbell record is written before we
2144                  * write MMIO send doorbell.
2145                  */
2146                 wmb();
2147
2148                 mthca_write64(dbhi, (qp->qpn << 8) | size0, dev->kar + MTHCA_SEND_DOORBELL,
2149                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
2150         }
2151
2152         /*
2153          * Make sure doorbells don't leak out of SQ spinlock and reach
2154          * the HCA out of order:
2155          */
2156         mmiowb();
2157
2158         spin_unlock_irqrestore(&qp->sq.lock, flags);
2159         return err;
2160 }
2161
2162 int mthca_arbel_post_receive(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
2163                              const struct ib_recv_wr **bad_wr)
2164 {
2165         struct mthca_dev *dev = to_mdev(ibqp->device);
2166         struct mthca_qp *qp = to_mqp(ibqp);
2167         unsigned long flags;
2168         int err = 0;
2169         int nreq;
2170         int ind;
2171         int i;
2172         void *wqe;
2173
2174         spin_lock_irqsave(&qp->rq.lock, flags);
2175
2176         /* XXX check that state is OK to post receive */
2177
2178         ind = qp->rq.head & (qp->rq.max - 1);
2179
2180         for (nreq = 0; wr; ++nreq, wr = wr->next) {
2181                 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
2182                         mthca_err(dev, "RQ %06x full (%u head, %u tail,"
2183                                         " %d max, %d nreq)\n", qp->qpn,
2184                                         qp->rq.head, qp->rq.tail,
2185                                         qp->rq.max, nreq);
2186                         err = -ENOMEM;
2187                         *bad_wr = wr;
2188                         goto out;
2189                 }
2190
2191                 wqe = get_recv_wqe(qp, ind);
2192
2193                 ((struct mthca_next_seg *) wqe)->flags = 0;
2194
2195                 wqe += sizeof (struct mthca_next_seg);
2196
2197                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
2198                         err = -EINVAL;
2199                         *bad_wr = wr;
2200                         goto out;
2201                 }
2202
2203                 for (i = 0; i < wr->num_sge; ++i) {
2204                         mthca_set_data_seg(wqe, wr->sg_list + i);
2205                         wqe += sizeof (struct mthca_data_seg);
2206                 }
2207
2208                 if (i < qp->rq.max_gs)
2209                         mthca_set_data_seg_inval(wqe);
2210
2211                 qp->wrid[ind] = wr->wr_id;
2212
2213                 ++ind;
2214                 if (unlikely(ind >= qp->rq.max))
2215                         ind -= qp->rq.max;
2216         }
2217 out:
2218         if (likely(nreq)) {
2219                 qp->rq.head += nreq;
2220
2221                 /*
2222                  * Make sure that descriptors are written before
2223                  * doorbell record.
2224                  */
2225                 wmb();
2226                 *qp->rq.db = cpu_to_be32(qp->rq.head & 0xffff);
2227         }
2228
2229         spin_unlock_irqrestore(&qp->rq.lock, flags);
2230         return err;
2231 }
2232
2233 void mthca_free_err_wqe(struct mthca_dev *dev, struct mthca_qp *qp, int is_send,
2234                         int index, int *dbd, __be32 *new_wqe)
2235 {
2236         struct mthca_next_seg *next;
2237
2238         /*
2239          * For SRQs, all receive WQEs generate a CQE, so we're always
2240          * at the end of the doorbell chain.
2241          */
2242         if (qp->ibqp.srq && !is_send) {
2243                 *new_wqe = 0;
2244                 return;
2245         }
2246
2247         if (is_send)
2248                 next = get_send_wqe(qp, index);
2249         else
2250                 next = get_recv_wqe(qp, index);
2251
2252         *dbd = !!(next->ee_nds & cpu_to_be32(MTHCA_NEXT_DBD));
2253         if (next->ee_nds & cpu_to_be32(0x3f))
2254                 *new_wqe = (next->nda_op & cpu_to_be32(~0x3f)) |
2255                         (next->ee_nds & cpu_to_be32(0x3f));
2256         else
2257                 *new_wqe = 0;
2258 }
2259
2260 int mthca_init_qp_table(struct mthca_dev *dev)
2261 {
2262         int err;
2263         int i;
2264
2265         spin_lock_init(&dev->qp_table.lock);
2266
2267         /*
2268          * We reserve 2 extra QPs per port for the special QPs.  The
2269          * special QP for port 1 has to be even, so round up.
2270          */
2271         dev->qp_table.sqp_start = (dev->limits.reserved_qps + 1) & ~1UL;
2272         err = mthca_alloc_init(&dev->qp_table.alloc,
2273                                dev->limits.num_qps,
2274                                (1 << 24) - 1,
2275                                dev->qp_table.sqp_start +
2276                                MTHCA_MAX_PORTS * 2);
2277         if (err)
2278                 return err;
2279
2280         err = mthca_array_init(&dev->qp_table.qp,
2281                                dev->limits.num_qps);
2282         if (err) {
2283                 mthca_alloc_cleanup(&dev->qp_table.alloc);
2284                 return err;
2285         }
2286
2287         for (i = 0; i < 2; ++i) {
2288                 err = mthca_CONF_SPECIAL_QP(dev, i ? IB_QPT_GSI : IB_QPT_SMI,
2289                                     dev->qp_table.sqp_start + i * 2);
2290                 if (err) {
2291                         mthca_warn(dev, "CONF_SPECIAL_QP returned "
2292                                    "%d, aborting.\n", err);
2293                         goto err_out;
2294                 }
2295         }
2296         return 0;
2297
2298  err_out:
2299         for (i = 0; i < 2; ++i)
2300                 mthca_CONF_SPECIAL_QP(dev, i, 0);
2301
2302         mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2303         mthca_alloc_cleanup(&dev->qp_table.alloc);
2304
2305         return err;
2306 }
2307
2308 void mthca_cleanup_qp_table(struct mthca_dev *dev)
2309 {
2310         int i;
2311
2312         for (i = 0; i < 2; ++i)
2313                 mthca_CONF_SPECIAL_QP(dev, i, 0);
2314
2315         mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2316         mthca_alloc_cleanup(&dev->qp_table.alloc);
2317 }