2 * Copyright (c) 2010 Alexander Motin <mav@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/module.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
35 #include <sys/endian.h>
36 #include <sys/malloc.h>
38 #include <sys/mutex.h>
40 #include <machine/stdarg.h>
41 #include <machine/resource.h>
42 #include <machine/bus.h>
44 #include <dev/pci/pcivar.h>
45 #include <dev/pci/pcireg.h>
48 /* local prototypes */
49 static int mvs_setup_interrupt(device_t dev);
50 static void mvs_intr(void *data);
51 static int mvs_suspend(device_t dev);
52 static int mvs_resume(device_t dev);
53 static int mvs_ctlr_setup(device_t dev);
62 {0x504011ab, 0x00, "Marvell 88SX5040", 4, MVS_Q_GENI},
63 {0x504111ab, 0x00, "Marvell 88SX5041", 4, MVS_Q_GENI},
64 {0x508011ab, 0x00, "Marvell 88SX5080", 8, MVS_Q_GENI},
65 {0x508111ab, 0x00, "Marvell 88SX5081", 8, MVS_Q_GENI},
66 {0x604011ab, 0x00, "Marvell 88SX6040", 4, MVS_Q_GENII},
67 {0x604111ab, 0x00, "Marvell 88SX6041", 4, MVS_Q_GENII},
68 {0x604211ab, 0x00, "Marvell 88SX6042", 4, MVS_Q_GENIIE},
69 {0x608011ab, 0x00, "Marvell 88SX6080", 8, MVS_Q_GENII},
70 {0x608111ab, 0x00, "Marvell 88SX6081", 8, MVS_Q_GENII},
71 {0x704211ab, 0x00, "Marvell 88SX7042", 4, MVS_Q_GENIIE|MVS_Q_CT},
72 {0x02419005, 0x00, "Adaptec 1420SA", 4, MVS_Q_GENII},
73 {0x02439005, 0x00, "Adaptec 1430SA", 4, MVS_Q_GENIIE|MVS_Q_CT},
74 {0x00000000, 0x00, NULL, 0, 0}
78 mvs_probe(device_t dev)
82 uint32_t devid = pci_get_devid(dev);
83 uint8_t revid = pci_get_revid(dev);
85 for (i = 0; mvs_ids[i].id != 0; i++) {
86 if (mvs_ids[i].id == devid &&
87 mvs_ids[i].rev <= revid) {
88 snprintf(buf, sizeof(buf), "%s SATA controller",
90 device_set_desc_copy(dev, buf);
91 return (BUS_PROBE_VENDOR);
98 mvs_attach(device_t dev)
100 struct mvs_controller *ctlr = device_get_softc(dev);
103 uint32_t devid = pci_get_devid(dev);
104 uint8_t revid = pci_get_revid(dev);
108 while (mvs_ids[i].id != 0 &&
109 (mvs_ids[i].id != devid ||
110 mvs_ids[i].rev > revid))
112 ctlr->channels = mvs_ids[i].ports;
113 ctlr->quirks = mvs_ids[i].quirks;
115 resource_int_value(device_get_name(dev),
116 device_get_unit(dev), "ccc", &ctlr->ccc);
118 resource_int_value(device_get_name(dev),
119 device_get_unit(dev), "cccc", &ctlr->cccc);
120 if (ctlr->ccc == 0 || ctlr->cccc == 0) {
124 if (ctlr->ccc > 100000)
127 "Gen-%s, %d %sGbps ports, Port Multiplier %s%s\n",
128 ((ctlr->quirks & MVS_Q_GENI) ? "I" :
129 ((ctlr->quirks & MVS_Q_GENII) ? "II" : "IIe")),
131 ((ctlr->quirks & MVS_Q_GENI) ? "1.5" : "3"),
132 ((ctlr->quirks & MVS_Q_GENI) ?
133 "not supported" : "supported"),
134 ((ctlr->quirks & MVS_Q_GENIIE) ?
136 mtx_init(&ctlr->mtx, "MVS controller lock", NULL, MTX_DEF);
137 /* We should have a memory BAR(0). */
138 ctlr->r_rid = PCIR_BAR(0);
139 if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
140 &ctlr->r_rid, RF_ACTIVE)))
142 /* Setup our own memory management for channels. */
143 ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem);
144 ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem);
145 ctlr->sc_iomem.rm_type = RMAN_ARRAY;
146 ctlr->sc_iomem.rm_descr = "I/O memory addresses";
147 if ((error = rman_init(&ctlr->sc_iomem)) != 0) {
148 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
151 if ((error = rman_manage_region(&ctlr->sc_iomem,
152 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) {
153 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
154 rman_fini(&ctlr->sc_iomem);
157 pci_enable_busmaster(dev);
159 /* Setup interrupts. */
160 if (mvs_setup_interrupt(dev)) {
161 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
162 rman_fini(&ctlr->sc_iomem);
165 /* Attach all channels on this controller */
166 for (unit = 0; unit < ctlr->channels; unit++) {
167 child = device_add_child(dev, "mvsch", -1);
169 device_printf(dev, "failed to add channel device\n");
171 device_set_ivars(child, (void *)(intptr_t)unit);
173 bus_generic_attach(dev);
178 mvs_detach(device_t dev)
180 struct mvs_controller *ctlr = device_get_softc(dev);
182 /* Detach & delete all children */
183 device_delete_children(dev);
185 /* Free interrupt. */
186 if (ctlr->irq.r_irq) {
187 bus_teardown_intr(dev, ctlr->irq.r_irq,
189 bus_release_resource(dev, SYS_RES_IRQ,
190 ctlr->irq.r_irq_rid, ctlr->irq.r_irq);
192 pci_release_msi(dev);
194 rman_fini(&ctlr->sc_iomem);
196 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
197 mtx_destroy(&ctlr->mtx);
202 mvs_ctlr_setup(device_t dev)
204 struct mvs_controller *ctlr = device_get_softc(dev);
205 int i, ccc = ctlr->ccc, cccc = ctlr->cccc, ccim = 0;
207 /* Mask chip interrupts */
208 ATA_OUTL(ctlr->r_mem, CHIP_MIM, 0x00000000);
209 /* Mask PCI interrupts */
210 ATA_OUTL(ctlr->r_mem, CHIP_PCIIM, 0x00000000);
211 /* Clear PCI interrupts */
212 ATA_OUTL(ctlr->r_mem, CHIP_PCIIC, 0x00000000);
213 if (ccc && bootverbose) {
215 "CCC with %dus/%dcmd enabled\n",
216 ctlr->ccc, ctlr->cccc);
219 /* Configure chip-global CCC */
220 if (ctlr->channels > 4 && (ctlr->quirks & MVS_Q_GENI) == 0) {
221 ATA_OUTL(ctlr->r_mem, CHIP_ICT, cccc);
222 ATA_OUTL(ctlr->r_mem, CHIP_ITT, ccc);
223 ATA_OUTL(ctlr->r_mem, CHIP_ICC, ~CHIP_ICC_ALL_PORTS);
225 ccim |= IC_ALL_PORTS_COAL_DONE;
229 for (i = 0; i < ctlr->channels / 4; i++) {
230 /* Configure per-HC CCC */
231 ATA_OUTL(ctlr->r_mem, HC_BASE(i) + HC_ICT, cccc);
232 ATA_OUTL(ctlr->r_mem, HC_BASE(i) + HC_ITT, ccc);
234 ccim |= (IC_HC0_COAL_DONE << (i * IC_HC_SHIFT));
235 /* Clear HC interrupts */
236 ATA_OUTL(ctlr->r_mem, HC_BASE(i) + HC_IC, 0x00000000);
238 /* Enable chip interrupts */
239 ctlr->gmim = (ccim ? ccim : (IC_DONE_HC0 | IC_DONE_HC1)) |
240 IC_ERR_HC0 | IC_ERR_HC1;
241 ctlr->mim = ctlr->gmim | ctlr->pmim;
242 ATA_OUTL(ctlr->r_mem, CHIP_MIM, ctlr->mim);
243 /* Enable PCI interrupts */
244 ATA_OUTL(ctlr->r_mem, CHIP_PCIIM, 0x007fffff);
249 mvs_edma(device_t dev, device_t child, int mode)
251 struct mvs_controller *ctlr = device_get_softc(dev);
252 int unit = ((struct mvs_channel *)device_get_softc(child))->unit;
253 int bit = IC_DONE_IRQ << (unit * 2 + unit / 4) ;
257 /* CCC is not working for non-EDMA mode. Unmask device interrupts. */
258 mtx_lock(&ctlr->mtx);
259 if (mode == MVS_EDMA_OFF)
263 ctlr->mim = ctlr->gmim | ctlr->pmim;
265 ATA_OUTL(ctlr->r_mem, CHIP_MIM, ctlr->mim);
266 mtx_unlock(&ctlr->mtx);
270 mvs_suspend(device_t dev)
272 struct mvs_controller *ctlr = device_get_softc(dev);
274 bus_generic_suspend(dev);
275 /* Mask chip interrupts */
276 ATA_OUTL(ctlr->r_mem, CHIP_MIM, 0x00000000);
277 /* Mask PCI interrupts */
278 ATA_OUTL(ctlr->r_mem, CHIP_PCIIM, 0x00000000);
283 mvs_resume(device_t dev)
287 return (bus_generic_resume(dev));
291 mvs_setup_interrupt(device_t dev)
293 struct mvs_controller *ctlr = device_get_softc(dev);
297 resource_int_value(device_get_name(dev),
298 device_get_unit(dev), "msi", &msi);
302 msi = min(1, pci_msi_count(dev));
303 /* Allocate MSI if needed/present. */
304 if (msi && pci_alloc_msi(dev, &msi) != 0)
307 /* Allocate all IRQs. */
308 ctlr->irq.r_irq_rid = msi ? 1 : 0;
309 if (!(ctlr->irq.r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
310 &ctlr->irq.r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) {
311 device_printf(dev, "unable to map interrupt\n");
314 if ((bus_setup_intr(dev, ctlr->irq.r_irq, ATA_INTR_FLAGS, NULL,
315 mvs_intr, ctlr, &ctlr->irq.handle))) {
316 device_printf(dev, "unable to setup interrupt\n");
317 bus_release_resource(dev, SYS_RES_IRQ,
318 ctlr->irq.r_irq_rid, ctlr->irq.r_irq);
326 * Common case interrupt handler.
331 struct mvs_controller *ctlr = data;
332 struct mvs_intr_arg arg;
333 void (*function)(void *);
337 ic = ATA_INL(ctlr->r_mem, CHIP_MIC);
339 /* We have to to mask MSI during processing. */
340 mtx_lock(&ctlr->mtx);
341 ATA_OUTL(ctlr->r_mem, CHIP_MIM, 0);
342 ctlr->msia = 1; /* Deny MIM update during processing. */
343 mtx_unlock(&ctlr->mtx);
346 /* Acknowledge all-ports CCC interrupt. */
347 if (ic & IC_ALL_PORTS_COAL_DONE)
348 ATA_OUTL(ctlr->r_mem, CHIP_ICC, ~CHIP_ICC_ALL_PORTS);
349 for (p = 0; p < ctlr->channels; p++) {
353 if ((ic & IC_HC0) == 0) {
358 /* Acknowledge interrupts of this HC. */
360 if (ic & (IC_DONE_IRQ << 0))
361 aic |= HC_IC_DONE(0) | HC_IC_DEV(0);
362 if (ic & (IC_DONE_IRQ << 2))
363 aic |= HC_IC_DONE(1) | HC_IC_DEV(1);
364 if (ic & (IC_DONE_IRQ << 4))
365 aic |= HC_IC_DONE(2) | HC_IC_DEV(2);
366 if (ic & (IC_DONE_IRQ << 6))
367 aic |= HC_IC_DONE(3) | HC_IC_DEV(3);
368 if (ic & IC_HC0_COAL_DONE)
370 ATA_OUTL(ctlr->r_mem, HC_BASE(p == 4) + HC_IC, ~aic);
372 /* Call per-port interrupt handler. */
373 arg.cause = ic & (IC_ERR_IRQ|IC_DONE_IRQ);
374 if ((arg.cause != 0) &&
375 (function = ctlr->interrupt[p].function)) {
376 arg.arg = ctlr->interrupt[p].argument;
382 /* Unmasking MSI triggers next interrupt, if needed. */
383 mtx_lock(&ctlr->mtx);
384 ctlr->msia = 0; /* Allow MIM update. */
385 ATA_OUTL(ctlr->r_mem, CHIP_MIM, ctlr->mim);
386 mtx_unlock(&ctlr->mtx);
390 static struct resource *
391 mvs_alloc_resource(device_t dev, device_t child, int type, int *rid,
392 u_long start, u_long end, u_long count, u_int flags)
394 struct mvs_controller *ctlr = device_get_softc(dev);
395 int unit = ((struct mvs_channel *)device_get_softc(child))->unit;
396 struct resource *res = NULL;
397 int offset = HC_BASE(unit >> 2) + PORT_BASE(unit & 0x03);
402 st = rman_get_start(ctlr->r_mem);
403 res = rman_reserve_resource(&ctlr->sc_iomem, st + offset,
404 st + offset + PORT_SIZE - 1, PORT_SIZE, RF_ACTIVE, child);
406 bus_space_handle_t bsh;
408 bsh = rman_get_bushandle(ctlr->r_mem);
409 bst = rman_get_bustag(ctlr->r_mem);
410 bus_space_subregion(bst, bsh, offset, PORT_SIZE, &bsh);
411 rman_set_bushandle(res, bsh);
412 rman_set_bustag(res, bst);
416 if (*rid == ATA_IRQ_RID)
417 res = ctlr->irq.r_irq;
424 mvs_release_resource(device_t dev, device_t child, int type, int rid,
430 rman_release_resource(r);
433 if (rid != ATA_IRQ_RID)
441 mvs_setup_intr(device_t dev, device_t child, struct resource *irq,
442 int flags, driver_filter_t *filter, driver_intr_t *function,
443 void *argument, void **cookiep)
445 struct mvs_controller *ctlr = device_get_softc(dev);
446 int unit = (intptr_t)device_get_ivars(child);
448 if (filter != NULL) {
449 printf("mvs.c: we cannot use a filter here\n");
452 ctlr->interrupt[unit].function = function;
453 ctlr->interrupt[unit].argument = argument;
458 mvs_teardown_intr(device_t dev, device_t child, struct resource *irq,
461 struct mvs_controller *ctlr = device_get_softc(dev);
462 int unit = (intptr_t)device_get_ivars(child);
464 ctlr->interrupt[unit].function = NULL;
465 ctlr->interrupt[unit].argument = NULL;
470 mvs_print_child(device_t dev, device_t child)
474 retval = bus_print_child_header(dev, child);
475 retval += printf(" at channel %d",
476 (int)(intptr_t)device_get_ivars(child));
477 retval += bus_print_child_footer(dev, child);
483 mvs_child_location_str(device_t dev, device_t child, char *buf,
487 snprintf(buf, buflen, "channel=%d",
488 (int)(intptr_t)device_get_ivars(child));
493 mvs_get_dma_tag(device_t bus, device_t child)
496 return (bus_get_dma_tag(bus));
499 static device_method_t mvs_methods[] = {
500 DEVMETHOD(device_probe, mvs_probe),
501 DEVMETHOD(device_attach, mvs_attach),
502 DEVMETHOD(device_detach, mvs_detach),
503 DEVMETHOD(device_suspend, mvs_suspend),
504 DEVMETHOD(device_resume, mvs_resume),
505 DEVMETHOD(bus_print_child, mvs_print_child),
506 DEVMETHOD(bus_alloc_resource, mvs_alloc_resource),
507 DEVMETHOD(bus_release_resource, mvs_release_resource),
508 DEVMETHOD(bus_setup_intr, mvs_setup_intr),
509 DEVMETHOD(bus_teardown_intr,mvs_teardown_intr),
510 DEVMETHOD(bus_child_location_str, mvs_child_location_str),
511 DEVMETHOD(bus_get_dma_tag, mvs_get_dma_tag),
512 DEVMETHOD(mvs_edma, mvs_edma),
515 static driver_t mvs_driver = {
518 sizeof(struct mvs_controller)
520 DRIVER_MODULE(mvs, pci, mvs_driver, mvs_devclass, 0, 0);
521 MODULE_VERSION(mvs, 1);
522 MODULE_DEPEND(mvs, cam, 1, 1, 1);