2 * Copyright (c) 2007-2009 Sam Leffler, Errno Consulting
3 * Copyright (c) 2007-2009 Marvell Semiconductor, Inc.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer,
11 * without modification.
12 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
13 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
14 * redistribution must be conditioned upon including a substantially
15 * similar Disclaimer requirement for further binary redistribution.
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
21 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
22 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
23 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
26 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
28 * THE POSSIBILITY OF SUCH DAMAGES.
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/sysctl.h>
36 #include <sys/malloc.h>
38 #include <sys/mutex.h>
39 #include <sys/kernel.h>
40 #include <sys/errno.h>
42 #include <sys/endian.h>
44 #include <sys/linker.h>
45 #include <sys/firmware.h>
47 #include <machine/bus.h>
49 #include <dev/mwl/mwlhal.h>
50 #include <dev/mwl/mwlreg.h>
52 #include <sys/socket.h>
53 #include <sys/sockio.h>
55 #include <dev/mwl/mwldiag.h>
57 #define MWLHAL_DEBUG /* debug msgs */
60 WL_ANTENNAMODE_RX = 0xffff,
61 WL_ANTENNAMODE_TX = 2,
65 WL_TX_POWERLEVEL_LOW = 5,
66 WL_TX_POWERLEVEL_MEDIUM = 10,
67 WL_TX_POWERLEVEL_HIGH = 15,
70 #define MWL_CMDBUF_SIZE 0x4000 /* size of f/w command buffer */
71 #define MWL_BASTREAMS_MAX 7 /* max BA streams (NB: fw >3.3.5.9) */
72 #define MWL_BAQID_MAX 8 /* max BA Q id's (NB: fw >3.3.5.9) */
73 #define MWL_MBSS_AP_MAX 8 /* max ap vap's */
74 #define MWL_MBSS_STA_MAX 24 /* max station/client vap's */
75 #define MWL_MBSS_MAX (MWL_MBSS_AP_MAX+MWL_MBSS_STA_MAX)
78 * BA stream -> queue ID mapping
80 * The first 2 streams map to h/w; the remaining streams are
81 * implemented in firmware.
83 static const int ba2qid[MWL_BASTREAMS_MAX] = {
84 5, 6 /* h/w supported */
85 #if MWL_BASTREAMS_MAX == 7
86 , 7, 0, 1, 2, 3 /* f/w supported */
89 static int qid2ba[MWL_BAQID_MAX];
91 #define IEEE80211_ADDR_LEN 6 /* XXX */
92 #define IEEE80211_ADDR_COPY(_dst, _src) \
93 memcpy(_dst, _src, IEEE80211_ADDR_LEN)
94 #define IEEE80211_ADDR_EQ(_dst, _src) \
95 (memcmp(_dst, _src, IEEE80211_ADDR_LEN) == 0)
97 #define _CMD_SETUP(pCmd, type, cmd) do { \
98 pCmd = (type *)&mh->mh_cmdbuf[0]; \
99 memset(pCmd, 0, sizeof(type)); \
100 pCmd->CmdHdr.Cmd = htole16(cmd); \
101 pCmd->CmdHdr.Length = htole16(sizeof(type)); \
104 #define _VCMD_SETUP(vap, pCmd, type, cmd) do { \
105 _CMD_SETUP(pCmd, type, cmd); \
106 pCmd->CmdHdr.MacId = vap->macid; \
109 #define PWTAGETRATETABLE20M 14*4
110 #define PWTAGETRATETABLE40M 9*4
111 #define PWTAGETRATETABLE20M_5G 35*4
112 #define PWTAGETRATETABLE40M_5G 16*4
114 struct mwl_hal_bastream {
115 MWL_HAL_BASTREAM public; /* public state */
116 uint8_t stream; /* stream # */
117 uint8_t setup; /* f/w cmd sent */
118 uint8_t ba_policy; /* direct/delayed BA policy */
121 uint8_t macaddr[IEEE80211_ADDR_LEN];
127 struct mwl_hal_priv *mh; /* back pointer */
128 uint16_t bss_type; /* f/w type */
129 uint8_t vap_type; /* MWL_HAL_BSSTYPE */
130 uint8_t macid; /* for passing to f/w */
132 #define MVF_RUNNING 0x01 /* BSS_START issued */
133 #define MVF_STATION 0x02 /* sta db entry created */
134 uint8_t mac[IEEE80211_ADDR_LEN];/* mac address */
136 #define MWLVAP(_vap) ((_vap)->mh)
139 * Per-device state. We allocate a single cmd buffer for
140 * submitting operations to the firmware. Access to this
141 * buffer (and the f/w) are single-threaded. At present
142 * we spin waiting for cmds to complete which is bad. Not
143 * sure if it's possible to submit multiple requests or
144 * control when we get cmd done interrupts. There's no
145 * documentation and no example code to indicate what can
146 * or cannot be done so all we can do right now is follow the
147 * linux driver logic. This falls apart when the f/w fails;
148 * the system comes to a crawl as we spin waiting for operations
151 struct mwl_hal_priv {
152 struct mwl_hal public; /* public area */
156 bus_dma_tag_t mh_dmat; /* bus DMA tag for cmd buffer */
157 bus_dma_segment_t mh_seg; /* segment for cmd buffer */
158 bus_dmamap_t mh_dmamap; /* DMA map for cmd buffer */
159 uint16_t *mh_cmdbuf; /* f/w cmd buffer */
160 bus_addr_t mh_cmdaddr; /* physaddr of cmd buffer */
162 #define MHF_CALDATA 0x0001 /* cal data retrieved */
163 #define MHF_FWHANG 0x0002 /* fw appears hung */
164 #define MHF_MBSS 0x0004 /* mbss enabled */
165 struct mwl_hal_vap mh_vaps[MWL_MBSS_MAX+1];
166 int mh_bastreams; /* bit mask of available BA streams */
167 int mh_regioncode; /* XXX last region code sent to fw */
168 struct mwl_hal_bastream mh_streams[MWL_BASTREAMS_MAX];
170 MWL_HAL_CHANNELINFO mh_20M;
171 MWL_HAL_CHANNELINFO mh_40M;
172 MWL_HAL_CHANNELINFO mh_20M_5G;
173 MWL_HAL_CHANNELINFO mh_40M_5G;
174 int mh_SDRAMSIZE_Addr;
175 uint32_t mh_RTSSuccesses;/* cumulative stats for read-on-clear */
176 uint32_t mh_RTSFailures;
177 uint32_t mh_RxDuplicateFrames;
178 uint32_t mh_FCSErrorCount;
179 MWL_DIAG_REVS mh_revs;
181 #define MWLPRIV(_mh) ((struct mwl_hal_priv *)(_mh))
183 static int mwl_hal_setmac_locked(struct mwl_hal_vap *,
184 const uint8_t addr[IEEE80211_ADDR_LEN]);
185 static int mwlExecuteCmd(struct mwl_hal_priv *, unsigned short cmd);
186 static int mwlGetPwrCalTable(struct mwl_hal_priv *);
188 static const char *mwlcmdname(int cmd);
189 static void dumpresult(struct mwl_hal_priv *, int showresult);
190 #endif /* MWLHAL_DEBUG */
192 SYSCTL_DECL(_hw_mwl);
193 static SYSCTL_NODE(_hw_mwl, OID_AUTO, hal, CTLFLAG_RD, 0,
194 "Marvell HAL parameters");
197 MWL_HAL_LOCK(struct mwl_hal_priv *mh)
199 mtx_lock(&mh->mh_mtx);
203 MWL_HAL_LOCK_ASSERT(struct mwl_hal_priv *mh)
205 mtx_assert(&mh->mh_mtx, MA_OWNED);
209 MWL_HAL_UNLOCK(struct mwl_hal_priv *mh)
211 mtx_unlock(&mh->mh_mtx);
214 static __inline uint32_t
215 RD4(struct mwl_hal_priv *mh, bus_size_t off)
217 return bus_space_read_4(mh->public.mh_iot, mh->public.mh_ioh, off);
221 WR4(struct mwl_hal_priv *mh, bus_size_t off, uint32_t val)
223 bus_space_write_4(mh->public.mh_iot, mh->public.mh_ioh, off, val);
227 mwl_hal_load_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
229 bus_addr_t *paddr = (bus_addr_t*) arg;
230 KASSERT(error == 0, ("error %u on bus_dma callback", error));
231 *paddr = segs->ds_addr;
235 * Setup for communication with the device. We allocate
236 * a command buffer and map it for bus dma use. The pci
237 * device id is used to identify whether the device has
238 * SRAM on it (in which case f/w download must include a
239 * memory controller reset). All bus i/o operations happen
240 * in BAR 1; the driver passes in the tag and handle we need.
243 mwl_hal_attach(device_t dev, uint16_t devid,
244 bus_space_handle_t ioh, bus_space_tag_t iot, bus_dma_tag_t tag)
246 struct mwl_hal_priv *mh;
247 struct mwl_hal_vap *hvap;
250 mh = malloc(sizeof(struct mwl_hal_priv), M_DEVBUF, M_NOWAIT | M_ZERO);
254 mh->public.mh_ioh = ioh;
255 mh->public.mh_iot = iot;
256 for (i = 0; i < MWL_BASTREAMS_MAX; i++) {
257 mh->mh_streams[i].public.txq = ba2qid[i];
258 mh->mh_streams[i].stream = i;
259 /* construct back-mapping while we're at it */
260 if (mh->mh_streams[i].public.txq < MWL_BAQID_MAX)
261 qid2ba[mh->mh_streams[i].public.txq] = i;
263 device_printf(dev, "unexpected BA tx qid %d for "
264 "stream %d\n", mh->mh_streams[i].public.txq, i);
266 /* setup constant portion of vap state */
267 /* XXX should get max ap/client vap's from f/w */
269 hvap = &mh->mh_vaps[i];
270 hvap->vap_type = MWL_HAL_AP;
271 hvap->bss_type = htole16(WL_MAC_TYPE_PRIMARY_AP);
273 for (i++; i < MWL_MBSS_AP_MAX; i++) {
274 hvap = &mh->mh_vaps[i];
275 hvap->vap_type = MWL_HAL_AP;
276 hvap->bss_type = htole16(WL_MAC_TYPE_SECONDARY_AP);
279 hvap = &mh->mh_vaps[i];
280 hvap->vap_type = MWL_HAL_STA;
281 hvap->bss_type = htole16(WL_MAC_TYPE_PRIMARY_CLIENT);
283 for (i++; i < MWL_MBSS_MAX; i++) {
284 hvap = &mh->mh_vaps[i];
285 hvap->vap_type = MWL_HAL_STA;
286 hvap->bss_type = htole16(WL_MAC_TYPE_SECONDARY_CLIENT);
289 mh->mh_revs.mh_devid = devid;
290 snprintf(mh->mh_mtxname, sizeof(mh->mh_mtxname),
291 "%s_hal", device_get_nameunit(dev));
292 mtx_init(&mh->mh_mtx, mh->mh_mtxname, NULL, MTX_DEF);
295 * Allocate the command buffer and map into the address
296 * space of the h/w. We request "coherent" memory which
297 * will be uncached on some architectures.
299 error = bus_dma_tag_create(tag, /* parent */
300 PAGE_SIZE, 0, /* alignment, bounds */
301 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
302 BUS_SPACE_MAXADDR, /* highaddr */
303 NULL, NULL, /* filter, filterarg */
304 MWL_CMDBUF_SIZE, /* maxsize */
306 MWL_CMDBUF_SIZE, /* maxsegsize */
307 BUS_DMA_ALLOCNOW, /* flags */
312 device_printf(dev, "unable to allocate memory for cmd buffer, "
313 "error %u\n", error);
317 /* allocate descriptors */
318 error = bus_dmamap_create(mh->mh_dmat, BUS_DMA_NOWAIT, &mh->mh_dmamap);
320 device_printf(dev, "unable to create dmamap for cmd buffers, "
321 "error %u\n", error);
325 error = bus_dmamem_alloc(mh->mh_dmat, (void**) &mh->mh_cmdbuf,
326 BUS_DMA_NOWAIT | BUS_DMA_COHERENT,
329 device_printf(dev, "unable to allocate memory for cmd buffer, "
330 "error %u\n", error);
334 error = bus_dmamap_load(mh->mh_dmat, mh->mh_dmamap,
335 mh->mh_cmdbuf, MWL_CMDBUF_SIZE,
336 mwl_hal_load_cb, &mh->mh_cmdaddr,
339 device_printf(dev, "unable to load cmd buffer, error %u\n",
345 * Some cards have SDRAM. When loading firmware we need
346 * to reset the SDRAM controller prior to doing this.
347 * When the SDRAMSIZE is non-zero we do that work in
351 case 0x2a02: /* CB82 */
352 case 0x2a03: /* CB85 */
353 case 0x2a08: /* MC85_B1 */
354 case 0x2a0b: /* CB85AP */
356 mh->mh_SDRAMSIZE_Addr = 0x40fe70b7; /* 8M SDRAM */
358 case 0x2a04: /* MC85 */
359 mh->mh_SDRAMSIZE_Addr = 0x40fc70b7; /* 16M SDRAM */
366 bus_dmamem_free(mh->mh_dmat, mh->mh_cmdbuf, mh->mh_dmamap);
368 bus_dmamap_destroy(mh->mh_dmat, mh->mh_dmamap);
370 bus_dma_tag_destroy(mh->mh_dmat);
371 mtx_destroy(&mh->mh_mtx);
377 mwl_hal_detach(struct mwl_hal *mh0)
379 struct mwl_hal_priv *mh = MWLPRIV(mh0);
381 bus_dmamem_free(mh->mh_dmat, mh->mh_cmdbuf, mh->mh_dmamap);
382 bus_dmamap_destroy(mh->mh_dmat, mh->mh_dmamap);
383 bus_dma_tag_destroy(mh->mh_dmat);
384 mtx_destroy(&mh->mh_mtx);
389 * Reset internal state after a firmware download.
392 mwlResetHalState(struct mwl_hal_priv *mh)
396 /* XXX get from f/w */
397 mh->mh_bastreams = (1<<MWL_BASTREAMS_MAX)-1;
398 for (i = 0; i < MWL_MBSS_MAX; i++)
399 mh->mh_vaps[i].mh = NULL;
401 * Clear cumulative stats.
403 mh->mh_RTSSuccesses = 0;
404 mh->mh_RTSFailures = 0;
405 mh->mh_RxDuplicateFrames = 0;
406 mh->mh_FCSErrorCount = 0;
408 * Fetch cal data for later use.
409 * XXX may want to fetch other stuff too.
411 /* XXX check return */
412 if ((mh->mh_flags & MHF_CALDATA) == 0)
413 mwlGetPwrCalTable(mh);
418 mwl_hal_newvap(struct mwl_hal *mh0, MWL_HAL_BSSTYPE type,
419 const uint8_t mac[IEEE80211_ADDR_LEN])
421 struct mwl_hal_priv *mh = MWLPRIV(mh0);
422 struct mwl_hal_vap *vap;
426 /* NB: could optimize but not worth it w/ max 32 bss */
427 for (i = 0; i < MWL_MBSS_MAX; i++) {
428 vap = &mh->mh_vaps[i];
429 if (vap->vap_type == type && vap->mh == NULL) {
431 mwl_hal_setmac_locked(vap, mac);
436 return (i < MWL_MBSS_MAX) ? vap : NULL;
440 mwl_hal_delvap(struct mwl_hal_vap *vap)
442 /* NB: locking not needed for single write */
447 * Manipulate the debug mask. Note debug
448 * msgs are only provided when this code is
449 * compiled with MWLHAL_DEBUG defined.
453 mwl_hal_setdebug(struct mwl_hal *mh, int debug)
455 MWLPRIV(mh)->mh_debug = debug;
459 mwl_hal_getdebug(struct mwl_hal *mh)
461 return MWLPRIV(mh)->mh_debug;
465 mwl_hal_setbastreams(struct mwl_hal *mh, int mask)
467 MWLPRIV(mh)->mh_bastreams = mask & ((1<<MWL_BASTREAMS_MAX)-1);
471 mwl_hal_getbastreams(struct mwl_hal *mh)
473 return MWLPRIV(mh)->mh_bastreams;
477 mwl_hal_ismbsscapable(struct mwl_hal *mh)
479 return (MWLPRIV(mh)->mh_flags & MHF_MBSS) != 0;
485 * Return the current ISR setting and clear the cause.
486 * XXX maybe make inline
489 mwl_hal_getisr(struct mwl_hal *mh0, uint32_t *status)
491 struct mwl_hal_priv *mh = MWLPRIV(mh0);
494 cause = RD4(mh, MACREG_REG_A2H_INTERRUPT_CAUSE);
495 if (cause == 0xffffffff) { /* card removed */
496 device_printf(mh->mh_dev, "%s: cause 0x%x\n", __func__, cause);
498 } else if (cause != 0) {
499 /* clear cause bits */
500 WR4(mh, MACREG_REG_A2H_INTERRUPT_CAUSE,
501 cause &~ mh->public.mh_imask);
502 RD4(mh, MACREG_REG_INT_CODE); /* XXX flush write? */
509 * Set the interrupt mask.
512 mwl_hal_intrset(struct mwl_hal *mh0, uint32_t mask)
514 struct mwl_hal_priv *mh = MWLPRIV(mh0);
516 WR4(mh, MACREG_REG_A2H_INTERRUPT_MASK, 0);
517 RD4(mh, MACREG_REG_INT_CODE);
519 mh->public.mh_imask = mask;
520 WR4(mh, MACREG_REG_A2H_INTERRUPT_MASK, mask);
521 RD4(mh, MACREG_REG_INT_CODE);
527 * Kick the firmware to tell it there are new tx descriptors
528 * for processing. The driver says what h/w q has work in
529 * case the f/w ever gets smarter.
532 mwl_hal_txstart(struct mwl_hal *mh0, int qnum)
534 struct mwl_hal_priv *mh = MWLPRIV(mh0);
537 WR4(mh, MACREG_REG_H2A_INTERRUPT_EVENTS, MACREG_H2ARIC_BIT_PPA_READY);
538 dummy = RD4(mh, MACREG_REG_INT_CODE);
543 * Callback from the driver on a cmd done interrupt.
544 * Nothing to do right now as we spin waiting for
548 mwl_hal_cmddone(struct mwl_hal *mh0)
551 struct mwl_hal_priv *mh = MWLPRIV(mh0);
553 if (mh->mh_debug & MWL_HAL_DEBUG_CMDDONE) {
554 device_printf(mh->mh_dev, "cmd done interrupt:\n");
561 * Return "hw specs". Note this must be the first
562 * cmd MUST be done after a firmware download or the
564 * XXX move into the hal so driver doesn't need to be responsible
567 mwl_hal_gethwspecs(struct mwl_hal *mh0, struct mwl_hal_hwspec *hw)
569 struct mwl_hal_priv *mh = MWLPRIV(mh0);
570 HostCmd_DS_GET_HW_SPEC *pCmd;
574 _CMD_SETUP(pCmd, HostCmd_DS_GET_HW_SPEC, HostCmd_CMD_GET_HW_SPEC);
575 memset(&pCmd->PermanentAddr[0], 0xff, IEEE80211_ADDR_LEN);
576 pCmd->ulFwAwakeCookie = htole32((unsigned int)mh->mh_cmdaddr+2048);
578 retval = mwlExecuteCmd(mh, HostCmd_CMD_GET_HW_SPEC);
580 IEEE80211_ADDR_COPY(hw->macAddr, pCmd->PermanentAddr);
581 hw->wcbBase[0] = le32toh(pCmd->WcbBase0) & 0x0000ffff;
582 hw->wcbBase[1] = le32toh(pCmd->WcbBase1[0]) & 0x0000ffff;
583 hw->wcbBase[2] = le32toh(pCmd->WcbBase1[1]) & 0x0000ffff;
584 hw->wcbBase[3] = le32toh(pCmd->WcbBase1[2]) & 0x0000ffff;
585 hw->rxDescRead = le32toh(pCmd->RxPdRdPtr)& 0x0000ffff;
586 hw->rxDescWrite = le32toh(pCmd->RxPdWrPtr)& 0x0000ffff;
587 hw->regionCode = le16toh(pCmd->RegionCode) & 0x00ff;
588 hw->fwReleaseNumber = le32toh(pCmd->FWReleaseNumber);
589 hw->maxNumWCB = le16toh(pCmd->NumOfWCB);
590 hw->maxNumMCAddr = le16toh(pCmd->NumOfMCastAddr);
591 hw->numAntennas = le16toh(pCmd->NumberOfAntenna);
592 hw->hwVersion = pCmd->Version;
593 hw->hostInterface = pCmd->HostIf;
595 mh->mh_revs.mh_macRev = hw->hwVersion; /* XXX */
596 mh->mh_revs.mh_phyRev = hw->hostInterface; /* XXX */
598 minrev = ((hw->fwReleaseNumber) >> 16) & 0xff;
600 /* starting with 3.4.x.x s/w BA streams supported */
601 mh->mh_bastreams &= (1<<MWL_BASTREAMS_MAX)-1;
603 mh->mh_bastreams &= (1<<2)-1;
610 * Inform the f/w about location of the tx/rx dma data structures
611 * and related state. This cmd must be done immediately after a
612 * mwl_hal_gethwspecs call or the f/w will lockup.
615 mwl_hal_sethwdma(struct mwl_hal *mh0, const struct mwl_hal_txrxdma *dma)
617 struct mwl_hal_priv *mh = MWLPRIV(mh0);
618 HostCmd_DS_SET_HW_SPEC *pCmd;
622 _CMD_SETUP(pCmd, HostCmd_DS_SET_HW_SPEC, HostCmd_CMD_SET_HW_SPEC);
623 pCmd->WcbBase[0] = htole32(dma->wcbBase[0]);
624 pCmd->WcbBase[1] = htole32(dma->wcbBase[1]);
625 pCmd->WcbBase[2] = htole32(dma->wcbBase[2]);
626 pCmd->WcbBase[3] = htole32(dma->wcbBase[3]);
627 pCmd->TxWcbNumPerQueue = htole32(dma->maxNumTxWcb);
628 pCmd->NumTxQueues = htole32(dma->maxNumWCB);
629 pCmd->TotalRxWcb = htole32(1); /* XXX */
630 pCmd->RxPdWrPtr = htole32(dma->rxDescRead);
631 pCmd->Flags = htole32(SET_HW_SPEC_HOSTFORM_BEACON
632 #ifdef MWL_HOST_PS_SUPPORT
633 | SET_HW_SPEC_HOST_POWERSAVE
635 | SET_HW_SPEC_HOSTFORM_PROBERESP);
636 /* disable multi-bss operation for A1-A4 parts */
637 if (mh->mh_revs.mh_macRev < 5)
638 pCmd->Flags |= htole32(SET_HW_SPEC_DISABLEMBSS);
640 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_HW_SPEC);
642 if (pCmd->Flags & htole32(SET_HW_SPEC_DISABLEMBSS))
643 mh->mh_flags &= ~MHF_MBSS;
645 mh->mh_flags |= MHF_MBSS;
652 * Retrieve statistics from the f/w.
653 * XXX should be in memory shared w/ driver
656 mwl_hal_gethwstats(struct mwl_hal *mh0, struct mwl_hal_hwstats *stats)
658 struct mwl_hal_priv *mh = MWLPRIV(mh0);
659 HostCmd_DS_802_11_GET_STAT *pCmd;
663 _CMD_SETUP(pCmd, HostCmd_DS_802_11_GET_STAT,
664 HostCmd_CMD_802_11_GET_STAT);
666 retval = mwlExecuteCmd(mh, HostCmd_CMD_802_11_GET_STAT);
668 const uint32_t *sp = (const uint32_t *)&pCmd->TxRetrySuccesses;
669 uint32_t *dp = (uint32_t *)&stats->TxRetrySuccesses;
672 for (i = 0; i < sizeof(*stats)/sizeof(uint32_t); i++)
673 dp[i] = le32toh(sp[i]);
675 * Update stats not returned by f/w but available
676 * through public registers. Note these registers
677 * are "clear on read" so we maintain cumulative data.
678 * XXX register defines
680 mh->mh_RTSSuccesses += RD4(mh, 0xa834);
681 mh->mh_RTSFailures += RD4(mh, 0xa830);
682 mh->mh_RxDuplicateFrames += RD4(mh, 0xa84c);
683 mh->mh_FCSErrorCount += RD4(mh, 0xa840);
687 stats->RTSSuccesses = mh->mh_RTSSuccesses;
688 stats->RTSFailures = mh->mh_RTSFailures;
689 stats->RxDuplicateFrames = mh->mh_RxDuplicateFrames;
690 stats->FCSErrorCount = mh->mh_FCSErrorCount;
695 * Set HT guard interval handling.
696 * Takes effect immediately.
699 mwl_hal_sethtgi(struct mwl_hal_vap *vap, int GIType)
701 struct mwl_hal_priv *mh = MWLVAP(vap);
702 HostCmd_FW_HT_GUARD_INTERVAL *pCmd;
706 _VCMD_SETUP(vap, pCmd, HostCmd_FW_HT_GUARD_INTERVAL,
707 HostCmd_CMD_HT_GUARD_INTERVAL);
708 pCmd->Action = htole32(HostCmd_ACT_GEN_SET);
711 pCmd->GIType = htole32(GI_TYPE_LONG);
712 } else if (GIType == 1) {
713 pCmd->GIType = htole32(GI_TYPE_LONG | GI_TYPE_SHORT);
715 pCmd->GIType = htole32(GI_TYPE_LONG);
718 retval = mwlExecuteCmd(mh, HostCmd_CMD_HT_GUARD_INTERVAL);
725 * Takes effect immediately.
726 * XXX preamble installed after set fixed rate cmd
729 mwl_hal_setradio(struct mwl_hal *mh0, int onoff, MWL_HAL_PREAMBLE preamble)
731 struct mwl_hal_priv *mh = MWLPRIV(mh0);
732 HostCmd_DS_802_11_RADIO_CONTROL *pCmd;
736 _CMD_SETUP(pCmd, HostCmd_DS_802_11_RADIO_CONTROL,
737 HostCmd_CMD_802_11_RADIO_CONTROL);
738 pCmd->Action = htole16(HostCmd_ACT_GEN_SET);
742 pCmd->Control = htole16(preamble);
743 pCmd->RadioOn = htole16(onoff);
745 retval = mwlExecuteCmd(mh, HostCmd_CMD_802_11_RADIO_CONTROL);
751 * Configure antenna use.
752 * Takes effect immediately.
753 * XXX tx antenna setting ignored
754 * XXX rx antenna setting should always be 3 (for now)
757 mwl_hal_setantenna(struct mwl_hal *mh0, MWL_HAL_ANTENNA dirSet, int ant)
759 struct mwl_hal_priv *mh = MWLPRIV(mh0);
760 HostCmd_DS_802_11_RF_ANTENNA *pCmd;
763 if (!(dirSet == WL_ANTENNATYPE_RX || dirSet == WL_ANTENNATYPE_TX))
767 _CMD_SETUP(pCmd, HostCmd_DS_802_11_RF_ANTENNA,
768 HostCmd_CMD_802_11_RF_ANTENNA);
769 pCmd->Action = htole16(dirSet);
770 if (ant == 0) /* default to all/both antennae */
772 pCmd->AntennaMode = htole16(ant);
774 retval = mwlExecuteCmd(mh, HostCmd_CMD_802_11_RF_ANTENNA);
780 * Set packet size threshold for implicit use of RTS.
781 * Takes effect immediately.
782 * XXX packet length > threshold =>'s RTS
785 mwl_hal_setrtsthreshold(struct mwl_hal_vap *vap, int threshold)
787 struct mwl_hal_priv *mh = MWLVAP(vap);
788 HostCmd_DS_802_11_RTS_THSD *pCmd;
792 _VCMD_SETUP(vap, pCmd, HostCmd_DS_802_11_RTS_THSD,
793 HostCmd_CMD_802_11_RTS_THSD);
794 pCmd->Action = htole16(HostCmd_ACT_GEN_SET);
795 pCmd->Threshold = htole16(threshold);
797 retval = mwlExecuteCmd(mh, HostCmd_CMD_802_11_RTS_THSD);
803 * Enable sta-mode operation (disables beacon frame xmit).
806 mwl_hal_setinframode(struct mwl_hal_vap *vap)
808 struct mwl_hal_priv *mh = MWLVAP(vap);
809 HostCmd_FW_SET_INFRA_MODE *pCmd;
813 _VCMD_SETUP(vap, pCmd, HostCmd_FW_SET_INFRA_MODE,
814 HostCmd_CMD_SET_INFRA_MODE);
816 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_INFRA_MODE);
822 * Configure radar detection in support of 802.11h.
825 mwl_hal_setradardetection(struct mwl_hal *mh0, MWL_HAL_RADAR action)
827 struct mwl_hal_priv *mh = MWLPRIV(mh0);
828 HostCmd_802_11h_Detect_Radar *pCmd;
832 _CMD_SETUP(pCmd, HostCmd_802_11h_Detect_Radar,
833 HostCmd_CMD_802_11H_DETECT_RADAR);
834 pCmd->CmdHdr.Length = htole16(sizeof(HostCmd_802_11h_Detect_Radar));
835 pCmd->Action = htole16(action);
836 if (mh->mh_regioncode == DOMAIN_CODE_ETSI_131)
837 pCmd->RadarTypeCode = htole16(131);
839 retval = mwlExecuteCmd(mh, HostCmd_CMD_802_11H_DETECT_RADAR);
845 * Convert public channel flags definition to a
846 * value suitable for feeding to the firmware.
847 * Note this includes byte swapping.
850 cvtChannelFlags(const MWL_HAL_CHANNEL *chan)
855 * NB: f/w only understands FREQ_BAND_5GHZ, supplying the more
856 * precise band info causes it to lockup (sometimes).
858 w = (chan->channelFlags.FreqBand == MWL_FREQ_BAND_2DOT4GHZ) ?
859 FREQ_BAND_2DOT4GHZ : FREQ_BAND_5GHZ;
860 switch (chan->channelFlags.ChnlWidth) {
861 case MWL_CH_10_MHz_WIDTH:
862 w |= CH_10_MHz_WIDTH;
864 case MWL_CH_20_MHz_WIDTH:
865 w |= CH_20_MHz_WIDTH;
867 case MWL_CH_40_MHz_WIDTH:
869 w |= CH_40_MHz_WIDTH;
872 switch (chan->channelFlags.ExtChnlOffset) {
873 case MWL_EXT_CH_NONE:
876 case MWL_EXT_CH_ABOVE_CTRL_CH:
877 w |= EXT_CH_ABOVE_CTRL_CH;
879 case MWL_EXT_CH_BELOW_CTRL_CH:
880 w |= EXT_CH_BELOW_CTRL_CH;
887 * Start a channel switch announcement countdown. The IE
888 * in the beacon frame is allowed to go out and the firmware
889 * counts down and notifies the host when it's time to switch
893 mwl_hal_setchannelswitchie(struct mwl_hal *mh0,
894 const MWL_HAL_CHANNEL *nextchan, uint32_t mode, uint32_t count)
896 struct mwl_hal_priv *mh = MWLPRIV(mh0);
897 HostCmd_SET_SWITCH_CHANNEL *pCmd;
901 _CMD_SETUP(pCmd, HostCmd_SET_SWITCH_CHANNEL,
902 HostCmd_CMD_SET_SWITCH_CHANNEL);
903 pCmd->Next11hChannel = htole32(nextchan->channel);
904 pCmd->Mode = htole32(mode);
905 pCmd->InitialCount = htole32(count+1);
906 pCmd->ChannelFlags = cvtChannelFlags(nextchan);
908 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_SWITCH_CHANNEL);
914 * Set the region code that selects the radar bin'ing agorithm.
917 mwl_hal_setregioncode(struct mwl_hal *mh0, int regionCode)
919 struct mwl_hal_priv *mh = MWLPRIV(mh0);
920 HostCmd_SET_REGIONCODE_INFO *pCmd;
924 _CMD_SETUP(pCmd, HostCmd_SET_REGIONCODE_INFO,
925 HostCmd_CMD_SET_REGION_CODE);
926 /* XXX map pseudo-codes to fw codes */
927 switch (regionCode) {
928 case DOMAIN_CODE_ETSI_131:
929 pCmd->regionCode = htole16(DOMAIN_CODE_ETSI);
932 pCmd->regionCode = htole16(regionCode);
936 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_REGION_CODE);
938 mh->mh_regioncode = regionCode;
943 #define RATEVAL(r) ((r) &~ RATE_MCS)
944 #define RATETYPE(r) (((r) & RATE_MCS) ? HT_RATE_TYPE : LEGACY_RATE_TYPE)
947 mwl_hal_settxrate(struct mwl_hal_vap *vap, MWL_HAL_TXRATE_HANDLING handling,
948 const MWL_HAL_TXRATE *rate)
950 struct mwl_hal_priv *mh = MWLVAP(vap);
951 HostCmd_FW_USE_FIXED_RATE *pCmd;
952 FIXED_RATE_ENTRY *fp;
956 _VCMD_SETUP(vap, pCmd, HostCmd_FW_USE_FIXED_RATE,
957 HostCmd_CMD_SET_FIXED_RATE);
959 pCmd->MulticastRate = RATEVAL(rate->McastRate);
960 pCmd->MultiRateTxType = RATETYPE(rate->McastRate);
961 /* NB: no rate type field */
962 pCmd->ManagementRate = RATEVAL(rate->MgtRate);
963 memset(pCmd->FixedRateTable, 0, sizeof(pCmd->FixedRateTable));
964 if (handling == RATE_FIXED) {
965 pCmd->Action = htole32(HostCmd_ACT_GEN_SET);
966 pCmd->AllowRateDrop = htole32(FIXED_RATE_WITHOUT_AUTORATE_DROP);
967 fp = pCmd->FixedRateTable;
969 htole32(RATEVAL(rate->RateSeries[0].Rate));
970 fp->FixRateTypeFlags.FixRateType =
971 htole32(RATETYPE(rate->RateSeries[0].Rate));
972 pCmd->EntryCount = htole32(1);
973 } else if (handling == RATE_FIXED_DROP) {
974 pCmd->Action = htole32(HostCmd_ACT_GEN_SET);
975 pCmd->AllowRateDrop = htole32(FIXED_RATE_WITH_AUTO_RATE_DROP);
977 fp = pCmd->FixedRateTable;
978 for (i = 0; i < 4; i++) {
979 if (rate->RateSeries[0].TryCount == 0)
981 fp->FixRateTypeFlags.FixRateType =
982 htole32(RATETYPE(rate->RateSeries[i].Rate));
984 htole32(RATEVAL(rate->RateSeries[i].Rate));
985 fp->FixRateTypeFlags.RetryCountValid =
986 htole32(RETRY_COUNT_VALID);
988 htole32(rate->RateSeries[i].TryCount-1);
991 pCmd->EntryCount = htole32(n);
993 pCmd->Action = htole32(HostCmd_ACT_NOT_USE_FIXED_RATE);
995 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_FIXED_RATE);
1001 mwl_hal_settxrate_auto(struct mwl_hal *mh0, const MWL_HAL_TXRATE *rate)
1003 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1004 HostCmd_FW_USE_FIXED_RATE *pCmd;
1008 _CMD_SETUP(pCmd, HostCmd_FW_USE_FIXED_RATE,
1009 HostCmd_CMD_SET_FIXED_RATE);
1011 pCmd->MulticastRate = RATEVAL(rate->McastRate);
1012 pCmd->MultiRateTxType = RATETYPE(rate->McastRate);
1013 /* NB: no rate type field */
1014 pCmd->ManagementRate = RATEVAL(rate->MgtRate);
1015 memset(pCmd->FixedRateTable, 0, sizeof(pCmd->FixedRateTable));
1016 pCmd->Action = htole32(HostCmd_ACT_NOT_USE_FIXED_RATE);
1018 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_FIXED_RATE);
1027 mwl_hal_setslottime(struct mwl_hal *mh0, int usecs)
1029 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1030 HostCmd_FW_SET_SLOT *pCmd;
1033 if (usecs != 9 && usecs != 20)
1037 _CMD_SETUP(pCmd, HostCmd_FW_SET_SLOT,
1038 HostCmd_CMD_802_11_SET_SLOT);
1039 pCmd->Action = htole16(HostCmd_ACT_GEN_SET);
1040 pCmd->Slot = (usecs == 9 ? 1 : 0);
1042 retval = mwlExecuteCmd(mh, HostCmd_CMD_802_11_SET_SLOT);
1048 mwl_hal_adjusttxpower(struct mwl_hal *mh0, uint32_t level)
1050 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1051 HostCmd_DS_802_11_RF_TX_POWER *pCmd;
1055 _CMD_SETUP(pCmd, HostCmd_DS_802_11_RF_TX_POWER,
1056 HostCmd_CMD_802_11_RF_TX_POWER);
1057 pCmd->Action = htole16(HostCmd_ACT_GEN_SET);
1060 pCmd->SupportTxPowerLevel = htole16(WL_TX_POWERLEVEL_LOW);
1061 } else if (level >= 30 && level < 60) {
1062 pCmd->SupportTxPowerLevel = htole16(WL_TX_POWERLEVEL_MEDIUM);
1064 pCmd->SupportTxPowerLevel = htole16(WL_TX_POWERLEVEL_HIGH);
1067 retval = mwlExecuteCmd(mh, HostCmd_CMD_802_11_RF_TX_POWER);
1072 static const struct mwl_hal_channel *
1073 findchannel(const struct mwl_hal_priv *mh, const MWL_HAL_CHANNEL *c)
1075 const struct mwl_hal_channel *hc;
1076 const MWL_HAL_CHANNELINFO *ci;
1077 int chan = c->channel, i;
1079 if (c->channelFlags.FreqBand == MWL_FREQ_BAND_2DOT4GHZ) {
1081 if (c->channelFlags.ChnlWidth == MWL_CH_40_MHz_WIDTH) {
1083 if (c->channelFlags.ExtChnlOffset == MWL_EXT_CH_BELOW_CTRL_CH)
1087 /* 2.4G channel table is directly indexed */
1088 hc = ((unsigned)i < ci->nchannels) ? &ci->channels[i] : NULL;
1089 } else if (c->channelFlags.FreqBand == MWL_FREQ_BAND_5GHZ) {
1090 if (c->channelFlags.ChnlWidth == MWL_CH_40_MHz_WIDTH) {
1091 ci = &mh->mh_40M_5G;
1092 if (c->channelFlags.ExtChnlOffset == MWL_EXT_CH_BELOW_CTRL_CH)
1095 ci = &mh->mh_20M_5G;
1096 /* 5GHz channel table is sparse and must be searched */
1097 for (i = 0; i < ci->nchannels; i++)
1098 if (ci->channels[i].ieee == chan)
1100 hc = (i < ci->nchannels) ? &ci->channels[i] : NULL;
1107 mwl_hal_settxpower(struct mwl_hal *mh0, const MWL_HAL_CHANNEL *c, uint8_t maxtxpow)
1109 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1110 HostCmd_DS_802_11_RF_TX_POWER *pCmd;
1111 const struct mwl_hal_channel *hc;
1114 hc = findchannel(mh, c);
1116 /* XXX temp while testing */
1117 device_printf(mh->mh_dev,
1118 "%s: no cal data for channel %u band %u width %u ext %u\n",
1119 __func__, c->channel, c->channelFlags.FreqBand,
1120 c->channelFlags.ChnlWidth, c->channelFlags.ExtChnlOffset);
1125 _CMD_SETUP(pCmd, HostCmd_DS_802_11_RF_TX_POWER,
1126 HostCmd_CMD_802_11_RF_TX_POWER);
1127 pCmd->Action = htole16(HostCmd_ACT_GEN_SET_LIST);
1129 /* NB: 5Ghz cal data have the channel # in [0]; don't truncate */
1130 if (c->channelFlags.FreqBand == MWL_FREQ_BAND_5GHZ)
1131 pCmd->PowerLevelList[i++] = htole16(hc->targetPowers[0]);
1132 for (; i < 4; i++) {
1133 uint16_t pow = hc->targetPowers[i];
1136 pCmd->PowerLevelList[i] = htole16(pow);
1138 retval = mwlExecuteCmd(mh, HostCmd_CMD_802_11_RF_TX_POWER);
1144 mwl_hal_getchannelinfo(struct mwl_hal *mh0, int band, int chw,
1145 const MWL_HAL_CHANNELINFO **ci)
1147 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1150 case MWL_FREQ_BAND_2DOT4GHZ:
1151 *ci = (chw == MWL_CH_20_MHz_WIDTH) ? &mh->mh_20M : &mh->mh_40M;
1153 case MWL_FREQ_BAND_5GHZ:
1154 *ci = (chw == MWL_CH_20_MHz_WIDTH) ?
1155 &mh->mh_20M_5G : &mh->mh_40M_5G;
1160 return ((*ci)->freqLow == (*ci)->freqHigh) ? EINVAL : 0;
1164 mwl_hal_setmcast(struct mwl_hal *mh0, int nmc, const uint8_t macs[])
1166 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1167 HostCmd_DS_MAC_MULTICAST_ADR *pCmd;
1170 if (nmc > MWL_HAL_MCAST_MAX)
1174 _CMD_SETUP(pCmd, HostCmd_DS_MAC_MULTICAST_ADR,
1175 HostCmd_CMD_MAC_MULTICAST_ADR);
1176 memcpy(pCmd->MACList, macs, nmc*IEEE80211_ADDR_LEN);
1177 pCmd->NumOfAdrs = htole16(nmc);
1178 pCmd->Action = htole16(0xffff);
1180 retval = mwlExecuteCmd(mh, HostCmd_CMD_MAC_MULTICAST_ADR);
1186 mwl_hal_keyset(struct mwl_hal_vap *vap, const MWL_HAL_KEYVAL *kv,
1187 const uint8_t mac[IEEE80211_ADDR_LEN])
1189 struct mwl_hal_priv *mh = MWLVAP(vap);
1190 HostCmd_FW_UPDATE_ENCRYPTION_SET_KEY *pCmd;
1194 _VCMD_SETUP(vap, pCmd, HostCmd_FW_UPDATE_ENCRYPTION_SET_KEY,
1195 HostCmd_CMD_UPDATE_ENCRYPTION);
1196 if (kv->keyFlags & (KEY_FLAG_TXGROUPKEY|KEY_FLAG_RXGROUPKEY))
1197 pCmd->ActionType = htole32(EncrActionTypeSetGroupKey);
1199 pCmd->ActionType = htole32(EncrActionTypeSetKey);
1200 pCmd->KeyParam.Length = htole16(sizeof(pCmd->KeyParam));
1201 pCmd->KeyParam.KeyTypeId = htole16(kv->keyTypeId);
1202 pCmd->KeyParam.KeyInfo = htole32(kv->keyFlags);
1203 pCmd->KeyParam.KeyIndex = htole32(kv->keyIndex);
1204 /* NB: includes TKIP MIC keys */
1205 memcpy(&pCmd->KeyParam.Key, &kv->key, kv->keyLen);
1206 switch (kv->keyTypeId) {
1207 case KEY_TYPE_ID_WEP:
1208 pCmd->KeyParam.KeyLen = htole16(kv->keyLen);
1210 case KEY_TYPE_ID_TKIP:
1211 pCmd->KeyParam.KeyLen = htole16(sizeof(TKIP_TYPE_KEY));
1212 pCmd->KeyParam.Key.TkipKey.TkipRsc.low =
1213 htole16(kv->key.tkip.rsc.low);
1214 pCmd->KeyParam.Key.TkipKey.TkipRsc.high =
1215 htole32(kv->key.tkip.rsc.high);
1216 pCmd->KeyParam.Key.TkipKey.TkipTsc.low =
1217 htole16(kv->key.tkip.tsc.low);
1218 pCmd->KeyParam.Key.TkipKey.TkipTsc.high =
1219 htole32(kv->key.tkip.tsc.high);
1221 case KEY_TYPE_ID_AES:
1222 pCmd->KeyParam.KeyLen = htole16(sizeof(AES_TYPE_KEY));
1225 #ifdef MWL_MBSS_SUPPORT
1226 IEEE80211_ADDR_COPY(pCmd->KeyParam.Macaddr, mac);
1228 IEEE80211_ADDR_COPY(pCmd->Macaddr, mac);
1230 retval = mwlExecuteCmd(mh, HostCmd_CMD_UPDATE_ENCRYPTION);
1236 mwl_hal_keyreset(struct mwl_hal_vap *vap, const MWL_HAL_KEYVAL *kv, const uint8_t mac[IEEE80211_ADDR_LEN])
1238 struct mwl_hal_priv *mh = MWLVAP(vap);
1239 HostCmd_FW_UPDATE_ENCRYPTION_SET_KEY *pCmd;
1243 _VCMD_SETUP(vap, pCmd, HostCmd_FW_UPDATE_ENCRYPTION_SET_KEY,
1244 HostCmd_CMD_UPDATE_ENCRYPTION);
1245 pCmd->ActionType = htole16(EncrActionTypeRemoveKey);
1246 pCmd->KeyParam.Length = htole16(sizeof(pCmd->KeyParam));
1247 pCmd->KeyParam.KeyTypeId = htole16(kv->keyTypeId);
1248 pCmd->KeyParam.KeyInfo = htole32(kv->keyFlags);
1249 pCmd->KeyParam.KeyIndex = htole32(kv->keyIndex);
1250 #ifdef MWL_MBSS_SUPPORT
1251 IEEE80211_ADDR_COPY(pCmd->KeyParam.Macaddr, mac);
1253 IEEE80211_ADDR_COPY(pCmd->Macaddr, mac);
1255 retval = mwlExecuteCmd(mh, HostCmd_CMD_UPDATE_ENCRYPTION);
1261 mwl_hal_setmac_locked(struct mwl_hal_vap *vap,
1262 const uint8_t addr[IEEE80211_ADDR_LEN])
1264 struct mwl_hal_priv *mh = MWLVAP(vap);
1265 HostCmd_DS_SET_MAC *pCmd;
1267 _VCMD_SETUP(vap, pCmd, HostCmd_DS_SET_MAC, HostCmd_CMD_SET_MAC_ADDR);
1268 IEEE80211_ADDR_COPY(&pCmd->MacAddr[0], addr);
1269 #ifdef MWL_MBSS_SUPPORT
1270 pCmd->MacType = vap->bss_type; /* NB: already byte swapped */
1271 IEEE80211_ADDR_COPY(vap->mac, addr); /* XXX do only if success */
1273 return mwlExecuteCmd(mh, HostCmd_CMD_SET_MAC_ADDR);
1277 mwl_hal_setmac(struct mwl_hal_vap *vap, const uint8_t addr[IEEE80211_ADDR_LEN])
1279 struct mwl_hal_priv *mh = MWLVAP(vap);
1283 retval = mwl_hal_setmac_locked(vap, addr);
1289 mwl_hal_setbeacon(struct mwl_hal_vap *vap, const void *frame, size_t frameLen)
1291 struct mwl_hal_priv *mh = MWLVAP(vap);
1292 HostCmd_DS_SET_BEACON *pCmd;
1295 /* XXX verify frameLen fits */
1297 _VCMD_SETUP(vap, pCmd, HostCmd_DS_SET_BEACON, HostCmd_CMD_SET_BEACON);
1298 /* XXX override _VCMD_SETUP */
1299 pCmd->CmdHdr.Length = htole16(sizeof(HostCmd_DS_SET_BEACON)-1+frameLen);
1300 pCmd->FrmBodyLen = htole16(frameLen);
1301 memcpy(pCmd->FrmBody, frame, frameLen);
1303 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_BEACON);
1309 mwl_hal_setpowersave_bss(struct mwl_hal_vap *vap, uint8_t nsta)
1311 struct mwl_hal_priv *mh = MWLVAP(vap);
1312 HostCmd_SET_POWERSAVESTATION *pCmd;
1316 _VCMD_SETUP(vap, pCmd, HostCmd_SET_POWERSAVESTATION,
1317 HostCmd_CMD_SET_POWERSAVESTATION);
1318 pCmd->NumberOfPowersave = nsta;
1320 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_POWERSAVESTATION);
1326 mwl_hal_setpowersave_sta(struct mwl_hal_vap *vap, uint16_t aid, int ena)
1328 struct mwl_hal_priv *mh = MWLVAP(vap);
1329 HostCmd_SET_TIM *pCmd;
1333 _VCMD_SETUP(vap, pCmd, HostCmd_SET_TIM, HostCmd_CMD_SET_TIM);
1334 pCmd->Aid = htole16(aid);
1335 pCmd->Set = htole32(ena);
1337 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_TIM);
1343 mwl_hal_setassocid(struct mwl_hal_vap *vap,
1344 const uint8_t bssId[IEEE80211_ADDR_LEN], uint16_t assocId)
1346 struct mwl_hal_priv *mh = MWLVAP(vap);
1347 HostCmd_FW_SET_AID *pCmd = (HostCmd_FW_SET_AID *) &mh->mh_cmdbuf[0];
1351 _VCMD_SETUP(vap, pCmd, HostCmd_FW_SET_AID, HostCmd_CMD_SET_AID);
1352 pCmd->AssocID = htole16(assocId);
1353 IEEE80211_ADDR_COPY(&pCmd->MacAddr[0], bssId);
1355 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_AID);
1361 mwl_hal_setchannel(struct mwl_hal *mh0, const MWL_HAL_CHANNEL *chan)
1363 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1364 HostCmd_FW_SET_RF_CHANNEL *pCmd;
1368 _CMD_SETUP(pCmd, HostCmd_FW_SET_RF_CHANNEL, HostCmd_CMD_SET_RF_CHANNEL);
1369 pCmd->Action = htole16(HostCmd_ACT_GEN_SET);
1370 pCmd->CurrentChannel = chan->channel;
1371 pCmd->ChannelFlags = cvtChannelFlags(chan); /* NB: byte-swapped */
1373 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_RF_CHANNEL);
1379 bastream_check_available(struct mwl_hal_vap *vap, int qid,
1380 const uint8_t Macaddr[IEEE80211_ADDR_LEN],
1381 uint8_t Tid, uint8_t ParamInfo)
1383 struct mwl_hal_priv *mh = MWLVAP(vap);
1384 HostCmd_FW_BASTREAM *pCmd;
1387 MWL_HAL_LOCK_ASSERT(mh);
1389 _VCMD_SETUP(vap, pCmd, HostCmd_FW_BASTREAM, HostCmd_CMD_BASTREAM);
1390 pCmd->ActionType = htole32(BaCheckCreateStream);
1391 pCmd->BaInfo.CreateParams.BarThrs = htole32(63);
1392 pCmd->BaInfo.CreateParams.WindowSize = htole32(64);
1393 pCmd->BaInfo.CreateParams.IdleThrs = htole32(0x22000);
1394 IEEE80211_ADDR_COPY(&pCmd->BaInfo.CreateParams.PeerMacAddr[0], Macaddr);
1395 pCmd->BaInfo.CreateParams.DialogToken = 10;
1396 pCmd->BaInfo.CreateParams.Tid = Tid;
1397 pCmd->BaInfo.CreateParams.QueueId = qid;
1398 pCmd->BaInfo.CreateParams.ParamInfo = (uint8_t) ParamInfo;
1400 cvtBAFlags(&pCmd->BaInfo.CreateParams.Flags, sp->ba_policy, 0);
1402 pCmd->BaInfo.CreateParams.Flags =
1403 htole32(BASTREAM_FLAG_IMMEDIATE_TYPE)
1404 | htole32(BASTREAM_FLAG_DIRECTION_UPSTREAM)
1408 retval = mwlExecuteCmd(mh, HostCmd_CMD_BASTREAM);
1411 * NB: BA stream create may fail when the stream is
1412 * h/w backed under some (as yet not understood) conditions.
1413 * Check the result code to catch this.
1415 if (le16toh(pCmd->CmdHdr.Result) != HostCmd_RESULT_OK)
1421 const MWL_HAL_BASTREAM *
1422 mwl_hal_bastream_alloc(struct mwl_hal_vap *vap, int ba_policy,
1423 const uint8_t Macaddr[IEEE80211_ADDR_LEN],
1424 uint8_t Tid, uint8_t ParamInfo, void *a1, void *a2)
1426 struct mwl_hal_priv *mh = MWLVAP(vap);
1427 struct mwl_hal_bastream *sp;
1431 if (mh->mh_bastreams == 0) {
1432 /* no streams available */
1436 for (s = 0; (mh->mh_bastreams & (1<<s)) == 0; s++)
1438 if (bastream_check_available(vap, s, Macaddr, Tid, ParamInfo)) {
1442 sp = &mh->mh_streams[s];
1443 mh->mh_bastreams &= ~(1<<s);
1444 sp->public.data[0] = a1;
1445 sp->public.data[1] = a2;
1446 IEEE80211_ADDR_COPY(sp->macaddr, Macaddr);
1448 sp->paraminfo = ParamInfo;
1450 sp->ba_policy = ba_policy;
1452 return sp != NULL ? &sp->public : NULL;
1455 const MWL_HAL_BASTREAM *
1456 mwl_hal_bastream_lookup(struct mwl_hal *mh0, int s)
1458 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1460 if (!(0 <= s && s < MWL_BASTREAMS_MAX))
1462 if (mh->mh_bastreams & (1<<s))
1464 return &mh->mh_streams[s].public;
1468 #define __DECONST(type, var) ((type)(uintptr_t)(const void *)(var))
1472 mwl_hal_bastream_create(struct mwl_hal_vap *vap,
1473 const MWL_HAL_BASTREAM *s, int BarThrs, int WindowSize, uint16_t seqno)
1475 struct mwl_hal_priv *mh = MWLVAP(vap);
1476 struct mwl_hal_bastream *sp = __DECONST(struct mwl_hal_bastream *, s);
1477 HostCmd_FW_BASTREAM *pCmd;
1481 _VCMD_SETUP(vap, pCmd, HostCmd_FW_BASTREAM, HostCmd_CMD_BASTREAM);
1482 pCmd->ActionType = htole32(BaCreateStream);
1483 pCmd->BaInfo.CreateParams.BarThrs = htole32(BarThrs);
1484 pCmd->BaInfo.CreateParams.WindowSize = htole32(WindowSize);
1485 pCmd->BaInfo.CreateParams.IdleThrs = htole32(0x22000);
1486 IEEE80211_ADDR_COPY(&pCmd->BaInfo.CreateParams.PeerMacAddr[0],
1489 memset(&pCmd->BaInfo.CreateParams.StaSrcMacAddr, 0, IEEE80211_ADDR_LEN);
1491 pCmd->BaInfo.CreateParams.DialogToken = DialogToken;
1493 pCmd->BaInfo.CreateParams.DialogToken = 10;
1495 pCmd->BaInfo.CreateParams.Tid = sp->tid;
1496 pCmd->BaInfo.CreateParams.QueueId = sp->stream;
1497 pCmd->BaInfo.CreateParams.ParamInfo = sp->paraminfo;
1498 /* NB: ResetSeqNo known to be zero */
1499 pCmd->BaInfo.CreateParams.StartSeqNo = htole16(seqno);
1501 cvtBAFlags(&pCmd->BaInfo.CreateParams.Flags, sp->ba_policy, 0);
1503 pCmd->BaInfo.CreateParams.Flags =
1504 htole32(BASTREAM_FLAG_IMMEDIATE_TYPE)
1505 | htole32(BASTREAM_FLAG_DIRECTION_UPSTREAM)
1509 retval = mwlExecuteCmd(mh, HostCmd_CMD_BASTREAM);
1512 * NB: BA stream create may fail when the stream is
1513 * h/w backed under some (as yet not understood) conditions.
1514 * Check the result code to catch this.
1516 if (le16toh(pCmd->CmdHdr.Result) != HostCmd_RESULT_OK)
1526 mwl_hal_bastream_destroy(struct mwl_hal *mh0, const MWL_HAL_BASTREAM *s)
1528 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1529 struct mwl_hal_bastream *sp = __DECONST(struct mwl_hal_bastream *, s);
1530 HostCmd_FW_BASTREAM *pCmd;
1533 if (sp->stream >= MWL_BASTREAMS_MAX) {
1539 _CMD_SETUP(pCmd, HostCmd_FW_BASTREAM, HostCmd_CMD_BASTREAM);
1540 pCmd->ActionType = htole32(BaDestroyStream);
1541 pCmd->BaInfo.DestroyParams.FwBaContext.Context =
1542 htole32(sp->stream);
1544 retval = mwlExecuteCmd(mh, HostCmd_CMD_BASTREAM);
1547 /* NB: always reclaim stream */
1548 mh->mh_bastreams |= 1<<sp->stream;
1549 sp->public.data[0] = NULL;
1550 sp->public.data[1] = NULL;
1557 mwl_hal_bastream_get_seqno(struct mwl_hal *mh0,
1558 const MWL_HAL_BASTREAM *s, const uint8_t Macaddr[IEEE80211_ADDR_LEN],
1561 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1562 struct mwl_hal_bastream *sp = __DECONST(struct mwl_hal_bastream *, s);
1563 HostCmd_GET_SEQNO *pCmd;
1567 _CMD_SETUP(pCmd, HostCmd_GET_SEQNO, HostCmd_CMD_GET_SEQNO);
1568 IEEE80211_ADDR_COPY(pCmd->MacAddr, Macaddr);
1569 pCmd->TID = sp->tid;
1571 retval = mwlExecuteCmd(mh, HostCmd_CMD_GET_SEQNO);
1573 *pseqno = le16toh(pCmd->SeqNo);
1579 mwl_hal_getwatchdogbitmap(struct mwl_hal *mh0, uint8_t bitmap[1])
1581 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1582 HostCmd_FW_GET_WATCHDOG_BITMAP *pCmd;
1586 _CMD_SETUP(pCmd, HostCmd_FW_GET_WATCHDOG_BITMAP,
1587 HostCmd_CMD_GET_WATCHDOG_BITMAP);
1589 retval = mwlExecuteCmd(mh, HostCmd_CMD_GET_WATCHDOG_BITMAP);
1591 bitmap[0] = pCmd->Watchdogbitmap;
1592 /* fw returns qid, map it to BA stream */
1593 if (bitmap[0] < MWL_BAQID_MAX)
1594 bitmap[0] = qid2ba[bitmap[0]];
1601 * Configure aggressive Ampdu rate mode.
1604 mwl_hal_setaggampduratemode(struct mwl_hal *mh0, int mode, int threshold)
1606 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1607 HostCmd_FW_AMPDU_RETRY_RATEDROP_MODE *pCmd;
1611 _CMD_SETUP(pCmd, HostCmd_FW_AMPDU_RETRY_RATEDROP_MODE,
1612 HostCmd_CMD_AMPDU_RETRY_RATEDROP_MODE);
1613 pCmd->Action = htole16(1);
1614 pCmd->Option = htole32(mode);
1615 pCmd->Threshold = htole32(threshold);
1617 retval = mwlExecuteCmd(mh, HostCmd_CMD_AMPDU_RETRY_RATEDROP_MODE);
1623 mwl_hal_getaggampduratemode(struct mwl_hal *mh0, int *mode, int *threshold)
1625 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1626 HostCmd_FW_AMPDU_RETRY_RATEDROP_MODE *pCmd;
1630 _CMD_SETUP(pCmd, HostCmd_FW_AMPDU_RETRY_RATEDROP_MODE,
1631 HostCmd_CMD_AMPDU_RETRY_RATEDROP_MODE);
1632 pCmd->Action = htole16(0);
1634 retval = mwlExecuteCmd(mh, HostCmd_CMD_AMPDU_RETRY_RATEDROP_MODE);
1636 *mode = le32toh(pCmd->Option);
1637 *threshold = le32toh(pCmd->Threshold);
1642 * Set CFEND status Enable/Disable
1645 mwl_hal_setcfend(struct mwl_hal *mh0, int ena)
1647 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1648 HostCmd_CFEND_ENABLE *pCmd;
1652 _CMD_SETUP(pCmd, HostCmd_CFEND_ENABLE,
1653 HostCmd_CMD_CFEND_ENABLE);
1654 pCmd->Enable = htole32(ena);
1656 retval = mwlExecuteCmd(mh, HostCmd_CMD_CFEND_ENABLE);
1662 mwl_hal_setdwds(struct mwl_hal *mh0, int ena)
1664 HostCmd_DWDS_ENABLE *pCmd;
1665 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1669 _CMD_SETUP(pCmd, HostCmd_DWDS_ENABLE, HostCmd_CMD_DWDS_ENABLE);
1670 pCmd->Enable = htole32(ena);
1671 retval = mwlExecuteCmd(mh, HostCmd_CMD_DWDS_ENABLE);
1677 cvtPeerInfo(PeerInfo_t *to, const MWL_HAL_PEERINFO *from)
1679 to->LegacyRateBitMap = htole32(from->LegacyRateBitMap);
1680 to->HTRateBitMap = htole32(from->HTRateBitMap);
1681 to->CapInfo = htole16(from->CapInfo);
1682 to->HTCapabilitiesInfo = htole16(from->HTCapabilitiesInfo);
1683 to->MacHTParamInfo = from->MacHTParamInfo;
1684 to->AddHtInfo.ControlChan = from->AddHtInfo.ControlChan;
1685 to->AddHtInfo.AddChan = from->AddHtInfo.AddChan;
1686 to->AddHtInfo.OpMode = htole16(from->AddHtInfo.OpMode);
1687 to->AddHtInfo.stbc = htole16(from->AddHtInfo.stbc);
1690 /* XXX station id must be in [0..63] */
1692 mwl_hal_newstation(struct mwl_hal_vap *vap,
1693 const uint8_t addr[IEEE80211_ADDR_LEN], uint16_t aid, uint16_t sid,
1694 const MWL_HAL_PEERINFO *peer, int isQosSta, int wmeInfo)
1696 struct mwl_hal_priv *mh = MWLVAP(vap);
1697 HostCmd_FW_SET_NEW_STN *pCmd;
1701 _VCMD_SETUP(vap, pCmd, HostCmd_FW_SET_NEW_STN, HostCmd_CMD_SET_NEW_STN);
1702 pCmd->AID = htole16(aid);
1703 pCmd->StnId = htole16(sid);
1704 pCmd->Action = htole16(0); /* SET */
1706 /* NB: must fix up byte order */
1707 cvtPeerInfo(&pCmd->PeerInfo, peer);
1709 IEEE80211_ADDR_COPY(&pCmd->MacAddr[0], addr);
1710 pCmd->Qosinfo = wmeInfo;
1711 pCmd->isQosSta = (isQosSta != 0);
1713 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_NEW_STN);
1714 if (retval == 0 && IEEE80211_ADDR_EQ(vap->mac, addr))
1715 vap->flags |= MVF_STATION;
1721 mwl_hal_delstation(struct mwl_hal_vap *vap,
1722 const uint8_t addr[IEEE80211_ADDR_LEN])
1724 struct mwl_hal_priv *mh = MWLVAP(vap);
1725 HostCmd_FW_SET_NEW_STN *pCmd;
1726 int retval, islocal;
1729 islocal = IEEE80211_ADDR_EQ(vap->mac, addr);
1730 if (!islocal || (vap->flags & MVF_STATION)) {
1731 _VCMD_SETUP(vap, pCmd, HostCmd_FW_SET_NEW_STN,
1732 HostCmd_CMD_SET_NEW_STN);
1733 pCmd->Action = htole16(2); /* REMOVE */
1734 IEEE80211_ADDR_COPY(&pCmd->MacAddr[0], addr);
1735 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_NEW_STN);
1737 vap->flags &= ~MVF_STATION;
1745 * Prod the firmware to age packets on station power
1746 * save queues and reap frames on the tx aggregation q's.
1749 mwl_hal_setkeepalive(struct mwl_hal *mh0)
1751 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1752 HostCmd_FW_SET_KEEP_ALIVE_TICK *pCmd;
1756 _CMD_SETUP(pCmd, HostCmd_FW_SET_KEEP_ALIVE_TICK,
1757 HostCmd_CMD_SET_KEEP_ALIVE);
1759 * NB: tick must be 0 to prod the f/w;
1760 * a non-zero value is a noop.
1764 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_KEEP_ALIVE);
1770 mwl_hal_setapmode(struct mwl_hal_vap *vap, MWL_HAL_APMODE ApMode)
1772 struct mwl_hal_priv *mh = MWLVAP(vap);
1773 HostCmd_FW_SET_APMODE *pCmd;
1776 /* XXX validate ApMode? */
1779 _VCMD_SETUP(vap, pCmd, HostCmd_FW_SET_APMODE, HostCmd_CMD_SET_APMODE);
1780 pCmd->ApMode = ApMode;
1782 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_APMODE);
1788 mwl_hal_stop(struct mwl_hal_vap *vap)
1790 struct mwl_hal_priv *mh = MWLVAP(vap);
1791 HostCmd_DS_BSS_START *pCmd;
1795 if (vap->flags & MVF_RUNNING) {
1796 _VCMD_SETUP(vap, pCmd, HostCmd_DS_BSS_START,
1797 HostCmd_CMD_BSS_START);
1798 pCmd->Enable = htole32(HostCmd_ACT_GEN_OFF);
1799 retval = mwlExecuteCmd(mh, HostCmd_CMD_BSS_START);
1802 /* NB: mark !running regardless */
1803 vap->flags &= ~MVF_RUNNING;
1809 mwl_hal_start(struct mwl_hal_vap *vap)
1811 struct mwl_hal_priv *mh = MWLVAP(vap);
1812 HostCmd_DS_BSS_START *pCmd;
1816 _VCMD_SETUP(vap, pCmd, HostCmd_DS_BSS_START, HostCmd_CMD_BSS_START);
1817 pCmd->Enable = htole32(HostCmd_ACT_GEN_ON);
1819 retval = mwlExecuteCmd(mh, HostCmd_CMD_BSS_START);
1821 vap->flags |= MVF_RUNNING;
1827 mwl_hal_setgprot(struct mwl_hal *mh0, int prot)
1829 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1830 HostCmd_FW_SET_G_PROTECT_FLAG *pCmd;
1834 _CMD_SETUP(pCmd, HostCmd_FW_SET_G_PROTECT_FLAG,
1835 HostCmd_CMD_SET_G_PROTECT_FLAG);
1836 pCmd->GProtectFlag = htole32(prot);
1838 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_G_PROTECT_FLAG);
1844 mwl_hal_setwmm(struct mwl_hal *mh0, int onoff)
1846 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1847 HostCmd_FW_SetWMMMode *pCmd;
1851 _CMD_SETUP(pCmd, HostCmd_FW_SetWMMMode,
1852 HostCmd_CMD_SET_WMM_MODE);
1853 pCmd->Action = htole16(onoff);
1855 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_WMM_MODE);
1861 mwl_hal_setedcaparams(struct mwl_hal *mh0, uint8_t qnum,
1862 uint32_t CWmin, uint32_t CWmax, uint8_t AIFSN, uint16_t TXOPLimit)
1864 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1865 HostCmd_FW_SET_EDCA_PARAMS *pCmd;
1869 _CMD_SETUP(pCmd, HostCmd_FW_SET_EDCA_PARAMS,
1870 HostCmd_CMD_SET_EDCA_PARAMS);
1872 * NB: CWmin and CWmax are always set.
1873 * TxOpLimit is set if bit 0x2 is marked in Action
1874 * AIFSN is set if bit 0x4 is marked in Action
1876 pCmd->Action = htole16(0xffff); /* NB: set everything */
1877 pCmd->TxOP = htole16(TXOPLimit);
1878 pCmd->CWMax = htole32(CWmax);
1879 pCmd->CWMin = htole32(CWmin);
1880 pCmd->AIFSN = AIFSN;
1881 pCmd->TxQNum = qnum; /* XXX check */
1883 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_EDCA_PARAMS);
1888 /* XXX 0 = indoor, 1 = outdoor */
1890 mwl_hal_setrateadaptmode(struct mwl_hal *mh0, uint16_t mode)
1892 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1893 HostCmd_DS_SET_RATE_ADAPT_MODE *pCmd;
1897 _CMD_SETUP(pCmd, HostCmd_DS_SET_RATE_ADAPT_MODE,
1898 HostCmd_CMD_SET_RATE_ADAPT_MODE);
1899 pCmd->Action = htole16(HostCmd_ACT_GEN_SET);
1900 pCmd->RateAdaptMode = htole16(mode);
1902 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_RATE_ADAPT_MODE);
1908 mwl_hal_setcsmode(struct mwl_hal *mh0, MWL_HAL_CSMODE csmode)
1910 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1911 HostCmd_DS_SET_LINKADAPT_CS_MODE *pCmd;
1915 _CMD_SETUP(pCmd, HostCmd_DS_SET_LINKADAPT_CS_MODE,
1916 HostCmd_CMD_SET_LINKADAPT_CS_MODE);
1917 pCmd->Action = htole16(HostCmd_ACT_GEN_SET);
1918 pCmd->CSMode = htole16(csmode);
1920 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_LINKADAPT_CS_MODE);
1926 mwl_hal_setnprot(struct mwl_hal_vap *vap, MWL_HAL_HTPROTECT mode)
1928 struct mwl_hal_priv *mh = MWLVAP(vap);
1929 HostCmd_FW_SET_N_PROTECT_FLAG *pCmd;
1932 /* XXX validate mode */
1934 _VCMD_SETUP(vap, pCmd, HostCmd_FW_SET_N_PROTECT_FLAG,
1935 HostCmd_CMD_SET_N_PROTECT_FLAG);
1936 pCmd->NProtectFlag = htole32(mode);
1938 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_N_PROTECT_FLAG);
1944 mwl_hal_setnprotmode(struct mwl_hal_vap *vap, uint8_t mode)
1946 struct mwl_hal_priv *mh = MWLVAP(vap);
1947 HostCmd_FW_SET_N_PROTECT_OPMODE *pCmd;
1951 _VCMD_SETUP(vap, pCmd, HostCmd_FW_SET_N_PROTECT_OPMODE,
1952 HostCmd_CMD_SET_N_PROTECT_OPMODE);
1953 pCmd->NProtectOpMode = mode;
1955 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_N_PROTECT_OPMODE);
1961 mwl_hal_setoptimizationlevel(struct mwl_hal *mh0, int level)
1963 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1964 HostCmd_FW_SET_OPTIMIZATION_LEVEL *pCmd;
1968 _CMD_SETUP(pCmd, HostCmd_FW_SET_OPTIMIZATION_LEVEL,
1969 HostCmd_CMD_SET_OPTIMIZATION_LEVEL);
1970 pCmd->OptLevel = level;
1972 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_OPTIMIZATION_LEVEL);
1978 mwl_hal_setmimops(struct mwl_hal *mh0, const uint8_t addr[IEEE80211_ADDR_LEN],
1979 uint8_t enable, uint8_t mode)
1981 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1982 HostCmd_FW_SET_MIMOPSHT *pCmd;
1986 _CMD_SETUP(pCmd, HostCmd_FW_SET_MIMOPSHT, HostCmd_CMD_SET_MIMOPSHT);
1987 IEEE80211_ADDR_COPY(pCmd->Addr, addr);
1988 pCmd->Enable = enable;
1991 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_MIMOPSHT);
1997 mwlGetCalTable(struct mwl_hal_priv *mh, uint8_t annex, uint8_t index)
1999 HostCmd_FW_GET_CALTABLE *pCmd;
2002 MWL_HAL_LOCK_ASSERT(mh);
2004 _CMD_SETUP(pCmd, HostCmd_FW_GET_CALTABLE, HostCmd_CMD_GET_CALTABLE);
2005 pCmd->annex = annex;
2006 pCmd->index = index;
2007 memset(pCmd->calTbl, 0, sizeof(pCmd->calTbl));
2009 retval = mwlExecuteCmd(mh, HostCmd_CMD_GET_CALTABLE);
2011 pCmd->calTbl[0] != annex && annex != 0 && annex != 255)
2017 * Calculate the max tx power from the channel's cal data.
2020 setmaxtxpow(struct mwl_hal_channel *hc, int i, int maxix)
2022 hc->maxTxPow = hc->targetPowers[i];
2023 for (i++; i < maxix; i++)
2024 if (hc->targetPowers[i] > hc->maxTxPow)
2025 hc->maxTxPow = hc->targetPowers[i];
2029 * Construct channel info for 5GHz channels from cal data.
2032 get5Ghz(MWL_HAL_CHANNELINFO *ci, const uint8_t table[], int len)
2039 for (i = 0; i < len; i += 4) {
2040 struct mwl_hal_channel *hc;
2044 f = 5000 + 5*table[i];
2049 hc = &ci->channels[j];
2051 hc->ieee = table[i];
2052 memcpy(hc->targetPowers, &table[i], 4);
2053 setmaxtxpow(hc, 1, 4); /* NB: col 1 is the freq, skip*/
2057 ci->freqLow = (l == 32000) ? 0 : l;
2067 return 2407 + chan*5;
2068 return 2512 + (chan-15)*20;
2072 * Construct channel info for 2.4GHz channels from cal data.
2075 get2Ghz(MWL_HAL_CHANNELINFO *ci, const uint8_t table[], int len)
2080 for (i = 0; i < len; i += 4) {
2081 struct mwl_hal_channel *hc = &ci->channels[j];
2083 hc->freq = ieee2mhz(1+j);
2084 memcpy(hc->targetPowers, &table[i], 4);
2085 setmaxtxpow(hc, 0, 4);
2089 ci->freqLow = ieee2mhz(1);
2090 ci->freqHigh = ieee2mhz(j);
2096 dumpcaldata(const char *name, const uint8_t *table, int n)
2099 printf("\n%s:\n", name);
2100 for (i = 0; i < n; i += 4)
2101 printf("[%2d] %3d %3d %3d %3d\n", i/4, table[i+0], table[i+1], table[i+2], table[i+3]);
2106 mwlGetPwrCalTable(struct mwl_hal_priv *mh)
2108 const uint8_t *data;
2109 MWL_HAL_CHANNELINFO *ci;
2113 /* NB: we hold the lock so it's ok to use cmdbuf */
2114 data = ((const HostCmd_FW_GET_CALTABLE *) mh->mh_cmdbuf)->calTbl;
2115 if (mwlGetCalTable(mh, 33, 0) == 0) {
2116 len = (data[2] | (data[3] << 8)) - 12;
2117 if (len > PWTAGETRATETABLE20M)
2118 len = PWTAGETRATETABLE20M;
2120 dumpcaldata("2.4G 20M", &data[12], len);/*XXX*/
2122 get2Ghz(&mh->mh_20M, &data[12], len);
2124 if (mwlGetCalTable(mh, 34, 0) == 0) {
2125 len = (data[2] | (data[3] << 8)) - 12;
2126 if (len > PWTAGETRATETABLE40M)
2127 len = PWTAGETRATETABLE40M;
2129 dumpcaldata("2.4G 40M", &data[12], len);/*XXX*/
2132 get2Ghz(ci, &data[12], len);
2134 if (mwlGetCalTable(mh, 35, 0) == 0) {
2135 len = (data[2] | (data[3] << 8)) - 20;
2136 if (len > PWTAGETRATETABLE20M_5G)
2137 len = PWTAGETRATETABLE20M_5G;
2139 dumpcaldata("5G 20M", &data[20], len);/*XXX*/
2141 get5Ghz(&mh->mh_20M_5G, &data[20], len);
2143 if (mwlGetCalTable(mh, 36, 0) == 0) {
2144 len = (data[2] | (data[3] << 8)) - 20;
2145 if (len > PWTAGETRATETABLE40M_5G)
2146 len = PWTAGETRATETABLE40M_5G;
2148 dumpcaldata("5G 40M", &data[20], len);/*XXX*/
2150 ci = &mh->mh_40M_5G;
2151 get5Ghz(ci, &data[20], len);
2153 mh->mh_flags |= MHF_CALDATA;
2159 mwl_hal_getregioncode(struct mwl_hal *mh0, uint8_t *countryCode)
2161 struct mwl_hal_priv *mh = MWLPRIV(mh0);
2165 retval = mwlGetCalTable(mh, 0, 0);
2167 const HostCmd_FW_GET_CALTABLE *pCmd =
2168 (const HostCmd_FW_GET_CALTABLE *) mh->mh_cmdbuf;
2169 *countryCode = pCmd->calTbl[16];
2176 mwl_hal_setpromisc(struct mwl_hal *mh0, int ena)
2178 struct mwl_hal_priv *mh = MWLPRIV(mh0);
2182 v = RD4(mh, MACREG_REG_PROMISCUOUS);
2183 WR4(mh, MACREG_REG_PROMISCUOUS, ena ? v | 1 : v &~ 1);
2189 mwl_hal_getpromisc(struct mwl_hal *mh0)
2191 struct mwl_hal_priv *mh = MWLPRIV(mh0);
2195 v = RD4(mh, MACREG_REG_PROMISCUOUS);
2197 return (v & 1) != 0;
2201 mwl_hal_GetBeacon(struct mwl_hal *mh0, uint8_t *pBcn, uint16_t *pLen)
2203 struct mwl_hal_priv *mh = MWLPRIV(mh0);
2204 HostCmd_FW_GET_BEACON *pCmd;
2208 _CMD_SETUP(pCmd, HostCmd_FW_GET_BEACON, HostCmd_CMD_GET_BEACON);
2209 pCmd->Bcnlen = htole16(0);
2211 retval = mwlExecuteCmd(mh, HostCmd_CMD_GET_BEACON);
2213 /* XXX bounds check */
2214 memcpy(pBcn, &pCmd->Bcn, pCmd->Bcnlen);
2215 *pLen = pCmd->Bcnlen;
2222 mwl_hal_SetRifs(struct mwl_hal *mh0, uint8_t QNum)
2224 struct mwl_hal_priv *mh = MWLPRIV(mh0);
2225 HostCmd_FW_SET_RIFS *pCmd;
2229 _CMD_SETUP(pCmd, HostCmd_FW_SET_RIFS, HostCmd_CMD_SET_RIFS);
2232 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_RIFS);
2238 * Diagnostic api's for set/get registers.
2242 getRFReg(struct mwl_hal_priv *mh, int flag, uint32_t reg, uint32_t *val)
2244 HostCmd_DS_RF_REG_ACCESS *pCmd;
2248 _CMD_SETUP(pCmd, HostCmd_DS_RF_REG_ACCESS, HostCmd_CMD_RF_REG_ACCESS);
2249 pCmd->Offset = htole16(reg);
2250 pCmd->Action = htole16(flag);
2251 pCmd->Value = htole32(*val);
2253 retval = mwlExecuteCmd(mh, HostCmd_CMD_RF_REG_ACCESS);
2261 getBBReg(struct mwl_hal_priv *mh, int flag, uint32_t reg, uint32_t *val)
2263 HostCmd_DS_BBP_REG_ACCESS *pCmd;
2267 _CMD_SETUP(pCmd, HostCmd_DS_BBP_REG_ACCESS, HostCmd_CMD_BBP_REG_ACCESS);
2268 pCmd->Offset = htole16(reg);
2269 pCmd->Action = htole16(flag);
2270 pCmd->Value = htole32(*val);
2272 retval = mwlExecuteCmd(mh, HostCmd_CMD_BBP_REG_ACCESS);
2280 mwl_hal_getregdump(struct mwl_hal_priv *mh, const MWL_DIAG_REGRANGE *regs,
2281 void *dstbuf, int space)
2283 uint32_t *dp = dstbuf;
2286 for (i = 0; space >= 2*sizeof(uint32_t); i++) {
2287 u_int r = regs[i].start;
2288 u_int e = regs[i].end;
2289 *dp++ = (r<<16) | e;
2290 space -= sizeof(uint32_t);
2292 if (MWL_DIAG_ISMAC(r))
2294 else if (MWL_DIAG_ISBB(r))
2295 getBBReg(mh, HostCmd_ACT_GEN_READ,
2296 r - MWL_DIAG_BASE_BB, dp);
2297 else if (MWL_DIAG_ISRF(r))
2298 getRFReg(mh, HostCmd_ACT_GEN_READ,
2299 r - MWL_DIAG_BASE_RF, dp);
2300 else if (r < 0x1000 || r == MACREG_REG_FW_PRESENT)
2305 r += sizeof(uint32_t);
2306 space -= sizeof(uint32_t);
2307 } while (r <= e && space >= sizeof(uint32_t));
2309 return (char *) dp - (char *) dstbuf;
2313 mwl_hal_getdiagstate(struct mwl_hal *mh0, int request,
2314 const void *args, uint32_t argsize,
2315 void **result, uint32_t *resultsize)
2317 struct mwl_hal_priv *mh = MWLPRIV(mh0);
2320 case MWL_DIAG_CMD_REVS:
2321 *result = &mh->mh_revs;
2322 *resultsize = sizeof(mh->mh_revs);
2324 case MWL_DIAG_CMD_REGS:
2325 *resultsize = mwl_hal_getregdump(mh, args, *result, *resultsize);
2327 case MWL_DIAG_CMD_HOSTCMD: {
2328 FWCmdHdr *pCmd = (FWCmdHdr *) &mh->mh_cmdbuf[0];
2332 memcpy(pCmd, args, argsize);
2333 retval = mwlExecuteCmd(mh, le16toh(pCmd->Cmd));
2334 *result = (*resultsize != 0) ? pCmd : NULL;
2336 return (retval == 0);
2338 case MWL_DIAG_CMD_FWLOAD:
2339 if (mwl_hal_fwload(mh0, __DECONST(void *, args))) {
2340 device_printf(mh->mh_dev, "problem loading fw image\n");
2349 * Low level firmware cmd block handshake support.
2353 mwlSendCmd(struct mwl_hal_priv *mh)
2357 bus_dmamap_sync(mh->mh_dmat, mh->mh_dmamap,
2358 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2360 WR4(mh, MACREG_REG_GEN_PTR, mh->mh_cmdaddr);
2361 dummy = RD4(mh, MACREG_REG_INT_CODE);
2363 WR4(mh, MACREG_REG_H2A_INTERRUPT_EVENTS, MACREG_H2ARIC_BIT_DOOR_BELL);
2367 mwlWaitForCmdComplete(struct mwl_hal_priv *mh, uint16_t cmdCode)
2369 #define MAX_WAIT_FW_COMPLETE_ITERATIONS 10000
2372 for (i = 0; i < MAX_WAIT_FW_COMPLETE_ITERATIONS; i++) {
2373 if (mh->mh_cmdbuf[0] == le16toh(cmdCode))
2378 #undef MAX_WAIT_FW_COMPLETE_ITERATIONS
2382 mwlExecuteCmd(struct mwl_hal_priv *mh, unsigned short cmd)
2385 MWL_HAL_LOCK_ASSERT(mh);
2387 if ((mh->mh_flags & MHF_FWHANG) &&
2388 (mh->mh_debug & MWL_HAL_DEBUG_IGNHANG) == 0) {
2390 device_printf(mh->mh_dev, "firmware hung, skipping cmd %s\n",
2393 device_printf(mh->mh_dev, "firmware hung, skipping cmd 0x%x\n",
2398 if (RD4(mh, MACREG_REG_INT_CODE) == 0xffffffff) {
2399 device_printf(mh->mh_dev, "%s: device not present!\n",
2404 if (mh->mh_debug & MWL_HAL_DEBUG_SENDCMD)
2408 if (!mwlWaitForCmdComplete(mh, 0x8000 | cmd)) {
2410 device_printf(mh->mh_dev,
2411 "timeout waiting for f/w cmd %s\n", mwlcmdname(cmd));
2413 device_printf(mh->mh_dev,
2414 "timeout waiting for f/w cmd 0x%x\n", cmd);
2416 mh->mh_flags |= MHF_FWHANG;
2419 bus_dmamap_sync(mh->mh_dmat, mh->mh_dmamap,
2420 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2422 if (mh->mh_debug & MWL_HAL_DEBUG_CMDDONE)
2429 * Firmware download support.
2431 #define FW_DOWNLOAD_BLOCK_SIZE 256
2432 #define FW_CHECK_USECS (5*1000) /* 5ms */
2433 #define FW_MAX_NUM_CHECKS 200
2436 /* XXX read f/w from file */
2437 #include <dev/mwl/mwlbootfw.h>
2438 #include <dev/mwl/mwl88W8363fw.h>
2442 mwlFwReset(struct mwl_hal_priv *mh)
2444 if (RD4(mh, MACREG_REG_INT_CODE) == 0xffffffff) {
2445 device_printf(mh->mh_dev, "%s: device not present!\n",
2449 WR4(mh, MACREG_REG_H2A_INTERRUPT_EVENTS, ISR_RESET);
2450 mh->mh_flags &= ~MHF_FWHANG;
2454 mwlTriggerPciCmd(struct mwl_hal_priv *mh)
2458 bus_dmamap_sync(mh->mh_dmat, mh->mh_dmamap, BUS_DMASYNC_PREWRITE);
2460 WR4(mh, MACREG_REG_GEN_PTR, mh->mh_cmdaddr);
2461 dummy = RD4(mh, MACREG_REG_INT_CODE);
2463 WR4(mh, MACREG_REG_INT_CODE, 0x00);
2464 dummy = RD4(mh, MACREG_REG_INT_CODE);
2466 WR4(mh, MACREG_REG_H2A_INTERRUPT_EVENTS, MACREG_H2ARIC_BIT_DOOR_BELL);
2467 dummy = RD4(mh, MACREG_REG_INT_CODE);
2471 mwlWaitFor(struct mwl_hal_priv *mh, uint32_t val)
2475 for (i = 0; i < FW_MAX_NUM_CHECKS; i++) {
2476 DELAY(FW_CHECK_USECS);
2477 if (RD4(mh, MACREG_REG_INT_CODE) == val)
2484 * Firmware block xmit when talking to the boot-rom.
2487 mwlSendBlock(struct mwl_hal_priv *mh, int bsize, const void *data, size_t dsize)
2489 mh->mh_cmdbuf[0] = htole16(HostCmd_CMD_CODE_DNLD);
2490 mh->mh_cmdbuf[1] = htole16(bsize);
2491 memcpy(&mh->mh_cmdbuf[4], data , dsize);
2492 mwlTriggerPciCmd(mh);
2493 /* XXX 2000 vs 200 */
2494 if (mwlWaitFor(mh, MACREG_INT_CODE_CMD_FINISHED)) {
2495 WR4(mh, MACREG_REG_INT_CODE, 0);
2498 device_printf(mh->mh_dev,
2499 "%s: timeout waiting for CMD_FINISHED, INT_CODE 0x%x\n",
2500 __func__, RD4(mh, MACREG_REG_INT_CODE));
2505 * Firmware block xmit when talking to the 1st-stage loader.
2508 mwlSendBlock2(struct mwl_hal_priv *mh, const void *data, size_t dsize)
2510 memcpy(&mh->mh_cmdbuf[0], data, dsize);
2511 mwlTriggerPciCmd(mh);
2512 if (mwlWaitFor(mh, MACREG_INT_CODE_CMD_FINISHED)) {
2513 WR4(mh, MACREG_REG_INT_CODE, 0);
2516 device_printf(mh->mh_dev,
2517 "%s: timeout waiting for CMD_FINISHED, INT_CODE 0x%x\n",
2518 __func__, RD4(mh, MACREG_REG_INT_CODE));
2523 mwlPokeSdramController(struct mwl_hal_priv *mh, int SDRAMSIZE_Addr)
2525 /** Set up sdram controller for superflyv2 **/
2526 WR4(mh, 0x00006014, 0x33);
2527 WR4(mh, 0x00006018, 0xa3a2632);
2528 WR4(mh, 0x00006010, SDRAMSIZE_Addr);
2532 mwl_hal_fwload(struct mwl_hal *mh0, void *fwargs)
2534 struct mwl_hal_priv *mh = MWLPRIV(mh0);
2535 const char *fwname = "mw88W8363fw";
2536 const char *fwbootname = "mwlboot";
2537 const struct firmware *fwboot = NULL;
2538 const struct firmware *fw;
2539 /* XXX get from firmware header */
2540 uint32_t FwReadySignature = HostCmd_SOFTAP_FWRDY_SIGNATURE;
2541 uint32_t OpMode = HostCmd_SOFTAP_MODE;
2542 const uint8_t *fp, *ep;
2543 const uint8_t *fmdata;
2544 uint32_t blocksize, nbytes, fmsize;
2545 int i, error, ntries;
2547 fw = firmware_get(fwname);
2549 device_printf(mh->mh_dev,
2550 "could not load firmware image %s\n", fwname);
2554 fmsize = fw->datasize;
2556 device_printf(mh->mh_dev, "firmware image %s too small\n",
2561 if (fmdata[0] == 0x01 && fmdata[1] == 0x00 &&
2562 fmdata[2] == 0x00 && fmdata[3] == 0x00) {
2564 * 2-stage load, get the boot firmware.
2566 fwboot = firmware_get(fwbootname);
2567 if (fwboot == NULL) {
2568 device_printf(mh->mh_dev,
2569 "could not load firmware image %s\n", fwbootname);
2578 WR4(mh, MACREG_REG_A2H_INTERRUPT_CLEAR_SEL, MACREG_A2HRIC_BIT_MASK);
2579 WR4(mh, MACREG_REG_A2H_INTERRUPT_CAUSE, 0x00);
2580 WR4(mh, MACREG_REG_A2H_INTERRUPT_MASK, 0x00);
2581 WR4(mh, MACREG_REG_A2H_INTERRUPT_STATUS_MASK, MACREG_A2HRIC_BIT_MASK);
2582 if (mh->mh_SDRAMSIZE_Addr != 0) {
2583 /** Set up sdram controller for superflyv2 **/
2584 mwlPokeSdramController(mh, mh->mh_SDRAMSIZE_Addr);
2586 device_printf(mh->mh_dev, "load %s firmware image (%u bytes)\n",
2588 if (fwboot != NULL) {
2590 * Do 2-stage load. The 1st stage loader is setup
2591 * with the bootrom loader then we load the real
2592 * image using a different handshake. With this
2593 * mechanism the firmware is segmented into chunks
2594 * that have a CRC. If a chunk is incorrect we'll
2595 * be told to retransmit.
2597 /* XXX assumes hlpimage fits in a block */
2598 /* NB: zero size block indicates download is finished */
2599 if (!mwlSendBlock(mh, fwboot->datasize, fwboot->data, fwboot->datasize) ||
2600 !mwlSendBlock(mh, 0, NULL, 0)) {
2604 DELAY(200*FW_CHECK_USECS);
2605 if (mh->mh_SDRAMSIZE_Addr != 0) {
2606 /** Set up sdram controller for superflyv2 **/
2607 mwlPokeSdramController(mh, mh->mh_SDRAMSIZE_Addr);
2609 nbytes = ntries = 0; /* NB: silence compiler */
2610 for (fp = fmdata, ep = fp + fmsize; fp < ep; ) {
2611 WR4(mh, MACREG_REG_INT_CODE, 0);
2612 blocksize = RD4(mh, MACREG_REG_SCRATCH);
2613 if (blocksize == 0) /* download complete */
2615 if (blocksize > 0x00000c00) {
2619 if ((blocksize & 0x1) == 0) {
2620 /* block successfully downloaded, advance */
2626 * Guard against f/w telling us to
2632 /* clear NAK bit/flag */
2635 if (blocksize > ep - fp) {
2636 /* XXX this should not happen, what to do? */
2637 blocksize = ep - fp;
2640 if (!mwlSendBlock2(mh, fp, nbytes)) {
2646 for (fp = fmdata, ep = fp + fmsize; fp < ep;) {
2648 if (nbytes > FW_DOWNLOAD_BLOCK_SIZE)
2649 nbytes = FW_DOWNLOAD_BLOCK_SIZE;
2650 if (!mwlSendBlock(mh, FW_DOWNLOAD_BLOCK_SIZE, fp, nbytes)) {
2657 /* done with firmware... */
2659 firmware_put(fwboot, FIRMWARE_UNLOAD);
2660 firmware_put(fw, FIRMWARE_UNLOAD);
2662 * Wait for firmware to startup; we monitor the
2663 * INT_CODE register waiting for a signature to
2664 * written back indicating it's ready to go.
2666 mh->mh_cmdbuf[1] = 0;
2668 * XXX WAR for mfg fw download
2670 if (OpMode != HostCmd_STA_MODE)
2671 mwlTriggerPciCmd(mh);
2672 for (i = 0; i < FW_MAX_NUM_CHECKS; i++) {
2673 WR4(mh, MACREG_REG_GEN_PTR, OpMode);
2674 DELAY(FW_CHECK_USECS);
2675 if (RD4(mh, MACREG_REG_INT_CODE) == FwReadySignature) {
2676 WR4(mh, MACREG_REG_INT_CODE, 0x00);
2677 return mwlResetHalState(mh);
2684 /* done with firmware... */
2686 firmware_put(fwboot, FIRMWARE_UNLOAD);
2687 firmware_put(fw, FIRMWARE_UNLOAD);
2695 static char buf[12];
2696 #define CMD(x) case HostCmd_CMD_##x: return #x
2701 CMD(MAC_MULTICAST_ADR);
2702 CMD(802_11_GET_STAT);
2703 CMD(MAC_REG_ACCESS);
2704 CMD(BBP_REG_ACCESS);
2706 CMD(802_11_RADIO_CONTROL);
2707 CMD(802_11_RF_TX_POWER);
2708 CMD(802_11_RF_ANTENNA);
2710 CMD(SET_RF_CHANNEL);
2712 CMD(SET_INFRA_MODE);
2713 CMD(SET_G_PROTECT_FLAG);
2714 CMD(802_11_RTS_THSD);
2715 CMD(802_11_SET_SLOT);
2716 CMD(SET_EDCA_PARAMS);
2717 CMD(802_11H_DETECT_RADAR);
2719 CMD(HT_GUARD_INTERVAL);
2720 CMD(SET_FIXED_RATE);
2721 CMD(SET_LINKADAPT_CS_MODE);
2723 CMD(SET_RATE_ADAPT_MODE);
2726 CMD(SET_KEEP_ALIVE);
2728 CMD(SET_SWITCH_CHANNEL);
2729 CMD(UPDATE_ENCRYPTION);
2732 CMD(SET_N_PROTECT_FLAG);
2733 CMD(SET_N_PROTECT_OPMODE);
2734 CMD(SET_OPTIMIZATION_LEVEL);
2738 CMD(SET_REGION_CODE);
2739 CMD(SET_POWERSAVESTATION);
2744 CMD(AMPDU_RETRY_RATEDROP_MODE);
2747 snprintf(buf, sizeof(buf), "0x%x", cmd);
2753 dumpresult(struct mwl_hal_priv *mh, int showresult)
2755 const FWCmdHdr *h = (const FWCmdHdr *)mh->mh_cmdbuf;
2759 len = le16toh(h->Length);
2760 #ifdef MWL_MBSS_SUPPORT
2761 device_printf(mh->mh_dev, "Cmd %s Length %d SeqNum %d MacId %d",
2762 mwlcmdname(le16toh(h->Cmd) &~ 0x8000), len, h->SeqNum, h->MacId);
2764 device_printf(mh->mh_dev, "Cmd %s Length %d SeqNum %d",
2765 mwlcmdname(le16toh(h->Cmd) &~ 0x8000), len, le16toh(h->SeqNum));
2768 const char *results[] =
2769 { "OK", "ERROR", "NOT_SUPPORT", "PENDING", "BUSY",
2771 int result = le16toh(h->Result);
2773 if (result <= HostCmd_RESULT_PARTIAL_DATA)
2774 printf(" Result %s", results[result]);
2776 printf(" Result %d", result);
2778 cp = (const uint8_t *)h;
2779 for (i = 0; i < len; i++) {
2781 printf("\n%02x", cp[i]);
2783 printf(" %02x", cp[i]);
2787 #endif /* MWLHAL_DEBUG */