2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2007-2009 Sam Leffler, Errno Consulting
5 * Copyright (c) 2007-2009 Marvell Semiconductor, Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer,
13 * without modification.
14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
15 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
16 * redistribution must be conditioned upon including a substantially
17 * similar Disclaimer requirement for further binary redistribution.
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
23 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
24 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
25 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
28 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGES.
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/sysctl.h>
38 #include <sys/malloc.h>
40 #include <sys/mutex.h>
41 #include <sys/kernel.h>
42 #include <sys/errno.h>
44 #include <sys/endian.h>
46 #include <sys/linker.h>
47 #include <sys/firmware.h>
49 #include <machine/bus.h>
51 #include <dev/mwl/mwlhal.h>
52 #include <dev/mwl/mwlreg.h>
54 #include <sys/socket.h>
55 #include <sys/sockio.h>
57 #include <dev/mwl/mwldiag.h>
59 #define MWLHAL_DEBUG /* debug msgs */
62 WL_ANTENNAMODE_RX = 0xffff,
63 WL_ANTENNAMODE_TX = 2,
67 WL_TX_POWERLEVEL_LOW = 5,
68 WL_TX_POWERLEVEL_MEDIUM = 10,
69 WL_TX_POWERLEVEL_HIGH = 15,
72 #define MWL_CMDBUF_SIZE 0x4000 /* size of f/w command buffer */
73 #define MWL_BASTREAMS_MAX 7 /* max BA streams (NB: fw >3.3.5.9) */
74 #define MWL_BAQID_MAX 8 /* max BA Q id's (NB: fw >3.3.5.9) */
75 #define MWL_MBSS_AP_MAX 8 /* max ap vap's */
76 #define MWL_MBSS_STA_MAX 24 /* max station/client vap's */
77 #define MWL_MBSS_MAX (MWL_MBSS_AP_MAX+MWL_MBSS_STA_MAX)
80 * BA stream -> queue ID mapping
82 * The first 2 streams map to h/w; the remaining streams are
83 * implemented in firmware.
85 static const int ba2qid[MWL_BASTREAMS_MAX] = {
86 5, 6 /* h/w supported */
87 #if MWL_BASTREAMS_MAX == 7
88 , 7, 0, 1, 2, 3 /* f/w supported */
91 static int qid2ba[MWL_BAQID_MAX];
93 #define IEEE80211_ADDR_LEN 6 /* XXX */
94 #define IEEE80211_ADDR_COPY(_dst, _src) \
95 memcpy(_dst, _src, IEEE80211_ADDR_LEN)
96 #define IEEE80211_ADDR_EQ(_dst, _src) \
97 (memcmp(_dst, _src, IEEE80211_ADDR_LEN) == 0)
99 #define _CMD_SETUP(pCmd, type, cmd) do { \
100 pCmd = (type *)&mh->mh_cmdbuf[0]; \
101 memset(pCmd, 0, sizeof(type)); \
102 pCmd->CmdHdr.Cmd = htole16(cmd); \
103 pCmd->CmdHdr.Length = htole16(sizeof(type)); \
106 #define _VCMD_SETUP(vap, pCmd, type, cmd) do { \
107 _CMD_SETUP(pCmd, type, cmd); \
108 pCmd->CmdHdr.MacId = vap->macid; \
111 #define PWTAGETRATETABLE20M 14*4
112 #define PWTAGETRATETABLE40M 9*4
113 #define PWTAGETRATETABLE20M_5G 35*4
114 #define PWTAGETRATETABLE40M_5G 16*4
116 struct mwl_hal_bastream {
117 MWL_HAL_BASTREAM public; /* public state */
118 uint8_t stream; /* stream # */
119 uint8_t setup; /* f/w cmd sent */
120 uint8_t ba_policy; /* direct/delayed BA policy */
123 uint8_t macaddr[IEEE80211_ADDR_LEN];
129 struct mwl_hal_priv *mh; /* back pointer */
130 uint16_t bss_type; /* f/w type */
131 uint8_t vap_type; /* MWL_HAL_BSSTYPE */
132 uint8_t macid; /* for passing to f/w */
134 #define MVF_RUNNING 0x01 /* BSS_START issued */
135 #define MVF_STATION 0x02 /* sta db entry created */
136 uint8_t mac[IEEE80211_ADDR_LEN];/* mac address */
138 #define MWLVAP(_vap) ((_vap)->mh)
141 * Per-device state. We allocate a single cmd buffer for
142 * submitting operations to the firmware. Access to this
143 * buffer (and the f/w) are single-threaded. At present
144 * we spin waiting for cmds to complete which is bad. Not
145 * sure if it's possible to submit multiple requests or
146 * control when we get cmd done interrupts. There's no
147 * documentation and no example code to indicate what can
148 * or cannot be done so all we can do right now is follow the
149 * linux driver logic. This falls apart when the f/w fails;
150 * the system comes to a crawl as we spin waiting for operations
153 struct mwl_hal_priv {
154 struct mwl_hal public; /* public area */
158 bus_dma_tag_t mh_dmat; /* bus DMA tag for cmd buffer */
159 bus_dma_segment_t mh_seg; /* segment for cmd buffer */
160 bus_dmamap_t mh_dmamap; /* DMA map for cmd buffer */
161 uint16_t *mh_cmdbuf; /* f/w cmd buffer */
162 bus_addr_t mh_cmdaddr; /* physaddr of cmd buffer */
164 #define MHF_CALDATA 0x0001 /* cal data retrieved */
165 #define MHF_FWHANG 0x0002 /* fw appears hung */
166 #define MHF_MBSS 0x0004 /* mbss enabled */
167 struct mwl_hal_vap mh_vaps[MWL_MBSS_MAX+1];
168 int mh_bastreams; /* bit mask of available BA streams */
169 int mh_regioncode; /* XXX last region code sent to fw */
170 struct mwl_hal_bastream mh_streams[MWL_BASTREAMS_MAX];
172 MWL_HAL_CHANNELINFO mh_20M;
173 MWL_HAL_CHANNELINFO mh_40M;
174 MWL_HAL_CHANNELINFO mh_20M_5G;
175 MWL_HAL_CHANNELINFO mh_40M_5G;
176 int mh_SDRAMSIZE_Addr;
177 uint32_t mh_RTSSuccesses;/* cumulative stats for read-on-clear */
178 uint32_t mh_RTSFailures;
179 uint32_t mh_RxDuplicateFrames;
180 uint32_t mh_FCSErrorCount;
181 MWL_DIAG_REVS mh_revs;
183 #define MWLPRIV(_mh) ((struct mwl_hal_priv *)(_mh))
185 static int mwl_hal_setmac_locked(struct mwl_hal_vap *,
186 const uint8_t addr[IEEE80211_ADDR_LEN]);
187 static int mwlExecuteCmd(struct mwl_hal_priv *, unsigned short cmd);
188 static int mwlGetPwrCalTable(struct mwl_hal_priv *);
190 static const char *mwlcmdname(int cmd);
191 static void dumpresult(struct mwl_hal_priv *, int showresult);
192 #endif /* MWLHAL_DEBUG */
194 SYSCTL_DECL(_hw_mwl);
195 static SYSCTL_NODE(_hw_mwl, OID_AUTO, hal, CTLFLAG_RD, 0,
196 "Marvell HAL parameters");
199 MWL_HAL_LOCK(struct mwl_hal_priv *mh)
201 mtx_lock(&mh->mh_mtx);
205 MWL_HAL_LOCK_ASSERT(struct mwl_hal_priv *mh)
207 mtx_assert(&mh->mh_mtx, MA_OWNED);
211 MWL_HAL_UNLOCK(struct mwl_hal_priv *mh)
213 mtx_unlock(&mh->mh_mtx);
216 static __inline uint32_t
217 RD4(struct mwl_hal_priv *mh, bus_size_t off)
219 return bus_space_read_4(mh->public.mh_iot, mh->public.mh_ioh, off);
223 WR4(struct mwl_hal_priv *mh, bus_size_t off, uint32_t val)
225 bus_space_write_4(mh->public.mh_iot, mh->public.mh_ioh, off, val);
229 mwl_hal_load_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
231 bus_addr_t *paddr = (bus_addr_t*) arg;
232 KASSERT(error == 0, ("error %u on bus_dma callback", error));
233 *paddr = segs->ds_addr;
237 * Setup for communication with the device. We allocate
238 * a command buffer and map it for bus dma use. The pci
239 * device id is used to identify whether the device has
240 * SRAM on it (in which case f/w download must include a
241 * memory controller reset). All bus i/o operations happen
242 * in BAR 1; the driver passes in the tag and handle we need.
245 mwl_hal_attach(device_t dev, uint16_t devid,
246 bus_space_handle_t ioh, bus_space_tag_t iot, bus_dma_tag_t tag)
248 struct mwl_hal_priv *mh;
249 struct mwl_hal_vap *hvap;
252 mh = malloc(sizeof(struct mwl_hal_priv), M_DEVBUF, M_NOWAIT | M_ZERO);
256 mh->public.mh_ioh = ioh;
257 mh->public.mh_iot = iot;
258 for (i = 0; i < MWL_BASTREAMS_MAX; i++) {
259 mh->mh_streams[i].public.txq = ba2qid[i];
260 mh->mh_streams[i].stream = i;
261 /* construct back-mapping while we're at it */
262 if (mh->mh_streams[i].public.txq < MWL_BAQID_MAX)
263 qid2ba[mh->mh_streams[i].public.txq] = i;
265 device_printf(dev, "unexpected BA tx qid %d for "
266 "stream %d\n", mh->mh_streams[i].public.txq, i);
268 /* setup constant portion of vap state */
269 /* XXX should get max ap/client vap's from f/w */
271 hvap = &mh->mh_vaps[i];
272 hvap->vap_type = MWL_HAL_AP;
273 hvap->bss_type = htole16(WL_MAC_TYPE_PRIMARY_AP);
275 for (i++; i < MWL_MBSS_AP_MAX; i++) {
276 hvap = &mh->mh_vaps[i];
277 hvap->vap_type = MWL_HAL_AP;
278 hvap->bss_type = htole16(WL_MAC_TYPE_SECONDARY_AP);
281 hvap = &mh->mh_vaps[i];
282 hvap->vap_type = MWL_HAL_STA;
283 hvap->bss_type = htole16(WL_MAC_TYPE_PRIMARY_CLIENT);
285 for (i++; i < MWL_MBSS_MAX; i++) {
286 hvap = &mh->mh_vaps[i];
287 hvap->vap_type = MWL_HAL_STA;
288 hvap->bss_type = htole16(WL_MAC_TYPE_SECONDARY_CLIENT);
291 mh->mh_revs.mh_devid = devid;
292 snprintf(mh->mh_mtxname, sizeof(mh->mh_mtxname),
293 "%s_hal", device_get_nameunit(dev));
294 mtx_init(&mh->mh_mtx, mh->mh_mtxname, NULL, MTX_DEF);
297 * Allocate the command buffer and map into the address
298 * space of the h/w. We request "coherent" memory which
299 * will be uncached on some architectures.
301 error = bus_dma_tag_create(tag, /* parent */
302 PAGE_SIZE, 0, /* alignment, bounds */
303 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
304 BUS_SPACE_MAXADDR, /* highaddr */
305 NULL, NULL, /* filter, filterarg */
306 MWL_CMDBUF_SIZE, /* maxsize */
308 MWL_CMDBUF_SIZE, /* maxsegsize */
309 BUS_DMA_ALLOCNOW, /* flags */
314 device_printf(dev, "unable to allocate memory for cmd tag, "
315 "error %u\n", error);
319 /* allocate descriptors */
320 error = bus_dmamem_alloc(mh->mh_dmat, (void**) &mh->mh_cmdbuf,
321 BUS_DMA_NOWAIT | BUS_DMA_COHERENT,
324 device_printf(dev, "unable to allocate memory for cmd buffer, "
325 "error %u\n", error);
329 error = bus_dmamap_load(mh->mh_dmat, mh->mh_dmamap,
330 mh->mh_cmdbuf, MWL_CMDBUF_SIZE,
331 mwl_hal_load_cb, &mh->mh_cmdaddr,
334 device_printf(dev, "unable to load cmd buffer, error %u\n",
340 * Some cards have SDRAM. When loading firmware we need
341 * to reset the SDRAM controller prior to doing this.
342 * When the SDRAMSIZE is non-zero we do that work in
346 case 0x2a02: /* CB82 */
347 case 0x2a03: /* CB85 */
348 case 0x2a08: /* MC85_B1 */
349 case 0x2a0b: /* CB85AP */
351 mh->mh_SDRAMSIZE_Addr = 0x40fe70b7; /* 8M SDRAM */
353 case 0x2a04: /* MC85 */
354 mh->mh_SDRAMSIZE_Addr = 0x40fc70b7; /* 16M SDRAM */
361 bus_dmamem_free(mh->mh_dmat, mh->mh_cmdbuf, mh->mh_dmamap);
363 bus_dma_tag_destroy(mh->mh_dmat);
365 mtx_destroy(&mh->mh_mtx);
371 mwl_hal_detach(struct mwl_hal *mh0)
373 struct mwl_hal_priv *mh = MWLPRIV(mh0);
375 bus_dmamem_free(mh->mh_dmat, mh->mh_cmdbuf, mh->mh_dmamap);
376 bus_dma_tag_destroy(mh->mh_dmat);
377 mtx_destroy(&mh->mh_mtx);
382 * Reset internal state after a firmware download.
385 mwlResetHalState(struct mwl_hal_priv *mh)
389 /* XXX get from f/w */
390 mh->mh_bastreams = (1<<MWL_BASTREAMS_MAX)-1;
391 for (i = 0; i < MWL_MBSS_MAX; i++)
392 mh->mh_vaps[i].mh = NULL;
394 * Clear cumulative stats.
396 mh->mh_RTSSuccesses = 0;
397 mh->mh_RTSFailures = 0;
398 mh->mh_RxDuplicateFrames = 0;
399 mh->mh_FCSErrorCount = 0;
401 * Fetch cal data for later use.
402 * XXX may want to fetch other stuff too.
404 /* XXX check return */
405 if ((mh->mh_flags & MHF_CALDATA) == 0)
406 mwlGetPwrCalTable(mh);
411 mwl_hal_newvap(struct mwl_hal *mh0, MWL_HAL_BSSTYPE type,
412 const uint8_t mac[IEEE80211_ADDR_LEN])
414 struct mwl_hal_priv *mh = MWLPRIV(mh0);
415 struct mwl_hal_vap *vap;
419 /* NB: could optimize but not worth it w/ max 32 bss */
420 for (i = 0; i < MWL_MBSS_MAX; i++) {
421 vap = &mh->mh_vaps[i];
422 if (vap->vap_type == type && vap->mh == NULL) {
424 mwl_hal_setmac_locked(vap, mac);
429 return (i < MWL_MBSS_MAX) ? vap : NULL;
433 mwl_hal_delvap(struct mwl_hal_vap *vap)
435 /* NB: locking not needed for single write */
440 * Manipulate the debug mask. Note debug
441 * msgs are only provided when this code is
442 * compiled with MWLHAL_DEBUG defined.
446 mwl_hal_setdebug(struct mwl_hal *mh, int debug)
448 MWLPRIV(mh)->mh_debug = debug;
452 mwl_hal_getdebug(struct mwl_hal *mh)
454 return MWLPRIV(mh)->mh_debug;
458 mwl_hal_setbastreams(struct mwl_hal *mh, int mask)
460 MWLPRIV(mh)->mh_bastreams = mask & ((1<<MWL_BASTREAMS_MAX)-1);
464 mwl_hal_getbastreams(struct mwl_hal *mh)
466 return MWLPRIV(mh)->mh_bastreams;
470 mwl_hal_ismbsscapable(struct mwl_hal *mh)
472 return (MWLPRIV(mh)->mh_flags & MHF_MBSS) != 0;
478 * Return the current ISR setting and clear the cause.
479 * XXX maybe make inline
482 mwl_hal_getisr(struct mwl_hal *mh0, uint32_t *status)
484 struct mwl_hal_priv *mh = MWLPRIV(mh0);
487 cause = RD4(mh, MACREG_REG_A2H_INTERRUPT_CAUSE);
488 if (cause == 0xffffffff) { /* card removed */
489 device_printf(mh->mh_dev, "%s: cause 0x%x\n", __func__, cause);
491 } else if (cause != 0) {
492 /* clear cause bits */
493 WR4(mh, MACREG_REG_A2H_INTERRUPT_CAUSE,
494 cause &~ mh->public.mh_imask);
495 RD4(mh, MACREG_REG_INT_CODE); /* XXX flush write? */
502 * Set the interrupt mask.
505 mwl_hal_intrset(struct mwl_hal *mh0, uint32_t mask)
507 struct mwl_hal_priv *mh = MWLPRIV(mh0);
509 WR4(mh, MACREG_REG_A2H_INTERRUPT_MASK, 0);
510 RD4(mh, MACREG_REG_INT_CODE);
512 mh->public.mh_imask = mask;
513 WR4(mh, MACREG_REG_A2H_INTERRUPT_MASK, mask);
514 RD4(mh, MACREG_REG_INT_CODE);
520 * Kick the firmware to tell it there are new tx descriptors
521 * for processing. The driver says what h/w q has work in
522 * case the f/w ever gets smarter.
525 mwl_hal_txstart(struct mwl_hal *mh0, int qnum)
527 struct mwl_hal_priv *mh = MWLPRIV(mh0);
530 WR4(mh, MACREG_REG_H2A_INTERRUPT_EVENTS, MACREG_H2ARIC_BIT_PPA_READY);
531 dummy = RD4(mh, MACREG_REG_INT_CODE);
536 * Callback from the driver on a cmd done interrupt.
537 * Nothing to do right now as we spin waiting for
541 mwl_hal_cmddone(struct mwl_hal *mh0)
544 struct mwl_hal_priv *mh = MWLPRIV(mh0);
546 if (mh->mh_debug & MWL_HAL_DEBUG_CMDDONE) {
547 device_printf(mh->mh_dev, "cmd done interrupt:\n");
554 * Return "hw specs". Note this must be the first
555 * cmd MUST be done after a firmware download or the
557 * XXX move into the hal so driver doesn't need to be responsible
560 mwl_hal_gethwspecs(struct mwl_hal *mh0, struct mwl_hal_hwspec *hw)
562 struct mwl_hal_priv *mh = MWLPRIV(mh0);
563 HostCmd_DS_GET_HW_SPEC *pCmd;
567 _CMD_SETUP(pCmd, HostCmd_DS_GET_HW_SPEC, HostCmd_CMD_GET_HW_SPEC);
568 memset(&pCmd->PermanentAddr[0], 0xff, IEEE80211_ADDR_LEN);
569 pCmd->ulFwAwakeCookie = htole32((unsigned int)mh->mh_cmdaddr+2048);
571 retval = mwlExecuteCmd(mh, HostCmd_CMD_GET_HW_SPEC);
573 IEEE80211_ADDR_COPY(hw->macAddr, pCmd->PermanentAddr);
574 hw->wcbBase[0] = le32toh(pCmd->WcbBase0) & 0x0000ffff;
575 hw->wcbBase[1] = le32toh(pCmd->WcbBase1[0]) & 0x0000ffff;
576 hw->wcbBase[2] = le32toh(pCmd->WcbBase1[1]) & 0x0000ffff;
577 hw->wcbBase[3] = le32toh(pCmd->WcbBase1[2]) & 0x0000ffff;
578 hw->rxDescRead = le32toh(pCmd->RxPdRdPtr)& 0x0000ffff;
579 hw->rxDescWrite = le32toh(pCmd->RxPdWrPtr)& 0x0000ffff;
580 hw->regionCode = le16toh(pCmd->RegionCode) & 0x00ff;
581 hw->fwReleaseNumber = le32toh(pCmd->FWReleaseNumber);
582 hw->maxNumWCB = le16toh(pCmd->NumOfWCB);
583 hw->maxNumMCAddr = le16toh(pCmd->NumOfMCastAddr);
584 hw->numAntennas = le16toh(pCmd->NumberOfAntenna);
585 hw->hwVersion = pCmd->Version;
586 hw->hostInterface = pCmd->HostIf;
588 mh->mh_revs.mh_macRev = hw->hwVersion; /* XXX */
589 mh->mh_revs.mh_phyRev = hw->hostInterface; /* XXX */
591 minrev = ((hw->fwReleaseNumber) >> 16) & 0xff;
593 /* starting with 3.4.x.x s/w BA streams supported */
594 mh->mh_bastreams &= (1<<MWL_BASTREAMS_MAX)-1;
596 mh->mh_bastreams &= (1<<2)-1;
603 * Inform the f/w about location of the tx/rx dma data structures
604 * and related state. This cmd must be done immediately after a
605 * mwl_hal_gethwspecs call or the f/w will lockup.
608 mwl_hal_sethwdma(struct mwl_hal *mh0, const struct mwl_hal_txrxdma *dma)
610 struct mwl_hal_priv *mh = MWLPRIV(mh0);
611 HostCmd_DS_SET_HW_SPEC *pCmd;
615 _CMD_SETUP(pCmd, HostCmd_DS_SET_HW_SPEC, HostCmd_CMD_SET_HW_SPEC);
616 pCmd->WcbBase[0] = htole32(dma->wcbBase[0]);
617 pCmd->WcbBase[1] = htole32(dma->wcbBase[1]);
618 pCmd->WcbBase[2] = htole32(dma->wcbBase[2]);
619 pCmd->WcbBase[3] = htole32(dma->wcbBase[3]);
620 pCmd->TxWcbNumPerQueue = htole32(dma->maxNumTxWcb);
621 pCmd->NumTxQueues = htole32(dma->maxNumWCB);
622 pCmd->TotalRxWcb = htole32(1); /* XXX */
623 pCmd->RxPdWrPtr = htole32(dma->rxDescRead);
624 pCmd->Flags = htole32(SET_HW_SPEC_HOSTFORM_BEACON
625 #ifdef MWL_HOST_PS_SUPPORT
626 | SET_HW_SPEC_HOST_POWERSAVE
628 | SET_HW_SPEC_HOSTFORM_PROBERESP);
629 /* disable multi-bss operation for A1-A4 parts */
630 if (mh->mh_revs.mh_macRev < 5)
631 pCmd->Flags |= htole32(SET_HW_SPEC_DISABLEMBSS);
633 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_HW_SPEC);
635 if (pCmd->Flags & htole32(SET_HW_SPEC_DISABLEMBSS))
636 mh->mh_flags &= ~MHF_MBSS;
638 mh->mh_flags |= MHF_MBSS;
645 * Retrieve statistics from the f/w.
646 * XXX should be in memory shared w/ driver
649 mwl_hal_gethwstats(struct mwl_hal *mh0, struct mwl_hal_hwstats *stats)
651 struct mwl_hal_priv *mh = MWLPRIV(mh0);
652 HostCmd_DS_802_11_GET_STAT *pCmd;
656 _CMD_SETUP(pCmd, HostCmd_DS_802_11_GET_STAT,
657 HostCmd_CMD_802_11_GET_STAT);
659 retval = mwlExecuteCmd(mh, HostCmd_CMD_802_11_GET_STAT);
661 const uint32_t *sp = (const uint32_t *)&pCmd->TxRetrySuccesses;
662 uint32_t *dp = (uint32_t *)&stats->TxRetrySuccesses;
665 for (i = 0; i < sizeof(*stats)/sizeof(uint32_t); i++)
666 dp[i] = le32toh(sp[i]);
668 * Update stats not returned by f/w but available
669 * through public registers. Note these registers
670 * are "clear on read" so we maintain cumulative data.
671 * XXX register defines
673 mh->mh_RTSSuccesses += RD4(mh, 0xa834);
674 mh->mh_RTSFailures += RD4(mh, 0xa830);
675 mh->mh_RxDuplicateFrames += RD4(mh, 0xa84c);
676 mh->mh_FCSErrorCount += RD4(mh, 0xa840);
680 stats->RTSSuccesses = mh->mh_RTSSuccesses;
681 stats->RTSFailures = mh->mh_RTSFailures;
682 stats->RxDuplicateFrames = mh->mh_RxDuplicateFrames;
683 stats->FCSErrorCount = mh->mh_FCSErrorCount;
688 * Set HT guard interval handling.
689 * Takes effect immediately.
692 mwl_hal_sethtgi(struct mwl_hal_vap *vap, int GIType)
694 struct mwl_hal_priv *mh = MWLVAP(vap);
695 HostCmd_FW_HT_GUARD_INTERVAL *pCmd;
699 _VCMD_SETUP(vap, pCmd, HostCmd_FW_HT_GUARD_INTERVAL,
700 HostCmd_CMD_HT_GUARD_INTERVAL);
701 pCmd->Action = htole32(HostCmd_ACT_GEN_SET);
704 pCmd->GIType = htole32(GI_TYPE_LONG);
705 } else if (GIType == 1) {
706 pCmd->GIType = htole32(GI_TYPE_LONG | GI_TYPE_SHORT);
708 pCmd->GIType = htole32(GI_TYPE_LONG);
711 retval = mwlExecuteCmd(mh, HostCmd_CMD_HT_GUARD_INTERVAL);
718 * Takes effect immediately.
719 * XXX preamble installed after set fixed rate cmd
722 mwl_hal_setradio(struct mwl_hal *mh0, int onoff, MWL_HAL_PREAMBLE preamble)
724 struct mwl_hal_priv *mh = MWLPRIV(mh0);
725 HostCmd_DS_802_11_RADIO_CONTROL *pCmd;
729 _CMD_SETUP(pCmd, HostCmd_DS_802_11_RADIO_CONTROL,
730 HostCmd_CMD_802_11_RADIO_CONTROL);
731 pCmd->Action = htole16(HostCmd_ACT_GEN_SET);
735 pCmd->Control = htole16(preamble);
736 pCmd->RadioOn = htole16(onoff);
738 retval = mwlExecuteCmd(mh, HostCmd_CMD_802_11_RADIO_CONTROL);
744 * Configure antenna use.
745 * Takes effect immediately.
746 * XXX tx antenna setting ignored
747 * XXX rx antenna setting should always be 3 (for now)
750 mwl_hal_setantenna(struct mwl_hal *mh0, MWL_HAL_ANTENNA dirSet, int ant)
752 struct mwl_hal_priv *mh = MWLPRIV(mh0);
753 HostCmd_DS_802_11_RF_ANTENNA *pCmd;
756 if (!(dirSet == WL_ANTENNATYPE_RX || dirSet == WL_ANTENNATYPE_TX))
760 _CMD_SETUP(pCmd, HostCmd_DS_802_11_RF_ANTENNA,
761 HostCmd_CMD_802_11_RF_ANTENNA);
762 pCmd->Action = htole16(dirSet);
763 if (ant == 0) /* default to all/both antennae */
765 pCmd->AntennaMode = htole16(ant);
767 retval = mwlExecuteCmd(mh, HostCmd_CMD_802_11_RF_ANTENNA);
773 * Set packet size threshold for implicit use of RTS.
774 * Takes effect immediately.
775 * XXX packet length > threshold =>'s RTS
778 mwl_hal_setrtsthreshold(struct mwl_hal_vap *vap, int threshold)
780 struct mwl_hal_priv *mh = MWLVAP(vap);
781 HostCmd_DS_802_11_RTS_THSD *pCmd;
785 _VCMD_SETUP(vap, pCmd, HostCmd_DS_802_11_RTS_THSD,
786 HostCmd_CMD_802_11_RTS_THSD);
787 pCmd->Action = htole16(HostCmd_ACT_GEN_SET);
788 pCmd->Threshold = htole16(threshold);
790 retval = mwlExecuteCmd(mh, HostCmd_CMD_802_11_RTS_THSD);
796 * Enable sta-mode operation (disables beacon frame xmit).
799 mwl_hal_setinframode(struct mwl_hal_vap *vap)
801 struct mwl_hal_priv *mh = MWLVAP(vap);
802 HostCmd_FW_SET_INFRA_MODE *pCmd;
806 _VCMD_SETUP(vap, pCmd, HostCmd_FW_SET_INFRA_MODE,
807 HostCmd_CMD_SET_INFRA_MODE);
809 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_INFRA_MODE);
815 * Configure radar detection in support of 802.11h.
818 mwl_hal_setradardetection(struct mwl_hal *mh0, MWL_HAL_RADAR action)
820 struct mwl_hal_priv *mh = MWLPRIV(mh0);
821 HostCmd_802_11h_Detect_Radar *pCmd;
825 _CMD_SETUP(pCmd, HostCmd_802_11h_Detect_Radar,
826 HostCmd_CMD_802_11H_DETECT_RADAR);
827 pCmd->CmdHdr.Length = htole16(sizeof(HostCmd_802_11h_Detect_Radar));
828 pCmd->Action = htole16(action);
829 if (mh->mh_regioncode == DOMAIN_CODE_ETSI_131)
830 pCmd->RadarTypeCode = htole16(131);
832 retval = mwlExecuteCmd(mh, HostCmd_CMD_802_11H_DETECT_RADAR);
838 * Convert public channel flags definition to a
839 * value suitable for feeding to the firmware.
840 * Note this includes byte swapping.
843 cvtChannelFlags(const MWL_HAL_CHANNEL *chan)
848 * NB: f/w only understands FREQ_BAND_5GHZ, supplying the more
849 * precise band info causes it to lockup (sometimes).
851 w = (chan->channelFlags.FreqBand == MWL_FREQ_BAND_2DOT4GHZ) ?
852 FREQ_BAND_2DOT4GHZ : FREQ_BAND_5GHZ;
853 switch (chan->channelFlags.ChnlWidth) {
854 case MWL_CH_10_MHz_WIDTH:
855 w |= CH_10_MHz_WIDTH;
857 case MWL_CH_20_MHz_WIDTH:
858 w |= CH_20_MHz_WIDTH;
860 case MWL_CH_40_MHz_WIDTH:
862 w |= CH_40_MHz_WIDTH;
865 switch (chan->channelFlags.ExtChnlOffset) {
866 case MWL_EXT_CH_NONE:
869 case MWL_EXT_CH_ABOVE_CTRL_CH:
870 w |= EXT_CH_ABOVE_CTRL_CH;
872 case MWL_EXT_CH_BELOW_CTRL_CH:
873 w |= EXT_CH_BELOW_CTRL_CH;
880 * Start a channel switch announcement countdown. The IE
881 * in the beacon frame is allowed to go out and the firmware
882 * counts down and notifies the host when it's time to switch
886 mwl_hal_setchannelswitchie(struct mwl_hal *mh0,
887 const MWL_HAL_CHANNEL *nextchan, uint32_t mode, uint32_t count)
889 struct mwl_hal_priv *mh = MWLPRIV(mh0);
890 HostCmd_SET_SWITCH_CHANNEL *pCmd;
894 _CMD_SETUP(pCmd, HostCmd_SET_SWITCH_CHANNEL,
895 HostCmd_CMD_SET_SWITCH_CHANNEL);
896 pCmd->Next11hChannel = htole32(nextchan->channel);
897 pCmd->Mode = htole32(mode);
898 pCmd->InitialCount = htole32(count+1);
899 pCmd->ChannelFlags = cvtChannelFlags(nextchan);
901 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_SWITCH_CHANNEL);
907 * Set the region code that selects the radar bin'ing agorithm.
910 mwl_hal_setregioncode(struct mwl_hal *mh0, int regionCode)
912 struct mwl_hal_priv *mh = MWLPRIV(mh0);
913 HostCmd_SET_REGIONCODE_INFO *pCmd;
917 _CMD_SETUP(pCmd, HostCmd_SET_REGIONCODE_INFO,
918 HostCmd_CMD_SET_REGION_CODE);
919 /* XXX map pseudo-codes to fw codes */
920 switch (regionCode) {
921 case DOMAIN_CODE_ETSI_131:
922 pCmd->regionCode = htole16(DOMAIN_CODE_ETSI);
925 pCmd->regionCode = htole16(regionCode);
929 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_REGION_CODE);
931 mh->mh_regioncode = regionCode;
936 #define RATEVAL(r) ((r) &~ RATE_MCS)
937 #define RATETYPE(r) (((r) & RATE_MCS) ? HT_RATE_TYPE : LEGACY_RATE_TYPE)
940 mwl_hal_settxrate(struct mwl_hal_vap *vap, MWL_HAL_TXRATE_HANDLING handling,
941 const MWL_HAL_TXRATE *rate)
943 struct mwl_hal_priv *mh = MWLVAP(vap);
944 HostCmd_FW_USE_FIXED_RATE *pCmd;
945 FIXED_RATE_ENTRY *fp;
949 _VCMD_SETUP(vap, pCmd, HostCmd_FW_USE_FIXED_RATE,
950 HostCmd_CMD_SET_FIXED_RATE);
952 pCmd->MulticastRate = RATEVAL(rate->McastRate);
953 pCmd->MultiRateTxType = RATETYPE(rate->McastRate);
954 /* NB: no rate type field */
955 pCmd->ManagementRate = RATEVAL(rate->MgtRate);
956 memset(pCmd->FixedRateTable, 0, sizeof(pCmd->FixedRateTable));
957 if (handling == RATE_FIXED) {
958 pCmd->Action = htole32(HostCmd_ACT_GEN_SET);
959 pCmd->AllowRateDrop = htole32(FIXED_RATE_WITHOUT_AUTORATE_DROP);
960 fp = pCmd->FixedRateTable;
962 htole32(RATEVAL(rate->RateSeries[0].Rate));
963 fp->FixRateTypeFlags.FixRateType =
964 htole32(RATETYPE(rate->RateSeries[0].Rate));
965 pCmd->EntryCount = htole32(1);
966 } else if (handling == RATE_FIXED_DROP) {
967 pCmd->Action = htole32(HostCmd_ACT_GEN_SET);
968 pCmd->AllowRateDrop = htole32(FIXED_RATE_WITH_AUTO_RATE_DROP);
970 fp = pCmd->FixedRateTable;
971 for (i = 0; i < 4; i++) {
972 if (rate->RateSeries[0].TryCount == 0)
974 fp->FixRateTypeFlags.FixRateType =
975 htole32(RATETYPE(rate->RateSeries[i].Rate));
977 htole32(RATEVAL(rate->RateSeries[i].Rate));
978 fp->FixRateTypeFlags.RetryCountValid =
979 htole32(RETRY_COUNT_VALID);
981 htole32(rate->RateSeries[i].TryCount-1);
984 pCmd->EntryCount = htole32(n);
986 pCmd->Action = htole32(HostCmd_ACT_NOT_USE_FIXED_RATE);
988 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_FIXED_RATE);
994 mwl_hal_settxrate_auto(struct mwl_hal *mh0, const MWL_HAL_TXRATE *rate)
996 struct mwl_hal_priv *mh = MWLPRIV(mh0);
997 HostCmd_FW_USE_FIXED_RATE *pCmd;
1001 _CMD_SETUP(pCmd, HostCmd_FW_USE_FIXED_RATE,
1002 HostCmd_CMD_SET_FIXED_RATE);
1004 pCmd->MulticastRate = RATEVAL(rate->McastRate);
1005 pCmd->MultiRateTxType = RATETYPE(rate->McastRate);
1006 /* NB: no rate type field */
1007 pCmd->ManagementRate = RATEVAL(rate->MgtRate);
1008 memset(pCmd->FixedRateTable, 0, sizeof(pCmd->FixedRateTable));
1009 pCmd->Action = htole32(HostCmd_ACT_NOT_USE_FIXED_RATE);
1011 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_FIXED_RATE);
1020 mwl_hal_setslottime(struct mwl_hal *mh0, int usecs)
1022 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1023 HostCmd_FW_SET_SLOT *pCmd;
1026 if (usecs != 9 && usecs != 20)
1030 _CMD_SETUP(pCmd, HostCmd_FW_SET_SLOT,
1031 HostCmd_CMD_802_11_SET_SLOT);
1032 pCmd->Action = htole16(HostCmd_ACT_GEN_SET);
1033 pCmd->Slot = (usecs == 9 ? 1 : 0);
1035 retval = mwlExecuteCmd(mh, HostCmd_CMD_802_11_SET_SLOT);
1041 mwl_hal_adjusttxpower(struct mwl_hal *mh0, uint32_t level)
1043 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1044 HostCmd_DS_802_11_RF_TX_POWER *pCmd;
1048 _CMD_SETUP(pCmd, HostCmd_DS_802_11_RF_TX_POWER,
1049 HostCmd_CMD_802_11_RF_TX_POWER);
1050 pCmd->Action = htole16(HostCmd_ACT_GEN_SET);
1053 pCmd->SupportTxPowerLevel = htole16(WL_TX_POWERLEVEL_LOW);
1054 } else if (level >= 30 && level < 60) {
1055 pCmd->SupportTxPowerLevel = htole16(WL_TX_POWERLEVEL_MEDIUM);
1057 pCmd->SupportTxPowerLevel = htole16(WL_TX_POWERLEVEL_HIGH);
1060 retval = mwlExecuteCmd(mh, HostCmd_CMD_802_11_RF_TX_POWER);
1065 static const struct mwl_hal_channel *
1066 findchannel(const struct mwl_hal_priv *mh, const MWL_HAL_CHANNEL *c)
1068 const struct mwl_hal_channel *hc;
1069 const MWL_HAL_CHANNELINFO *ci;
1070 int chan = c->channel, i;
1072 if (c->channelFlags.FreqBand == MWL_FREQ_BAND_2DOT4GHZ) {
1074 if (c->channelFlags.ChnlWidth == MWL_CH_40_MHz_WIDTH) {
1076 if (c->channelFlags.ExtChnlOffset == MWL_EXT_CH_BELOW_CTRL_CH)
1080 /* 2.4G channel table is directly indexed */
1081 hc = ((unsigned)i < ci->nchannels) ? &ci->channels[i] : NULL;
1082 } else if (c->channelFlags.FreqBand == MWL_FREQ_BAND_5GHZ) {
1083 if (c->channelFlags.ChnlWidth == MWL_CH_40_MHz_WIDTH) {
1084 ci = &mh->mh_40M_5G;
1085 if (c->channelFlags.ExtChnlOffset == MWL_EXT_CH_BELOW_CTRL_CH)
1088 ci = &mh->mh_20M_5G;
1089 /* 5GHz channel table is sparse and must be searched */
1090 for (i = 0; i < ci->nchannels; i++)
1091 if (ci->channels[i].ieee == chan)
1093 hc = (i < ci->nchannels) ? &ci->channels[i] : NULL;
1100 mwl_hal_settxpower(struct mwl_hal *mh0, const MWL_HAL_CHANNEL *c, uint8_t maxtxpow)
1102 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1103 HostCmd_DS_802_11_RF_TX_POWER *pCmd;
1104 const struct mwl_hal_channel *hc;
1107 hc = findchannel(mh, c);
1109 /* XXX temp while testing */
1110 device_printf(mh->mh_dev,
1111 "%s: no cal data for channel %u band %u width %u ext %u\n",
1112 __func__, c->channel, c->channelFlags.FreqBand,
1113 c->channelFlags.ChnlWidth, c->channelFlags.ExtChnlOffset);
1118 _CMD_SETUP(pCmd, HostCmd_DS_802_11_RF_TX_POWER,
1119 HostCmd_CMD_802_11_RF_TX_POWER);
1120 pCmd->Action = htole16(HostCmd_ACT_GEN_SET_LIST);
1122 /* NB: 5Ghz cal data have the channel # in [0]; don't truncate */
1123 if (c->channelFlags.FreqBand == MWL_FREQ_BAND_5GHZ)
1124 pCmd->PowerLevelList[i++] = htole16(hc->targetPowers[0]);
1125 for (; i < 4; i++) {
1126 uint16_t pow = hc->targetPowers[i];
1129 pCmd->PowerLevelList[i] = htole16(pow);
1131 retval = mwlExecuteCmd(mh, HostCmd_CMD_802_11_RF_TX_POWER);
1137 mwl_hal_getchannelinfo(struct mwl_hal *mh0, int band, int chw,
1138 const MWL_HAL_CHANNELINFO **ci)
1140 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1143 case MWL_FREQ_BAND_2DOT4GHZ:
1144 *ci = (chw == MWL_CH_20_MHz_WIDTH) ? &mh->mh_20M : &mh->mh_40M;
1146 case MWL_FREQ_BAND_5GHZ:
1147 *ci = (chw == MWL_CH_20_MHz_WIDTH) ?
1148 &mh->mh_20M_5G : &mh->mh_40M_5G;
1153 return ((*ci)->freqLow == (*ci)->freqHigh) ? EINVAL : 0;
1157 mwl_hal_setmcast(struct mwl_hal *mh0, int nmc, const uint8_t macs[])
1159 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1160 HostCmd_DS_MAC_MULTICAST_ADR *pCmd;
1163 if (nmc > MWL_HAL_MCAST_MAX)
1167 _CMD_SETUP(pCmd, HostCmd_DS_MAC_MULTICAST_ADR,
1168 HostCmd_CMD_MAC_MULTICAST_ADR);
1169 memcpy(pCmd->MACList, macs, nmc*IEEE80211_ADDR_LEN);
1170 pCmd->NumOfAdrs = htole16(nmc);
1171 pCmd->Action = htole16(0xffff);
1173 retval = mwlExecuteCmd(mh, HostCmd_CMD_MAC_MULTICAST_ADR);
1179 mwl_hal_keyset(struct mwl_hal_vap *vap, const MWL_HAL_KEYVAL *kv,
1180 const uint8_t mac[IEEE80211_ADDR_LEN])
1182 struct mwl_hal_priv *mh = MWLVAP(vap);
1183 HostCmd_FW_UPDATE_ENCRYPTION_SET_KEY *pCmd;
1187 _VCMD_SETUP(vap, pCmd, HostCmd_FW_UPDATE_ENCRYPTION_SET_KEY,
1188 HostCmd_CMD_UPDATE_ENCRYPTION);
1189 if (kv->keyFlags & (KEY_FLAG_TXGROUPKEY|KEY_FLAG_RXGROUPKEY))
1190 pCmd->ActionType = htole32(EncrActionTypeSetGroupKey);
1192 pCmd->ActionType = htole32(EncrActionTypeSetKey);
1193 pCmd->KeyParam.Length = htole16(sizeof(pCmd->KeyParam));
1194 pCmd->KeyParam.KeyTypeId = htole16(kv->keyTypeId);
1195 pCmd->KeyParam.KeyInfo = htole32(kv->keyFlags);
1196 pCmd->KeyParam.KeyIndex = htole32(kv->keyIndex);
1197 /* NB: includes TKIP MIC keys */
1198 memcpy(&pCmd->KeyParam.Key, &kv->key, kv->keyLen);
1199 switch (kv->keyTypeId) {
1200 case KEY_TYPE_ID_WEP:
1201 pCmd->KeyParam.KeyLen = htole16(kv->keyLen);
1203 case KEY_TYPE_ID_TKIP:
1204 pCmd->KeyParam.KeyLen = htole16(sizeof(TKIP_TYPE_KEY));
1205 pCmd->KeyParam.Key.TkipKey.TkipRsc.low =
1206 htole16(kv->key.tkip.rsc.low);
1207 pCmd->KeyParam.Key.TkipKey.TkipRsc.high =
1208 htole32(kv->key.tkip.rsc.high);
1209 pCmd->KeyParam.Key.TkipKey.TkipTsc.low =
1210 htole16(kv->key.tkip.tsc.low);
1211 pCmd->KeyParam.Key.TkipKey.TkipTsc.high =
1212 htole32(kv->key.tkip.tsc.high);
1214 case KEY_TYPE_ID_AES:
1215 pCmd->KeyParam.KeyLen = htole16(sizeof(AES_TYPE_KEY));
1218 #ifdef MWL_MBSS_SUPPORT
1219 IEEE80211_ADDR_COPY(pCmd->KeyParam.Macaddr, mac);
1221 IEEE80211_ADDR_COPY(pCmd->Macaddr, mac);
1223 retval = mwlExecuteCmd(mh, HostCmd_CMD_UPDATE_ENCRYPTION);
1229 mwl_hal_keyreset(struct mwl_hal_vap *vap, const MWL_HAL_KEYVAL *kv, const uint8_t mac[IEEE80211_ADDR_LEN])
1231 struct mwl_hal_priv *mh = MWLVAP(vap);
1232 HostCmd_FW_UPDATE_ENCRYPTION_SET_KEY *pCmd;
1236 _VCMD_SETUP(vap, pCmd, HostCmd_FW_UPDATE_ENCRYPTION_SET_KEY,
1237 HostCmd_CMD_UPDATE_ENCRYPTION);
1238 pCmd->ActionType = htole16(EncrActionTypeRemoveKey);
1239 pCmd->KeyParam.Length = htole16(sizeof(pCmd->KeyParam));
1240 pCmd->KeyParam.KeyTypeId = htole16(kv->keyTypeId);
1241 pCmd->KeyParam.KeyInfo = htole32(kv->keyFlags);
1242 pCmd->KeyParam.KeyIndex = htole32(kv->keyIndex);
1243 #ifdef MWL_MBSS_SUPPORT
1244 IEEE80211_ADDR_COPY(pCmd->KeyParam.Macaddr, mac);
1246 IEEE80211_ADDR_COPY(pCmd->Macaddr, mac);
1248 retval = mwlExecuteCmd(mh, HostCmd_CMD_UPDATE_ENCRYPTION);
1254 mwl_hal_setmac_locked(struct mwl_hal_vap *vap,
1255 const uint8_t addr[IEEE80211_ADDR_LEN])
1257 struct mwl_hal_priv *mh = MWLVAP(vap);
1258 HostCmd_DS_SET_MAC *pCmd;
1260 _VCMD_SETUP(vap, pCmd, HostCmd_DS_SET_MAC, HostCmd_CMD_SET_MAC_ADDR);
1261 IEEE80211_ADDR_COPY(&pCmd->MacAddr[0], addr);
1262 #ifdef MWL_MBSS_SUPPORT
1263 pCmd->MacType = vap->bss_type; /* NB: already byte swapped */
1264 IEEE80211_ADDR_COPY(vap->mac, addr); /* XXX do only if success */
1266 return mwlExecuteCmd(mh, HostCmd_CMD_SET_MAC_ADDR);
1270 mwl_hal_setmac(struct mwl_hal_vap *vap, const uint8_t addr[IEEE80211_ADDR_LEN])
1272 struct mwl_hal_priv *mh = MWLVAP(vap);
1276 retval = mwl_hal_setmac_locked(vap, addr);
1282 mwl_hal_setbeacon(struct mwl_hal_vap *vap, const void *frame, size_t frameLen)
1284 struct mwl_hal_priv *mh = MWLVAP(vap);
1285 HostCmd_DS_SET_BEACON *pCmd;
1288 /* XXX verify frameLen fits */
1290 _VCMD_SETUP(vap, pCmd, HostCmd_DS_SET_BEACON, HostCmd_CMD_SET_BEACON);
1291 /* XXX override _VCMD_SETUP */
1292 pCmd->CmdHdr.Length = htole16(sizeof(HostCmd_DS_SET_BEACON)-1+frameLen);
1293 pCmd->FrmBodyLen = htole16(frameLen);
1294 memcpy(pCmd->FrmBody, frame, frameLen);
1296 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_BEACON);
1302 mwl_hal_setpowersave_bss(struct mwl_hal_vap *vap, uint8_t nsta)
1304 struct mwl_hal_priv *mh = MWLVAP(vap);
1305 HostCmd_SET_POWERSAVESTATION *pCmd;
1309 _VCMD_SETUP(vap, pCmd, HostCmd_SET_POWERSAVESTATION,
1310 HostCmd_CMD_SET_POWERSAVESTATION);
1311 pCmd->NumberOfPowersave = nsta;
1313 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_POWERSAVESTATION);
1319 mwl_hal_setpowersave_sta(struct mwl_hal_vap *vap, uint16_t aid, int ena)
1321 struct mwl_hal_priv *mh = MWLVAP(vap);
1322 HostCmd_SET_TIM *pCmd;
1326 _VCMD_SETUP(vap, pCmd, HostCmd_SET_TIM, HostCmd_CMD_SET_TIM);
1327 pCmd->Aid = htole16(aid);
1328 pCmd->Set = htole32(ena);
1330 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_TIM);
1336 mwl_hal_setassocid(struct mwl_hal_vap *vap,
1337 const uint8_t bssId[IEEE80211_ADDR_LEN], uint16_t assocId)
1339 struct mwl_hal_priv *mh = MWLVAP(vap);
1340 HostCmd_FW_SET_AID *pCmd = (HostCmd_FW_SET_AID *) &mh->mh_cmdbuf[0];
1344 _VCMD_SETUP(vap, pCmd, HostCmd_FW_SET_AID, HostCmd_CMD_SET_AID);
1345 pCmd->AssocID = htole16(assocId);
1346 IEEE80211_ADDR_COPY(&pCmd->MacAddr[0], bssId);
1348 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_AID);
1354 mwl_hal_setchannel(struct mwl_hal *mh0, const MWL_HAL_CHANNEL *chan)
1356 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1357 HostCmd_FW_SET_RF_CHANNEL *pCmd;
1361 _CMD_SETUP(pCmd, HostCmd_FW_SET_RF_CHANNEL, HostCmd_CMD_SET_RF_CHANNEL);
1362 pCmd->Action = htole16(HostCmd_ACT_GEN_SET);
1363 pCmd->CurrentChannel = chan->channel;
1364 pCmd->ChannelFlags = cvtChannelFlags(chan); /* NB: byte-swapped */
1366 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_RF_CHANNEL);
1372 bastream_check_available(struct mwl_hal_vap *vap, int qid,
1373 const uint8_t Macaddr[IEEE80211_ADDR_LEN],
1374 uint8_t Tid, uint8_t ParamInfo)
1376 struct mwl_hal_priv *mh = MWLVAP(vap);
1377 HostCmd_FW_BASTREAM *pCmd;
1380 MWL_HAL_LOCK_ASSERT(mh);
1382 _VCMD_SETUP(vap, pCmd, HostCmd_FW_BASTREAM, HostCmd_CMD_BASTREAM);
1383 pCmd->ActionType = htole32(BaCheckCreateStream);
1384 pCmd->BaInfo.CreateParams.BarThrs = htole32(63);
1385 pCmd->BaInfo.CreateParams.WindowSize = htole32(64);
1386 pCmd->BaInfo.CreateParams.IdleThrs = htole32(0x22000);
1387 IEEE80211_ADDR_COPY(&pCmd->BaInfo.CreateParams.PeerMacAddr[0], Macaddr);
1388 pCmd->BaInfo.CreateParams.DialogToken = 10;
1389 pCmd->BaInfo.CreateParams.Tid = Tid;
1390 pCmd->BaInfo.CreateParams.QueueId = qid;
1391 pCmd->BaInfo.CreateParams.ParamInfo = (uint8_t) ParamInfo;
1393 cvtBAFlags(&pCmd->BaInfo.CreateParams.Flags, sp->ba_policy, 0);
1395 pCmd->BaInfo.CreateParams.Flags =
1396 htole32(BASTREAM_FLAG_IMMEDIATE_TYPE)
1397 | htole32(BASTREAM_FLAG_DIRECTION_UPSTREAM)
1401 retval = mwlExecuteCmd(mh, HostCmd_CMD_BASTREAM);
1404 * NB: BA stream create may fail when the stream is
1405 * h/w backed under some (as yet not understood) conditions.
1406 * Check the result code to catch this.
1408 if (le16toh(pCmd->CmdHdr.Result) != HostCmd_RESULT_OK)
1414 const MWL_HAL_BASTREAM *
1415 mwl_hal_bastream_alloc(struct mwl_hal_vap *vap, int ba_policy,
1416 const uint8_t Macaddr[IEEE80211_ADDR_LEN],
1417 uint8_t Tid, uint8_t ParamInfo, void *a1, void *a2)
1419 struct mwl_hal_priv *mh = MWLVAP(vap);
1420 struct mwl_hal_bastream *sp;
1424 if (mh->mh_bastreams == 0) {
1425 /* no streams available */
1429 for (s = 0; (mh->mh_bastreams & (1<<s)) == 0; s++)
1431 if (bastream_check_available(vap, s, Macaddr, Tid, ParamInfo)) {
1435 sp = &mh->mh_streams[s];
1436 mh->mh_bastreams &= ~(1<<s);
1437 sp->public.data[0] = a1;
1438 sp->public.data[1] = a2;
1439 IEEE80211_ADDR_COPY(sp->macaddr, Macaddr);
1441 sp->paraminfo = ParamInfo;
1443 sp->ba_policy = ba_policy;
1448 const MWL_HAL_BASTREAM *
1449 mwl_hal_bastream_lookup(struct mwl_hal *mh0, int s)
1451 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1453 if (!(0 <= s && s < MWL_BASTREAMS_MAX))
1455 if (mh->mh_bastreams & (1<<s))
1457 return &mh->mh_streams[s].public;
1461 #define __DECONST(type, var) ((type)(uintptr_t)(const void *)(var))
1465 mwl_hal_bastream_create(struct mwl_hal_vap *vap,
1466 const MWL_HAL_BASTREAM *s, int BarThrs, int WindowSize, uint16_t seqno)
1468 struct mwl_hal_priv *mh = MWLVAP(vap);
1469 struct mwl_hal_bastream *sp = __DECONST(struct mwl_hal_bastream *, s);
1470 HostCmd_FW_BASTREAM *pCmd;
1474 _VCMD_SETUP(vap, pCmd, HostCmd_FW_BASTREAM, HostCmd_CMD_BASTREAM);
1475 pCmd->ActionType = htole32(BaCreateStream);
1476 pCmd->BaInfo.CreateParams.BarThrs = htole32(BarThrs);
1477 pCmd->BaInfo.CreateParams.WindowSize = htole32(WindowSize);
1478 pCmd->BaInfo.CreateParams.IdleThrs = htole32(0x22000);
1479 IEEE80211_ADDR_COPY(&pCmd->BaInfo.CreateParams.PeerMacAddr[0],
1482 memset(&pCmd->BaInfo.CreateParams.StaSrcMacAddr, 0, IEEE80211_ADDR_LEN);
1484 pCmd->BaInfo.CreateParams.DialogToken = DialogToken;
1486 pCmd->BaInfo.CreateParams.DialogToken = 10;
1488 pCmd->BaInfo.CreateParams.Tid = sp->tid;
1489 pCmd->BaInfo.CreateParams.QueueId = sp->stream;
1490 pCmd->BaInfo.CreateParams.ParamInfo = sp->paraminfo;
1491 /* NB: ResetSeqNo known to be zero */
1492 pCmd->BaInfo.CreateParams.StartSeqNo = htole16(seqno);
1494 cvtBAFlags(&pCmd->BaInfo.CreateParams.Flags, sp->ba_policy, 0);
1496 pCmd->BaInfo.CreateParams.Flags =
1497 htole32(BASTREAM_FLAG_IMMEDIATE_TYPE)
1498 | htole32(BASTREAM_FLAG_DIRECTION_UPSTREAM)
1502 retval = mwlExecuteCmd(mh, HostCmd_CMD_BASTREAM);
1505 * NB: BA stream create may fail when the stream is
1506 * h/w backed under some (as yet not understood) conditions.
1507 * Check the result code to catch this.
1509 if (le16toh(pCmd->CmdHdr.Result) != HostCmd_RESULT_OK)
1519 mwl_hal_bastream_destroy(struct mwl_hal *mh0, const MWL_HAL_BASTREAM *s)
1521 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1522 struct mwl_hal_bastream *sp = __DECONST(struct mwl_hal_bastream *, s);
1523 HostCmd_FW_BASTREAM *pCmd;
1526 if (sp->stream >= MWL_BASTREAMS_MAX) {
1532 _CMD_SETUP(pCmd, HostCmd_FW_BASTREAM, HostCmd_CMD_BASTREAM);
1533 pCmd->ActionType = htole32(BaDestroyStream);
1534 pCmd->BaInfo.DestroyParams.FwBaContext.Context =
1535 htole32(sp->stream);
1537 retval = mwlExecuteCmd(mh, HostCmd_CMD_BASTREAM);
1540 /* NB: always reclaim stream */
1541 mh->mh_bastreams |= 1<<sp->stream;
1542 sp->public.data[0] = NULL;
1543 sp->public.data[1] = NULL;
1550 mwl_hal_bastream_get_seqno(struct mwl_hal *mh0,
1551 const MWL_HAL_BASTREAM *s, const uint8_t Macaddr[IEEE80211_ADDR_LEN],
1554 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1555 struct mwl_hal_bastream *sp = __DECONST(struct mwl_hal_bastream *, s);
1556 HostCmd_GET_SEQNO *pCmd;
1560 _CMD_SETUP(pCmd, HostCmd_GET_SEQNO, HostCmd_CMD_GET_SEQNO);
1561 IEEE80211_ADDR_COPY(pCmd->MacAddr, Macaddr);
1562 pCmd->TID = sp->tid;
1564 retval = mwlExecuteCmd(mh, HostCmd_CMD_GET_SEQNO);
1566 *pseqno = le16toh(pCmd->SeqNo);
1572 mwl_hal_getwatchdogbitmap(struct mwl_hal *mh0, uint8_t bitmap[1])
1574 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1575 HostCmd_FW_GET_WATCHDOG_BITMAP *pCmd;
1579 _CMD_SETUP(pCmd, HostCmd_FW_GET_WATCHDOG_BITMAP,
1580 HostCmd_CMD_GET_WATCHDOG_BITMAP);
1582 retval = mwlExecuteCmd(mh, HostCmd_CMD_GET_WATCHDOG_BITMAP);
1584 bitmap[0] = pCmd->Watchdogbitmap;
1585 /* fw returns qid, map it to BA stream */
1586 if (bitmap[0] < MWL_BAQID_MAX)
1587 bitmap[0] = qid2ba[bitmap[0]];
1594 * Configure aggressive Ampdu rate mode.
1597 mwl_hal_setaggampduratemode(struct mwl_hal *mh0, int mode, int threshold)
1599 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1600 HostCmd_FW_AMPDU_RETRY_RATEDROP_MODE *pCmd;
1604 _CMD_SETUP(pCmd, HostCmd_FW_AMPDU_RETRY_RATEDROP_MODE,
1605 HostCmd_CMD_AMPDU_RETRY_RATEDROP_MODE);
1606 pCmd->Action = htole16(1);
1607 pCmd->Option = htole32(mode);
1608 pCmd->Threshold = htole32(threshold);
1610 retval = mwlExecuteCmd(mh, HostCmd_CMD_AMPDU_RETRY_RATEDROP_MODE);
1616 mwl_hal_getaggampduratemode(struct mwl_hal *mh0, int *mode, int *threshold)
1618 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1619 HostCmd_FW_AMPDU_RETRY_RATEDROP_MODE *pCmd;
1623 _CMD_SETUP(pCmd, HostCmd_FW_AMPDU_RETRY_RATEDROP_MODE,
1624 HostCmd_CMD_AMPDU_RETRY_RATEDROP_MODE);
1625 pCmd->Action = htole16(0);
1627 retval = mwlExecuteCmd(mh, HostCmd_CMD_AMPDU_RETRY_RATEDROP_MODE);
1629 *mode = le32toh(pCmd->Option);
1630 *threshold = le32toh(pCmd->Threshold);
1635 * Set CFEND status Enable/Disable
1638 mwl_hal_setcfend(struct mwl_hal *mh0, int ena)
1640 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1641 HostCmd_CFEND_ENABLE *pCmd;
1645 _CMD_SETUP(pCmd, HostCmd_CFEND_ENABLE,
1646 HostCmd_CMD_CFEND_ENABLE);
1647 pCmd->Enable = htole32(ena);
1649 retval = mwlExecuteCmd(mh, HostCmd_CMD_CFEND_ENABLE);
1655 mwl_hal_setdwds(struct mwl_hal *mh0, int ena)
1657 HostCmd_DWDS_ENABLE *pCmd;
1658 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1662 _CMD_SETUP(pCmd, HostCmd_DWDS_ENABLE, HostCmd_CMD_DWDS_ENABLE);
1663 pCmd->Enable = htole32(ena);
1664 retval = mwlExecuteCmd(mh, HostCmd_CMD_DWDS_ENABLE);
1670 cvtPeerInfo(PeerInfo_t *to, const MWL_HAL_PEERINFO *from)
1672 to->LegacyRateBitMap = htole32(from->LegacyRateBitMap);
1673 to->HTRateBitMap = htole32(from->HTRateBitMap);
1674 to->CapInfo = htole16(from->CapInfo);
1675 to->HTCapabilitiesInfo = htole16(from->HTCapabilitiesInfo);
1676 to->MacHTParamInfo = from->MacHTParamInfo;
1677 to->AddHtInfo.ControlChan = from->AddHtInfo.ControlChan;
1678 to->AddHtInfo.AddChan = from->AddHtInfo.AddChan;
1679 to->AddHtInfo.OpMode = htole16(from->AddHtInfo.OpMode);
1680 to->AddHtInfo.stbc = htole16(from->AddHtInfo.stbc);
1683 /* XXX station id must be in [0..63] */
1685 mwl_hal_newstation(struct mwl_hal_vap *vap,
1686 const uint8_t addr[IEEE80211_ADDR_LEN], uint16_t aid, uint16_t sid,
1687 const MWL_HAL_PEERINFO *peer, int isQosSta, int wmeInfo)
1689 struct mwl_hal_priv *mh = MWLVAP(vap);
1690 HostCmd_FW_SET_NEW_STN *pCmd;
1694 _VCMD_SETUP(vap, pCmd, HostCmd_FW_SET_NEW_STN, HostCmd_CMD_SET_NEW_STN);
1695 pCmd->AID = htole16(aid);
1696 pCmd->StnId = htole16(sid);
1697 pCmd->Action = htole16(0); /* SET */
1699 /* NB: must fix up byte order */
1700 cvtPeerInfo(&pCmd->PeerInfo, peer);
1702 IEEE80211_ADDR_COPY(&pCmd->MacAddr[0], addr);
1703 pCmd->Qosinfo = wmeInfo;
1704 pCmd->isQosSta = (isQosSta != 0);
1706 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_NEW_STN);
1707 if (retval == 0 && IEEE80211_ADDR_EQ(vap->mac, addr))
1708 vap->flags |= MVF_STATION;
1714 mwl_hal_delstation(struct mwl_hal_vap *vap,
1715 const uint8_t addr[IEEE80211_ADDR_LEN])
1717 struct mwl_hal_priv *mh = MWLVAP(vap);
1718 HostCmd_FW_SET_NEW_STN *pCmd;
1719 int retval, islocal;
1722 islocal = IEEE80211_ADDR_EQ(vap->mac, addr);
1723 if (!islocal || (vap->flags & MVF_STATION)) {
1724 _VCMD_SETUP(vap, pCmd, HostCmd_FW_SET_NEW_STN,
1725 HostCmd_CMD_SET_NEW_STN);
1726 pCmd->Action = htole16(2); /* REMOVE */
1727 IEEE80211_ADDR_COPY(&pCmd->MacAddr[0], addr);
1728 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_NEW_STN);
1730 vap->flags &= ~MVF_STATION;
1738 * Prod the firmware to age packets on station power
1739 * save queues and reap frames on the tx aggregation q's.
1742 mwl_hal_setkeepalive(struct mwl_hal *mh0)
1744 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1745 HostCmd_FW_SET_KEEP_ALIVE_TICK *pCmd;
1749 _CMD_SETUP(pCmd, HostCmd_FW_SET_KEEP_ALIVE_TICK,
1750 HostCmd_CMD_SET_KEEP_ALIVE);
1752 * NB: tick must be 0 to prod the f/w;
1753 * a non-zero value is a noop.
1757 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_KEEP_ALIVE);
1763 mwl_hal_setapmode(struct mwl_hal_vap *vap, MWL_HAL_APMODE ApMode)
1765 struct mwl_hal_priv *mh = MWLVAP(vap);
1766 HostCmd_FW_SET_APMODE *pCmd;
1769 /* XXX validate ApMode? */
1772 _VCMD_SETUP(vap, pCmd, HostCmd_FW_SET_APMODE, HostCmd_CMD_SET_APMODE);
1773 pCmd->ApMode = ApMode;
1775 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_APMODE);
1781 mwl_hal_stop(struct mwl_hal_vap *vap)
1783 struct mwl_hal_priv *mh = MWLVAP(vap);
1784 HostCmd_DS_BSS_START *pCmd;
1788 if (vap->flags & MVF_RUNNING) {
1789 _VCMD_SETUP(vap, pCmd, HostCmd_DS_BSS_START,
1790 HostCmd_CMD_BSS_START);
1791 pCmd->Enable = htole32(HostCmd_ACT_GEN_OFF);
1792 retval = mwlExecuteCmd(mh, HostCmd_CMD_BSS_START);
1795 /* NB: mark !running regardless */
1796 vap->flags &= ~MVF_RUNNING;
1802 mwl_hal_start(struct mwl_hal_vap *vap)
1804 struct mwl_hal_priv *mh = MWLVAP(vap);
1805 HostCmd_DS_BSS_START *pCmd;
1809 _VCMD_SETUP(vap, pCmd, HostCmd_DS_BSS_START, HostCmd_CMD_BSS_START);
1810 pCmd->Enable = htole32(HostCmd_ACT_GEN_ON);
1812 retval = mwlExecuteCmd(mh, HostCmd_CMD_BSS_START);
1814 vap->flags |= MVF_RUNNING;
1820 mwl_hal_setgprot(struct mwl_hal *mh0, int prot)
1822 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1823 HostCmd_FW_SET_G_PROTECT_FLAG *pCmd;
1827 _CMD_SETUP(pCmd, HostCmd_FW_SET_G_PROTECT_FLAG,
1828 HostCmd_CMD_SET_G_PROTECT_FLAG);
1829 pCmd->GProtectFlag = htole32(prot);
1831 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_G_PROTECT_FLAG);
1837 mwl_hal_setwmm(struct mwl_hal *mh0, int onoff)
1839 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1840 HostCmd_FW_SetWMMMode *pCmd;
1844 _CMD_SETUP(pCmd, HostCmd_FW_SetWMMMode,
1845 HostCmd_CMD_SET_WMM_MODE);
1846 pCmd->Action = htole16(onoff);
1848 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_WMM_MODE);
1854 mwl_hal_setedcaparams(struct mwl_hal *mh0, uint8_t qnum,
1855 uint32_t CWmin, uint32_t CWmax, uint8_t AIFSN, uint16_t TXOPLimit)
1857 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1858 HostCmd_FW_SET_EDCA_PARAMS *pCmd;
1862 _CMD_SETUP(pCmd, HostCmd_FW_SET_EDCA_PARAMS,
1863 HostCmd_CMD_SET_EDCA_PARAMS);
1865 * NB: CWmin and CWmax are always set.
1866 * TxOpLimit is set if bit 0x2 is marked in Action
1867 * AIFSN is set if bit 0x4 is marked in Action
1869 pCmd->Action = htole16(0xffff); /* NB: set everything */
1870 pCmd->TxOP = htole16(TXOPLimit);
1871 pCmd->CWMax = htole32(CWmax);
1872 pCmd->CWMin = htole32(CWmin);
1873 pCmd->AIFSN = AIFSN;
1874 pCmd->TxQNum = qnum; /* XXX check */
1876 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_EDCA_PARAMS);
1881 /* XXX 0 = indoor, 1 = outdoor */
1883 mwl_hal_setrateadaptmode(struct mwl_hal *mh0, uint16_t mode)
1885 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1886 HostCmd_DS_SET_RATE_ADAPT_MODE *pCmd;
1890 _CMD_SETUP(pCmd, HostCmd_DS_SET_RATE_ADAPT_MODE,
1891 HostCmd_CMD_SET_RATE_ADAPT_MODE);
1892 pCmd->Action = htole16(HostCmd_ACT_GEN_SET);
1893 pCmd->RateAdaptMode = htole16(mode);
1895 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_RATE_ADAPT_MODE);
1901 mwl_hal_setcsmode(struct mwl_hal *mh0, MWL_HAL_CSMODE csmode)
1903 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1904 HostCmd_DS_SET_LINKADAPT_CS_MODE *pCmd;
1908 _CMD_SETUP(pCmd, HostCmd_DS_SET_LINKADAPT_CS_MODE,
1909 HostCmd_CMD_SET_LINKADAPT_CS_MODE);
1910 pCmd->Action = htole16(HostCmd_ACT_GEN_SET);
1911 pCmd->CSMode = htole16(csmode);
1913 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_LINKADAPT_CS_MODE);
1919 mwl_hal_setnprot(struct mwl_hal_vap *vap, MWL_HAL_HTPROTECT mode)
1921 struct mwl_hal_priv *mh = MWLVAP(vap);
1922 HostCmd_FW_SET_N_PROTECT_FLAG *pCmd;
1925 /* XXX validate mode */
1927 _VCMD_SETUP(vap, pCmd, HostCmd_FW_SET_N_PROTECT_FLAG,
1928 HostCmd_CMD_SET_N_PROTECT_FLAG);
1929 pCmd->NProtectFlag = htole32(mode);
1931 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_N_PROTECT_FLAG);
1937 mwl_hal_setnprotmode(struct mwl_hal_vap *vap, uint8_t mode)
1939 struct mwl_hal_priv *mh = MWLVAP(vap);
1940 HostCmd_FW_SET_N_PROTECT_OPMODE *pCmd;
1944 _VCMD_SETUP(vap, pCmd, HostCmd_FW_SET_N_PROTECT_OPMODE,
1945 HostCmd_CMD_SET_N_PROTECT_OPMODE);
1946 pCmd->NProtectOpMode = mode;
1948 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_N_PROTECT_OPMODE);
1954 mwl_hal_setoptimizationlevel(struct mwl_hal *mh0, int level)
1956 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1957 HostCmd_FW_SET_OPTIMIZATION_LEVEL *pCmd;
1961 _CMD_SETUP(pCmd, HostCmd_FW_SET_OPTIMIZATION_LEVEL,
1962 HostCmd_CMD_SET_OPTIMIZATION_LEVEL);
1963 pCmd->OptLevel = level;
1965 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_OPTIMIZATION_LEVEL);
1971 mwl_hal_setmimops(struct mwl_hal *mh0, const uint8_t addr[IEEE80211_ADDR_LEN],
1972 uint8_t enable, uint8_t mode)
1974 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1975 HostCmd_FW_SET_MIMOPSHT *pCmd;
1979 _CMD_SETUP(pCmd, HostCmd_FW_SET_MIMOPSHT, HostCmd_CMD_SET_MIMOPSHT);
1980 IEEE80211_ADDR_COPY(pCmd->Addr, addr);
1981 pCmd->Enable = enable;
1984 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_MIMOPSHT);
1990 mwlGetCalTable(struct mwl_hal_priv *mh, uint8_t annex, uint8_t index)
1992 HostCmd_FW_GET_CALTABLE *pCmd;
1995 MWL_HAL_LOCK_ASSERT(mh);
1997 _CMD_SETUP(pCmd, HostCmd_FW_GET_CALTABLE, HostCmd_CMD_GET_CALTABLE);
1998 pCmd->annex = annex;
1999 pCmd->index = index;
2000 memset(pCmd->calTbl, 0, sizeof(pCmd->calTbl));
2002 retval = mwlExecuteCmd(mh, HostCmd_CMD_GET_CALTABLE);
2004 pCmd->calTbl[0] != annex && annex != 0 && annex != 255)
2010 * Calculate the max tx power from the channel's cal data.
2013 setmaxtxpow(struct mwl_hal_channel *hc, int i, int maxix)
2015 hc->maxTxPow = hc->targetPowers[i];
2016 for (i++; i < maxix; i++)
2017 if (hc->targetPowers[i] > hc->maxTxPow)
2018 hc->maxTxPow = hc->targetPowers[i];
2022 * Construct channel info for 5GHz channels from cal data.
2025 get5Ghz(MWL_HAL_CHANNELINFO *ci, const uint8_t table[], int len)
2032 for (i = 0; i < len; i += 4) {
2033 struct mwl_hal_channel *hc;
2037 f = 5000 + 5*table[i];
2042 hc = &ci->channels[j];
2044 hc->ieee = table[i];
2045 memcpy(hc->targetPowers, &table[i], 4);
2046 setmaxtxpow(hc, 1, 4); /* NB: col 1 is the freq, skip*/
2050 ci->freqLow = (l == 32000) ? 0 : l;
2060 return 2407 + chan*5;
2061 return 2512 + (chan-15)*20;
2065 * Construct channel info for 2.4GHz channels from cal data.
2068 get2Ghz(MWL_HAL_CHANNELINFO *ci, const uint8_t table[], int len)
2073 for (i = 0; i < len; i += 4) {
2074 struct mwl_hal_channel *hc = &ci->channels[j];
2076 hc->freq = ieee2mhz(1+j);
2077 memcpy(hc->targetPowers, &table[i], 4);
2078 setmaxtxpow(hc, 0, 4);
2082 ci->freqLow = ieee2mhz(1);
2083 ci->freqHigh = ieee2mhz(j);
2089 dumpcaldata(const char *name, const uint8_t *table, int n)
2092 printf("\n%s:\n", name);
2093 for (i = 0; i < n; i += 4)
2094 printf("[%2d] %3d %3d %3d %3d\n", i/4, table[i+0], table[i+1], table[i+2], table[i+3]);
2099 mwlGetPwrCalTable(struct mwl_hal_priv *mh)
2101 const uint8_t *data;
2102 MWL_HAL_CHANNELINFO *ci;
2106 /* NB: we hold the lock so it's ok to use cmdbuf */
2107 data = ((const HostCmd_FW_GET_CALTABLE *) mh->mh_cmdbuf)->calTbl;
2108 if (mwlGetCalTable(mh, 33, 0) == 0) {
2109 len = (data[2] | (data[3] << 8)) - 12;
2110 if (len > PWTAGETRATETABLE20M)
2111 len = PWTAGETRATETABLE20M;
2113 dumpcaldata("2.4G 20M", &data[12], len);/*XXX*/
2115 get2Ghz(&mh->mh_20M, &data[12], len);
2117 if (mwlGetCalTable(mh, 34, 0) == 0) {
2118 len = (data[2] | (data[3] << 8)) - 12;
2119 if (len > PWTAGETRATETABLE40M)
2120 len = PWTAGETRATETABLE40M;
2122 dumpcaldata("2.4G 40M", &data[12], len);/*XXX*/
2125 get2Ghz(ci, &data[12], len);
2127 if (mwlGetCalTable(mh, 35, 0) == 0) {
2128 len = (data[2] | (data[3] << 8)) - 20;
2129 if (len > PWTAGETRATETABLE20M_5G)
2130 len = PWTAGETRATETABLE20M_5G;
2132 dumpcaldata("5G 20M", &data[20], len);/*XXX*/
2134 get5Ghz(&mh->mh_20M_5G, &data[20], len);
2136 if (mwlGetCalTable(mh, 36, 0) == 0) {
2137 len = (data[2] | (data[3] << 8)) - 20;
2138 if (len > PWTAGETRATETABLE40M_5G)
2139 len = PWTAGETRATETABLE40M_5G;
2141 dumpcaldata("5G 40M", &data[20], len);/*XXX*/
2143 ci = &mh->mh_40M_5G;
2144 get5Ghz(ci, &data[20], len);
2146 mh->mh_flags |= MHF_CALDATA;
2152 mwl_hal_getregioncode(struct mwl_hal *mh0, uint8_t *countryCode)
2154 struct mwl_hal_priv *mh = MWLPRIV(mh0);
2158 retval = mwlGetCalTable(mh, 0, 0);
2160 const HostCmd_FW_GET_CALTABLE *pCmd =
2161 (const HostCmd_FW_GET_CALTABLE *) mh->mh_cmdbuf;
2162 *countryCode = pCmd->calTbl[16];
2169 mwl_hal_setpromisc(struct mwl_hal *mh0, int ena)
2171 struct mwl_hal_priv *mh = MWLPRIV(mh0);
2175 v = RD4(mh, MACREG_REG_PROMISCUOUS);
2176 WR4(mh, MACREG_REG_PROMISCUOUS, ena ? v | 1 : v &~ 1);
2182 mwl_hal_getpromisc(struct mwl_hal *mh0)
2184 struct mwl_hal_priv *mh = MWLPRIV(mh0);
2188 v = RD4(mh, MACREG_REG_PROMISCUOUS);
2190 return (v & 1) != 0;
2194 mwl_hal_GetBeacon(struct mwl_hal *mh0, uint8_t *pBcn, uint16_t *pLen)
2196 struct mwl_hal_priv *mh = MWLPRIV(mh0);
2197 HostCmd_FW_GET_BEACON *pCmd;
2201 _CMD_SETUP(pCmd, HostCmd_FW_GET_BEACON, HostCmd_CMD_GET_BEACON);
2202 pCmd->Bcnlen = htole16(0);
2204 retval = mwlExecuteCmd(mh, HostCmd_CMD_GET_BEACON);
2206 /* XXX bounds check */
2207 memcpy(pBcn, &pCmd->Bcn, pCmd->Bcnlen);
2208 *pLen = pCmd->Bcnlen;
2215 mwl_hal_SetRifs(struct mwl_hal *mh0, uint8_t QNum)
2217 struct mwl_hal_priv *mh = MWLPRIV(mh0);
2218 HostCmd_FW_SET_RIFS *pCmd;
2222 _CMD_SETUP(pCmd, HostCmd_FW_SET_RIFS, HostCmd_CMD_SET_RIFS);
2225 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_RIFS);
2231 * Diagnostic api's for set/get registers.
2235 getRFReg(struct mwl_hal_priv *mh, int flag, uint32_t reg, uint32_t *val)
2237 HostCmd_DS_RF_REG_ACCESS *pCmd;
2241 _CMD_SETUP(pCmd, HostCmd_DS_RF_REG_ACCESS, HostCmd_CMD_RF_REG_ACCESS);
2242 pCmd->Offset = htole16(reg);
2243 pCmd->Action = htole16(flag);
2244 pCmd->Value = htole32(*val);
2246 retval = mwlExecuteCmd(mh, HostCmd_CMD_RF_REG_ACCESS);
2254 getBBReg(struct mwl_hal_priv *mh, int flag, uint32_t reg, uint32_t *val)
2256 HostCmd_DS_BBP_REG_ACCESS *pCmd;
2260 _CMD_SETUP(pCmd, HostCmd_DS_BBP_REG_ACCESS, HostCmd_CMD_BBP_REG_ACCESS);
2261 pCmd->Offset = htole16(reg);
2262 pCmd->Action = htole16(flag);
2263 pCmd->Value = htole32(*val);
2265 retval = mwlExecuteCmd(mh, HostCmd_CMD_BBP_REG_ACCESS);
2273 mwl_hal_getregdump(struct mwl_hal_priv *mh, const MWL_DIAG_REGRANGE *regs,
2274 void *dstbuf, int space)
2276 uint32_t *dp = dstbuf;
2279 for (i = 0; space >= 2*sizeof(uint32_t); i++) {
2280 u_int r = regs[i].start;
2281 u_int e = regs[i].end;
2282 *dp++ = (r<<16) | e;
2283 space -= sizeof(uint32_t);
2285 if (MWL_DIAG_ISMAC(r))
2287 else if (MWL_DIAG_ISBB(r))
2288 getBBReg(mh, HostCmd_ACT_GEN_READ,
2289 r - MWL_DIAG_BASE_BB, dp);
2290 else if (MWL_DIAG_ISRF(r))
2291 getRFReg(mh, HostCmd_ACT_GEN_READ,
2292 r - MWL_DIAG_BASE_RF, dp);
2293 else if (r < 0x1000 || r == MACREG_REG_FW_PRESENT)
2298 r += sizeof(uint32_t);
2299 space -= sizeof(uint32_t);
2300 } while (r <= e && space >= sizeof(uint32_t));
2302 return (char *) dp - (char *) dstbuf;
2306 mwl_hal_getdiagstate(struct mwl_hal *mh0, int request,
2307 const void *args, uint32_t argsize,
2308 void **result, uint32_t *resultsize)
2310 struct mwl_hal_priv *mh = MWLPRIV(mh0);
2313 case MWL_DIAG_CMD_REVS:
2314 *result = &mh->mh_revs;
2315 *resultsize = sizeof(mh->mh_revs);
2317 case MWL_DIAG_CMD_REGS:
2318 *resultsize = mwl_hal_getregdump(mh, args, *result, *resultsize);
2320 case MWL_DIAG_CMD_HOSTCMD: {
2321 FWCmdHdr *pCmd = (FWCmdHdr *) &mh->mh_cmdbuf[0];
2325 memcpy(pCmd, args, argsize);
2326 retval = mwlExecuteCmd(mh, le16toh(pCmd->Cmd));
2327 *result = (*resultsize != 0) ? pCmd : NULL;
2329 return (retval == 0);
2331 case MWL_DIAG_CMD_FWLOAD:
2332 if (mwl_hal_fwload(mh0, __DECONST(void *, args))) {
2333 device_printf(mh->mh_dev, "problem loading fw image\n");
2342 * Low level firmware cmd block handshake support.
2346 mwlSendCmd(struct mwl_hal_priv *mh)
2350 bus_dmamap_sync(mh->mh_dmat, mh->mh_dmamap,
2351 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2353 WR4(mh, MACREG_REG_GEN_PTR, mh->mh_cmdaddr);
2354 dummy = RD4(mh, MACREG_REG_INT_CODE);
2356 WR4(mh, MACREG_REG_H2A_INTERRUPT_EVENTS, MACREG_H2ARIC_BIT_DOOR_BELL);
2360 mwlWaitForCmdComplete(struct mwl_hal_priv *mh, uint16_t cmdCode)
2362 #define MAX_WAIT_FW_COMPLETE_ITERATIONS 10000
2365 for (i = 0; i < MAX_WAIT_FW_COMPLETE_ITERATIONS; i++) {
2366 if (mh->mh_cmdbuf[0] == le16toh(cmdCode))
2371 #undef MAX_WAIT_FW_COMPLETE_ITERATIONS
2375 mwlExecuteCmd(struct mwl_hal_priv *mh, unsigned short cmd)
2378 MWL_HAL_LOCK_ASSERT(mh);
2380 if ((mh->mh_flags & MHF_FWHANG) &&
2381 (mh->mh_debug & MWL_HAL_DEBUG_IGNHANG) == 0) {
2383 device_printf(mh->mh_dev, "firmware hung, skipping cmd %s\n",
2386 device_printf(mh->mh_dev, "firmware hung, skipping cmd 0x%x\n",
2391 if (RD4(mh, MACREG_REG_INT_CODE) == 0xffffffff) {
2392 device_printf(mh->mh_dev, "%s: device not present!\n",
2397 if (mh->mh_debug & MWL_HAL_DEBUG_SENDCMD)
2401 if (!mwlWaitForCmdComplete(mh, 0x8000 | cmd)) {
2403 device_printf(mh->mh_dev,
2404 "timeout waiting for f/w cmd %s\n", mwlcmdname(cmd));
2406 device_printf(mh->mh_dev,
2407 "timeout waiting for f/w cmd 0x%x\n", cmd);
2409 mh->mh_flags |= MHF_FWHANG;
2412 bus_dmamap_sync(mh->mh_dmat, mh->mh_dmamap,
2413 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2415 if (mh->mh_debug & MWL_HAL_DEBUG_CMDDONE)
2422 * Firmware download support.
2424 #define FW_DOWNLOAD_BLOCK_SIZE 256
2425 #define FW_CHECK_USECS (5*1000) /* 5ms */
2426 #define FW_MAX_NUM_CHECKS 200
2429 /* XXX read f/w from file */
2430 #include <dev/mwl/mwlbootfw.h>
2431 #include <dev/mwl/mwl88W8363fw.h>
2435 mwlFwReset(struct mwl_hal_priv *mh)
2437 if (RD4(mh, MACREG_REG_INT_CODE) == 0xffffffff) {
2438 device_printf(mh->mh_dev, "%s: device not present!\n",
2442 WR4(mh, MACREG_REG_H2A_INTERRUPT_EVENTS, ISR_RESET);
2443 mh->mh_flags &= ~MHF_FWHANG;
2447 mwlTriggerPciCmd(struct mwl_hal_priv *mh)
2451 bus_dmamap_sync(mh->mh_dmat, mh->mh_dmamap, BUS_DMASYNC_PREWRITE);
2453 WR4(mh, MACREG_REG_GEN_PTR, mh->mh_cmdaddr);
2454 dummy = RD4(mh, MACREG_REG_INT_CODE);
2456 WR4(mh, MACREG_REG_INT_CODE, 0x00);
2457 dummy = RD4(mh, MACREG_REG_INT_CODE);
2459 WR4(mh, MACREG_REG_H2A_INTERRUPT_EVENTS, MACREG_H2ARIC_BIT_DOOR_BELL);
2460 dummy = RD4(mh, MACREG_REG_INT_CODE);
2464 mwlWaitFor(struct mwl_hal_priv *mh, uint32_t val)
2468 for (i = 0; i < FW_MAX_NUM_CHECKS; i++) {
2469 DELAY(FW_CHECK_USECS);
2470 if (RD4(mh, MACREG_REG_INT_CODE) == val)
2477 * Firmware block xmit when talking to the boot-rom.
2480 mwlSendBlock(struct mwl_hal_priv *mh, int bsize, const void *data, size_t dsize)
2482 mh->mh_cmdbuf[0] = htole16(HostCmd_CMD_CODE_DNLD);
2483 mh->mh_cmdbuf[1] = htole16(bsize);
2484 memcpy(&mh->mh_cmdbuf[4], data , dsize);
2485 mwlTriggerPciCmd(mh);
2486 /* XXX 2000 vs 200 */
2487 if (mwlWaitFor(mh, MACREG_INT_CODE_CMD_FINISHED)) {
2488 WR4(mh, MACREG_REG_INT_CODE, 0);
2491 device_printf(mh->mh_dev,
2492 "%s: timeout waiting for CMD_FINISHED, INT_CODE 0x%x\n",
2493 __func__, RD4(mh, MACREG_REG_INT_CODE));
2498 * Firmware block xmit when talking to the 1st-stage loader.
2501 mwlSendBlock2(struct mwl_hal_priv *mh, const void *data, size_t dsize)
2503 memcpy(&mh->mh_cmdbuf[0], data, dsize);
2504 mwlTriggerPciCmd(mh);
2505 if (mwlWaitFor(mh, MACREG_INT_CODE_CMD_FINISHED)) {
2506 WR4(mh, MACREG_REG_INT_CODE, 0);
2509 device_printf(mh->mh_dev,
2510 "%s: timeout waiting for CMD_FINISHED, INT_CODE 0x%x\n",
2511 __func__, RD4(mh, MACREG_REG_INT_CODE));
2516 mwlPokeSdramController(struct mwl_hal_priv *mh, int SDRAMSIZE_Addr)
2518 /** Set up sdram controller for superflyv2 **/
2519 WR4(mh, 0x00006014, 0x33);
2520 WR4(mh, 0x00006018, 0xa3a2632);
2521 WR4(mh, 0x00006010, SDRAMSIZE_Addr);
2525 mwl_hal_fwload(struct mwl_hal *mh0, void *fwargs)
2527 struct mwl_hal_priv *mh = MWLPRIV(mh0);
2528 const char *fwname = "mw88W8363fw";
2529 const char *fwbootname = "mwlboot";
2530 const struct firmware *fwboot = NULL;
2531 const struct firmware *fw;
2532 /* XXX get from firmware header */
2533 uint32_t FwReadySignature = HostCmd_SOFTAP_FWRDY_SIGNATURE;
2534 uint32_t OpMode = HostCmd_SOFTAP_MODE;
2535 const uint8_t *fp, *ep;
2536 const uint8_t *fmdata;
2537 uint32_t blocksize, nbytes, fmsize;
2538 int i, error, ntries;
2540 fw = firmware_get(fwname);
2542 device_printf(mh->mh_dev,
2543 "could not load firmware image %s\n", fwname);
2547 fmsize = fw->datasize;
2549 device_printf(mh->mh_dev, "firmware image %s too small\n",
2554 if (fmdata[0] == 0x01 && fmdata[1] == 0x00 &&
2555 fmdata[2] == 0x00 && fmdata[3] == 0x00) {
2557 * 2-stage load, get the boot firmware.
2559 fwboot = firmware_get(fwbootname);
2560 if (fwboot == NULL) {
2561 device_printf(mh->mh_dev,
2562 "could not load firmware image %s\n", fwbootname);
2571 WR4(mh, MACREG_REG_A2H_INTERRUPT_CLEAR_SEL, MACREG_A2HRIC_BIT_MASK);
2572 WR4(mh, MACREG_REG_A2H_INTERRUPT_CAUSE, 0x00);
2573 WR4(mh, MACREG_REG_A2H_INTERRUPT_MASK, 0x00);
2574 WR4(mh, MACREG_REG_A2H_INTERRUPT_STATUS_MASK, MACREG_A2HRIC_BIT_MASK);
2575 if (mh->mh_SDRAMSIZE_Addr != 0) {
2576 /** Set up sdram controller for superflyv2 **/
2577 mwlPokeSdramController(mh, mh->mh_SDRAMSIZE_Addr);
2579 device_printf(mh->mh_dev, "load %s firmware image (%u bytes)\n",
2581 if (fwboot != NULL) {
2583 * Do 2-stage load. The 1st stage loader is setup
2584 * with the bootrom loader then we load the real
2585 * image using a different handshake. With this
2586 * mechanism the firmware is segmented into chunks
2587 * that have a CRC. If a chunk is incorrect we'll
2588 * be told to retransmit.
2590 /* XXX assumes hlpimage fits in a block */
2591 /* NB: zero size block indicates download is finished */
2592 if (!mwlSendBlock(mh, fwboot->datasize, fwboot->data, fwboot->datasize) ||
2593 !mwlSendBlock(mh, 0, NULL, 0)) {
2597 DELAY(200*FW_CHECK_USECS);
2598 if (mh->mh_SDRAMSIZE_Addr != 0) {
2599 /** Set up sdram controller for superflyv2 **/
2600 mwlPokeSdramController(mh, mh->mh_SDRAMSIZE_Addr);
2602 nbytes = ntries = 0; /* NB: silence compiler */
2603 for (fp = fmdata, ep = fp + fmsize; fp < ep; ) {
2604 WR4(mh, MACREG_REG_INT_CODE, 0);
2605 blocksize = RD4(mh, MACREG_REG_SCRATCH);
2606 if (blocksize == 0) /* download complete */
2608 if (blocksize > 0x00000c00) {
2612 if ((blocksize & 0x1) == 0) {
2613 /* block successfully downloaded, advance */
2619 * Guard against f/w telling us to
2625 /* clear NAK bit/flag */
2628 if (blocksize > ep - fp) {
2629 /* XXX this should not happen, what to do? */
2630 blocksize = ep - fp;
2633 if (!mwlSendBlock2(mh, fp, nbytes)) {
2639 for (fp = fmdata, ep = fp + fmsize; fp < ep;) {
2641 if (nbytes > FW_DOWNLOAD_BLOCK_SIZE)
2642 nbytes = FW_DOWNLOAD_BLOCK_SIZE;
2643 if (!mwlSendBlock(mh, FW_DOWNLOAD_BLOCK_SIZE, fp, nbytes)) {
2650 /* done with firmware... */
2652 firmware_put(fwboot, FIRMWARE_UNLOAD);
2653 firmware_put(fw, FIRMWARE_UNLOAD);
2655 * Wait for firmware to startup; we monitor the
2656 * INT_CODE register waiting for a signature to
2657 * written back indicating it's ready to go.
2659 mh->mh_cmdbuf[1] = 0;
2661 * XXX WAR for mfg fw download
2663 if (OpMode != HostCmd_STA_MODE)
2664 mwlTriggerPciCmd(mh);
2665 for (i = 0; i < FW_MAX_NUM_CHECKS; i++) {
2666 WR4(mh, MACREG_REG_GEN_PTR, OpMode);
2667 DELAY(FW_CHECK_USECS);
2668 if (RD4(mh, MACREG_REG_INT_CODE) == FwReadySignature) {
2669 WR4(mh, MACREG_REG_INT_CODE, 0x00);
2670 return mwlResetHalState(mh);
2677 /* done with firmware... */
2679 firmware_put(fwboot, FIRMWARE_UNLOAD);
2680 firmware_put(fw, FIRMWARE_UNLOAD);
2688 static char buf[12];
2689 #define CMD(x) case HostCmd_CMD_##x: return #x
2694 CMD(MAC_MULTICAST_ADR);
2695 CMD(802_11_GET_STAT);
2696 CMD(MAC_REG_ACCESS);
2697 CMD(BBP_REG_ACCESS);
2699 CMD(802_11_RADIO_CONTROL);
2700 CMD(802_11_RF_TX_POWER);
2701 CMD(802_11_RF_ANTENNA);
2703 CMD(SET_RF_CHANNEL);
2705 CMD(SET_INFRA_MODE);
2706 CMD(SET_G_PROTECT_FLAG);
2707 CMD(802_11_RTS_THSD);
2708 CMD(802_11_SET_SLOT);
2709 CMD(SET_EDCA_PARAMS);
2710 CMD(802_11H_DETECT_RADAR);
2712 CMD(HT_GUARD_INTERVAL);
2713 CMD(SET_FIXED_RATE);
2714 CMD(SET_LINKADAPT_CS_MODE);
2716 CMD(SET_RATE_ADAPT_MODE);
2719 CMD(SET_KEEP_ALIVE);
2721 CMD(SET_SWITCH_CHANNEL);
2722 CMD(UPDATE_ENCRYPTION);
2725 CMD(SET_N_PROTECT_FLAG);
2726 CMD(SET_N_PROTECT_OPMODE);
2727 CMD(SET_OPTIMIZATION_LEVEL);
2731 CMD(SET_REGION_CODE);
2732 CMD(SET_POWERSAVESTATION);
2737 CMD(AMPDU_RETRY_RATEDROP_MODE);
2740 snprintf(buf, sizeof(buf), "0x%x", cmd);
2746 dumpresult(struct mwl_hal_priv *mh, int showresult)
2748 const FWCmdHdr *h = (const FWCmdHdr *)mh->mh_cmdbuf;
2752 len = le16toh(h->Length);
2753 #ifdef MWL_MBSS_SUPPORT
2754 device_printf(mh->mh_dev, "Cmd %s Length %d SeqNum %d MacId %d",
2755 mwlcmdname(le16toh(h->Cmd) &~ 0x8000), len, h->SeqNum, h->MacId);
2757 device_printf(mh->mh_dev, "Cmd %s Length %d SeqNum %d",
2758 mwlcmdname(le16toh(h->Cmd) &~ 0x8000), len, le16toh(h->SeqNum));
2761 const char *results[] =
2762 { "OK", "ERROR", "NOT_SUPPORT", "PENDING", "BUSY",
2764 int result = le16toh(h->Result);
2766 if (result <= HostCmd_RESULT_PARTIAL_DATA)
2767 printf(" Result %s", results[result]);
2769 printf(" Result %d", result);
2771 cp = (const uint8_t *)h;
2772 for (i = 0; i < len; i++) {
2774 printf("\n%02x", cp[i]);
2776 printf(" %02x", cp[i]);
2780 #endif /* MWLHAL_DEBUG */