2 * Copyright (c) 2007-2009 Sam Leffler, Errno Consulting
3 * Copyright (c) 2007-2009 Marvell Semiconductor, Inc.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer,
11 * without modification.
12 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
13 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
14 * redistribution must be conditioned upon including a substantially
15 * similar Disclaimer requirement for further binary redistribution.
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
21 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
22 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
23 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
26 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
28 * THE POSSIBILITY OF SUCH DAMAGES.
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/sysctl.h>
36 #include <sys/malloc.h>
38 #include <sys/mutex.h>
39 #include <sys/kernel.h>
40 #include <sys/errno.h>
42 #include <sys/endian.h>
44 #include <sys/linker.h>
45 #include <sys/firmware.h>
47 #include <machine/bus.h>
49 #include <dev/mwl/mwlhal.h>
50 #include <dev/mwl/mwlreg.h>
52 #include <sys/socket.h>
53 #include <sys/sockio.h>
55 #include <dev/mwl/mwldiag.h>
57 #define MWLHAL_DEBUG /* debug msgs */
60 WL_ANTENNAMODE_RX = 0xffff,
61 WL_ANTENNAMODE_TX = 2,
65 WL_TX_POWERLEVEL_LOW = 5,
66 WL_TX_POWERLEVEL_MEDIUM = 10,
67 WL_TX_POWERLEVEL_HIGH = 15,
70 #define MWL_CMDBUF_SIZE 0x4000 /* size of f/w command buffer */
71 #define MWL_BASTREAMS_MAX 7 /* max BA streams (NB: fw >3.3.5.9) */
72 #define MWL_BAQID_MAX 8 /* max BA Q id's (NB: fw >3.3.5.9) */
73 #define MWL_MBSS_AP_MAX 8 /* max ap vap's */
74 #define MWL_MBSS_STA_MAX 24 /* max station/client vap's */
75 #define MWL_MBSS_MAX (MWL_MBSS_AP_MAX+MWL_MBSS_STA_MAX)
78 * BA stream -> queue ID mapping
80 * The first 2 streams map to h/w; the remaining streams are
81 * implemented in firmware.
83 static const int ba2qid[MWL_BASTREAMS_MAX] = {
84 5, 6 /* h/w supported */
85 #if MWL_BASTREAMS_MAX == 7
86 , 7, 0, 1, 2, 3 /* f/w supported */
89 static int qid2ba[MWL_BAQID_MAX];
91 #define IEEE80211_ADDR_LEN 6 /* XXX */
92 #define IEEE80211_ADDR_COPY(_dst, _src) \
93 memcpy(_dst, _src, IEEE80211_ADDR_LEN)
94 #define IEEE80211_ADDR_EQ(_dst, _src) \
95 (memcmp(_dst, _src, IEEE80211_ADDR_LEN) == 0)
97 #define _CMD_SETUP(pCmd, type, cmd) do { \
98 pCmd = (type *)&mh->mh_cmdbuf[0]; \
99 memset(pCmd, 0, sizeof(type)); \
100 pCmd->CmdHdr.Cmd = htole16(cmd); \
101 pCmd->CmdHdr.Length = htole16(sizeof(type)); \
104 #define _VCMD_SETUP(vap, pCmd, type, cmd) do { \
105 _CMD_SETUP(pCmd, type, cmd); \
106 pCmd->CmdHdr.MacId = vap->macid; \
109 #define PWTAGETRATETABLE20M 14*4
110 #define PWTAGETRATETABLE40M 9*4
111 #define PWTAGETRATETABLE20M_5G 35*4
112 #define PWTAGETRATETABLE40M_5G 16*4
114 struct mwl_hal_bastream {
115 MWL_HAL_BASTREAM public; /* public state */
116 uint8_t stream; /* stream # */
117 uint8_t setup; /* f/w cmd sent */
118 uint8_t ba_policy; /* direct/delayed BA policy */
121 uint8_t macaddr[IEEE80211_ADDR_LEN];
127 struct mwl_hal_priv *mh; /* back pointer */
128 uint16_t bss_type; /* f/w type */
129 uint8_t vap_type; /* MWL_HAL_BSSTYPE */
130 uint8_t macid; /* for passing to f/w */
132 #define MVF_RUNNING 0x01 /* BSS_START issued */
133 #define MVF_STATION 0x02 /* sta db entry created */
134 uint8_t mac[IEEE80211_ADDR_LEN];/* mac address */
136 #define MWLVAP(_vap) ((_vap)->mh)
139 * Per-device state. We allocate a single cmd buffer for
140 * submitting operations to the firmware. Access to this
141 * buffer (and the f/w) are single-threaded. At present
142 * we spin waiting for cmds to complete which is bad. Not
143 * sure if it's possible to submit multiple requests or
144 * control when we get cmd done interrupts. There's no
145 * documentation and no example code to indicate what can
146 * or cannot be done so all we can do right now is follow the
147 * linux driver logic. This falls apart when the f/w fails;
148 * the system comes to a crawl as we spin waiting for operations
151 struct mwl_hal_priv {
152 struct mwl_hal public; /* public area */
156 bus_dma_tag_t mh_dmat; /* bus DMA tag for cmd buffer */
157 bus_dma_segment_t mh_seg; /* segment for cmd buffer */
158 bus_dmamap_t mh_dmamap; /* DMA map for cmd buffer */
159 uint16_t *mh_cmdbuf; /* f/w cmd buffer */
160 bus_addr_t mh_cmdaddr; /* physaddr of cmd buffer */
162 #define MHF_CALDATA 0x0001 /* cal data retrieved */
163 #define MHF_FWHANG 0x0002 /* fw appears hung */
164 #define MHF_MBSS 0x0004 /* mbss enabled */
165 struct mwl_hal_vap mh_vaps[MWL_MBSS_MAX+1];
166 int mh_bastreams; /* bit mask of available BA streams */
167 int mh_regioncode; /* XXX last region code sent to fw */
168 struct mwl_hal_bastream mh_streams[MWL_BASTREAMS_MAX];
170 MWL_HAL_CHANNELINFO mh_20M;
171 MWL_HAL_CHANNELINFO mh_40M;
172 MWL_HAL_CHANNELINFO mh_20M_5G;
173 MWL_HAL_CHANNELINFO mh_40M_5G;
174 int mh_SDRAMSIZE_Addr;
175 uint32_t mh_RTSSuccesses;/* cumulative stats for read-on-clear */
176 uint32_t mh_RTSFailures;
177 uint32_t mh_RxDuplicateFrames;
178 uint32_t mh_FCSErrorCount;
179 MWL_DIAG_REVS mh_revs;
181 #define MWLPRIV(_mh) ((struct mwl_hal_priv *)(_mh))
183 static int mwl_hal_setmac_locked(struct mwl_hal_vap *,
184 const uint8_t addr[IEEE80211_ADDR_LEN]);
185 static int mwlExecuteCmd(struct mwl_hal_priv *, unsigned short cmd);
186 static int mwlGetPwrCalTable(struct mwl_hal_priv *);
188 static const char *mwlcmdname(int cmd);
189 static void dumpresult(struct mwl_hal_priv *, int showresult);
190 #endif /* MWLHAL_DEBUG */
192 SYSCTL_DECL(_hw_mwl);
193 static SYSCTL_NODE(_hw_mwl, OID_AUTO, hal, CTLFLAG_RD, 0,
194 "Marvell HAL parameters");
197 MWL_HAL_LOCK(struct mwl_hal_priv *mh)
199 mtx_lock(&mh->mh_mtx);
203 MWL_HAL_LOCK_ASSERT(struct mwl_hal_priv *mh)
205 mtx_assert(&mh->mh_mtx, MA_OWNED);
209 MWL_HAL_UNLOCK(struct mwl_hal_priv *mh)
211 mtx_unlock(&mh->mh_mtx);
214 static __inline uint32_t
215 RD4(struct mwl_hal_priv *mh, bus_size_t off)
217 return bus_space_read_4(mh->public.mh_iot, mh->public.mh_ioh, off);
221 WR4(struct mwl_hal_priv *mh, bus_size_t off, uint32_t val)
223 bus_space_write_4(mh->public.mh_iot, mh->public.mh_ioh, off, val);
227 mwl_hal_load_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
229 bus_addr_t *paddr = (bus_addr_t*) arg;
230 KASSERT(error == 0, ("error %u on bus_dma callback", error));
231 *paddr = segs->ds_addr;
235 * Setup for communication with the device. We allocate
236 * a command buffer and map it for bus dma use. The pci
237 * device id is used to identify whether the device has
238 * SRAM on it (in which case f/w download must include a
239 * memory controller reset). All bus i/o operations happen
240 * in BAR 1; the driver passes in the tag and handle we need.
243 mwl_hal_attach(device_t dev, uint16_t devid,
244 bus_space_handle_t ioh, bus_space_tag_t iot, bus_dma_tag_t tag)
246 struct mwl_hal_priv *mh;
247 struct mwl_hal_vap *hvap;
250 mh = malloc(sizeof(struct mwl_hal_priv), M_DEVBUF, M_NOWAIT | M_ZERO);
254 mh->public.mh_ioh = ioh;
255 mh->public.mh_iot = iot;
256 for (i = 0; i < MWL_BASTREAMS_MAX; i++) {
257 mh->mh_streams[i].public.txq = ba2qid[i];
258 mh->mh_streams[i].stream = i;
259 /* construct back-mapping while we're at it */
260 if (mh->mh_streams[i].public.txq < MWL_BAQID_MAX)
261 qid2ba[mh->mh_streams[i].public.txq] = i;
263 device_printf(dev, "unexpected BA tx qid %d for "
264 "stream %d\n", mh->mh_streams[i].public.txq, i);
266 /* setup constant portion of vap state */
267 /* XXX should get max ap/client vap's from f/w */
269 hvap = &mh->mh_vaps[i];
270 hvap->vap_type = MWL_HAL_AP;
271 hvap->bss_type = htole16(WL_MAC_TYPE_PRIMARY_AP);
273 for (i++; i < MWL_MBSS_AP_MAX; i++) {
274 hvap = &mh->mh_vaps[i];
275 hvap->vap_type = MWL_HAL_AP;
276 hvap->bss_type = htole16(WL_MAC_TYPE_SECONDARY_AP);
279 hvap = &mh->mh_vaps[i];
280 hvap->vap_type = MWL_HAL_STA;
281 hvap->bss_type = htole16(WL_MAC_TYPE_PRIMARY_CLIENT);
283 for (i++; i < MWL_MBSS_MAX; i++) {
284 hvap = &mh->mh_vaps[i];
285 hvap->vap_type = MWL_HAL_STA;
286 hvap->bss_type = htole16(WL_MAC_TYPE_SECONDARY_CLIENT);
289 mh->mh_revs.mh_devid = devid;
290 snprintf(mh->mh_mtxname, sizeof(mh->mh_mtxname),
291 "%s_hal", device_get_nameunit(dev));
292 mtx_init(&mh->mh_mtx, mh->mh_mtxname, NULL, MTX_DEF);
295 * Allocate the command buffer and map into the address
296 * space of the h/w. We request "coherent" memory which
297 * will be uncached on some architectures.
299 error = bus_dma_tag_create(tag, /* parent */
300 PAGE_SIZE, 0, /* alignment, bounds */
301 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
302 BUS_SPACE_MAXADDR, /* highaddr */
303 NULL, NULL, /* filter, filterarg */
304 MWL_CMDBUF_SIZE, /* maxsize */
306 MWL_CMDBUF_SIZE, /* maxsegsize */
307 BUS_DMA_ALLOCNOW, /* flags */
312 device_printf(dev, "unable to allocate memory for cmd tag, "
313 "error %u\n", error);
317 /* allocate descriptors */
318 error = bus_dmamem_alloc(mh->mh_dmat, (void**) &mh->mh_cmdbuf,
319 BUS_DMA_NOWAIT | BUS_DMA_COHERENT,
322 device_printf(dev, "unable to allocate memory for cmd buffer, "
323 "error %u\n", error);
327 error = bus_dmamap_load(mh->mh_dmat, mh->mh_dmamap,
328 mh->mh_cmdbuf, MWL_CMDBUF_SIZE,
329 mwl_hal_load_cb, &mh->mh_cmdaddr,
332 device_printf(dev, "unable to load cmd buffer, error %u\n",
338 * Some cards have SDRAM. When loading firmware we need
339 * to reset the SDRAM controller prior to doing this.
340 * When the SDRAMSIZE is non-zero we do that work in
344 case 0x2a02: /* CB82 */
345 case 0x2a03: /* CB85 */
346 case 0x2a08: /* MC85_B1 */
347 case 0x2a0b: /* CB85AP */
349 mh->mh_SDRAMSIZE_Addr = 0x40fe70b7; /* 8M SDRAM */
351 case 0x2a04: /* MC85 */
352 mh->mh_SDRAMSIZE_Addr = 0x40fc70b7; /* 16M SDRAM */
359 bus_dmamem_free(mh->mh_dmat, mh->mh_cmdbuf, mh->mh_dmamap);
361 bus_dma_tag_destroy(mh->mh_dmat);
363 mtx_destroy(&mh->mh_mtx);
369 mwl_hal_detach(struct mwl_hal *mh0)
371 struct mwl_hal_priv *mh = MWLPRIV(mh0);
373 bus_dmamem_free(mh->mh_dmat, mh->mh_cmdbuf, mh->mh_dmamap);
374 bus_dma_tag_destroy(mh->mh_dmat);
375 mtx_destroy(&mh->mh_mtx);
380 * Reset internal state after a firmware download.
383 mwlResetHalState(struct mwl_hal_priv *mh)
387 /* XXX get from f/w */
388 mh->mh_bastreams = (1<<MWL_BASTREAMS_MAX)-1;
389 for (i = 0; i < MWL_MBSS_MAX; i++)
390 mh->mh_vaps[i].mh = NULL;
392 * Clear cumulative stats.
394 mh->mh_RTSSuccesses = 0;
395 mh->mh_RTSFailures = 0;
396 mh->mh_RxDuplicateFrames = 0;
397 mh->mh_FCSErrorCount = 0;
399 * Fetch cal data for later use.
400 * XXX may want to fetch other stuff too.
402 /* XXX check return */
403 if ((mh->mh_flags & MHF_CALDATA) == 0)
404 mwlGetPwrCalTable(mh);
409 mwl_hal_newvap(struct mwl_hal *mh0, MWL_HAL_BSSTYPE type,
410 const uint8_t mac[IEEE80211_ADDR_LEN])
412 struct mwl_hal_priv *mh = MWLPRIV(mh0);
413 struct mwl_hal_vap *vap;
417 /* NB: could optimize but not worth it w/ max 32 bss */
418 for (i = 0; i < MWL_MBSS_MAX; i++) {
419 vap = &mh->mh_vaps[i];
420 if (vap->vap_type == type && vap->mh == NULL) {
422 mwl_hal_setmac_locked(vap, mac);
427 return (i < MWL_MBSS_MAX) ? vap : NULL;
431 mwl_hal_delvap(struct mwl_hal_vap *vap)
433 /* NB: locking not needed for single write */
438 * Manipulate the debug mask. Note debug
439 * msgs are only provided when this code is
440 * compiled with MWLHAL_DEBUG defined.
444 mwl_hal_setdebug(struct mwl_hal *mh, int debug)
446 MWLPRIV(mh)->mh_debug = debug;
450 mwl_hal_getdebug(struct mwl_hal *mh)
452 return MWLPRIV(mh)->mh_debug;
456 mwl_hal_setbastreams(struct mwl_hal *mh, int mask)
458 MWLPRIV(mh)->mh_bastreams = mask & ((1<<MWL_BASTREAMS_MAX)-1);
462 mwl_hal_getbastreams(struct mwl_hal *mh)
464 return MWLPRIV(mh)->mh_bastreams;
468 mwl_hal_ismbsscapable(struct mwl_hal *mh)
470 return (MWLPRIV(mh)->mh_flags & MHF_MBSS) != 0;
476 * Return the current ISR setting and clear the cause.
477 * XXX maybe make inline
480 mwl_hal_getisr(struct mwl_hal *mh0, uint32_t *status)
482 struct mwl_hal_priv *mh = MWLPRIV(mh0);
485 cause = RD4(mh, MACREG_REG_A2H_INTERRUPT_CAUSE);
486 if (cause == 0xffffffff) { /* card removed */
487 device_printf(mh->mh_dev, "%s: cause 0x%x\n", __func__, cause);
489 } else if (cause != 0) {
490 /* clear cause bits */
491 WR4(mh, MACREG_REG_A2H_INTERRUPT_CAUSE,
492 cause &~ mh->public.mh_imask);
493 RD4(mh, MACREG_REG_INT_CODE); /* XXX flush write? */
500 * Set the interrupt mask.
503 mwl_hal_intrset(struct mwl_hal *mh0, uint32_t mask)
505 struct mwl_hal_priv *mh = MWLPRIV(mh0);
507 WR4(mh, MACREG_REG_A2H_INTERRUPT_MASK, 0);
508 RD4(mh, MACREG_REG_INT_CODE);
510 mh->public.mh_imask = mask;
511 WR4(mh, MACREG_REG_A2H_INTERRUPT_MASK, mask);
512 RD4(mh, MACREG_REG_INT_CODE);
518 * Kick the firmware to tell it there are new tx descriptors
519 * for processing. The driver says what h/w q has work in
520 * case the f/w ever gets smarter.
523 mwl_hal_txstart(struct mwl_hal *mh0, int qnum)
525 struct mwl_hal_priv *mh = MWLPRIV(mh0);
528 WR4(mh, MACREG_REG_H2A_INTERRUPT_EVENTS, MACREG_H2ARIC_BIT_PPA_READY);
529 dummy = RD4(mh, MACREG_REG_INT_CODE);
534 * Callback from the driver on a cmd done interrupt.
535 * Nothing to do right now as we spin waiting for
539 mwl_hal_cmddone(struct mwl_hal *mh0)
542 struct mwl_hal_priv *mh = MWLPRIV(mh0);
544 if (mh->mh_debug & MWL_HAL_DEBUG_CMDDONE) {
545 device_printf(mh->mh_dev, "cmd done interrupt:\n");
552 * Return "hw specs". Note this must be the first
553 * cmd MUST be done after a firmware download or the
555 * XXX move into the hal so driver doesn't need to be responsible
558 mwl_hal_gethwspecs(struct mwl_hal *mh0, struct mwl_hal_hwspec *hw)
560 struct mwl_hal_priv *mh = MWLPRIV(mh0);
561 HostCmd_DS_GET_HW_SPEC *pCmd;
565 _CMD_SETUP(pCmd, HostCmd_DS_GET_HW_SPEC, HostCmd_CMD_GET_HW_SPEC);
566 memset(&pCmd->PermanentAddr[0], 0xff, IEEE80211_ADDR_LEN);
567 pCmd->ulFwAwakeCookie = htole32((unsigned int)mh->mh_cmdaddr+2048);
569 retval = mwlExecuteCmd(mh, HostCmd_CMD_GET_HW_SPEC);
571 IEEE80211_ADDR_COPY(hw->macAddr, pCmd->PermanentAddr);
572 hw->wcbBase[0] = le32toh(pCmd->WcbBase0) & 0x0000ffff;
573 hw->wcbBase[1] = le32toh(pCmd->WcbBase1[0]) & 0x0000ffff;
574 hw->wcbBase[2] = le32toh(pCmd->WcbBase1[1]) & 0x0000ffff;
575 hw->wcbBase[3] = le32toh(pCmd->WcbBase1[2]) & 0x0000ffff;
576 hw->rxDescRead = le32toh(pCmd->RxPdRdPtr)& 0x0000ffff;
577 hw->rxDescWrite = le32toh(pCmd->RxPdWrPtr)& 0x0000ffff;
578 hw->regionCode = le16toh(pCmd->RegionCode) & 0x00ff;
579 hw->fwReleaseNumber = le32toh(pCmd->FWReleaseNumber);
580 hw->maxNumWCB = le16toh(pCmd->NumOfWCB);
581 hw->maxNumMCAddr = le16toh(pCmd->NumOfMCastAddr);
582 hw->numAntennas = le16toh(pCmd->NumberOfAntenna);
583 hw->hwVersion = pCmd->Version;
584 hw->hostInterface = pCmd->HostIf;
586 mh->mh_revs.mh_macRev = hw->hwVersion; /* XXX */
587 mh->mh_revs.mh_phyRev = hw->hostInterface; /* XXX */
589 minrev = ((hw->fwReleaseNumber) >> 16) & 0xff;
591 /* starting with 3.4.x.x s/w BA streams supported */
592 mh->mh_bastreams &= (1<<MWL_BASTREAMS_MAX)-1;
594 mh->mh_bastreams &= (1<<2)-1;
601 * Inform the f/w about location of the tx/rx dma data structures
602 * and related state. This cmd must be done immediately after a
603 * mwl_hal_gethwspecs call or the f/w will lockup.
606 mwl_hal_sethwdma(struct mwl_hal *mh0, const struct mwl_hal_txrxdma *dma)
608 struct mwl_hal_priv *mh = MWLPRIV(mh0);
609 HostCmd_DS_SET_HW_SPEC *pCmd;
613 _CMD_SETUP(pCmd, HostCmd_DS_SET_HW_SPEC, HostCmd_CMD_SET_HW_SPEC);
614 pCmd->WcbBase[0] = htole32(dma->wcbBase[0]);
615 pCmd->WcbBase[1] = htole32(dma->wcbBase[1]);
616 pCmd->WcbBase[2] = htole32(dma->wcbBase[2]);
617 pCmd->WcbBase[3] = htole32(dma->wcbBase[3]);
618 pCmd->TxWcbNumPerQueue = htole32(dma->maxNumTxWcb);
619 pCmd->NumTxQueues = htole32(dma->maxNumWCB);
620 pCmd->TotalRxWcb = htole32(1); /* XXX */
621 pCmd->RxPdWrPtr = htole32(dma->rxDescRead);
622 pCmd->Flags = htole32(SET_HW_SPEC_HOSTFORM_BEACON
623 #ifdef MWL_HOST_PS_SUPPORT
624 | SET_HW_SPEC_HOST_POWERSAVE
626 | SET_HW_SPEC_HOSTFORM_PROBERESP);
627 /* disable multi-bss operation for A1-A4 parts */
628 if (mh->mh_revs.mh_macRev < 5)
629 pCmd->Flags |= htole32(SET_HW_SPEC_DISABLEMBSS);
631 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_HW_SPEC);
633 if (pCmd->Flags & htole32(SET_HW_SPEC_DISABLEMBSS))
634 mh->mh_flags &= ~MHF_MBSS;
636 mh->mh_flags |= MHF_MBSS;
643 * Retrieve statistics from the f/w.
644 * XXX should be in memory shared w/ driver
647 mwl_hal_gethwstats(struct mwl_hal *mh0, struct mwl_hal_hwstats *stats)
649 struct mwl_hal_priv *mh = MWLPRIV(mh0);
650 HostCmd_DS_802_11_GET_STAT *pCmd;
654 _CMD_SETUP(pCmd, HostCmd_DS_802_11_GET_STAT,
655 HostCmd_CMD_802_11_GET_STAT);
657 retval = mwlExecuteCmd(mh, HostCmd_CMD_802_11_GET_STAT);
659 const uint32_t *sp = (const uint32_t *)&pCmd->TxRetrySuccesses;
660 uint32_t *dp = (uint32_t *)&stats->TxRetrySuccesses;
663 for (i = 0; i < sizeof(*stats)/sizeof(uint32_t); i++)
664 dp[i] = le32toh(sp[i]);
666 * Update stats not returned by f/w but available
667 * through public registers. Note these registers
668 * are "clear on read" so we maintain cumulative data.
669 * XXX register defines
671 mh->mh_RTSSuccesses += RD4(mh, 0xa834);
672 mh->mh_RTSFailures += RD4(mh, 0xa830);
673 mh->mh_RxDuplicateFrames += RD4(mh, 0xa84c);
674 mh->mh_FCSErrorCount += RD4(mh, 0xa840);
678 stats->RTSSuccesses = mh->mh_RTSSuccesses;
679 stats->RTSFailures = mh->mh_RTSFailures;
680 stats->RxDuplicateFrames = mh->mh_RxDuplicateFrames;
681 stats->FCSErrorCount = mh->mh_FCSErrorCount;
686 * Set HT guard interval handling.
687 * Takes effect immediately.
690 mwl_hal_sethtgi(struct mwl_hal_vap *vap, int GIType)
692 struct mwl_hal_priv *mh = MWLVAP(vap);
693 HostCmd_FW_HT_GUARD_INTERVAL *pCmd;
697 _VCMD_SETUP(vap, pCmd, HostCmd_FW_HT_GUARD_INTERVAL,
698 HostCmd_CMD_HT_GUARD_INTERVAL);
699 pCmd->Action = htole32(HostCmd_ACT_GEN_SET);
702 pCmd->GIType = htole32(GI_TYPE_LONG);
703 } else if (GIType == 1) {
704 pCmd->GIType = htole32(GI_TYPE_LONG | GI_TYPE_SHORT);
706 pCmd->GIType = htole32(GI_TYPE_LONG);
709 retval = mwlExecuteCmd(mh, HostCmd_CMD_HT_GUARD_INTERVAL);
716 * Takes effect immediately.
717 * XXX preamble installed after set fixed rate cmd
720 mwl_hal_setradio(struct mwl_hal *mh0, int onoff, MWL_HAL_PREAMBLE preamble)
722 struct mwl_hal_priv *mh = MWLPRIV(mh0);
723 HostCmd_DS_802_11_RADIO_CONTROL *pCmd;
727 _CMD_SETUP(pCmd, HostCmd_DS_802_11_RADIO_CONTROL,
728 HostCmd_CMD_802_11_RADIO_CONTROL);
729 pCmd->Action = htole16(HostCmd_ACT_GEN_SET);
733 pCmd->Control = htole16(preamble);
734 pCmd->RadioOn = htole16(onoff);
736 retval = mwlExecuteCmd(mh, HostCmd_CMD_802_11_RADIO_CONTROL);
742 * Configure antenna use.
743 * Takes effect immediately.
744 * XXX tx antenna setting ignored
745 * XXX rx antenna setting should always be 3 (for now)
748 mwl_hal_setantenna(struct mwl_hal *mh0, MWL_HAL_ANTENNA dirSet, int ant)
750 struct mwl_hal_priv *mh = MWLPRIV(mh0);
751 HostCmd_DS_802_11_RF_ANTENNA *pCmd;
754 if (!(dirSet == WL_ANTENNATYPE_RX || dirSet == WL_ANTENNATYPE_TX))
758 _CMD_SETUP(pCmd, HostCmd_DS_802_11_RF_ANTENNA,
759 HostCmd_CMD_802_11_RF_ANTENNA);
760 pCmd->Action = htole16(dirSet);
761 if (ant == 0) /* default to all/both antennae */
763 pCmd->AntennaMode = htole16(ant);
765 retval = mwlExecuteCmd(mh, HostCmd_CMD_802_11_RF_ANTENNA);
771 * Set packet size threshold for implicit use of RTS.
772 * Takes effect immediately.
773 * XXX packet length > threshold =>'s RTS
776 mwl_hal_setrtsthreshold(struct mwl_hal_vap *vap, int threshold)
778 struct mwl_hal_priv *mh = MWLVAP(vap);
779 HostCmd_DS_802_11_RTS_THSD *pCmd;
783 _VCMD_SETUP(vap, pCmd, HostCmd_DS_802_11_RTS_THSD,
784 HostCmd_CMD_802_11_RTS_THSD);
785 pCmd->Action = htole16(HostCmd_ACT_GEN_SET);
786 pCmd->Threshold = htole16(threshold);
788 retval = mwlExecuteCmd(mh, HostCmd_CMD_802_11_RTS_THSD);
794 * Enable sta-mode operation (disables beacon frame xmit).
797 mwl_hal_setinframode(struct mwl_hal_vap *vap)
799 struct mwl_hal_priv *mh = MWLVAP(vap);
800 HostCmd_FW_SET_INFRA_MODE *pCmd;
804 _VCMD_SETUP(vap, pCmd, HostCmd_FW_SET_INFRA_MODE,
805 HostCmd_CMD_SET_INFRA_MODE);
807 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_INFRA_MODE);
813 * Configure radar detection in support of 802.11h.
816 mwl_hal_setradardetection(struct mwl_hal *mh0, MWL_HAL_RADAR action)
818 struct mwl_hal_priv *mh = MWLPRIV(mh0);
819 HostCmd_802_11h_Detect_Radar *pCmd;
823 _CMD_SETUP(pCmd, HostCmd_802_11h_Detect_Radar,
824 HostCmd_CMD_802_11H_DETECT_RADAR);
825 pCmd->CmdHdr.Length = htole16(sizeof(HostCmd_802_11h_Detect_Radar));
826 pCmd->Action = htole16(action);
827 if (mh->mh_regioncode == DOMAIN_CODE_ETSI_131)
828 pCmd->RadarTypeCode = htole16(131);
830 retval = mwlExecuteCmd(mh, HostCmd_CMD_802_11H_DETECT_RADAR);
836 * Convert public channel flags definition to a
837 * value suitable for feeding to the firmware.
838 * Note this includes byte swapping.
841 cvtChannelFlags(const MWL_HAL_CHANNEL *chan)
846 * NB: f/w only understands FREQ_BAND_5GHZ, supplying the more
847 * precise band info causes it to lockup (sometimes).
849 w = (chan->channelFlags.FreqBand == MWL_FREQ_BAND_2DOT4GHZ) ?
850 FREQ_BAND_2DOT4GHZ : FREQ_BAND_5GHZ;
851 switch (chan->channelFlags.ChnlWidth) {
852 case MWL_CH_10_MHz_WIDTH:
853 w |= CH_10_MHz_WIDTH;
855 case MWL_CH_20_MHz_WIDTH:
856 w |= CH_20_MHz_WIDTH;
858 case MWL_CH_40_MHz_WIDTH:
860 w |= CH_40_MHz_WIDTH;
863 switch (chan->channelFlags.ExtChnlOffset) {
864 case MWL_EXT_CH_NONE:
867 case MWL_EXT_CH_ABOVE_CTRL_CH:
868 w |= EXT_CH_ABOVE_CTRL_CH;
870 case MWL_EXT_CH_BELOW_CTRL_CH:
871 w |= EXT_CH_BELOW_CTRL_CH;
878 * Start a channel switch announcement countdown. The IE
879 * in the beacon frame is allowed to go out and the firmware
880 * counts down and notifies the host when it's time to switch
884 mwl_hal_setchannelswitchie(struct mwl_hal *mh0,
885 const MWL_HAL_CHANNEL *nextchan, uint32_t mode, uint32_t count)
887 struct mwl_hal_priv *mh = MWLPRIV(mh0);
888 HostCmd_SET_SWITCH_CHANNEL *pCmd;
892 _CMD_SETUP(pCmd, HostCmd_SET_SWITCH_CHANNEL,
893 HostCmd_CMD_SET_SWITCH_CHANNEL);
894 pCmd->Next11hChannel = htole32(nextchan->channel);
895 pCmd->Mode = htole32(mode);
896 pCmd->InitialCount = htole32(count+1);
897 pCmd->ChannelFlags = cvtChannelFlags(nextchan);
899 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_SWITCH_CHANNEL);
905 * Set the region code that selects the radar bin'ing agorithm.
908 mwl_hal_setregioncode(struct mwl_hal *mh0, int regionCode)
910 struct mwl_hal_priv *mh = MWLPRIV(mh0);
911 HostCmd_SET_REGIONCODE_INFO *pCmd;
915 _CMD_SETUP(pCmd, HostCmd_SET_REGIONCODE_INFO,
916 HostCmd_CMD_SET_REGION_CODE);
917 /* XXX map pseudo-codes to fw codes */
918 switch (regionCode) {
919 case DOMAIN_CODE_ETSI_131:
920 pCmd->regionCode = htole16(DOMAIN_CODE_ETSI);
923 pCmd->regionCode = htole16(regionCode);
927 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_REGION_CODE);
929 mh->mh_regioncode = regionCode;
934 #define RATEVAL(r) ((r) &~ RATE_MCS)
935 #define RATETYPE(r) (((r) & RATE_MCS) ? HT_RATE_TYPE : LEGACY_RATE_TYPE)
938 mwl_hal_settxrate(struct mwl_hal_vap *vap, MWL_HAL_TXRATE_HANDLING handling,
939 const MWL_HAL_TXRATE *rate)
941 struct mwl_hal_priv *mh = MWLVAP(vap);
942 HostCmd_FW_USE_FIXED_RATE *pCmd;
943 FIXED_RATE_ENTRY *fp;
947 _VCMD_SETUP(vap, pCmd, HostCmd_FW_USE_FIXED_RATE,
948 HostCmd_CMD_SET_FIXED_RATE);
950 pCmd->MulticastRate = RATEVAL(rate->McastRate);
951 pCmd->MultiRateTxType = RATETYPE(rate->McastRate);
952 /* NB: no rate type field */
953 pCmd->ManagementRate = RATEVAL(rate->MgtRate);
954 memset(pCmd->FixedRateTable, 0, sizeof(pCmd->FixedRateTable));
955 if (handling == RATE_FIXED) {
956 pCmd->Action = htole32(HostCmd_ACT_GEN_SET);
957 pCmd->AllowRateDrop = htole32(FIXED_RATE_WITHOUT_AUTORATE_DROP);
958 fp = pCmd->FixedRateTable;
960 htole32(RATEVAL(rate->RateSeries[0].Rate));
961 fp->FixRateTypeFlags.FixRateType =
962 htole32(RATETYPE(rate->RateSeries[0].Rate));
963 pCmd->EntryCount = htole32(1);
964 } else if (handling == RATE_FIXED_DROP) {
965 pCmd->Action = htole32(HostCmd_ACT_GEN_SET);
966 pCmd->AllowRateDrop = htole32(FIXED_RATE_WITH_AUTO_RATE_DROP);
968 fp = pCmd->FixedRateTable;
969 for (i = 0; i < 4; i++) {
970 if (rate->RateSeries[0].TryCount == 0)
972 fp->FixRateTypeFlags.FixRateType =
973 htole32(RATETYPE(rate->RateSeries[i].Rate));
975 htole32(RATEVAL(rate->RateSeries[i].Rate));
976 fp->FixRateTypeFlags.RetryCountValid =
977 htole32(RETRY_COUNT_VALID);
979 htole32(rate->RateSeries[i].TryCount-1);
982 pCmd->EntryCount = htole32(n);
984 pCmd->Action = htole32(HostCmd_ACT_NOT_USE_FIXED_RATE);
986 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_FIXED_RATE);
992 mwl_hal_settxrate_auto(struct mwl_hal *mh0, const MWL_HAL_TXRATE *rate)
994 struct mwl_hal_priv *mh = MWLPRIV(mh0);
995 HostCmd_FW_USE_FIXED_RATE *pCmd;
999 _CMD_SETUP(pCmd, HostCmd_FW_USE_FIXED_RATE,
1000 HostCmd_CMD_SET_FIXED_RATE);
1002 pCmd->MulticastRate = RATEVAL(rate->McastRate);
1003 pCmd->MultiRateTxType = RATETYPE(rate->McastRate);
1004 /* NB: no rate type field */
1005 pCmd->ManagementRate = RATEVAL(rate->MgtRate);
1006 memset(pCmd->FixedRateTable, 0, sizeof(pCmd->FixedRateTable));
1007 pCmd->Action = htole32(HostCmd_ACT_NOT_USE_FIXED_RATE);
1009 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_FIXED_RATE);
1018 mwl_hal_setslottime(struct mwl_hal *mh0, int usecs)
1020 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1021 HostCmd_FW_SET_SLOT *pCmd;
1024 if (usecs != 9 && usecs != 20)
1028 _CMD_SETUP(pCmd, HostCmd_FW_SET_SLOT,
1029 HostCmd_CMD_802_11_SET_SLOT);
1030 pCmd->Action = htole16(HostCmd_ACT_GEN_SET);
1031 pCmd->Slot = (usecs == 9 ? 1 : 0);
1033 retval = mwlExecuteCmd(mh, HostCmd_CMD_802_11_SET_SLOT);
1039 mwl_hal_adjusttxpower(struct mwl_hal *mh0, uint32_t level)
1041 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1042 HostCmd_DS_802_11_RF_TX_POWER *pCmd;
1046 _CMD_SETUP(pCmd, HostCmd_DS_802_11_RF_TX_POWER,
1047 HostCmd_CMD_802_11_RF_TX_POWER);
1048 pCmd->Action = htole16(HostCmd_ACT_GEN_SET);
1051 pCmd->SupportTxPowerLevel = htole16(WL_TX_POWERLEVEL_LOW);
1052 } else if (level >= 30 && level < 60) {
1053 pCmd->SupportTxPowerLevel = htole16(WL_TX_POWERLEVEL_MEDIUM);
1055 pCmd->SupportTxPowerLevel = htole16(WL_TX_POWERLEVEL_HIGH);
1058 retval = mwlExecuteCmd(mh, HostCmd_CMD_802_11_RF_TX_POWER);
1063 static const struct mwl_hal_channel *
1064 findchannel(const struct mwl_hal_priv *mh, const MWL_HAL_CHANNEL *c)
1066 const struct mwl_hal_channel *hc;
1067 const MWL_HAL_CHANNELINFO *ci;
1068 int chan = c->channel, i;
1070 if (c->channelFlags.FreqBand == MWL_FREQ_BAND_2DOT4GHZ) {
1072 if (c->channelFlags.ChnlWidth == MWL_CH_40_MHz_WIDTH) {
1074 if (c->channelFlags.ExtChnlOffset == MWL_EXT_CH_BELOW_CTRL_CH)
1078 /* 2.4G channel table is directly indexed */
1079 hc = ((unsigned)i < ci->nchannels) ? &ci->channels[i] : NULL;
1080 } else if (c->channelFlags.FreqBand == MWL_FREQ_BAND_5GHZ) {
1081 if (c->channelFlags.ChnlWidth == MWL_CH_40_MHz_WIDTH) {
1082 ci = &mh->mh_40M_5G;
1083 if (c->channelFlags.ExtChnlOffset == MWL_EXT_CH_BELOW_CTRL_CH)
1086 ci = &mh->mh_20M_5G;
1087 /* 5GHz channel table is sparse and must be searched */
1088 for (i = 0; i < ci->nchannels; i++)
1089 if (ci->channels[i].ieee == chan)
1091 hc = (i < ci->nchannels) ? &ci->channels[i] : NULL;
1098 mwl_hal_settxpower(struct mwl_hal *mh0, const MWL_HAL_CHANNEL *c, uint8_t maxtxpow)
1100 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1101 HostCmd_DS_802_11_RF_TX_POWER *pCmd;
1102 const struct mwl_hal_channel *hc;
1105 hc = findchannel(mh, c);
1107 /* XXX temp while testing */
1108 device_printf(mh->mh_dev,
1109 "%s: no cal data for channel %u band %u width %u ext %u\n",
1110 __func__, c->channel, c->channelFlags.FreqBand,
1111 c->channelFlags.ChnlWidth, c->channelFlags.ExtChnlOffset);
1116 _CMD_SETUP(pCmd, HostCmd_DS_802_11_RF_TX_POWER,
1117 HostCmd_CMD_802_11_RF_TX_POWER);
1118 pCmd->Action = htole16(HostCmd_ACT_GEN_SET_LIST);
1120 /* NB: 5Ghz cal data have the channel # in [0]; don't truncate */
1121 if (c->channelFlags.FreqBand == MWL_FREQ_BAND_5GHZ)
1122 pCmd->PowerLevelList[i++] = htole16(hc->targetPowers[0]);
1123 for (; i < 4; i++) {
1124 uint16_t pow = hc->targetPowers[i];
1127 pCmd->PowerLevelList[i] = htole16(pow);
1129 retval = mwlExecuteCmd(mh, HostCmd_CMD_802_11_RF_TX_POWER);
1135 mwl_hal_getchannelinfo(struct mwl_hal *mh0, int band, int chw,
1136 const MWL_HAL_CHANNELINFO **ci)
1138 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1141 case MWL_FREQ_BAND_2DOT4GHZ:
1142 *ci = (chw == MWL_CH_20_MHz_WIDTH) ? &mh->mh_20M : &mh->mh_40M;
1144 case MWL_FREQ_BAND_5GHZ:
1145 *ci = (chw == MWL_CH_20_MHz_WIDTH) ?
1146 &mh->mh_20M_5G : &mh->mh_40M_5G;
1151 return ((*ci)->freqLow == (*ci)->freqHigh) ? EINVAL : 0;
1155 mwl_hal_setmcast(struct mwl_hal *mh0, int nmc, const uint8_t macs[])
1157 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1158 HostCmd_DS_MAC_MULTICAST_ADR *pCmd;
1161 if (nmc > MWL_HAL_MCAST_MAX)
1165 _CMD_SETUP(pCmd, HostCmd_DS_MAC_MULTICAST_ADR,
1166 HostCmd_CMD_MAC_MULTICAST_ADR);
1167 memcpy(pCmd->MACList, macs, nmc*IEEE80211_ADDR_LEN);
1168 pCmd->NumOfAdrs = htole16(nmc);
1169 pCmd->Action = htole16(0xffff);
1171 retval = mwlExecuteCmd(mh, HostCmd_CMD_MAC_MULTICAST_ADR);
1177 mwl_hal_keyset(struct mwl_hal_vap *vap, const MWL_HAL_KEYVAL *kv,
1178 const uint8_t mac[IEEE80211_ADDR_LEN])
1180 struct mwl_hal_priv *mh = MWLVAP(vap);
1181 HostCmd_FW_UPDATE_ENCRYPTION_SET_KEY *pCmd;
1185 _VCMD_SETUP(vap, pCmd, HostCmd_FW_UPDATE_ENCRYPTION_SET_KEY,
1186 HostCmd_CMD_UPDATE_ENCRYPTION);
1187 if (kv->keyFlags & (KEY_FLAG_TXGROUPKEY|KEY_FLAG_RXGROUPKEY))
1188 pCmd->ActionType = htole32(EncrActionTypeSetGroupKey);
1190 pCmd->ActionType = htole32(EncrActionTypeSetKey);
1191 pCmd->KeyParam.Length = htole16(sizeof(pCmd->KeyParam));
1192 pCmd->KeyParam.KeyTypeId = htole16(kv->keyTypeId);
1193 pCmd->KeyParam.KeyInfo = htole32(kv->keyFlags);
1194 pCmd->KeyParam.KeyIndex = htole32(kv->keyIndex);
1195 /* NB: includes TKIP MIC keys */
1196 memcpy(&pCmd->KeyParam.Key, &kv->key, kv->keyLen);
1197 switch (kv->keyTypeId) {
1198 case KEY_TYPE_ID_WEP:
1199 pCmd->KeyParam.KeyLen = htole16(kv->keyLen);
1201 case KEY_TYPE_ID_TKIP:
1202 pCmd->KeyParam.KeyLen = htole16(sizeof(TKIP_TYPE_KEY));
1203 pCmd->KeyParam.Key.TkipKey.TkipRsc.low =
1204 htole16(kv->key.tkip.rsc.low);
1205 pCmd->KeyParam.Key.TkipKey.TkipRsc.high =
1206 htole32(kv->key.tkip.rsc.high);
1207 pCmd->KeyParam.Key.TkipKey.TkipTsc.low =
1208 htole16(kv->key.tkip.tsc.low);
1209 pCmd->KeyParam.Key.TkipKey.TkipTsc.high =
1210 htole32(kv->key.tkip.tsc.high);
1212 case KEY_TYPE_ID_AES:
1213 pCmd->KeyParam.KeyLen = htole16(sizeof(AES_TYPE_KEY));
1216 #ifdef MWL_MBSS_SUPPORT
1217 IEEE80211_ADDR_COPY(pCmd->KeyParam.Macaddr, mac);
1219 IEEE80211_ADDR_COPY(pCmd->Macaddr, mac);
1221 retval = mwlExecuteCmd(mh, HostCmd_CMD_UPDATE_ENCRYPTION);
1227 mwl_hal_keyreset(struct mwl_hal_vap *vap, const MWL_HAL_KEYVAL *kv, const uint8_t mac[IEEE80211_ADDR_LEN])
1229 struct mwl_hal_priv *mh = MWLVAP(vap);
1230 HostCmd_FW_UPDATE_ENCRYPTION_SET_KEY *pCmd;
1234 _VCMD_SETUP(vap, pCmd, HostCmd_FW_UPDATE_ENCRYPTION_SET_KEY,
1235 HostCmd_CMD_UPDATE_ENCRYPTION);
1236 pCmd->ActionType = htole16(EncrActionTypeRemoveKey);
1237 pCmd->KeyParam.Length = htole16(sizeof(pCmd->KeyParam));
1238 pCmd->KeyParam.KeyTypeId = htole16(kv->keyTypeId);
1239 pCmd->KeyParam.KeyInfo = htole32(kv->keyFlags);
1240 pCmd->KeyParam.KeyIndex = htole32(kv->keyIndex);
1241 #ifdef MWL_MBSS_SUPPORT
1242 IEEE80211_ADDR_COPY(pCmd->KeyParam.Macaddr, mac);
1244 IEEE80211_ADDR_COPY(pCmd->Macaddr, mac);
1246 retval = mwlExecuteCmd(mh, HostCmd_CMD_UPDATE_ENCRYPTION);
1252 mwl_hal_setmac_locked(struct mwl_hal_vap *vap,
1253 const uint8_t addr[IEEE80211_ADDR_LEN])
1255 struct mwl_hal_priv *mh = MWLVAP(vap);
1256 HostCmd_DS_SET_MAC *pCmd;
1258 _VCMD_SETUP(vap, pCmd, HostCmd_DS_SET_MAC, HostCmd_CMD_SET_MAC_ADDR);
1259 IEEE80211_ADDR_COPY(&pCmd->MacAddr[0], addr);
1260 #ifdef MWL_MBSS_SUPPORT
1261 pCmd->MacType = vap->bss_type; /* NB: already byte swapped */
1262 IEEE80211_ADDR_COPY(vap->mac, addr); /* XXX do only if success */
1264 return mwlExecuteCmd(mh, HostCmd_CMD_SET_MAC_ADDR);
1268 mwl_hal_setmac(struct mwl_hal_vap *vap, const uint8_t addr[IEEE80211_ADDR_LEN])
1270 struct mwl_hal_priv *mh = MWLVAP(vap);
1274 retval = mwl_hal_setmac_locked(vap, addr);
1280 mwl_hal_setbeacon(struct mwl_hal_vap *vap, const void *frame, size_t frameLen)
1282 struct mwl_hal_priv *mh = MWLVAP(vap);
1283 HostCmd_DS_SET_BEACON *pCmd;
1286 /* XXX verify frameLen fits */
1288 _VCMD_SETUP(vap, pCmd, HostCmd_DS_SET_BEACON, HostCmd_CMD_SET_BEACON);
1289 /* XXX override _VCMD_SETUP */
1290 pCmd->CmdHdr.Length = htole16(sizeof(HostCmd_DS_SET_BEACON)-1+frameLen);
1291 pCmd->FrmBodyLen = htole16(frameLen);
1292 memcpy(pCmd->FrmBody, frame, frameLen);
1294 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_BEACON);
1300 mwl_hal_setpowersave_bss(struct mwl_hal_vap *vap, uint8_t nsta)
1302 struct mwl_hal_priv *mh = MWLVAP(vap);
1303 HostCmd_SET_POWERSAVESTATION *pCmd;
1307 _VCMD_SETUP(vap, pCmd, HostCmd_SET_POWERSAVESTATION,
1308 HostCmd_CMD_SET_POWERSAVESTATION);
1309 pCmd->NumberOfPowersave = nsta;
1311 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_POWERSAVESTATION);
1317 mwl_hal_setpowersave_sta(struct mwl_hal_vap *vap, uint16_t aid, int ena)
1319 struct mwl_hal_priv *mh = MWLVAP(vap);
1320 HostCmd_SET_TIM *pCmd;
1324 _VCMD_SETUP(vap, pCmd, HostCmd_SET_TIM, HostCmd_CMD_SET_TIM);
1325 pCmd->Aid = htole16(aid);
1326 pCmd->Set = htole32(ena);
1328 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_TIM);
1334 mwl_hal_setassocid(struct mwl_hal_vap *vap,
1335 const uint8_t bssId[IEEE80211_ADDR_LEN], uint16_t assocId)
1337 struct mwl_hal_priv *mh = MWLVAP(vap);
1338 HostCmd_FW_SET_AID *pCmd = (HostCmd_FW_SET_AID *) &mh->mh_cmdbuf[0];
1342 _VCMD_SETUP(vap, pCmd, HostCmd_FW_SET_AID, HostCmd_CMD_SET_AID);
1343 pCmd->AssocID = htole16(assocId);
1344 IEEE80211_ADDR_COPY(&pCmd->MacAddr[0], bssId);
1346 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_AID);
1352 mwl_hal_setchannel(struct mwl_hal *mh0, const MWL_HAL_CHANNEL *chan)
1354 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1355 HostCmd_FW_SET_RF_CHANNEL *pCmd;
1359 _CMD_SETUP(pCmd, HostCmd_FW_SET_RF_CHANNEL, HostCmd_CMD_SET_RF_CHANNEL);
1360 pCmd->Action = htole16(HostCmd_ACT_GEN_SET);
1361 pCmd->CurrentChannel = chan->channel;
1362 pCmd->ChannelFlags = cvtChannelFlags(chan); /* NB: byte-swapped */
1364 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_RF_CHANNEL);
1370 bastream_check_available(struct mwl_hal_vap *vap, int qid,
1371 const uint8_t Macaddr[IEEE80211_ADDR_LEN],
1372 uint8_t Tid, uint8_t ParamInfo)
1374 struct mwl_hal_priv *mh = MWLVAP(vap);
1375 HostCmd_FW_BASTREAM *pCmd;
1378 MWL_HAL_LOCK_ASSERT(mh);
1380 _VCMD_SETUP(vap, pCmd, HostCmd_FW_BASTREAM, HostCmd_CMD_BASTREAM);
1381 pCmd->ActionType = htole32(BaCheckCreateStream);
1382 pCmd->BaInfo.CreateParams.BarThrs = htole32(63);
1383 pCmd->BaInfo.CreateParams.WindowSize = htole32(64);
1384 pCmd->BaInfo.CreateParams.IdleThrs = htole32(0x22000);
1385 IEEE80211_ADDR_COPY(&pCmd->BaInfo.CreateParams.PeerMacAddr[0], Macaddr);
1386 pCmd->BaInfo.CreateParams.DialogToken = 10;
1387 pCmd->BaInfo.CreateParams.Tid = Tid;
1388 pCmd->BaInfo.CreateParams.QueueId = qid;
1389 pCmd->BaInfo.CreateParams.ParamInfo = (uint8_t) ParamInfo;
1391 cvtBAFlags(&pCmd->BaInfo.CreateParams.Flags, sp->ba_policy, 0);
1393 pCmd->BaInfo.CreateParams.Flags =
1394 htole32(BASTREAM_FLAG_IMMEDIATE_TYPE)
1395 | htole32(BASTREAM_FLAG_DIRECTION_UPSTREAM)
1399 retval = mwlExecuteCmd(mh, HostCmd_CMD_BASTREAM);
1402 * NB: BA stream create may fail when the stream is
1403 * h/w backed under some (as yet not understood) conditions.
1404 * Check the result code to catch this.
1406 if (le16toh(pCmd->CmdHdr.Result) != HostCmd_RESULT_OK)
1412 const MWL_HAL_BASTREAM *
1413 mwl_hal_bastream_alloc(struct mwl_hal_vap *vap, int ba_policy,
1414 const uint8_t Macaddr[IEEE80211_ADDR_LEN],
1415 uint8_t Tid, uint8_t ParamInfo, void *a1, void *a2)
1417 struct mwl_hal_priv *mh = MWLVAP(vap);
1418 struct mwl_hal_bastream *sp;
1422 if (mh->mh_bastreams == 0) {
1423 /* no streams available */
1427 for (s = 0; (mh->mh_bastreams & (1<<s)) == 0; s++)
1429 if (bastream_check_available(vap, s, Macaddr, Tid, ParamInfo)) {
1433 sp = &mh->mh_streams[s];
1434 mh->mh_bastreams &= ~(1<<s);
1435 sp->public.data[0] = a1;
1436 sp->public.data[1] = a2;
1437 IEEE80211_ADDR_COPY(sp->macaddr, Macaddr);
1439 sp->paraminfo = ParamInfo;
1441 sp->ba_policy = ba_policy;
1446 const MWL_HAL_BASTREAM *
1447 mwl_hal_bastream_lookup(struct mwl_hal *mh0, int s)
1449 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1451 if (!(0 <= s && s < MWL_BASTREAMS_MAX))
1453 if (mh->mh_bastreams & (1<<s))
1455 return &mh->mh_streams[s].public;
1459 #define __DECONST(type, var) ((type)(uintptr_t)(const void *)(var))
1463 mwl_hal_bastream_create(struct mwl_hal_vap *vap,
1464 const MWL_HAL_BASTREAM *s, int BarThrs, int WindowSize, uint16_t seqno)
1466 struct mwl_hal_priv *mh = MWLVAP(vap);
1467 struct mwl_hal_bastream *sp = __DECONST(struct mwl_hal_bastream *, s);
1468 HostCmd_FW_BASTREAM *pCmd;
1472 _VCMD_SETUP(vap, pCmd, HostCmd_FW_BASTREAM, HostCmd_CMD_BASTREAM);
1473 pCmd->ActionType = htole32(BaCreateStream);
1474 pCmd->BaInfo.CreateParams.BarThrs = htole32(BarThrs);
1475 pCmd->BaInfo.CreateParams.WindowSize = htole32(WindowSize);
1476 pCmd->BaInfo.CreateParams.IdleThrs = htole32(0x22000);
1477 IEEE80211_ADDR_COPY(&pCmd->BaInfo.CreateParams.PeerMacAddr[0],
1480 memset(&pCmd->BaInfo.CreateParams.StaSrcMacAddr, 0, IEEE80211_ADDR_LEN);
1482 pCmd->BaInfo.CreateParams.DialogToken = DialogToken;
1484 pCmd->BaInfo.CreateParams.DialogToken = 10;
1486 pCmd->BaInfo.CreateParams.Tid = sp->tid;
1487 pCmd->BaInfo.CreateParams.QueueId = sp->stream;
1488 pCmd->BaInfo.CreateParams.ParamInfo = sp->paraminfo;
1489 /* NB: ResetSeqNo known to be zero */
1490 pCmd->BaInfo.CreateParams.StartSeqNo = htole16(seqno);
1492 cvtBAFlags(&pCmd->BaInfo.CreateParams.Flags, sp->ba_policy, 0);
1494 pCmd->BaInfo.CreateParams.Flags =
1495 htole32(BASTREAM_FLAG_IMMEDIATE_TYPE)
1496 | htole32(BASTREAM_FLAG_DIRECTION_UPSTREAM)
1500 retval = mwlExecuteCmd(mh, HostCmd_CMD_BASTREAM);
1503 * NB: BA stream create may fail when the stream is
1504 * h/w backed under some (as yet not understood) conditions.
1505 * Check the result code to catch this.
1507 if (le16toh(pCmd->CmdHdr.Result) != HostCmd_RESULT_OK)
1517 mwl_hal_bastream_destroy(struct mwl_hal *mh0, const MWL_HAL_BASTREAM *s)
1519 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1520 struct mwl_hal_bastream *sp = __DECONST(struct mwl_hal_bastream *, s);
1521 HostCmd_FW_BASTREAM *pCmd;
1524 if (sp->stream >= MWL_BASTREAMS_MAX) {
1530 _CMD_SETUP(pCmd, HostCmd_FW_BASTREAM, HostCmd_CMD_BASTREAM);
1531 pCmd->ActionType = htole32(BaDestroyStream);
1532 pCmd->BaInfo.DestroyParams.FwBaContext.Context =
1533 htole32(sp->stream);
1535 retval = mwlExecuteCmd(mh, HostCmd_CMD_BASTREAM);
1538 /* NB: always reclaim stream */
1539 mh->mh_bastreams |= 1<<sp->stream;
1540 sp->public.data[0] = NULL;
1541 sp->public.data[1] = NULL;
1548 mwl_hal_bastream_get_seqno(struct mwl_hal *mh0,
1549 const MWL_HAL_BASTREAM *s, const uint8_t Macaddr[IEEE80211_ADDR_LEN],
1552 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1553 struct mwl_hal_bastream *sp = __DECONST(struct mwl_hal_bastream *, s);
1554 HostCmd_GET_SEQNO *pCmd;
1558 _CMD_SETUP(pCmd, HostCmd_GET_SEQNO, HostCmd_CMD_GET_SEQNO);
1559 IEEE80211_ADDR_COPY(pCmd->MacAddr, Macaddr);
1560 pCmd->TID = sp->tid;
1562 retval = mwlExecuteCmd(mh, HostCmd_CMD_GET_SEQNO);
1564 *pseqno = le16toh(pCmd->SeqNo);
1570 mwl_hal_getwatchdogbitmap(struct mwl_hal *mh0, uint8_t bitmap[1])
1572 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1573 HostCmd_FW_GET_WATCHDOG_BITMAP *pCmd;
1577 _CMD_SETUP(pCmd, HostCmd_FW_GET_WATCHDOG_BITMAP,
1578 HostCmd_CMD_GET_WATCHDOG_BITMAP);
1580 retval = mwlExecuteCmd(mh, HostCmd_CMD_GET_WATCHDOG_BITMAP);
1582 bitmap[0] = pCmd->Watchdogbitmap;
1583 /* fw returns qid, map it to BA stream */
1584 if (bitmap[0] < MWL_BAQID_MAX)
1585 bitmap[0] = qid2ba[bitmap[0]];
1592 * Configure aggressive Ampdu rate mode.
1595 mwl_hal_setaggampduratemode(struct mwl_hal *mh0, int mode, int threshold)
1597 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1598 HostCmd_FW_AMPDU_RETRY_RATEDROP_MODE *pCmd;
1602 _CMD_SETUP(pCmd, HostCmd_FW_AMPDU_RETRY_RATEDROP_MODE,
1603 HostCmd_CMD_AMPDU_RETRY_RATEDROP_MODE);
1604 pCmd->Action = htole16(1);
1605 pCmd->Option = htole32(mode);
1606 pCmd->Threshold = htole32(threshold);
1608 retval = mwlExecuteCmd(mh, HostCmd_CMD_AMPDU_RETRY_RATEDROP_MODE);
1614 mwl_hal_getaggampduratemode(struct mwl_hal *mh0, int *mode, int *threshold)
1616 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1617 HostCmd_FW_AMPDU_RETRY_RATEDROP_MODE *pCmd;
1621 _CMD_SETUP(pCmd, HostCmd_FW_AMPDU_RETRY_RATEDROP_MODE,
1622 HostCmd_CMD_AMPDU_RETRY_RATEDROP_MODE);
1623 pCmd->Action = htole16(0);
1625 retval = mwlExecuteCmd(mh, HostCmd_CMD_AMPDU_RETRY_RATEDROP_MODE);
1627 *mode = le32toh(pCmd->Option);
1628 *threshold = le32toh(pCmd->Threshold);
1633 * Set CFEND status Enable/Disable
1636 mwl_hal_setcfend(struct mwl_hal *mh0, int ena)
1638 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1639 HostCmd_CFEND_ENABLE *pCmd;
1643 _CMD_SETUP(pCmd, HostCmd_CFEND_ENABLE,
1644 HostCmd_CMD_CFEND_ENABLE);
1645 pCmd->Enable = htole32(ena);
1647 retval = mwlExecuteCmd(mh, HostCmd_CMD_CFEND_ENABLE);
1653 mwl_hal_setdwds(struct mwl_hal *mh0, int ena)
1655 HostCmd_DWDS_ENABLE *pCmd;
1656 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1660 _CMD_SETUP(pCmd, HostCmd_DWDS_ENABLE, HostCmd_CMD_DWDS_ENABLE);
1661 pCmd->Enable = htole32(ena);
1662 retval = mwlExecuteCmd(mh, HostCmd_CMD_DWDS_ENABLE);
1668 cvtPeerInfo(PeerInfo_t *to, const MWL_HAL_PEERINFO *from)
1670 to->LegacyRateBitMap = htole32(from->LegacyRateBitMap);
1671 to->HTRateBitMap = htole32(from->HTRateBitMap);
1672 to->CapInfo = htole16(from->CapInfo);
1673 to->HTCapabilitiesInfo = htole16(from->HTCapabilitiesInfo);
1674 to->MacHTParamInfo = from->MacHTParamInfo;
1675 to->AddHtInfo.ControlChan = from->AddHtInfo.ControlChan;
1676 to->AddHtInfo.AddChan = from->AddHtInfo.AddChan;
1677 to->AddHtInfo.OpMode = htole16(from->AddHtInfo.OpMode);
1678 to->AddHtInfo.stbc = htole16(from->AddHtInfo.stbc);
1681 /* XXX station id must be in [0..63] */
1683 mwl_hal_newstation(struct mwl_hal_vap *vap,
1684 const uint8_t addr[IEEE80211_ADDR_LEN], uint16_t aid, uint16_t sid,
1685 const MWL_HAL_PEERINFO *peer, int isQosSta, int wmeInfo)
1687 struct mwl_hal_priv *mh = MWLVAP(vap);
1688 HostCmd_FW_SET_NEW_STN *pCmd;
1692 _VCMD_SETUP(vap, pCmd, HostCmd_FW_SET_NEW_STN, HostCmd_CMD_SET_NEW_STN);
1693 pCmd->AID = htole16(aid);
1694 pCmd->StnId = htole16(sid);
1695 pCmd->Action = htole16(0); /* SET */
1697 /* NB: must fix up byte order */
1698 cvtPeerInfo(&pCmd->PeerInfo, peer);
1700 IEEE80211_ADDR_COPY(&pCmd->MacAddr[0], addr);
1701 pCmd->Qosinfo = wmeInfo;
1702 pCmd->isQosSta = (isQosSta != 0);
1704 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_NEW_STN);
1705 if (retval == 0 && IEEE80211_ADDR_EQ(vap->mac, addr))
1706 vap->flags |= MVF_STATION;
1712 mwl_hal_delstation(struct mwl_hal_vap *vap,
1713 const uint8_t addr[IEEE80211_ADDR_LEN])
1715 struct mwl_hal_priv *mh = MWLVAP(vap);
1716 HostCmd_FW_SET_NEW_STN *pCmd;
1717 int retval, islocal;
1720 islocal = IEEE80211_ADDR_EQ(vap->mac, addr);
1721 if (!islocal || (vap->flags & MVF_STATION)) {
1722 _VCMD_SETUP(vap, pCmd, HostCmd_FW_SET_NEW_STN,
1723 HostCmd_CMD_SET_NEW_STN);
1724 pCmd->Action = htole16(2); /* REMOVE */
1725 IEEE80211_ADDR_COPY(&pCmd->MacAddr[0], addr);
1726 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_NEW_STN);
1728 vap->flags &= ~MVF_STATION;
1736 * Prod the firmware to age packets on station power
1737 * save queues and reap frames on the tx aggregation q's.
1740 mwl_hal_setkeepalive(struct mwl_hal *mh0)
1742 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1743 HostCmd_FW_SET_KEEP_ALIVE_TICK *pCmd;
1747 _CMD_SETUP(pCmd, HostCmd_FW_SET_KEEP_ALIVE_TICK,
1748 HostCmd_CMD_SET_KEEP_ALIVE);
1750 * NB: tick must be 0 to prod the f/w;
1751 * a non-zero value is a noop.
1755 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_KEEP_ALIVE);
1761 mwl_hal_setapmode(struct mwl_hal_vap *vap, MWL_HAL_APMODE ApMode)
1763 struct mwl_hal_priv *mh = MWLVAP(vap);
1764 HostCmd_FW_SET_APMODE *pCmd;
1767 /* XXX validate ApMode? */
1770 _VCMD_SETUP(vap, pCmd, HostCmd_FW_SET_APMODE, HostCmd_CMD_SET_APMODE);
1771 pCmd->ApMode = ApMode;
1773 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_APMODE);
1779 mwl_hal_stop(struct mwl_hal_vap *vap)
1781 struct mwl_hal_priv *mh = MWLVAP(vap);
1782 HostCmd_DS_BSS_START *pCmd;
1786 if (vap->flags & MVF_RUNNING) {
1787 _VCMD_SETUP(vap, pCmd, HostCmd_DS_BSS_START,
1788 HostCmd_CMD_BSS_START);
1789 pCmd->Enable = htole32(HostCmd_ACT_GEN_OFF);
1790 retval = mwlExecuteCmd(mh, HostCmd_CMD_BSS_START);
1793 /* NB: mark !running regardless */
1794 vap->flags &= ~MVF_RUNNING;
1800 mwl_hal_start(struct mwl_hal_vap *vap)
1802 struct mwl_hal_priv *mh = MWLVAP(vap);
1803 HostCmd_DS_BSS_START *pCmd;
1807 _VCMD_SETUP(vap, pCmd, HostCmd_DS_BSS_START, HostCmd_CMD_BSS_START);
1808 pCmd->Enable = htole32(HostCmd_ACT_GEN_ON);
1810 retval = mwlExecuteCmd(mh, HostCmd_CMD_BSS_START);
1812 vap->flags |= MVF_RUNNING;
1818 mwl_hal_setgprot(struct mwl_hal *mh0, int prot)
1820 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1821 HostCmd_FW_SET_G_PROTECT_FLAG *pCmd;
1825 _CMD_SETUP(pCmd, HostCmd_FW_SET_G_PROTECT_FLAG,
1826 HostCmd_CMD_SET_G_PROTECT_FLAG);
1827 pCmd->GProtectFlag = htole32(prot);
1829 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_G_PROTECT_FLAG);
1835 mwl_hal_setwmm(struct mwl_hal *mh0, int onoff)
1837 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1838 HostCmd_FW_SetWMMMode *pCmd;
1842 _CMD_SETUP(pCmd, HostCmd_FW_SetWMMMode,
1843 HostCmd_CMD_SET_WMM_MODE);
1844 pCmd->Action = htole16(onoff);
1846 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_WMM_MODE);
1852 mwl_hal_setedcaparams(struct mwl_hal *mh0, uint8_t qnum,
1853 uint32_t CWmin, uint32_t CWmax, uint8_t AIFSN, uint16_t TXOPLimit)
1855 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1856 HostCmd_FW_SET_EDCA_PARAMS *pCmd;
1860 _CMD_SETUP(pCmd, HostCmd_FW_SET_EDCA_PARAMS,
1861 HostCmd_CMD_SET_EDCA_PARAMS);
1863 * NB: CWmin and CWmax are always set.
1864 * TxOpLimit is set if bit 0x2 is marked in Action
1865 * AIFSN is set if bit 0x4 is marked in Action
1867 pCmd->Action = htole16(0xffff); /* NB: set everything */
1868 pCmd->TxOP = htole16(TXOPLimit);
1869 pCmd->CWMax = htole32(CWmax);
1870 pCmd->CWMin = htole32(CWmin);
1871 pCmd->AIFSN = AIFSN;
1872 pCmd->TxQNum = qnum; /* XXX check */
1874 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_EDCA_PARAMS);
1879 /* XXX 0 = indoor, 1 = outdoor */
1881 mwl_hal_setrateadaptmode(struct mwl_hal *mh0, uint16_t mode)
1883 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1884 HostCmd_DS_SET_RATE_ADAPT_MODE *pCmd;
1888 _CMD_SETUP(pCmd, HostCmd_DS_SET_RATE_ADAPT_MODE,
1889 HostCmd_CMD_SET_RATE_ADAPT_MODE);
1890 pCmd->Action = htole16(HostCmd_ACT_GEN_SET);
1891 pCmd->RateAdaptMode = htole16(mode);
1893 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_RATE_ADAPT_MODE);
1899 mwl_hal_setcsmode(struct mwl_hal *mh0, MWL_HAL_CSMODE csmode)
1901 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1902 HostCmd_DS_SET_LINKADAPT_CS_MODE *pCmd;
1906 _CMD_SETUP(pCmd, HostCmd_DS_SET_LINKADAPT_CS_MODE,
1907 HostCmd_CMD_SET_LINKADAPT_CS_MODE);
1908 pCmd->Action = htole16(HostCmd_ACT_GEN_SET);
1909 pCmd->CSMode = htole16(csmode);
1911 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_LINKADAPT_CS_MODE);
1917 mwl_hal_setnprot(struct mwl_hal_vap *vap, MWL_HAL_HTPROTECT mode)
1919 struct mwl_hal_priv *mh = MWLVAP(vap);
1920 HostCmd_FW_SET_N_PROTECT_FLAG *pCmd;
1923 /* XXX validate mode */
1925 _VCMD_SETUP(vap, pCmd, HostCmd_FW_SET_N_PROTECT_FLAG,
1926 HostCmd_CMD_SET_N_PROTECT_FLAG);
1927 pCmd->NProtectFlag = htole32(mode);
1929 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_N_PROTECT_FLAG);
1935 mwl_hal_setnprotmode(struct mwl_hal_vap *vap, uint8_t mode)
1937 struct mwl_hal_priv *mh = MWLVAP(vap);
1938 HostCmd_FW_SET_N_PROTECT_OPMODE *pCmd;
1942 _VCMD_SETUP(vap, pCmd, HostCmd_FW_SET_N_PROTECT_OPMODE,
1943 HostCmd_CMD_SET_N_PROTECT_OPMODE);
1944 pCmd->NProtectOpMode = mode;
1946 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_N_PROTECT_OPMODE);
1952 mwl_hal_setoptimizationlevel(struct mwl_hal *mh0, int level)
1954 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1955 HostCmd_FW_SET_OPTIMIZATION_LEVEL *pCmd;
1959 _CMD_SETUP(pCmd, HostCmd_FW_SET_OPTIMIZATION_LEVEL,
1960 HostCmd_CMD_SET_OPTIMIZATION_LEVEL);
1961 pCmd->OptLevel = level;
1963 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_OPTIMIZATION_LEVEL);
1969 mwl_hal_setmimops(struct mwl_hal *mh0, const uint8_t addr[IEEE80211_ADDR_LEN],
1970 uint8_t enable, uint8_t mode)
1972 struct mwl_hal_priv *mh = MWLPRIV(mh0);
1973 HostCmd_FW_SET_MIMOPSHT *pCmd;
1977 _CMD_SETUP(pCmd, HostCmd_FW_SET_MIMOPSHT, HostCmd_CMD_SET_MIMOPSHT);
1978 IEEE80211_ADDR_COPY(pCmd->Addr, addr);
1979 pCmd->Enable = enable;
1982 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_MIMOPSHT);
1988 mwlGetCalTable(struct mwl_hal_priv *mh, uint8_t annex, uint8_t index)
1990 HostCmd_FW_GET_CALTABLE *pCmd;
1993 MWL_HAL_LOCK_ASSERT(mh);
1995 _CMD_SETUP(pCmd, HostCmd_FW_GET_CALTABLE, HostCmd_CMD_GET_CALTABLE);
1996 pCmd->annex = annex;
1997 pCmd->index = index;
1998 memset(pCmd->calTbl, 0, sizeof(pCmd->calTbl));
2000 retval = mwlExecuteCmd(mh, HostCmd_CMD_GET_CALTABLE);
2002 pCmd->calTbl[0] != annex && annex != 0 && annex != 255)
2008 * Calculate the max tx power from the channel's cal data.
2011 setmaxtxpow(struct mwl_hal_channel *hc, int i, int maxix)
2013 hc->maxTxPow = hc->targetPowers[i];
2014 for (i++; i < maxix; i++)
2015 if (hc->targetPowers[i] > hc->maxTxPow)
2016 hc->maxTxPow = hc->targetPowers[i];
2020 * Construct channel info for 5GHz channels from cal data.
2023 get5Ghz(MWL_HAL_CHANNELINFO *ci, const uint8_t table[], int len)
2030 for (i = 0; i < len; i += 4) {
2031 struct mwl_hal_channel *hc;
2035 f = 5000 + 5*table[i];
2040 hc = &ci->channels[j];
2042 hc->ieee = table[i];
2043 memcpy(hc->targetPowers, &table[i], 4);
2044 setmaxtxpow(hc, 1, 4); /* NB: col 1 is the freq, skip*/
2048 ci->freqLow = (l == 32000) ? 0 : l;
2058 return 2407 + chan*5;
2059 return 2512 + (chan-15)*20;
2063 * Construct channel info for 2.4GHz channels from cal data.
2066 get2Ghz(MWL_HAL_CHANNELINFO *ci, const uint8_t table[], int len)
2071 for (i = 0; i < len; i += 4) {
2072 struct mwl_hal_channel *hc = &ci->channels[j];
2074 hc->freq = ieee2mhz(1+j);
2075 memcpy(hc->targetPowers, &table[i], 4);
2076 setmaxtxpow(hc, 0, 4);
2080 ci->freqLow = ieee2mhz(1);
2081 ci->freqHigh = ieee2mhz(j);
2087 dumpcaldata(const char *name, const uint8_t *table, int n)
2090 printf("\n%s:\n", name);
2091 for (i = 0; i < n; i += 4)
2092 printf("[%2d] %3d %3d %3d %3d\n", i/4, table[i+0], table[i+1], table[i+2], table[i+3]);
2097 mwlGetPwrCalTable(struct mwl_hal_priv *mh)
2099 const uint8_t *data;
2100 MWL_HAL_CHANNELINFO *ci;
2104 /* NB: we hold the lock so it's ok to use cmdbuf */
2105 data = ((const HostCmd_FW_GET_CALTABLE *) mh->mh_cmdbuf)->calTbl;
2106 if (mwlGetCalTable(mh, 33, 0) == 0) {
2107 len = (data[2] | (data[3] << 8)) - 12;
2108 if (len > PWTAGETRATETABLE20M)
2109 len = PWTAGETRATETABLE20M;
2111 dumpcaldata("2.4G 20M", &data[12], len);/*XXX*/
2113 get2Ghz(&mh->mh_20M, &data[12], len);
2115 if (mwlGetCalTable(mh, 34, 0) == 0) {
2116 len = (data[2] | (data[3] << 8)) - 12;
2117 if (len > PWTAGETRATETABLE40M)
2118 len = PWTAGETRATETABLE40M;
2120 dumpcaldata("2.4G 40M", &data[12], len);/*XXX*/
2123 get2Ghz(ci, &data[12], len);
2125 if (mwlGetCalTable(mh, 35, 0) == 0) {
2126 len = (data[2] | (data[3] << 8)) - 20;
2127 if (len > PWTAGETRATETABLE20M_5G)
2128 len = PWTAGETRATETABLE20M_5G;
2130 dumpcaldata("5G 20M", &data[20], len);/*XXX*/
2132 get5Ghz(&mh->mh_20M_5G, &data[20], len);
2134 if (mwlGetCalTable(mh, 36, 0) == 0) {
2135 len = (data[2] | (data[3] << 8)) - 20;
2136 if (len > PWTAGETRATETABLE40M_5G)
2137 len = PWTAGETRATETABLE40M_5G;
2139 dumpcaldata("5G 40M", &data[20], len);/*XXX*/
2141 ci = &mh->mh_40M_5G;
2142 get5Ghz(ci, &data[20], len);
2144 mh->mh_flags |= MHF_CALDATA;
2150 mwl_hal_getregioncode(struct mwl_hal *mh0, uint8_t *countryCode)
2152 struct mwl_hal_priv *mh = MWLPRIV(mh0);
2156 retval = mwlGetCalTable(mh, 0, 0);
2158 const HostCmd_FW_GET_CALTABLE *pCmd =
2159 (const HostCmd_FW_GET_CALTABLE *) mh->mh_cmdbuf;
2160 *countryCode = pCmd->calTbl[16];
2167 mwl_hal_setpromisc(struct mwl_hal *mh0, int ena)
2169 struct mwl_hal_priv *mh = MWLPRIV(mh0);
2173 v = RD4(mh, MACREG_REG_PROMISCUOUS);
2174 WR4(mh, MACREG_REG_PROMISCUOUS, ena ? v | 1 : v &~ 1);
2180 mwl_hal_getpromisc(struct mwl_hal *mh0)
2182 struct mwl_hal_priv *mh = MWLPRIV(mh0);
2186 v = RD4(mh, MACREG_REG_PROMISCUOUS);
2188 return (v & 1) != 0;
2192 mwl_hal_GetBeacon(struct mwl_hal *mh0, uint8_t *pBcn, uint16_t *pLen)
2194 struct mwl_hal_priv *mh = MWLPRIV(mh0);
2195 HostCmd_FW_GET_BEACON *pCmd;
2199 _CMD_SETUP(pCmd, HostCmd_FW_GET_BEACON, HostCmd_CMD_GET_BEACON);
2200 pCmd->Bcnlen = htole16(0);
2202 retval = mwlExecuteCmd(mh, HostCmd_CMD_GET_BEACON);
2204 /* XXX bounds check */
2205 memcpy(pBcn, &pCmd->Bcn, pCmd->Bcnlen);
2206 *pLen = pCmd->Bcnlen;
2213 mwl_hal_SetRifs(struct mwl_hal *mh0, uint8_t QNum)
2215 struct mwl_hal_priv *mh = MWLPRIV(mh0);
2216 HostCmd_FW_SET_RIFS *pCmd;
2220 _CMD_SETUP(pCmd, HostCmd_FW_SET_RIFS, HostCmd_CMD_SET_RIFS);
2223 retval = mwlExecuteCmd(mh, HostCmd_CMD_SET_RIFS);
2229 * Diagnostic api's for set/get registers.
2233 getRFReg(struct mwl_hal_priv *mh, int flag, uint32_t reg, uint32_t *val)
2235 HostCmd_DS_RF_REG_ACCESS *pCmd;
2239 _CMD_SETUP(pCmd, HostCmd_DS_RF_REG_ACCESS, HostCmd_CMD_RF_REG_ACCESS);
2240 pCmd->Offset = htole16(reg);
2241 pCmd->Action = htole16(flag);
2242 pCmd->Value = htole32(*val);
2244 retval = mwlExecuteCmd(mh, HostCmd_CMD_RF_REG_ACCESS);
2252 getBBReg(struct mwl_hal_priv *mh, int flag, uint32_t reg, uint32_t *val)
2254 HostCmd_DS_BBP_REG_ACCESS *pCmd;
2258 _CMD_SETUP(pCmd, HostCmd_DS_BBP_REG_ACCESS, HostCmd_CMD_BBP_REG_ACCESS);
2259 pCmd->Offset = htole16(reg);
2260 pCmd->Action = htole16(flag);
2261 pCmd->Value = htole32(*val);
2263 retval = mwlExecuteCmd(mh, HostCmd_CMD_BBP_REG_ACCESS);
2271 mwl_hal_getregdump(struct mwl_hal_priv *mh, const MWL_DIAG_REGRANGE *regs,
2272 void *dstbuf, int space)
2274 uint32_t *dp = dstbuf;
2277 for (i = 0; space >= 2*sizeof(uint32_t); i++) {
2278 u_int r = regs[i].start;
2279 u_int e = regs[i].end;
2280 *dp++ = (r<<16) | e;
2281 space -= sizeof(uint32_t);
2283 if (MWL_DIAG_ISMAC(r))
2285 else if (MWL_DIAG_ISBB(r))
2286 getBBReg(mh, HostCmd_ACT_GEN_READ,
2287 r - MWL_DIAG_BASE_BB, dp);
2288 else if (MWL_DIAG_ISRF(r))
2289 getRFReg(mh, HostCmd_ACT_GEN_READ,
2290 r - MWL_DIAG_BASE_RF, dp);
2291 else if (r < 0x1000 || r == MACREG_REG_FW_PRESENT)
2296 r += sizeof(uint32_t);
2297 space -= sizeof(uint32_t);
2298 } while (r <= e && space >= sizeof(uint32_t));
2300 return (char *) dp - (char *) dstbuf;
2304 mwl_hal_getdiagstate(struct mwl_hal *mh0, int request,
2305 const void *args, uint32_t argsize,
2306 void **result, uint32_t *resultsize)
2308 struct mwl_hal_priv *mh = MWLPRIV(mh0);
2311 case MWL_DIAG_CMD_REVS:
2312 *result = &mh->mh_revs;
2313 *resultsize = sizeof(mh->mh_revs);
2315 case MWL_DIAG_CMD_REGS:
2316 *resultsize = mwl_hal_getregdump(mh, args, *result, *resultsize);
2318 case MWL_DIAG_CMD_HOSTCMD: {
2319 FWCmdHdr *pCmd = (FWCmdHdr *) &mh->mh_cmdbuf[0];
2323 memcpy(pCmd, args, argsize);
2324 retval = mwlExecuteCmd(mh, le16toh(pCmd->Cmd));
2325 *result = (*resultsize != 0) ? pCmd : NULL;
2327 return (retval == 0);
2329 case MWL_DIAG_CMD_FWLOAD:
2330 if (mwl_hal_fwload(mh0, __DECONST(void *, args))) {
2331 device_printf(mh->mh_dev, "problem loading fw image\n");
2340 * Low level firmware cmd block handshake support.
2344 mwlSendCmd(struct mwl_hal_priv *mh)
2348 bus_dmamap_sync(mh->mh_dmat, mh->mh_dmamap,
2349 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2351 WR4(mh, MACREG_REG_GEN_PTR, mh->mh_cmdaddr);
2352 dummy = RD4(mh, MACREG_REG_INT_CODE);
2354 WR4(mh, MACREG_REG_H2A_INTERRUPT_EVENTS, MACREG_H2ARIC_BIT_DOOR_BELL);
2358 mwlWaitForCmdComplete(struct mwl_hal_priv *mh, uint16_t cmdCode)
2360 #define MAX_WAIT_FW_COMPLETE_ITERATIONS 10000
2363 for (i = 0; i < MAX_WAIT_FW_COMPLETE_ITERATIONS; i++) {
2364 if (mh->mh_cmdbuf[0] == le16toh(cmdCode))
2369 #undef MAX_WAIT_FW_COMPLETE_ITERATIONS
2373 mwlExecuteCmd(struct mwl_hal_priv *mh, unsigned short cmd)
2376 MWL_HAL_LOCK_ASSERT(mh);
2378 if ((mh->mh_flags & MHF_FWHANG) &&
2379 (mh->mh_debug & MWL_HAL_DEBUG_IGNHANG) == 0) {
2381 device_printf(mh->mh_dev, "firmware hung, skipping cmd %s\n",
2384 device_printf(mh->mh_dev, "firmware hung, skipping cmd 0x%x\n",
2389 if (RD4(mh, MACREG_REG_INT_CODE) == 0xffffffff) {
2390 device_printf(mh->mh_dev, "%s: device not present!\n",
2395 if (mh->mh_debug & MWL_HAL_DEBUG_SENDCMD)
2399 if (!mwlWaitForCmdComplete(mh, 0x8000 | cmd)) {
2401 device_printf(mh->mh_dev,
2402 "timeout waiting for f/w cmd %s\n", mwlcmdname(cmd));
2404 device_printf(mh->mh_dev,
2405 "timeout waiting for f/w cmd 0x%x\n", cmd);
2407 mh->mh_flags |= MHF_FWHANG;
2410 bus_dmamap_sync(mh->mh_dmat, mh->mh_dmamap,
2411 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2413 if (mh->mh_debug & MWL_HAL_DEBUG_CMDDONE)
2420 * Firmware download support.
2422 #define FW_DOWNLOAD_BLOCK_SIZE 256
2423 #define FW_CHECK_USECS (5*1000) /* 5ms */
2424 #define FW_MAX_NUM_CHECKS 200
2427 /* XXX read f/w from file */
2428 #include <dev/mwl/mwlbootfw.h>
2429 #include <dev/mwl/mwl88W8363fw.h>
2433 mwlFwReset(struct mwl_hal_priv *mh)
2435 if (RD4(mh, MACREG_REG_INT_CODE) == 0xffffffff) {
2436 device_printf(mh->mh_dev, "%s: device not present!\n",
2440 WR4(mh, MACREG_REG_H2A_INTERRUPT_EVENTS, ISR_RESET);
2441 mh->mh_flags &= ~MHF_FWHANG;
2445 mwlTriggerPciCmd(struct mwl_hal_priv *mh)
2449 bus_dmamap_sync(mh->mh_dmat, mh->mh_dmamap, BUS_DMASYNC_PREWRITE);
2451 WR4(mh, MACREG_REG_GEN_PTR, mh->mh_cmdaddr);
2452 dummy = RD4(mh, MACREG_REG_INT_CODE);
2454 WR4(mh, MACREG_REG_INT_CODE, 0x00);
2455 dummy = RD4(mh, MACREG_REG_INT_CODE);
2457 WR4(mh, MACREG_REG_H2A_INTERRUPT_EVENTS, MACREG_H2ARIC_BIT_DOOR_BELL);
2458 dummy = RD4(mh, MACREG_REG_INT_CODE);
2462 mwlWaitFor(struct mwl_hal_priv *mh, uint32_t val)
2466 for (i = 0; i < FW_MAX_NUM_CHECKS; i++) {
2467 DELAY(FW_CHECK_USECS);
2468 if (RD4(mh, MACREG_REG_INT_CODE) == val)
2475 * Firmware block xmit when talking to the boot-rom.
2478 mwlSendBlock(struct mwl_hal_priv *mh, int bsize, const void *data, size_t dsize)
2480 mh->mh_cmdbuf[0] = htole16(HostCmd_CMD_CODE_DNLD);
2481 mh->mh_cmdbuf[1] = htole16(bsize);
2482 memcpy(&mh->mh_cmdbuf[4], data , dsize);
2483 mwlTriggerPciCmd(mh);
2484 /* XXX 2000 vs 200 */
2485 if (mwlWaitFor(mh, MACREG_INT_CODE_CMD_FINISHED)) {
2486 WR4(mh, MACREG_REG_INT_CODE, 0);
2489 device_printf(mh->mh_dev,
2490 "%s: timeout waiting for CMD_FINISHED, INT_CODE 0x%x\n",
2491 __func__, RD4(mh, MACREG_REG_INT_CODE));
2496 * Firmware block xmit when talking to the 1st-stage loader.
2499 mwlSendBlock2(struct mwl_hal_priv *mh, const void *data, size_t dsize)
2501 memcpy(&mh->mh_cmdbuf[0], data, dsize);
2502 mwlTriggerPciCmd(mh);
2503 if (mwlWaitFor(mh, MACREG_INT_CODE_CMD_FINISHED)) {
2504 WR4(mh, MACREG_REG_INT_CODE, 0);
2507 device_printf(mh->mh_dev,
2508 "%s: timeout waiting for CMD_FINISHED, INT_CODE 0x%x\n",
2509 __func__, RD4(mh, MACREG_REG_INT_CODE));
2514 mwlPokeSdramController(struct mwl_hal_priv *mh, int SDRAMSIZE_Addr)
2516 /** Set up sdram controller for superflyv2 **/
2517 WR4(mh, 0x00006014, 0x33);
2518 WR4(mh, 0x00006018, 0xa3a2632);
2519 WR4(mh, 0x00006010, SDRAMSIZE_Addr);
2523 mwl_hal_fwload(struct mwl_hal *mh0, void *fwargs)
2525 struct mwl_hal_priv *mh = MWLPRIV(mh0);
2526 const char *fwname = "mw88W8363fw";
2527 const char *fwbootname = "mwlboot";
2528 const struct firmware *fwboot = NULL;
2529 const struct firmware *fw;
2530 /* XXX get from firmware header */
2531 uint32_t FwReadySignature = HostCmd_SOFTAP_FWRDY_SIGNATURE;
2532 uint32_t OpMode = HostCmd_SOFTAP_MODE;
2533 const uint8_t *fp, *ep;
2534 const uint8_t *fmdata;
2535 uint32_t blocksize, nbytes, fmsize;
2536 int i, error, ntries;
2538 fw = firmware_get(fwname);
2540 device_printf(mh->mh_dev,
2541 "could not load firmware image %s\n", fwname);
2545 fmsize = fw->datasize;
2547 device_printf(mh->mh_dev, "firmware image %s too small\n",
2552 if (fmdata[0] == 0x01 && fmdata[1] == 0x00 &&
2553 fmdata[2] == 0x00 && fmdata[3] == 0x00) {
2555 * 2-stage load, get the boot firmware.
2557 fwboot = firmware_get(fwbootname);
2558 if (fwboot == NULL) {
2559 device_printf(mh->mh_dev,
2560 "could not load firmware image %s\n", fwbootname);
2569 WR4(mh, MACREG_REG_A2H_INTERRUPT_CLEAR_SEL, MACREG_A2HRIC_BIT_MASK);
2570 WR4(mh, MACREG_REG_A2H_INTERRUPT_CAUSE, 0x00);
2571 WR4(mh, MACREG_REG_A2H_INTERRUPT_MASK, 0x00);
2572 WR4(mh, MACREG_REG_A2H_INTERRUPT_STATUS_MASK, MACREG_A2HRIC_BIT_MASK);
2573 if (mh->mh_SDRAMSIZE_Addr != 0) {
2574 /** Set up sdram controller for superflyv2 **/
2575 mwlPokeSdramController(mh, mh->mh_SDRAMSIZE_Addr);
2577 device_printf(mh->mh_dev, "load %s firmware image (%u bytes)\n",
2579 if (fwboot != NULL) {
2581 * Do 2-stage load. The 1st stage loader is setup
2582 * with the bootrom loader then we load the real
2583 * image using a different handshake. With this
2584 * mechanism the firmware is segmented into chunks
2585 * that have a CRC. If a chunk is incorrect we'll
2586 * be told to retransmit.
2588 /* XXX assumes hlpimage fits in a block */
2589 /* NB: zero size block indicates download is finished */
2590 if (!mwlSendBlock(mh, fwboot->datasize, fwboot->data, fwboot->datasize) ||
2591 !mwlSendBlock(mh, 0, NULL, 0)) {
2595 DELAY(200*FW_CHECK_USECS);
2596 if (mh->mh_SDRAMSIZE_Addr != 0) {
2597 /** Set up sdram controller for superflyv2 **/
2598 mwlPokeSdramController(mh, mh->mh_SDRAMSIZE_Addr);
2600 nbytes = ntries = 0; /* NB: silence compiler */
2601 for (fp = fmdata, ep = fp + fmsize; fp < ep; ) {
2602 WR4(mh, MACREG_REG_INT_CODE, 0);
2603 blocksize = RD4(mh, MACREG_REG_SCRATCH);
2604 if (blocksize == 0) /* download complete */
2606 if (blocksize > 0x00000c00) {
2610 if ((blocksize & 0x1) == 0) {
2611 /* block successfully downloaded, advance */
2617 * Guard against f/w telling us to
2623 /* clear NAK bit/flag */
2626 if (blocksize > ep - fp) {
2627 /* XXX this should not happen, what to do? */
2628 blocksize = ep - fp;
2631 if (!mwlSendBlock2(mh, fp, nbytes)) {
2637 for (fp = fmdata, ep = fp + fmsize; fp < ep;) {
2639 if (nbytes > FW_DOWNLOAD_BLOCK_SIZE)
2640 nbytes = FW_DOWNLOAD_BLOCK_SIZE;
2641 if (!mwlSendBlock(mh, FW_DOWNLOAD_BLOCK_SIZE, fp, nbytes)) {
2648 /* done with firmware... */
2650 firmware_put(fwboot, FIRMWARE_UNLOAD);
2651 firmware_put(fw, FIRMWARE_UNLOAD);
2653 * Wait for firmware to startup; we monitor the
2654 * INT_CODE register waiting for a signature to
2655 * written back indicating it's ready to go.
2657 mh->mh_cmdbuf[1] = 0;
2659 * XXX WAR for mfg fw download
2661 if (OpMode != HostCmd_STA_MODE)
2662 mwlTriggerPciCmd(mh);
2663 for (i = 0; i < FW_MAX_NUM_CHECKS; i++) {
2664 WR4(mh, MACREG_REG_GEN_PTR, OpMode);
2665 DELAY(FW_CHECK_USECS);
2666 if (RD4(mh, MACREG_REG_INT_CODE) == FwReadySignature) {
2667 WR4(mh, MACREG_REG_INT_CODE, 0x00);
2668 return mwlResetHalState(mh);
2675 /* done with firmware... */
2677 firmware_put(fwboot, FIRMWARE_UNLOAD);
2678 firmware_put(fw, FIRMWARE_UNLOAD);
2686 static char buf[12];
2687 #define CMD(x) case HostCmd_CMD_##x: return #x
2692 CMD(MAC_MULTICAST_ADR);
2693 CMD(802_11_GET_STAT);
2694 CMD(MAC_REG_ACCESS);
2695 CMD(BBP_REG_ACCESS);
2697 CMD(802_11_RADIO_CONTROL);
2698 CMD(802_11_RF_TX_POWER);
2699 CMD(802_11_RF_ANTENNA);
2701 CMD(SET_RF_CHANNEL);
2703 CMD(SET_INFRA_MODE);
2704 CMD(SET_G_PROTECT_FLAG);
2705 CMD(802_11_RTS_THSD);
2706 CMD(802_11_SET_SLOT);
2707 CMD(SET_EDCA_PARAMS);
2708 CMD(802_11H_DETECT_RADAR);
2710 CMD(HT_GUARD_INTERVAL);
2711 CMD(SET_FIXED_RATE);
2712 CMD(SET_LINKADAPT_CS_MODE);
2714 CMD(SET_RATE_ADAPT_MODE);
2717 CMD(SET_KEEP_ALIVE);
2719 CMD(SET_SWITCH_CHANNEL);
2720 CMD(UPDATE_ENCRYPTION);
2723 CMD(SET_N_PROTECT_FLAG);
2724 CMD(SET_N_PROTECT_OPMODE);
2725 CMD(SET_OPTIMIZATION_LEVEL);
2729 CMD(SET_REGION_CODE);
2730 CMD(SET_POWERSAVESTATION);
2735 CMD(AMPDU_RETRY_RATEDROP_MODE);
2738 snprintf(buf, sizeof(buf), "0x%x", cmd);
2744 dumpresult(struct mwl_hal_priv *mh, int showresult)
2746 const FWCmdHdr *h = (const FWCmdHdr *)mh->mh_cmdbuf;
2750 len = le16toh(h->Length);
2751 #ifdef MWL_MBSS_SUPPORT
2752 device_printf(mh->mh_dev, "Cmd %s Length %d SeqNum %d MacId %d",
2753 mwlcmdname(le16toh(h->Cmd) &~ 0x8000), len, h->SeqNum, h->MacId);
2755 device_printf(mh->mh_dev, "Cmd %s Length %d SeqNum %d",
2756 mwlcmdname(le16toh(h->Cmd) &~ 0x8000), len, le16toh(h->SeqNum));
2759 const char *results[] =
2760 { "OK", "ERROR", "NOT_SUPPORT", "PENDING", "BUSY",
2762 int result = le16toh(h->Result);
2764 if (result <= HostCmd_RESULT_PARTIAL_DATA)
2765 printf(" Result %s", results[result]);
2767 printf(" Result %d", result);
2769 cp = (const uint8_t *)h;
2770 for (i = 0; i < len; i++) {
2772 printf("\n%02x", cp[i]);
2774 printf(" %02x", cp[i]);
2778 #endif /* MWLHAL_DEBUG */