2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2007-2009 Sam Leffler, Errno Consulting
5 * Copyright (c) 2007-2009 Marvell Semiconductor, Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer,
13 * without modification.
14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
15 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
16 * redistribution must be conditioned upon including a substantially
17 * similar Disclaimer requirement for further binary redistribution.
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
23 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
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28 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGES.
36 * Definitions for the Marvell Wireless LAN controller Hardware Access Layer.
38 #ifndef _MWL_HALREG_H_
39 #define _MWL_HALREG_H_
41 #define MWL_ANT_INFO_SUPPORT /* per-antenna data in rx descriptor */
43 #define MACREG_REG_TSF_LOW 0xa600 /* TSF lo */
44 #define MACREG_REG_TSF_HIGH 0xa604 /* TSF hi */
45 #define MACREG_REG_CHIP_REV 0xa814 /* chip rev */
47 // Map to 0x80000000 (Bus control) on BAR0
48 #define MACREG_REG_H2A_INTERRUPT_EVENTS 0x00000C18 // (From host to ARM)
49 #define MACREG_REG_H2A_INTERRUPT_CAUSE 0x00000C1C // (From host to ARM)
50 #define MACREG_REG_H2A_INTERRUPT_MASK 0x00000C20 // (From host to ARM)
51 #define MACREG_REG_H2A_INTERRUPT_CLEAR_SEL 0x00000C24 // (From host to ARM)
52 #define MACREG_REG_H2A_INTERRUPT_STATUS_MASK 0x00000C28 // (From host to ARM)
54 #define MACREG_REG_A2H_INTERRUPT_EVENTS 0x00000C2C // (From ARM to host)
55 #define MACREG_REG_A2H_INTERRUPT_CAUSE 0x00000C30 // (From ARM to host)
56 #define MACREG_REG_A2H_INTERRUPT_MASK 0x00000C34 // (From ARM to host)
57 #define MACREG_REG_A2H_INTERRUPT_CLEAR_SEL 0x00000C38 // (From ARM to host)
58 #define MACREG_REG_A2H_INTERRUPT_STATUS_MASK 0x00000C3C // (From ARM to host)
61 // Map to 0x80000000 on BAR1
62 #define MACREG_REG_GEN_PTR 0x00000C10
63 #define MACREG_REG_INT_CODE 0x00000C14
64 #define MACREG_REG_SCRATCH 0x00000C40
65 #define MACREG_REG_FW_PRESENT 0x0000BFFC
67 #define MACREG_REG_PROMISCUOUS 0xA300
69 // Bit definitio for MACREG_REG_A2H_INTERRUPT_CAUSE (A2HRIC)
70 #define MACREG_A2HRIC_BIT_TX_DONE 0x00000001 // bit 0
71 #define MACREG_A2HRIC_BIT_RX_RDY 0x00000002 // bit 1
72 #define MACREG_A2HRIC_BIT_OPC_DONE 0x00000004 // bit 2
73 #define MACREG_A2HRIC_BIT_MAC_EVENT 0x00000008 // bit 3
74 #define MACREG_A2HRIC_BIT_RX_PROBLEM 0x00000010 // bit 4
76 #define MACREG_A2HRIC_BIT_RADIO_OFF 0x00000020 // bit 5
77 #define MACREG_A2HRIC_BIT_RADIO_ON 0x00000040 // bit 6
79 #define MACREG_A2HRIC_BIT_RADAR_DETECT 0x00000080 // bit 7
81 #define MACREG_A2HRIC_BIT_ICV_ERROR 0x00000100 // bit 8
82 #define MACREG_A2HRIC_BIT_MIC_ERROR 0x00000200 // bit 9
83 #define MACREG_A2HRIC_BIT_QUEUE_EMPTY 0x00004000
84 #define MACREG_A2HRIC_BIT_QUEUE_FULL 0x00000800
85 #define MACREG_A2HRIC_BIT_CHAN_SWITCH 0x00001000
86 #define MACREG_A2HRIC_BIT_TX_WATCHDOG 0x00002000
87 #define MACREG_A2HRIC_BIT_BA_WATCHDOG 0x00000400
88 #define MACREQ_A2HRIC_BIT_TX_ACK 0x00008000
89 #define ISR_SRC_BITS ((MACREG_A2HRIC_BIT_RX_RDY) | \
90 (MACREG_A2HRIC_BIT_TX_DONE) | \
91 (MACREG_A2HRIC_BIT_OPC_DONE) | \
92 (MACREG_A2HRIC_BIT_MAC_EVENT)| \
93 (MACREG_A2HRIC_BIT_MIC_ERROR)| \
94 (MACREG_A2HRIC_BIT_ICV_ERROR)| \
95 (MACREG_A2HRIC_BIT_RADAR_DETECT)| \
96 (MACREG_A2HRIC_BIT_CHAN_SWITCH)| \
97 (MACREG_A2HRIC_BIT_TX_WATCHDOG)| \
98 (MACREG_A2HRIC_BIT_QUEUE_EMPTY)| \
99 (MACREG_A2HRIC_BIT_BA_WATCHDOG)| \
100 (MACREQ_A2HRIC_BIT_TX_ACK))
102 #define MACREG_A2HRIC_BIT_MASK ISR_SRC_BITS
105 // Bit definitio for MACREG_REG_H2A_INTERRUPT_CAUSE (H2ARIC)
106 #define MACREG_H2ARIC_BIT_PPA_READY 0x00000001 // bit 0
107 #define MACREG_H2ARIC_BIT_DOOR_BELL 0x00000002 // bit 1
108 #define ISR_RESET (1<<15)
110 // INT code register event definition
111 #define MACREG_INT_CODE_CMD_FINISHED 0x00000005
114 * Host/Firmware Interface definitions.
118 * Define total number of TX queues in the shared memory.
119 * This count includes the EDCA queues, Block Ack queues, and HCCA queues
120 * In addition to this, there could be a management packet queue some
123 #define NUM_EDCA_QUEUES 4
124 #define NUM_HCCA_QUEUES 0
125 #define NUM_BA_QUEUES 0
126 #define NUM_MGMT_QUEUES 0
127 #define NUM_ACK_EVENT_QUEUE 1
128 #define TOTAL_TX_QUEUES \
129 (NUM_EDCA_QUEUES + NUM_HCCA_QUEUES + NUM_BA_QUEUES + NUM_MGMT_QUEUES + NUM_ACK_EVENT_QUEUE)
130 #define MAX_TXWCB_QUEUES TOTAL_TX_QUEUES - NUM_ACK_EVENT_QUEUE
131 #define MAX_RXWCB_QUEUES 1
133 //=============================================================================
134 // PUBLIC DEFINITIONS
135 //=============================================================================
137 #define RATE_INDEX_MAX_ARRAY 14
138 #define WOW_MAX_STATION 32
141 * Hardware tx/rx descriptors.
143 * NB: tx descriptor size must match f/w expected size
144 * because f/w prefetch's the next descriptor linearly
145 * and doesn't chase the next pointer.
149 #define EAGLE_TXD_STATUS_IDLE 0x00000000
150 #define EAGLE_TXD_STATUS_USED 0x00000001
151 #define EAGLE_TXD_STATUS_OK 0x00000001
152 #define EAGLE_TXD_STATUS_OK_RETRY 0x00000002
153 #define EAGLE_TXD_STATUS_OK_MORE_RETRY 0x00000004
154 #define EAGLE_TXD_STATUS_MULTICAST_TX 0x00000008
155 #define EAGLE_TXD_STATUS_BROADCAST_TX 0x00000010
156 #define EAGLE_TXD_STATUS_FAILED_LINK_ERROR 0x00000020
157 #define EAGLE_TXD_STATUS_FAILED_EXCEED_LIMIT 0x00000040
158 #define EAGLE_TXD_STATUS_FAILED_XRETRY EAGLE_TXD_STATUS_FAILED_EXCEED_LIMIT
159 #define EAGLE_TXD_STATUS_FAILED_AGING 0x00000080
160 #define EAGLE_TXD_STATUS_FW_OWNED 0x80000000
169 #define EAGLE_TXD_MODE_BONLY 1
170 #define EAGLE_TXD_MODE_GONLY 2
171 #define EAGLE_TXD_MODE_BG 3
172 #define EAGLE_TXD_MODE_NONLY 4
173 #define EAGLE_TXD_MODE_BN 5
174 #define EAGLE_TXD_MODE_GN 6
175 #define EAGLE_TXD_MODE_BGN 7
176 #define EAGLE_TXD_MODE_AONLY 8
177 #define EAGLE_TXD_MODE_AG 10
178 #define EAGLE_TXD_MODE_AN 12
180 #define EAGLE_TXD_FORMAT 0x0001 /* frame format/rate */
181 #define EAGLE_TXD_FORMAT_LEGACY 0x0000 /* legacy rate frame */
182 #define EAGLE_TXD_FORMAT_HT 0x0001 /* HT rate frame */
183 #define EAGLE_TXD_GI 0x0002 /* guard interval */
184 #define EAGLE_TXD_GI_SHORT 0x0002 /* short guard interval */
185 #define EAGLE_TXD_GI_LONG 0x0000 /* long guard interval */
186 #define EAGLE_TXD_CHW 0x0004 /* channel width */
187 #define EAGLE_TXD_CHW_20 0x0000 /* 20MHz channel width */
188 #define EAGLE_TXD_CHW_40 0x0004 /* 40MHz channel width */
189 #define EAGLE_TXD_RATE 0x01f8 /* tx rate (legacy)/ MCS */
190 #define EAGLE_TXD_RATE_S 3
191 #define EAGLE_TXD_ADV 0x0600 /* advanced coding */
192 #define EAGLE_TXD_ADV_S 9
193 #define EAGLE_TXD_ADV_NONE 0x0000
194 #define EAGLE_TXD_ADV_LDPC 0x0200
195 #define EAGLE_TXD_ADV_RS 0x0400
196 /* NB: 3 is reserved */
197 #define EAGLE_TXD_ANTENNA 0x1800 /* antenna select */
198 #define EAGLE_TXD_ANTENNA_S 11
199 #define EAGLE_TXD_EXTCHAN 0x6000 /* extension channel */
200 #define EAGLE_TXD_EXTCHAN_S 13
201 #define EAGLE_TXD_EXTCHAN_HI 0x0000 /* above */
202 #define EAGLE_TXD_EXTCHAN_LO 0x2000 /* below */
203 #define EAGLE_TXD_PREAMBLE 0x8000
204 #define EAGLE_TXD_PREAMBLE_SHORT 0x8000 /* short preamble */
205 #define EAGLE_TXD_PREAMBLE_LONG 0x0000 /* long preamble */
206 uint16_t pad; /* align to 4-byte boundary */
207 #define EAGLE_TXD_FIXED_RATE 0x0100 /* get tx rate from Format */
208 #define EAGLE_TXD_DONT_AGGR 0x0200 /* don't aggregate frame */
209 uint32_t ack_wcb_addr;
212 struct mwl_ant_info {
213 uint8_t rssi_a; /* RSSI for antenna A */
214 uint8_t rssi_b; /* RSSI for antenna B */
215 uint8_t rssi_c; /* RSSI for antenna C */
216 uint8_t rsvd1; /* Reserved */
217 uint8_t nf_a; /* Noise floor for antenna A */
218 uint8_t nf_b; /* Noise floor for antenna B */
219 uint8_t nf_c; /* Noise floor for antenna C */
220 uint8_t rsvd2; /* Reserved */
221 uint8_t nf; /* Noise floor */
222 uint8_t rsvd3[3]; /* Reserved - To make word aligned */
226 uint8_t RxControl; /* control element */
227 #define EAGLE_RXD_CTRL_DRIVER_OWN 0x00
228 #define EAGLE_RXD_CTRL_OS_OWN 0x04
229 #define EAGLE_RXD_CTRL_DMA_OWN 0x80
230 uint8_t RSSI; /* received signal strengt indication */
231 uint8_t Status; /* status field w/ USED bit */
232 #define EAGLE_RXD_STATUS_IDLE 0x00
233 #define EAGLE_RXD_STATUS_OK 0x01
234 #define EAGLE_RXD_STATUS_MULTICAST_RX 0x02
235 #define EAGLE_RXD_STATUS_BROADCAST_RX 0x04
236 #define EAGLE_RXD_STATUS_FRAGMENT_RX 0x08
237 #define EAGLE_RXD_STATUS_GENERAL_DECRYPT_ERR 0xff
238 #define EAGLE_RXD_STATUS_DECRYPT_ERR_MASK 0x80
239 #define EAGLE_RXD_STATUS_TKIP_MIC_DECRYPT_ERR 0x02
240 #define EAGLE_RXD_STATUS_WEP_ICV_DECRYPT_ERR 0x04
241 #define EAGLE_RXD_STATUS_TKIP_ICV_DECRYPT_ERR 0x08
242 uint8_t Channel; /* channel # pkt received on */
243 uint16_t PktLen; /* total length of received data */
244 uint8_t SQ2; /* not used */
245 uint8_t Rate; /* received data rate */
246 uint32_t pPhysBuffData; /* physical address of payload data */
247 uint32_t pPhysNext; /* physical address of next RX desc */
248 uint16_t QosCtrl; /* received QosCtrl field variable */
249 uint16_t HtSig2; /* like name states */
250 #ifdef MWL_ANT_INFO_SUPPORT
251 struct mwl_ant_info ai; /* antenna info */
256 // Define OpMode for SoftAP/Station mode
258 // The following mode signature has to be written to PCI scratch register#0
259 // right after successfully downloading the last block of firmware and
260 // before waiting for firmware ready signature
262 #define HostCmd_STA_MODE 0x5A
263 #define HostCmd_SOFTAP_MODE 0xA5
265 #define HostCmd_STA_FWRDY_SIGNATURE 0xF0F1F2F4
266 #define HostCmd_SOFTAP_FWRDY_SIGNATURE 0xF1F2F4A5
268 //***************************************************************************
269 //***************************************************************************
271 //***************************************************************************
273 #define HostCmd_CMD_CODE_DNLD 0x0001
274 #define HostCmd_CMD_GET_HW_SPEC 0x0003
275 #define HostCmd_CMD_SET_HW_SPEC 0x0004
276 #define HostCmd_CMD_MAC_MULTICAST_ADR 0x0010
277 #define HostCmd_CMD_802_11_GET_STAT 0x0014
278 #define HostCmd_CMD_MAC_REG_ACCESS 0x0019
279 #define HostCmd_CMD_BBP_REG_ACCESS 0x001a
280 #define HostCmd_CMD_RF_REG_ACCESS 0x001b
281 #define HostCmd_CMD_802_11_RADIO_CONTROL 0x001c
282 #define HostCmd_CMD_802_11_RF_TX_POWER 0x001e
283 #define HostCmd_CMD_802_11_RF_ANTENNA 0x0020
284 #define HostCmd_CMD_SET_BEACON 0x0100
285 #define HostCmd_CMD_SET_AID 0x010d
286 #define HostCmd_CMD_SET_RF_CHANNEL 0x010a
287 #define HostCmd_CMD_SET_INFRA_MODE 0x010e
288 #define HostCmd_CMD_SET_G_PROTECT_FLAG 0x010f
289 #define HostCmd_CMD_802_11_RTS_THSD 0x0113
290 #define HostCmd_CMD_802_11_SET_SLOT 0x0114
292 #define HostCmd_CMD_802_11H_DETECT_RADAR 0x0120
293 #define HostCmd_CMD_SET_WMM_MODE 0x0123
294 #define HostCmd_CMD_HT_GUARD_INTERVAL 0x0124
295 #define HostCmd_CMD_SET_FIXED_RATE 0x0126
296 #define HostCmd_CMD_SET_LINKADAPT_CS_MODE 0x0129
297 #define HostCmd_CMD_SET_MAC_ADDR 0x0202
298 #define HostCmd_CMD_SET_RATE_ADAPT_MODE 0x0203
299 #define HostCmd_CMD_GET_WATCHDOG_BITMAP 0x0205
301 //SoftAP command code
302 #define HostCmd_CMD_BSS_START 0x1100
303 #define HostCmd_CMD_SET_NEW_STN 0x1111
304 #define HostCmd_CMD_SET_KEEP_ALIVE 0x1112
305 #define HostCmd_CMD_SET_APMODE 0x1114
306 #define HostCmd_CMD_SET_SWITCH_CHANNEL 0x1121
310 Command to update firmware encryption keys.
312 #define HostCmd_CMD_UPDATE_ENCRYPTION 0x1122
315 Command to create/destroy block ACK
317 #define HostCmd_CMD_BASTREAM 0x1125
318 #define HostCmd_CMD_SET_RIFS 0x1126
319 #define HostCmd_CMD_SET_N_PROTECT_FLAG 0x1131
320 #define HostCmd_CMD_SET_N_PROTECT_OPMODE 0x1132
321 #define HostCmd_CMD_SET_OPTIMIZATION_LEVEL 0x1133
322 #define HostCmd_CMD_GET_CALTABLE 0x1134
323 #define HostCmd_CMD_SET_MIMOPSHT 0x1135
324 #define HostCmd_CMD_GET_BEACON 0x1138
325 #define HostCmd_CMD_SET_REGION_CODE 0x1139
326 #define HostCmd_CMD_SET_POWERSAVESTATION 0x1140
327 #define HostCmd_CMD_SET_TIM 0x1141
328 #define HostCmd_CMD_GET_TIM 0x1142
329 #define HostCmd_CMD_GET_SEQNO 0x1143
330 #define HostCmd_CMD_DWDS_ENABLE 0x1144
331 #define HostCmd_CMD_AMPDU_RETRY_RATEDROP_MODE 0x1145
332 #define HostCmd_CMD_CFEND_ENABLE 0x1146
335 // Define general result code for each command
337 #define HostCmd_RESULT_OK 0x0000 // OK
338 #define HostCmd_RESULT_ERROR 0x0001 // Genenral error
339 #define HostCmd_RESULT_NOT_SUPPORT 0x0002 // Command is not valid
340 #define HostCmd_RESULT_PENDING 0x0003 // Command is pending (will be processed)
341 #define HostCmd_RESULT_BUSY 0x0004 // System is busy (command ignored)
342 #define HostCmd_RESULT_PARTIAL_DATA 0x0005 // Data buffer is not big enough
346 // Definition of action or option for each command
348 // Define general purpose action
350 #define HostCmd_ACT_GEN_READ 0x0000
351 #define HostCmd_ACT_GEN_WRITE 0x0001
352 #define HostCmd_ACT_GEN_GET 0x0000
353 #define HostCmd_ACT_GEN_SET 0x0001
354 #define HostCmd_ACT_GEN_OFF 0x0000
355 #define HostCmd_ACT_GEN_ON 0x0001
357 #define HostCmd_ACT_DIFF_CHANNEL 0x0002
358 #define HostCmd_ACT_GEN_SET_LIST 0x0002
360 // Define action or option for HostCmd_FW_USE_FIXED_RATE
361 #define HostCmd_ACT_USE_FIXED_RATE 0x0001
362 #define HostCmd_ACT_NOT_USE_FIXED_RATE 0x0002
364 // Define action or option for HostCmd_CMD_802_11_SET_WEP
365 //#define HostCmd_ACT_ENABLE 0x0001 // Use MAC control for WEP on/off
366 //#define HostCmd_ACT_DISABLE 0x0000
367 #define HostCmd_ACT_ADD 0x0002
368 #define HostCmd_ACT_REMOVE 0x0004
369 #define HostCmd_ACT_USE_DEFAULT 0x0008
371 #define HostCmd_TYPE_WEP_40_BIT 0x0001 // 40 bit
372 #define HostCmd_TYPE_WEP_104_BIT 0x0002 // 104 bit
373 #define HostCmd_TYPE_WEP_128_BIT 0x0003 // 128 bit
374 #define HostCmd_TYPE_WEP_TX_KEY 0x0004 // TX WEP
376 #define HostCmd_NUM_OF_WEP_KEYS 4
378 #define HostCmd_WEP_KEY_INDEX_MASK 0x3fffffff
381 // Define action or option for HostCmd_CMD_802_11_RESET
382 #define HostCmd_ACT_HALT 0x0001
383 #define HostCmd_ACT_RESTART 0x0002
385 // Define action or option for HostCmd_CMD_802_11_RADIO_CONTROL
386 #define HostCmd_TYPE_AUTO_PREAMBLE 0x0001
387 #define HostCmd_TYPE_SHORT_PREAMBLE 0x0002
388 #define HostCmd_TYPE_LONG_PREAMBLE 0x0003
390 // Define action or option for CMD_802_11_RF_CHANNEL
391 #define HostCmd_TYPE_802_11A 0x0001
392 #define HostCmd_TYPE_802_11B 0x0002
394 // Define action or option for HostCmd_CMD_802_11_RF_TX_POWER
395 #define HostCmd_ACT_TX_POWER_OPT_SET_HIGH 0x0003
396 #define HostCmd_ACT_TX_POWER_OPT_SET_MID 0x0002
397 #define HostCmd_ACT_TX_POWER_OPT_SET_LOW 0x0001
398 #define HostCmd_ACT_TX_POWER_OPT_SET_AUTO 0x0000
400 #define HostCmd_ACT_TX_POWER_LEVEL_MIN 0x000e // in dbm
401 #define HostCmd_ACT_TX_POWER_LEVEL_GAP 0x0001 // in dbm
402 // Define action or option for HostCmd_CMD_802_11_DATA_RATE
403 #define HostCmd_ACT_SET_TX_AUTO 0x0000
404 #define HostCmd_ACT_SET_TX_FIX_RATE 0x0001
405 #define HostCmd_ACT_GET_TX_RATE 0x0002
407 #define HostCmd_ACT_SET_RX 0x0001
408 #define HostCmd_ACT_SET_TX 0x0002
409 #define HostCmd_ACT_SET_BOTH 0x0003
410 #define HostCmd_ACT_GET_RX 0x0004
411 #define HostCmd_ACT_GET_TX 0x0008
412 #define HostCmd_ACT_GET_BOTH 0x000c
414 #define TYPE_ANTENNA_DIVERSITY 0xffff
416 // Define action or option for HostCmd_CMD_802_11_PS_MODE
417 #define HostCmd_TYPE_CAM 0x0000
418 #define HostCmd_TYPE_MAX_PSP 0x0001
419 #define HostCmd_TYPE_FAST_PSP 0x0002
421 #define HostCmd_CMD_SET_EDCA_PARAMS 0x0115
423 //=============================================================================
424 // HOST COMMAND DEFINITIONS
425 //=============================================================================
428 // Definition of data structure for each command
430 // Define general data structure
434 #ifdef MWL_MBSS_SUPPORT
445 uint8_t Version; // HW revision
446 uint8_t HostIf; // Host interface
447 uint16_t NumOfMCastAdr; // Max. number of Multicast address FW can handle
448 uint8_t PermanentAddr[6]; // MAC address
449 uint16_t RegionCode; // Region Code
450 uint32_t FWReleaseNumber; // 4 byte of FW release number
451 uint32_t ulFwAwakeCookie; // Firmware awake cookie
452 uint32_t DeviceCaps; // Device capabilities (see above)
453 uint32_t RxPdWrPtr; // Rx shared memory queue
454 uint32_t NumTxQueues; // # TX queues in WcbBase array
455 uint32_t WcbBase[MAX_TXWCB_QUEUES]; // TX WCB Rings
457 #define SET_HW_SPEC_DISABLEMBSS 0x08
458 #define SET_HW_SPEC_HOSTFORM_BEACON 0x10
459 #define SET_HW_SPEC_HOSTFORM_PROBERESP 0x20
460 #define SET_HW_SPEC_HOST_POWERSAVE 0x40
461 #define SET_HW_SPEC_HOSTENCRDECR_MGMT 0x80
462 uint32_t TxWcbNumPerQueue;
464 } __packed HostCmd_DS_SET_HW_SPEC;
468 u_int8_t Version; /* version of the HW */
469 u_int8_t HostIf; /* host interface */
470 u_int16_t NumOfWCB; /* Max. number of WCB FW can handle */
471 u_int16_t NumOfMCastAddr; /* MaxNbr of MC addresses FW can handle */
472 u_int8_t PermanentAddr[6]; /* MAC address programmed in HW */
473 u_int16_t RegionCode;
474 u_int16_t NumberOfAntenna; /* Number of antenna used */
475 u_int32_t FWReleaseNumber; /* 4 byte of FW release number */
479 u_int32_t ulFwAwakeCookie;
480 u_int32_t WcbBase1[TOTAL_TX_QUEUES-1];
481 } __packed HostCmd_DS_GET_HW_SPEC;
485 u_int32_t Enable; /* FALSE: Disable or TRUE: Enable */
486 } __packed HostCmd_DS_BSS_START;
492 u_int8_t OuiType[4]; /* 00:50:f2:01 */
494 u_int8_t GrpKeyCipher[4];
495 u_int8_t PwsKeyCnt[2];
496 u_int8_t PwsKeyCipherList[4];
497 u_int8_t AuthKeyCnt[2];
498 u_int8_t AuthKeyList[4];
505 u_int8_t GrpKeyCipher[4];
506 u_int8_t PwsKeyCnt[2];
507 u_int8_t PwsKeyCipherList[4];
508 u_int8_t AuthKeyCnt[2];
509 u_int8_t AuthKeyList[4];
511 } __packed Rsn48IE_t;
518 u_int16_t CfpMaxDuration;
519 u_int16_t CfpDurationRemaining;
520 } __packed CfParams_t;
525 u_int16_t AtimWindow;
526 } __packed IbssParams_t;
529 CfParams_t CfParamSet;
530 IbssParams_t IbssParamSet;
531 } __packed SsParams_t;
540 } __packed FhParams_t;
545 u_int8_t CurrentChan;
546 } __packed DsParams_t;
549 FhParams_t FhParamSet;
550 DsParams_t DsParamSet;
551 } __packed PhyParams_t;
554 u_int8_t FirstChannelNum;
555 u_int8_t NumOfChannels;
556 u_int8_t MaxTxPwrLevel;
557 } __packed ChannelInfo_t;
562 u_int8_t CountryStr[3];
563 ChannelInfo_t ChannelInfo[40];
564 } __packed Country_t;
572 }__packed ACIAIFSN_field_t;
575 u_int8_t ECW_min : 4;
576 u_int8_t ECW_max : 4;
577 }__packed ECWmin_max_field_t;
580 ACIAIFSN_field_t ACI_AIFSN;
581 ECWmin_max_field_t ECW_min_max;
583 }__packed ACparam_rcd_t;
597 } __packed WMM_param_elem_t ;
600 #ifdef MWL_MBSS_SUPPORT
601 u_int8_t StaMacAddr[6];
607 SsParams_t SsParamSet;
608 PhyParams_t PhyParamSet;
609 u_int16_t ProbeDelay;
610 u_int16_t CapInfo; /* see below */
611 u_int8_t BssBasicRateSet[14];
612 u_int8_t OpRateSet[14];
615 WMM_param_elem_t WMMParam;
617 u_int32_t ApRFType; /* 0->B, 1->G, 2->Mixed, 3->A, 4->11J */
618 } __packed StartCmd_t;
620 #define HostCmd_CAPINFO_DEFAULT 0x0000
621 #define HostCmd_CAPINFO_ESS 0x0001
622 #define HostCmd_CAPINFO_IBSS 0x0002
623 #define HostCmd_CAPINFO_CF_POLLABLE 0x0004
624 #define HostCmd_CAPINFO_CF_REQUEST 0x0008
625 #define HostCmd_CAPINFO_PRIVACY 0x0010
626 #define HostCmd_CAPINFO_SHORT_PREAMBLE 0x0020
627 #define HostCmd_CAPINFO_PBCC 0x0040
628 #define HostCmd_CAPINFO_CHANNEL_AGILITY 0x0080
629 #define HostCmd_CAPINFO_SHORT_SLOT 0x0400
630 #define HostCmd_CAPINFO_DSSS_OFDM 0x2000
635 } __packed HostCmd_DS_AP_BEACON;
640 uint8_t FrmBody[1]; /* NB: variable length */
641 } __packed HostCmd_DS_SET_BEACON;
643 // Define data structure for HostCmd_CMD_MAC_MULTICAST_ADR
648 #define MWL_HAL_MCAST_MAX 32
649 uint8_t MACList[6*32];
650 } __packed HostCmd_DS_MAC_MULTICAST_ADR;
652 // Indicate to FW the current state of AP ERP info
655 uint32_t GProtectFlag;
656 } __packed HostCmd_FW_SET_G_PROTECT_FLAG;
660 } __packed HostCmd_FW_SET_INFRA_MODE;
662 // Define data structure for HostCmd_CMD_802_11_RF_CHANNEL
666 uint8_t CurrentChannel; /* channel # */
667 uint32_t ChannelFlags; /* see below */
668 } __packed HostCmd_FW_SET_RF_CHANNEL;
670 /* bits 0-5 specify frequency band */
671 #define FREQ_BAND_2DOT4GHZ 0x0001
672 #define FREQ_BAND_4DOT9GHZ 0x0002 /* XXX not implemented */
673 #define FREQ_BAND_5GHZ 0x0004
674 #define FREQ_BAND_5DOT2GHZ 0x0008 /* XXX not implemented */
675 /* bits 6-10 specify channel width */
676 #define CH_AUTO_WIDTH 0x0000 /* XXX not used? */
677 #define CH_10_MHz_WIDTH 0x0040
678 #define CH_20_MHz_WIDTH 0x0080
679 #define CH_40_MHz_WIDTH 0x0100
680 /* bits 11-12 specify extension channel */
681 #define EXT_CH_NONE 0x0000 /* no extension channel */
682 #define EXT_CH_ABOVE_CTRL_CH 0x0800 /* extension channel above */
683 #define EXT_CH_AUTO 0x1000 /* XXX not used? */
684 #define EXT_CH_BELOW_CTRL_CH 0x1800 /* extension channel below */
685 /* bits 13-31 are reserved */
687 #define FIXED_RATE_WITH_AUTO_RATE_DROP 0
688 #define FIXED_RATE_WITHOUT_AUTORATE_DROP 1
690 #define LEGACY_RATE_TYPE 0
691 #define HT_RATE_TYPE 1
693 #define RETRY_COUNT_VALID 0
694 #define RETRY_COUNT_INVALID 1
697 // lower rate after the retry count
698 uint32_t FixRateType; //0: legacy, 1: HT
699 uint32_t RetryCountValid; //0: retry count is not valid, 1: use retry count specified
700 } __packed FIX_RATE_FLAG;
703 FIX_RATE_FLAG FixRateTypeFlags;
704 uint32_t FixedRate; // legacy rate(not index) or an MCS code.
706 } __packed FIXED_RATE_ENTRY;
710 uint32_t Action; //HostCmd_ACT_GEN_GET 0x0000
711 //HostCmd_ACT_GEN_SET 0x0001
712 //HostCmd_ACT_NOT_USE_FIXED_RATE 0x0002
713 uint32_t AllowRateDrop; // use fixed rate specified but firmware can drop to
715 FIXED_RATE_ENTRY FixedRateTable[4];
716 uint8_t MulticastRate;
717 uint8_t MultiRateTxType;
718 uint8_t ManagementRate;
719 } __packed HostCmd_FW_USE_FIXED_RATE;
722 uint32_t AllowRateDrop;
724 FIXED_RATE_ENTRY FixedRateTable[4];
725 } __packed USE_FIXED_RATE_INFO;
731 #define GI_TYPE_LONG 0x0001
732 #define GI_TYPE_SHORT 0x0002
733 } __packed HostCmd_FW_HT_GUARD_INTERVAL;
738 uint8_t RxAntennaMap;
739 uint8_t TxAntennaMap;
740 } __packed HostCmd_FW_HT_MIMO_CONFIG;
745 uint8_t Slot; // Slot=0 if regular, Slot=1 if short.
746 } __packed HostCmd_FW_SET_SLOT;
749 // Define data structure for HostCmd_CMD_802_11_GET_STAT
752 uint32_t TxRetrySuccesses;
753 uint32_t TxMultipleRetrySuccesses;
755 uint32_t RTSSuccesses;
756 uint32_t RTSFailures;
757 uint32_t AckFailures;
758 uint32_t RxDuplicateFrames;
759 uint32_t FCSErrorCount;
760 uint32_t TxWatchDogTimeouts;
761 uint32_t RxOverflows; //used
762 uint32_t RxFragErrors; //used
763 uint32_t RxMemErrors; //used
764 uint32_t PointerErrors; //used
765 uint32_t TxUnderflows; //used
767 uint32_t TxDoneBufTryPut;
768 uint32_t TxDoneBufPut;
769 uint32_t Wait4TxBuf; // Put size of requested buffer in here
771 uint32_t TxSuccesses;
772 uint32_t TxFragments;
773 uint32_t TxMulticasts;
774 uint32_t RxNonCtlPkts;
775 uint32_t RxMulticasts;
776 uint32_t RxUndecryptableFrames;
777 uint32_t RxICVErrors;
778 uint32_t RxExcludedFrames;
779 } __packed HostCmd_DS_802_11_GET_STAT;
782 // Define data structure for HostCmd_CMD_MAC_REG_ACCESS
789 } __packed HostCmd_DS_MAC_REG_ACCESS;
791 // Define data structure for HostCmd_CMD_BBP_REG_ACCESS
797 uint8_t Reserverd[3];
798 } __packed HostCmd_DS_BBP_REG_ACCESS;
800 // Define data structure for HostCmd_CMD_RF_REG_ACCESS
806 uint8_t Reserverd[3];
807 } __packed HostCmd_DS_RF_REG_ACCESS;
810 // Define data structure for HostCmd_CMD_802_11_RADIO_CONTROL
814 uint16_t Control; // @bit0: 1/0,on/off, @bit1: 1/0, long/short @bit2: 1/0,auto/fix
816 } __packed HostCmd_DS_802_11_RADIO_CONTROL;
819 #define TX_POWER_LEVEL_TOTAL 8
820 // Define data structure for HostCmd_CMD_802_11_RF_TX_POWER
824 uint16_t SupportTxPowerLevel;
825 uint16_t CurrentTxPowerLevel;
827 uint16_t PowerLevelList[TX_POWER_LEVEL_TOTAL];
828 } __packed HostCmd_DS_802_11_RF_TX_POWER;
830 // Define data structure for HostCmd_CMD_802_11_RF_ANTENNA
831 typedef struct _HostCmd_DS_802_11_RF_ANTENNA {
834 uint16_t AntennaMode; // Number of antennas or 0xffff(diversity)
835 } __packed HostCmd_DS_802_11_RF_ANTENNA;
837 // Define data structure for HostCmd_CMD_802_11_PS_MODE
841 uint16_t PowerMode; // CAM, Max.PSP or Fast PSP
842 } __packed HostCmd_DS_802_11_PS_MODE;
848 } __packed HostCmd_DS_802_11_RTS_THSD;
850 // used for stand alone bssid sets/clears
853 #ifdef MWL_MBSS_SUPPORT
855 #define WL_MAC_TYPE_PRIMARY_CLIENT 0
856 #define WL_MAC_TYPE_SECONDARY_CLIENT 1
857 #define WL_MAC_TYPE_PRIMARY_AP 2
858 #define WL_MAC_TYPE_SECONDARY_AP 3
861 } __packed HostCmd_DS_SET_MAC,
862 HostCmd_FW_SET_BSSID,
865 // Indicate to FW to send out PS Poll
869 } __packed HostCmd_FW_TX_POLL;
871 // used for AID sets/clears
875 uint8_t MacAddr[6]; //AP's Mac Address(BSSID)
876 uint32_t GProtection;
877 uint8_t ApRates[ RATE_INDEX_MAX_ARRAY];
878 } __packed HostCmd_FW_SET_AID;
881 uint32_t LegacyRateBitMap;
882 uint32_t HTRateBitMap;
884 uint16_t HTCapabilitiesInfo;
885 uint8_t MacHTParamInfo;
892 } __packed AddHtInfo;
893 } __packed PeerInfo_t;
906 } __packed HostCmd_FW_SET_NEW_STN;
911 } __packed HostCmd_FW_SET_KEEP_ALIVE_TICK;
916 } __packed HostCmd_FW_SET_RIFS;
921 } __packed HostCmd_FW_SET_APMODE;
925 uint16_t Action; // see following
926 uint16_t RadarTypeCode;
927 } __packed HostCmd_802_11h_Detect_Radar;
929 #define DR_DFS_DISABLE 0
930 #define DR_CHK_CHANNEL_AVAILABLE_START 1
931 #define DR_CHK_CHANNEL_AVAILABLE_STOP 2
932 #define DR_IN_SERVICE_MONITOR_START 3
934 //New Structure for Update Tim 30/9/2003
939 } __packed HostCmd_UpdateTIM;
943 uint32_t SsidBroadcastEnable;
944 } __packed HostCmd_SSID_BROADCAST;
949 } __packed HostCmd_WDS;
953 uint32_t Next11hChannel;
955 uint32_t InitialCount;
956 uint32_t ChannelFlags ;
957 } __packed HostCmd_SET_SWITCH_CHANNEL;
961 uint32_t SpectrumMgmt;
962 } __packed HostCmd_SET_SPECTRUM_MGMT;
966 int32_t PowerConstraint;
967 } __packed HostCmd_SET_POWER_CONSTRAINT;
970 uint8_t FirstChannelNo;
972 uint8_t MaxTransmitPw;
973 } __packed DomainChannelEntry;
976 uint8_t CountryString[3];
978 DomainChannelEntry DomainEntryG[1]; /** Assume only 1 G zone **/
980 DomainChannelEntry DomainEntryA[20]; /** Assume max of 5 A zone **/
981 } __packed DomainCountryInfo;
985 uint32_t Action ; // 0 -> unset, 1 ->set
986 DomainCountryInfo DomainInfo ;
987 } __packed HostCmd_SET_COUNTRY_INFO;
991 uint16_t regionCode ;
992 } __packed HostCmd_SET_REGIONCODE_INFO;
994 // for HostCmd_CMD_SET_WMM_MODE
997 uint16_t Action; // 0->unset, 1->set
998 } __packed HostCmd_FW_SetWMMMode;
1002 uint16_t Action; // 0->unset, 1->set
1004 uint8_t IeList[200];
1005 } __packed HostCmd_FW_SetIEs;
1007 #define EDCA_PARAM_SIZE 18
1008 #define BA_PARAM_SIZE 2
1012 uint16_t Action; //0 = get all, 0x1 =set CWMin/Max, 0x2 = set TXOP , 0x4 =set AIFSN
1013 uint16_t TxOP; // in unit of 32 us
1014 uint32_t CWMax; // 0~15
1015 uint32_t CWMin; // 0~15
1017 uint8_t TxQNum; // Tx Queue number.
1018 } __packed HostCmd_FW_SET_EDCA_PARAMS;
1020 /******************************************************************************
1022 Hardware Encryption related data structures and constant definitions.
1023 Note that all related changes are marked with the @HWENCR@ tag.
1024 *******************************************************************************/
1026 #define MAX_ENCR_KEY_LENGTH 16 /* max 128 bits - depends on type */
1027 #define MIC_KEY_LENGTH 8 /* size of Tx/Rx MIC key - 8 bytes*/
1029 #define ENCR_KEY_TYPE_ID_WEP 0x00 /* Key type is WEP */
1030 #define ENCR_KEY_TYPE_ID_TKIP 0x01 /* Key type is TKIP */
1031 #define ENCR_KEY_TYPE_ID_AES 0x02 /* Key type is AES-CCMP */
1033 /* flags used in structure - same as driver EKF_XXX flags */
1034 #define ENCR_KEY_FLAG_INUSE 0x00000001 /* indicate key is in use */
1035 #define ENCR_KEY_FLAG_RXGROUPKEY 0x00000002 /* Group key for RX only */
1036 #define ENCR_KEY_FLAG_TXGROUPKEY 0x00000004 /* Group key for TX */
1037 #define ENCR_KEY_FLAG_PAIRWISE 0x00000008 /* pairwise */
1038 #define ENCR_KEY_FLAG_RXONLY 0x00000010 /* only used for RX */
1039 // These flags are new additions - for hardware encryption commands only.
1040 #define ENCR_KEY_FLAG_AUTHENTICATOR 0x00000020 /* Key is for Authenticator */
1041 #define ENCR_KEY_FLAG_TSC_VALID 0x00000040 /* Sequence counters valid */
1042 #define ENCR_KEY_FLAG_WEP_TXKEY 0x01000000 /* Tx key for WEP */
1043 #define ENCR_KEY_FLAG_MICKEY_VALID 0x02000000 /* Tx/Rx MIC keys are valid */
1046 UPDATE_ENCRYPTION command action type.
1049 // request to enable/disable HW encryption
1050 EncrActionEnableHWEncryption,
1051 // request to set encryption key
1052 EncrActionTypeSetKey,
1053 // request to remove one or more keys
1054 EncrActionTypeRemoveKey,
1055 EncrActionTypeSetGroupKey
1059 Key material definitions (for WEP, TKIP, & AES-CCMP)
1063 WEP Key material definition
1064 ----------------------------
1065 WEPKey --> An array of 'MAX_ENCR_KEY_LENGTH' bytes.
1066 Note that we do not support 152bit WEP keys
1069 // WEP key material (max 128bit)
1070 uint8_t KeyMaterial[ MAX_ENCR_KEY_LENGTH ];
1071 } __packed WEP_TYPE_KEY;
1074 TKIP Key material definition
1075 ----------------------------
1076 This structure defines TKIP key material. Note that
1077 the TxMicKey and RxMicKey may or may not be valid.
1079 /* TKIP Sequence counter - 24 bits */
1080 /* Incremented on each fragment MPDU */
1084 } __packed ENCR_TKIPSEQCNT;
1087 // TKIP Key material. Key type (group or pairwise key) is
1088 // determined by flags in KEY_PARAM_SET structure.
1089 uint8_t KeyMaterial[ MAX_ENCR_KEY_LENGTH ];
1090 uint8_t TkipTxMicKey[ MIC_KEY_LENGTH ];
1091 uint8_t TkipRxMicKey[ MIC_KEY_LENGTH ];
1092 ENCR_TKIPSEQCNT TkipRsc;
1093 ENCR_TKIPSEQCNT TkipTsc;
1094 } __packed TKIP_TYPE_KEY;
1097 AES-CCMP Key material definition
1098 --------------------------------
1099 This structure defines AES-CCMP key material.
1103 uint8_t KeyMaterial[ MAX_ENCR_KEY_LENGTH ];
1104 } __packed AES_TYPE_KEY;
1107 Encryption key definition.
1108 --------------------------
1109 This structure provides all required/essential
1110 information about the key being set/removed.
1113 uint16_t Length; // Total length of this structure
1114 uint16_t KeyTypeId; // Key type - WEP, TKIP or AES-CCMP.
1115 uint32_t KeyInfo; // key flags (ENCR_KEY_FLAG_XXX_
1116 uint32_t KeyIndex; // For WEP only - actual key index
1117 uint16_t KeyLen; // Size of the key
1118 union { // Key material (variable size array)
1119 WEP_TYPE_KEY WepKey;
1120 TKIP_TYPE_KEY TkipKey;
1121 AES_TYPE_KEY AesKey;
1123 #ifdef MWL_MBSS_SUPPORT
1126 } __packed KEY_PARAM_SET;
1129 HostCmd_FW_UPDATE_ENCRYPTION
1130 ----------------------------
1131 Define data structure for updating firmware encryption keys.
1136 uint32_t ActionType; // ENCR_ACTION_TYPE
1137 uint32_t DataLength; // size of the data buffer attached.
1138 #ifdef MWL_MBSS_SUPPORT
1141 uint8_t ActionData[1];
1142 } __packed HostCmd_FW_UPDATE_ENCRYPTION;
1147 uint32_t ActionType; // ENCR_ACTION_TYPE
1148 uint32_t DataLength; // size of the data buffer attached.
1149 KEY_PARAM_SET KeyParam;
1150 #ifndef MWL_MBSS_SUPPORT
1151 uint8_t Macaddr[8]; /* XXX? */
1153 } __packed HostCmd_FW_UPDATE_ENCRYPTION_SET_KEY;
1156 // Rate flags - see above.
1158 // Rate in 500Kbps units.
1160 // 802.11 rate to conversion table index value.
1161 // This is the value required by the firmware/hardware.
1162 uint16_t RateCodeToIndex;
1163 }__packed RATE_INFO;
1166 UPDATE_STADB command action type.
1169 // request to add entry to stainfo db
1170 StaInfoDbActionAddEntry,
1171 // request to modify peer entry
1172 StaInfoDbActionModifyEntry,
1173 // request to remove peer from stainfo db
1174 StaInfoDbActionRemoveEntry
1175 }__packed STADB_ACTION_TYPE;
1179 802.11e/WMM Related command(s)/data structures
1182 // Flag to indicate if the stream is an immediate block ack stream.
1183 // if this bit is not set, the stream is delayed block ack stream.
1184 #define BASTREAM_FLAG_DELAYED_TYPE 0x00
1185 #define BASTREAM_FLAG_IMMEDIATE_TYPE 0x01
1187 // Flag to indicate the direction of the stream (upstream/downstream).
1188 // If this bit is not set, the direction is downstream.
1189 #define BASTREAM_FLAG_DIRECTION_UPSTREAM 0x00
1190 #define BASTREAM_FLAG_DIRECTION_DOWNSTREAM 0x02
1191 #define BASTREAM_FLAG_DIRECTION_DLP 0x04
1192 #define BASTREAM_FLAG_DIRECTION_BOTH 0x06
1200 } BASTREAM_ACTION_TYPE;
1204 } __packed BASTREAM_CONTEXT;
1206 // parameters for block ack creation
1208 // BA Creation flags - see above
1212 // block ack transmit threshold (after how many pkts should we send BAR?)
1214 // receiver window size
1215 uint32_t WindowSize;
1216 // MAC Address of the BA partner
1217 uint8_t PeerMacAddr[6];
1219 uint8_t DialogToken;
1220 //TID for the traffic stream in this BA
1222 // shared memory queue ID (not sure if this is required)
1225 // returned by firmware - firmware context pointer.
1226 // this context pointer will be passed to firmware for all future commands.
1227 BASTREAM_CONTEXT FwBaContext;
1228 uint8_t ResetSeqNo; /** 0 or 1**/
1229 uint16_t StartSeqNo;
1231 // proxy sta MAC Address
1232 uint8_t StaSrcMacAddr[6];
1233 }__packed BASTREAM_CREATE_STREAM;
1235 // new transmit sequence number information
1237 // BA flags - see above
1239 // returned by firmware in the create ba stream response
1240 BASTREAM_CONTEXT FwBaContext;
1241 // new sequence number for this block ack stream
1243 }__packed BASTREAM_UPDATE_STREAM;
1248 // returned by firmware in the create ba stream response
1249 BASTREAM_CONTEXT FwBaContext;
1250 }__packed BASTREAM_STREAM_INFO;
1252 //Command to create/destroy block ACK
1255 uint32_t ActionType;
1258 // information required to create BA Stream...
1259 BASTREAM_CREATE_STREAM CreateParams;
1260 // update starting/new sequence number etc.
1261 BASTREAM_UPDATE_STREAM UpdtSeqNum;
1262 // destroy an existing stream...
1263 BASTREAM_STREAM_INFO DestroyParams;
1264 // destroy an existing stream...
1265 BASTREAM_STREAM_INFO FlushParams;
1267 }__packed HostCmd_FW_BASTREAM;
1269 // Define data structure for HostCmd_CMD_GET_WATCHDOG_BITMAP
1272 uint8_t Watchdogbitmap; // for SW/BA
1273 } __packed HostCmd_FW_GET_WATCHDOG_BITMAP;
1277 // Define data structure for HostCmd_CMD_SET_REGION_POWER
1280 uint16_t MaxPowerLevel;
1282 } __packed HostCmd_DS_SET_REGION_POWER;
1284 // Define data structure for HostCmd_CMD_SET_RATE_ADAPT_MODE
1288 uint16_t RateAdaptMode;
1289 } __packed HostCmd_DS_SET_RATE_ADAPT_MODE;
1291 // Define data structure for HostCmd_CMD_SET_LINKADAPT_CS_MODE
1296 } __packed HostCmd_DS_SET_LINKADAPT_CS_MODE;
1300 uint32_t NProtectFlag;
1301 } __packed HostCmd_FW_SET_N_PROTECT_FLAG;
1305 uint8_t NProtectOpMode;
1306 } __packed HostCmd_FW_SET_N_PROTECT_OPMODE;
1311 } __packed HostCmd_FW_SET_OPTIMIZATION_LEVEL;
1319 #define CAL_TBL_SIZE 160
1320 uint8_t calTbl[CAL_TBL_SIZE];
1321 } __packed HostCmd_FW_GET_CALTABLE;
1328 } __packed HostCmd_FW_SET_MIMOPSHT;
1330 #define MAX_BEACON_SIZE 1024
1334 uint8_t Reserverd[2];
1335 uint8_t Bcn[MAX_BEACON_SIZE];
1336 } __packed HostCmd_FW_GET_BEACON;
1340 uint8_t NumberOfPowersave;
1342 } __packed HostCmd_SET_POWERSAVESTATION;
1349 } __packed HostCmd_SET_TIM;
1353 uint8_t TrafficMap[251];
1355 } __packed HostCmd_GET_TIM;
1363 } __packed HostCmd_GET_SEQNO;
1367 uint32_t Enable; //0 -- Disbale. or 1 -- Enable.
1368 } __packed HostCmd_DWDS_ENABLE;
1372 uint16_t Action; /* 0: Get. 1:Set */
1373 uint32_t Option; /* 0: default. 1:Aggressive */
1374 uint32_t Threshold; /* Range 0-200, default 8 */
1375 }__packed HostCmd_FW_AMPDU_RETRY_RATEDROP_MODE;
1379 uint32_t Enable; /* 0 -- Disable. or 1 -- Enable */
1380 }__packed HostCmd_CFEND_ENABLE;
1381 #endif /* _MWL_HALREG_H_ */