2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Written by: yen_cw@myson.com.tw
5 * Copyright (c) 2002 Myson Technology Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification, immediately at the beginning of the file.
14 * 2. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
21 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * Myson fast ethernet PCI NIC driver, available at: http://www.myson.com.tw/
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/sockio.h>
39 #include <sys/malloc.h>
40 #include <sys/kernel.h>
41 #include <sys/socket.h>
42 #include <sys/queue.h>
43 #include <sys/types.h>
44 #include <sys/module.h>
46 #include <sys/mutex.h>
51 #include <net/if_var.h>
52 #include <net/if_arp.h>
53 #include <net/ethernet.h>
54 #include <net/if_media.h>
55 #include <net/if_types.h>
56 #include <net/if_dl.h>
59 #include <vm/vm.h> /* for vtophys */
60 #include <vm/pmap.h> /* for vtophys */
61 #include <machine/bus.h>
62 #include <machine/resource.h>
66 #include <dev/pci/pcireg.h>
67 #include <dev/pci/pcivar.h>
70 * #define MY_USEIOSPACE
73 static int MY_USEIOSPACE = 1;
76 #define MY_RES SYS_RES_IOPORT
77 #define MY_RID MY_PCI_LOIO
79 #define MY_RES SYS_RES_MEMORY
80 #define MY_RID MY_PCI_LOMEM
83 #include <dev/my/if_myreg.h>
86 * Various supported device vendors/types and their names.
88 struct my_type *my_info_tmp;
89 static struct my_type my_devs[] = {
90 {MYSONVENDORID, MTD800ID, "Myson MTD80X Based Fast Ethernet Card"},
91 {MYSONVENDORID, MTD803ID, "Myson MTD80X Based Fast Ethernet Card"},
92 {MYSONVENDORID, MTD891ID, "Myson MTD89X Based Giga Ethernet Card"},
97 * Various supported PHY vendors/types and their names. Note that this driver
98 * will work with pretty much any MII-compliant PHY, so failure to positively
99 * identify the chip is not a fatal error.
101 static struct my_type my_phys[] = {
102 {MysonPHYID0, MysonPHYID0, "<MYSON MTD981>"},
103 {SeeqPHYID0, SeeqPHYID0, "<SEEQ 80225>"},
104 {AhdocPHYID0, AhdocPHYID0, "<AHDOC 101>"},
105 {MarvellPHYID0, MarvellPHYID0, "<MARVELL 88E1000>"},
106 {LevelOnePHYID0, LevelOnePHYID0, "<LevelOne LXT1000>"},
107 {0, 0, "<MII-compliant physical interface>"}
110 static int my_probe(device_t);
111 static int my_attach(device_t);
112 static int my_detach(device_t);
113 static int my_newbuf(struct my_softc *, struct my_chain_onefrag *);
114 static int my_encap(struct my_softc *, struct my_chain *, struct mbuf *);
115 static void my_rxeof(struct my_softc *);
116 static void my_txeof(struct my_softc *);
117 static void my_txeoc(struct my_softc *);
118 static void my_intr(void *);
119 static void my_start(struct ifnet *);
120 static void my_start_locked(struct ifnet *);
121 static int my_ioctl(struct ifnet *, u_long, caddr_t);
122 static void my_init(void *);
123 static void my_init_locked(struct my_softc *);
124 static void my_stop(struct my_softc *);
125 static void my_autoneg_timeout(void *);
126 static void my_watchdog(void *);
127 static int my_shutdown(device_t);
128 static int my_ifmedia_upd(struct ifnet *);
129 static void my_ifmedia_sts(struct ifnet *, struct ifmediareq *);
130 static u_int16_t my_phy_readreg(struct my_softc *, int);
131 static void my_phy_writereg(struct my_softc *, int, int);
132 static void my_autoneg_xmit(struct my_softc *);
133 static void my_autoneg_mii(struct my_softc *, int, int);
134 static void my_setmode_mii(struct my_softc *, int);
135 static void my_getmode_mii(struct my_softc *);
136 static void my_setcfg(struct my_softc *, int);
137 static void my_setmulti(struct my_softc *);
138 static void my_reset(struct my_softc *);
139 static int my_list_rx_init(struct my_softc *);
140 static int my_list_tx_init(struct my_softc *);
141 static long my_send_cmd_to_phy(struct my_softc *, int, int);
143 #define MY_SETBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
144 #define MY_CLRBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
146 static device_method_t my_methods[] = {
147 /* Device interface */
148 DEVMETHOD(device_probe, my_probe),
149 DEVMETHOD(device_attach, my_attach),
150 DEVMETHOD(device_detach, my_detach),
151 DEVMETHOD(device_shutdown, my_shutdown),
156 static driver_t my_driver = {
159 sizeof(struct my_softc)
162 static devclass_t my_devclass;
164 DRIVER_MODULE(my, pci, my_driver, my_devclass, 0, 0);
165 MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, my, my_devs,
166 nitems(my_devs) - 1);
167 MODULE_DEPEND(my, pci, 1, 1, 1);
168 MODULE_DEPEND(my, ether, 1, 1, 1);
171 my_send_cmd_to_phy(struct my_softc * sc, int opcode, int regad)
179 /* enable MII output */
180 miir = CSR_READ_4(sc, MY_MANAGEMENT);
183 miir |= MY_MASK_MIIR_MII_WRITE + MY_MASK_MIIR_MII_MDO;
185 /* send 32 1's preamble */
186 for (i = 0; i < 32; i++) {
187 /* low MDC; MDO is already high (miir) */
188 miir &= ~MY_MASK_MIIR_MII_MDC;
189 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
192 miir |= MY_MASK_MIIR_MII_MDC;
193 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
196 /* calculate ST+OP+PHYAD+REGAD+TA */
197 data = opcode | (sc->my_phy_addr << 7) | (regad << 2);
202 /* low MDC, prepare MDO */
203 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO);
205 miir |= MY_MASK_MIIR_MII_MDO;
207 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
209 miir |= MY_MASK_MIIR_MII_MDC;
210 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
215 if (mask == 0x2 && opcode == MY_OP_READ)
216 miir &= ~MY_MASK_MIIR_MII_WRITE;
223 my_phy_readreg(struct my_softc * sc, int reg)
230 if (sc->my_info->my_did == MTD803ID)
231 data = CSR_READ_2(sc, MY_PHYBASE + reg * 2);
233 miir = my_send_cmd_to_phy(sc, MY_OP_READ, reg);
240 miir &= ~MY_MASK_MIIR_MII_MDC;
241 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
244 miir = CSR_READ_4(sc, MY_MANAGEMENT);
245 if (miir & MY_MASK_MIIR_MII_MDI)
248 /* high MDC, and wait */
249 miir |= MY_MASK_MIIR_MII_MDC;
250 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
258 miir &= ~MY_MASK_MIIR_MII_MDC;
259 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
262 return (u_int16_t) data;
266 my_phy_writereg(struct my_softc * sc, int reg, int data)
273 if (sc->my_info->my_did == MTD803ID)
274 CSR_WRITE_2(sc, MY_PHYBASE + reg * 2, data);
276 miir = my_send_cmd_to_phy(sc, MY_OP_WRITE, reg);
281 /* low MDC, prepare MDO */
282 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO);
284 miir |= MY_MASK_MIIR_MII_MDO;
285 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
289 miir |= MY_MASK_MIIR_MII_MDC;
290 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
298 miir &= ~MY_MASK_MIIR_MII_MDC;
299 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
305 my_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
307 uint32_t *hashes = arg;
310 h = ~ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 26;
312 hashes[0] |= (1 << h);
314 hashes[1] |= (1 << (h - 32));
319 * Program the 64-bit multicast hash filter.
322 my_setmulti(struct my_softc * sc)
325 u_int32_t hashes[2] = {0, 0};
332 rxfilt = CSR_READ_4(sc, MY_TCRRCR);
334 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
336 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt);
337 CSR_WRITE_4(sc, MY_MAR0, 0xFFFFFFFF);
338 CSR_WRITE_4(sc, MY_MAR1, 0xFFFFFFFF);
342 /* first, zot all the existing hash bits */
343 CSR_WRITE_4(sc, MY_MAR0, 0);
344 CSR_WRITE_4(sc, MY_MAR1, 0);
346 /* now program new ones */
347 if (if_foreach_llmaddr(ifp, my_hash_maddr, hashes) > 0)
351 CSR_WRITE_4(sc, MY_MAR0, hashes[0]);
352 CSR_WRITE_4(sc, MY_MAR1, hashes[1]);
353 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt);
357 * Initiate an autonegotiation session.
360 my_autoneg_xmit(struct my_softc * sc)
362 u_int16_t phy_sts = 0;
366 my_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET);
368 while (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_RESET);
370 phy_sts = my_phy_readreg(sc, PHY_BMCR);
371 phy_sts |= PHY_BMCR_AUTONEGENBL | PHY_BMCR_AUTONEGRSTR;
372 my_phy_writereg(sc, PHY_BMCR, phy_sts);
378 my_autoneg_timeout(void *arg)
384 my_autoneg_mii(sc, MY_FLAG_DELAYTIMEO, 1);
388 * Invoke autonegotiation on a PHY.
391 my_autoneg_mii(struct my_softc * sc, int flag, int verbose)
393 u_int16_t phy_sts = 0, media, advert, ability;
394 u_int16_t ability2 = 0;
403 ifm->ifm_media = IFM_ETHER | IFM_AUTO;
405 #ifndef FORCE_AUTONEG_TFOUR
407 * First, see if autoneg is supported. If not, there's no point in
410 phy_sts = my_phy_readreg(sc, PHY_BMSR);
411 if (!(phy_sts & PHY_BMSR_CANAUTONEG)) {
413 device_printf(sc->my_dev,
414 "autonegotiation not supported\n");
415 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX;
420 case MY_FLAG_FORCEDELAY:
422 * XXX Never use this option anywhere but in the probe
423 * routine: making the kernel stop dead in its tracks for
424 * three whole seconds after we've gone multi-user is really
430 case MY_FLAG_SCHEDDELAY:
432 * Wait for the transmitter to go idle before starting an
433 * autoneg session, otherwise my_start() may clobber our
434 * timeout, and we don't want to allow transmission during an
435 * autoneg session since that can screw it up.
437 if (sc->my_cdata.my_tx_head != NULL) {
438 sc->my_want_auto = 1;
443 callout_reset(&sc->my_autoneg_timer, hz * 5, my_autoneg_timeout,
446 sc->my_want_auto = 0;
448 case MY_FLAG_DELAYTIMEO:
449 callout_stop(&sc->my_autoneg_timer);
453 device_printf(sc->my_dev, "invalid autoneg flag: %d\n", flag);
457 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) {
459 device_printf(sc->my_dev, "autoneg complete, ");
460 phy_sts = my_phy_readreg(sc, PHY_BMSR);
463 device_printf(sc->my_dev, "autoneg not complete, ");
466 media = my_phy_readreg(sc, PHY_BMCR);
468 /* Link is good. Report modes and set duplex mode. */
469 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) {
471 device_printf(sc->my_dev, "link status good. ");
472 advert = my_phy_readreg(sc, PHY_ANAR);
473 ability = my_phy_readreg(sc, PHY_LPAR);
474 if ((sc->my_pinfo->my_vid == MarvellPHYID0) ||
475 (sc->my_pinfo->my_vid == LevelOnePHYID0)) {
476 ability2 = my_phy_readreg(sc, PHY_1000SR);
477 if (ability2 & PHY_1000SR_1000BTXFULL) {
481 * this version did not support 1000M,
483 * IFM_ETHER|IFM_1000_T|IFM_FDX;
486 IFM_ETHER | IFM_100_TX | IFM_FDX;
487 media &= ~PHY_BMCR_SPEEDSEL;
488 media |= PHY_BMCR_1000;
489 media |= PHY_BMCR_DUPLEX;
490 printf("(full-duplex, 1000Mbps)\n");
491 } else if (ability2 & PHY_1000SR_1000BTXHALF) {
495 * this version did not support 1000M,
496 * ifm->ifm_media = IFM_ETHER|IFM_1000_T;
498 ifm->ifm_media = IFM_ETHER | IFM_100_TX;
499 media &= ~PHY_BMCR_SPEEDSEL;
500 media &= ~PHY_BMCR_DUPLEX;
501 media |= PHY_BMCR_1000;
502 printf("(half-duplex, 1000Mbps)\n");
505 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) {
506 ifm->ifm_media = IFM_ETHER | IFM_100_T4;
507 media |= PHY_BMCR_SPEEDSEL;
508 media &= ~PHY_BMCR_DUPLEX;
509 printf("(100baseT4)\n");
510 } else if (advert & PHY_ANAR_100BTXFULL &&
511 ability & PHY_ANAR_100BTXFULL) {
512 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX;
513 media |= PHY_BMCR_SPEEDSEL;
514 media |= PHY_BMCR_DUPLEX;
515 printf("(full-duplex, 100Mbps)\n");
516 } else if (advert & PHY_ANAR_100BTXHALF &&
517 ability & PHY_ANAR_100BTXHALF) {
518 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX;
519 media |= PHY_BMCR_SPEEDSEL;
520 media &= ~PHY_BMCR_DUPLEX;
521 printf("(half-duplex, 100Mbps)\n");
522 } else if (advert & PHY_ANAR_10BTFULL &&
523 ability & PHY_ANAR_10BTFULL) {
524 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX;
525 media &= ~PHY_BMCR_SPEEDSEL;
526 media |= PHY_BMCR_DUPLEX;
527 printf("(full-duplex, 10Mbps)\n");
529 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX;
530 media &= ~PHY_BMCR_SPEEDSEL;
531 media &= ~PHY_BMCR_DUPLEX;
532 printf("(half-duplex, 10Mbps)\n");
534 media &= ~PHY_BMCR_AUTONEGENBL;
536 /* Set ASIC's duplex mode to match the PHY. */
537 my_phy_writereg(sc, PHY_BMCR, media);
538 my_setcfg(sc, media);
541 device_printf(sc->my_dev, "no carrier\n");
545 if (sc->my_tx_pend) {
548 my_start_locked(ifp);
554 * To get PHY ability.
557 my_getmode_mii(struct my_softc * sc)
564 bmsr = my_phy_readreg(sc, PHY_BMSR);
566 device_printf(sc->my_dev, "PHY status word: %x\n", bmsr);
569 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX;
571 if (bmsr & PHY_BMSR_10BTHALF) {
573 device_printf(sc->my_dev,
574 "10Mbps half-duplex mode supported\n");
575 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_HDX,
577 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T, 0, NULL);
579 if (bmsr & PHY_BMSR_10BTFULL) {
581 device_printf(sc->my_dev,
582 "10Mbps full-duplex mode supported\n");
584 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX,
586 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX;
588 if (bmsr & PHY_BMSR_100BTXHALF) {
590 device_printf(sc->my_dev,
591 "100Mbps half-duplex mode supported\n");
592 ifp->if_baudrate = 100000000;
593 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL);
594 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_HDX,
596 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX;
598 if (bmsr & PHY_BMSR_100BTXFULL) {
600 device_printf(sc->my_dev,
601 "100Mbps full-duplex mode supported\n");
602 ifp->if_baudrate = 100000000;
603 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX,
605 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX;
607 /* Some also support 100BaseT4. */
608 if (bmsr & PHY_BMSR_100BT4) {
610 device_printf(sc->my_dev, "100baseT4 mode supported\n");
611 ifp->if_baudrate = 100000000;
612 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_T4, 0, NULL);
613 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_T4;
614 #ifdef FORCE_AUTONEG_TFOUR
616 device_printf(sc->my_dev,
617 "forcing on autoneg support for BT4\n");
618 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0 NULL):
619 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO;
622 #if 0 /* this version did not support 1000M, */
623 if (sc->my_pinfo->my_vid == MarvellPHYID0) {
625 device_printf(sc->my_dev,
626 "1000Mbps half-duplex mode supported\n");
628 ifp->if_baudrate = 1000000000;
629 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T, 0, NULL);
630 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_HDX,
633 device_printf(sc->my_dev,
634 "1000Mbps full-duplex mode supported\n");
635 ifp->if_baudrate = 1000000000;
636 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_FDX,
638 sc->ifmedia.ifm_media = IFM_ETHER | IFM_1000_T | IFM_FDX;
641 if (bmsr & PHY_BMSR_CANAUTONEG) {
643 device_printf(sc->my_dev, "autoneg supported\n");
644 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
645 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO;
651 * Set speed and duplex mode.
654 my_setmode_mii(struct my_softc * sc, int media)
660 * If an autoneg session is in progress, stop it.
662 if (sc->my_autoneg) {
663 device_printf(sc->my_dev, "canceling autoneg session\n");
664 callout_stop(&sc->my_autoneg_timer);
665 sc->my_autoneg = sc->my_want_auto = 0;
666 bmcr = my_phy_readreg(sc, PHY_BMCR);
667 bmcr &= ~PHY_BMCR_AUTONEGENBL;
668 my_phy_writereg(sc, PHY_BMCR, bmcr);
670 device_printf(sc->my_dev, "selecting MII, ");
671 bmcr = my_phy_readreg(sc, PHY_BMCR);
672 bmcr &= ~(PHY_BMCR_AUTONEGENBL | PHY_BMCR_SPEEDSEL | PHY_BMCR_1000 |
673 PHY_BMCR_DUPLEX | PHY_BMCR_LOOPBK);
675 #if 0 /* this version did not support 1000M, */
676 if (IFM_SUBTYPE(media) == IFM_1000_T) {
677 printf("1000Mbps/T4, half-duplex\n");
678 bmcr &= ~PHY_BMCR_SPEEDSEL;
679 bmcr &= ~PHY_BMCR_DUPLEX;
680 bmcr |= PHY_BMCR_1000;
683 if (IFM_SUBTYPE(media) == IFM_100_T4) {
684 printf("100Mbps/T4, half-duplex\n");
685 bmcr |= PHY_BMCR_SPEEDSEL;
686 bmcr &= ~PHY_BMCR_DUPLEX;
688 if (IFM_SUBTYPE(media) == IFM_100_TX) {
690 bmcr |= PHY_BMCR_SPEEDSEL;
692 if (IFM_SUBTYPE(media) == IFM_10_T) {
694 bmcr &= ~PHY_BMCR_SPEEDSEL;
696 if ((media & IFM_GMASK) == IFM_FDX) {
697 printf("full duplex\n");
698 bmcr |= PHY_BMCR_DUPLEX;
700 printf("half duplex\n");
701 bmcr &= ~PHY_BMCR_DUPLEX;
703 my_phy_writereg(sc, PHY_BMCR, bmcr);
709 * The Myson manual states that in order to fiddle with the 'full-duplex' and
710 * '100Mbps' bits in the netconfig register, we first have to put the
711 * transmit and/or receive logic in the idle state.
714 my_setcfg(struct my_softc * sc, int bmcr)
719 if (CSR_READ_4(sc, MY_TCRRCR) & (MY_TE | MY_RE)) {
721 MY_CLRBIT(sc, MY_TCRRCR, (MY_TE | MY_RE));
722 for (i = 0; i < MY_TIMEOUT; i++) {
724 if (!(CSR_READ_4(sc, MY_TCRRCR) &
725 (MY_TXRUN | MY_RXRUN)))
729 device_printf(sc->my_dev,
730 "failed to force tx and rx to idle \n");
732 MY_CLRBIT(sc, MY_TCRRCR, MY_PS1000);
733 MY_CLRBIT(sc, MY_TCRRCR, MY_PS10);
734 if (bmcr & PHY_BMCR_1000)
735 MY_SETBIT(sc, MY_TCRRCR, MY_PS1000);
736 else if (!(bmcr & PHY_BMCR_SPEEDSEL))
737 MY_SETBIT(sc, MY_TCRRCR, MY_PS10);
738 if (bmcr & PHY_BMCR_DUPLEX)
739 MY_SETBIT(sc, MY_TCRRCR, MY_FD);
741 MY_CLRBIT(sc, MY_TCRRCR, MY_FD);
743 MY_SETBIT(sc, MY_TCRRCR, MY_TE | MY_RE);
748 my_reset(struct my_softc * sc)
753 MY_SETBIT(sc, MY_BCR, MY_SWR);
754 for (i = 0; i < MY_TIMEOUT; i++) {
756 if (!(CSR_READ_4(sc, MY_BCR) & MY_SWR))
760 device_printf(sc->my_dev, "reset never completed!\n");
762 /* Wait a little while for the chip to get its brains in order. */
768 * Probe for a Myson chip. Check the PCI vendor and device IDs against our
769 * list and return a device name if we find a match.
772 my_probe(device_t dev)
777 while (t->my_name != NULL) {
778 if ((pci_get_vendor(dev) == t->my_vid) &&
779 (pci_get_device(dev) == t->my_did)) {
780 device_set_desc(dev, t->my_name);
782 return (BUS_PROBE_DEFAULT);
790 * Attach the interface. Allocate softc structures, do ifmedia setup and
791 * ethernet/BPF attach.
794 my_attach(device_t dev)
797 u_char eaddr[ETHER_ADDR_LEN];
801 int media = IFM_ETHER | IFM_100_TX | IFM_FDX;
805 u_int16_t phy_vid, phy_did, phy_sts = 0;
808 sc = device_get_softc(dev);
810 mtx_init(&sc->my_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
812 callout_init_mtx(&sc->my_autoneg_timer, &sc->my_mtx, 0);
813 callout_init_mtx(&sc->my_watchdog, &sc->my_mtx, 0);
816 * Map control/status registers.
818 pci_enable_busmaster(dev);
820 if (my_info_tmp->my_did == MTD800ID) {
821 iobase = pci_read_config(dev, MY_PCI_LOIO, 4);
827 sc->my_res = bus_alloc_resource_any(dev, MY_RES, &rid, RF_ACTIVE);
829 if (sc->my_res == NULL) {
830 device_printf(dev, "couldn't map ports/memory\n");
834 sc->my_btag = rman_get_bustag(sc->my_res);
835 sc->my_bhandle = rman_get_bushandle(sc->my_res);
838 sc->my_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
839 RF_SHAREABLE | RF_ACTIVE);
841 if (sc->my_irq == NULL) {
842 device_printf(dev, "couldn't map interrupt\n");
847 sc->my_info = my_info_tmp;
849 /* Reset the adapter. */
855 * Get station address
857 for (i = 0; i < ETHER_ADDR_LEN; ++i)
858 eaddr[i] = CSR_READ_1(sc, MY_PAR0 + i);
860 sc->my_ldata_ptr = malloc(sizeof(struct my_list_data) + 8,
862 if (sc->my_ldata_ptr == NULL) {
863 device_printf(dev, "no memory for list buffers!\n");
867 sc->my_ldata = (struct my_list_data *) sc->my_ldata_ptr;
868 round = (uintptr_t)sc->my_ldata_ptr & 0xF;
869 roundptr = sc->my_ldata_ptr;
870 for (i = 0; i < 8; i++) {
877 sc->my_ldata = (struct my_list_data *) roundptr;
878 bzero(sc->my_ldata, sizeof(struct my_list_data));
880 ifp = sc->my_ifp = if_alloc(IFT_ETHER);
882 device_printf(dev, "can not if_alloc()\n");
887 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
888 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
889 ifp->if_ioctl = my_ioctl;
890 ifp->if_start = my_start;
891 ifp->if_init = my_init;
892 ifp->if_baudrate = 10000000;
893 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
894 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen;
895 IFQ_SET_READY(&ifp->if_snd);
897 if (sc->my_info->my_did == MTD803ID)
898 sc->my_pinfo = my_phys;
901 device_printf(dev, "probing for a PHY\n");
903 for (i = MY_PHYADDR_MIN; i < MY_PHYADDR_MAX + 1; i++) {
905 device_printf(dev, "checking address: %d\n", i);
907 phy_sts = my_phy_readreg(sc, PHY_BMSR);
908 if ((phy_sts != 0) && (phy_sts != 0xffff))
914 phy_vid = my_phy_readreg(sc, PHY_VENID);
915 phy_did = my_phy_readreg(sc, PHY_DEVID);
917 device_printf(dev, "found PHY at address %d, ",
919 printf("vendor id: %x device id: %x\n",
924 if (phy_vid == p->my_vid) {
930 if (sc->my_pinfo == NULL)
931 sc->my_pinfo = &my_phys[PHY_UNKNOWN];
933 device_printf(dev, "PHY type: %s\n",
934 sc->my_pinfo->my_name);
937 device_printf(dev, "MII without any phy!\n");
944 /* Do ifmedia setup. */
945 ifmedia_init(&sc->ifmedia, 0, my_ifmedia_upd, my_ifmedia_sts);
948 my_autoneg_mii(sc, MY_FLAG_FORCEDELAY, 1);
949 media = sc->ifmedia.ifm_media;
952 ifmedia_set(&sc->ifmedia, media);
954 ether_ifattach(ifp, eaddr);
956 error = bus_setup_intr(dev, sc->my_irq, INTR_TYPE_NET | INTR_MPSAFE,
957 NULL, my_intr, sc, &sc->my_intrhand);
960 device_printf(dev, "couldn't set up irq\n");
971 free(sc->my_ldata_ptr, M_DEVBUF);
973 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq);
975 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res);
977 mtx_destroy(&sc->my_mtx);
982 my_detach(device_t dev)
987 sc = device_get_softc(dev);
993 bus_teardown_intr(dev, sc->my_irq, sc->my_intrhand);
994 callout_drain(&sc->my_watchdog);
995 callout_drain(&sc->my_autoneg_timer);
998 free(sc->my_ldata_ptr, M_DEVBUF);
1000 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq);
1001 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res);
1002 mtx_destroy(&sc->my_mtx);
1007 * Initialize the transmit descriptors.
1010 my_list_tx_init(struct my_softc * sc)
1012 struct my_chain_data *cd;
1013 struct my_list_data *ld;
1019 for (i = 0; i < MY_TX_LIST_CNT; i++) {
1020 cd->my_tx_chain[i].my_ptr = &ld->my_tx_list[i];
1021 if (i == (MY_TX_LIST_CNT - 1))
1022 cd->my_tx_chain[i].my_nextdesc = &cd->my_tx_chain[0];
1024 cd->my_tx_chain[i].my_nextdesc =
1025 &cd->my_tx_chain[i + 1];
1027 cd->my_tx_free = &cd->my_tx_chain[0];
1028 cd->my_tx_tail = cd->my_tx_head = NULL;
1033 * Initialize the RX descriptors and allocate mbufs for them. Note that we
1034 * arrange the descriptors in a closed ring, so that the last descriptor
1035 * points back to the first.
1038 my_list_rx_init(struct my_softc * sc)
1040 struct my_chain_data *cd;
1041 struct my_list_data *ld;
1047 for (i = 0; i < MY_RX_LIST_CNT; i++) {
1048 cd->my_rx_chain[i].my_ptr =
1049 (struct my_desc *) & ld->my_rx_list[i];
1050 if (my_newbuf(sc, &cd->my_rx_chain[i]) == ENOBUFS) {
1054 if (i == (MY_RX_LIST_CNT - 1)) {
1055 cd->my_rx_chain[i].my_nextdesc = &cd->my_rx_chain[0];
1056 ld->my_rx_list[i].my_next = vtophys(&ld->my_rx_list[0]);
1058 cd->my_rx_chain[i].my_nextdesc =
1059 &cd->my_rx_chain[i + 1];
1060 ld->my_rx_list[i].my_next =
1061 vtophys(&ld->my_rx_list[i + 1]);
1064 cd->my_rx_head = &cd->my_rx_chain[0];
1069 * Initialize an RX descriptor and attach an MBUF cluster.
1072 my_newbuf(struct my_softc * sc, struct my_chain_onefrag * c)
1074 struct mbuf *m_new = NULL;
1077 MGETHDR(m_new, M_NOWAIT, MT_DATA);
1078 if (m_new == NULL) {
1079 device_printf(sc->my_dev,
1080 "no memory for rx list -- packet dropped!\n");
1083 if (!(MCLGET(m_new, M_NOWAIT))) {
1084 device_printf(sc->my_dev,
1085 "no memory for rx list -- packet dropped!\n");
1090 c->my_ptr->my_data = vtophys(mtod(m_new, caddr_t));
1091 c->my_ptr->my_ctl = (MCLBYTES - 1) << MY_RBSShift;
1092 c->my_ptr->my_status = MY_OWNByNIC;
1097 * A frame has been uploaded: pass the resulting mbuf chain up to the higher
1101 my_rxeof(struct my_softc * sc)
1103 struct ether_header *eh;
1106 struct my_chain_onefrag *cur_rx;
1112 while (!((rxstat = sc->my_cdata.my_rx_head->my_ptr->my_status)
1114 cur_rx = sc->my_cdata.my_rx_head;
1115 sc->my_cdata.my_rx_head = cur_rx->my_nextdesc;
1117 if (rxstat & MY_ES) { /* error summary: give up this rx pkt */
1118 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1119 cur_rx->my_ptr->my_status = MY_OWNByNIC;
1122 /* No errors; receive the packet. */
1123 total_len = (rxstat & MY_FLNGMASK) >> MY_FLNGShift;
1124 total_len -= ETHER_CRC_LEN;
1126 if (total_len < MINCLSIZE) {
1127 m = m_devget(mtod(cur_rx->my_mbuf, char *),
1128 total_len, 0, ifp, NULL);
1129 cur_rx->my_ptr->my_status = MY_OWNByNIC;
1131 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1135 m = cur_rx->my_mbuf;
1137 * Try to conjure up a new mbuf cluster. If that
1138 * fails, it means we have an out of memory condition
1139 * and should leave the buffer in place and continue.
1140 * This will result in a lost packet, but there's
1141 * little else we can do in this situation.
1143 if (my_newbuf(sc, cur_rx) == ENOBUFS) {
1144 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1145 cur_rx->my_ptr->my_status = MY_OWNByNIC;
1148 m->m_pkthdr.rcvif = ifp;
1149 m->m_pkthdr.len = m->m_len = total_len;
1151 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
1152 eh = mtod(m, struct ether_header *);
1155 * Handle BPF listeners. Let the BPF user see the packet, but
1156 * don't pass it up to the ether_input() layer unless it's a
1157 * broadcast packet, multicast packet, matches our ethernet
1158 * address or the interface is in promiscuous mode.
1160 if (bpf_peers_present(ifp->if_bpf)) {
1161 bpf_mtap(ifp->if_bpf, m);
1162 if (ifp->if_flags & IFF_PROMISC &&
1163 (bcmp(eh->ether_dhost, IF_LLADDR(sc->my_ifp),
1165 (eh->ether_dhost[0] & 1) == 0)) {
1172 (*ifp->if_input)(ifp, m);
1179 * A frame was downloaded to the chip. It's safe for us to clean up the list
1183 my_txeof(struct my_softc * sc)
1185 struct my_chain *cur_tx;
1190 /* Clear the timeout timer. */
1192 if (sc->my_cdata.my_tx_head == NULL) {
1196 * Go through our tx list and free mbufs for those frames that have
1199 while (sc->my_cdata.my_tx_head->my_mbuf != NULL) {
1202 cur_tx = sc->my_cdata.my_tx_head;
1203 txstat = MY_TXSTATUS(cur_tx);
1204 if ((txstat & MY_OWNByNIC) || txstat == MY_UNSENT)
1206 if (!(CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced)) {
1207 if (txstat & MY_TXERR) {
1208 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1209 if (txstat & MY_EC) /* excessive collision */
1210 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
1211 if (txstat & MY_LC) /* late collision */
1212 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
1214 if_inc_counter(ifp, IFCOUNTER_COLLISIONS,
1215 (txstat & MY_NCRMASK) >> MY_NCRShift);
1217 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
1218 m_freem(cur_tx->my_mbuf);
1219 cur_tx->my_mbuf = NULL;
1220 if (sc->my_cdata.my_tx_head == sc->my_cdata.my_tx_tail) {
1221 sc->my_cdata.my_tx_head = NULL;
1222 sc->my_cdata.my_tx_tail = NULL;
1225 sc->my_cdata.my_tx_head = cur_tx->my_nextdesc;
1227 if (CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced) {
1228 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, (CSR_READ_4(sc, MY_TSR) & MY_NCRMask));
1234 * TX 'end of channel' interrupt handler.
1237 my_txeoc(struct my_softc * sc)
1244 if (sc->my_cdata.my_tx_head == NULL) {
1245 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1246 sc->my_cdata.my_tx_tail = NULL;
1247 if (sc->my_want_auto)
1248 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1);
1250 if (MY_TXOWN(sc->my_cdata.my_tx_head) == MY_UNSENT) {
1251 MY_TXOWN(sc->my_cdata.my_tx_head) = MY_OWNByNIC;
1253 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF);
1262 struct my_softc *sc;
1269 if (!(ifp->if_flags & IFF_UP)) {
1273 /* Disable interrupts. */
1274 CSR_WRITE_4(sc, MY_IMR, 0x00000000);
1277 status = CSR_READ_4(sc, MY_ISR);
1280 CSR_WRITE_4(sc, MY_ISR, status);
1284 if (status & MY_RI) /* receive interrupt */
1287 if ((status & MY_RBU) || (status & MY_RxErr)) {
1288 /* rx buffer unavailable or rx error */
1289 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1296 if (status & MY_TI) /* tx interrupt */
1298 if (status & MY_ETI) /* tx early interrupt */
1300 if (status & MY_TBU) /* tx buffer unavailable */
1303 #if 0 /* 90/1/18 delete */
1304 if (status & MY_FBE) {
1311 /* Re-enable interrupts. */
1312 CSR_WRITE_4(sc, MY_IMR, MY_INTRS);
1313 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1314 my_start_locked(ifp);
1320 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1321 * pointers to the fragment pointers.
1324 my_encap(struct my_softc * sc, struct my_chain * c, struct mbuf * m_head)
1326 struct my_desc *f = NULL;
1328 struct mbuf *m, *m_new = NULL;
1331 /* calculate the total tx pkt length */
1333 for (m = m_head; m != NULL; m = m->m_next)
1334 total_len += m->m_len;
1336 * Start packing the mbufs in this chain into the fragment pointers.
1337 * Stop when we run out of fragments or hit the end of the mbuf
1341 MGETHDR(m_new, M_NOWAIT, MT_DATA);
1342 if (m_new == NULL) {
1343 device_printf(sc->my_dev, "no memory for tx list");
1346 if (m_head->m_pkthdr.len > MHLEN) {
1347 if (!(MCLGET(m_new, M_NOWAIT))) {
1349 device_printf(sc->my_dev, "no memory for tx list");
1353 m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t));
1354 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1357 f = &c->my_ptr->my_frag[0];
1359 f->my_data = vtophys(mtod(m_new, caddr_t));
1360 total_len = m_new->m_len;
1361 f->my_ctl = MY_TXFD | MY_TXLD | MY_CRCEnable | MY_PADEnable;
1362 f->my_ctl |= total_len << MY_PKTShift; /* pkt size */
1363 f->my_ctl |= total_len; /* buffer size */
1364 /* 89/12/29 add, for mtd891 *//* [ 89? ] */
1365 if (sc->my_info->my_did == MTD891ID)
1366 f->my_ctl |= MY_ETIControl | MY_RetryTxLC;
1367 c->my_mbuf = m_head;
1369 MY_TXNEXT(c) = vtophys(&c->my_nextdesc->my_ptr->my_frag[0]);
1374 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1375 * to the mbuf data regions directly in the transmit lists. We also save a
1376 * copy of the pointers since the transmit list fragment pointers are
1377 * physical addresses.
1380 my_start(struct ifnet * ifp)
1382 struct my_softc *sc;
1386 my_start_locked(ifp);
1391 my_start_locked(struct ifnet * ifp)
1393 struct my_softc *sc;
1394 struct mbuf *m_head = NULL;
1395 struct my_chain *cur_tx = NULL, *start_tx;
1399 if (sc->my_autoneg) {
1404 * Check for an available queue slot. If there are none, punt.
1406 if (sc->my_cdata.my_tx_free->my_mbuf != NULL) {
1407 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1410 start_tx = sc->my_cdata.my_tx_free;
1411 while (sc->my_cdata.my_tx_free->my_mbuf == NULL) {
1412 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1416 /* Pick a descriptor off the free list. */
1417 cur_tx = sc->my_cdata.my_tx_free;
1418 sc->my_cdata.my_tx_free = cur_tx->my_nextdesc;
1420 /* Pack the data into the descriptor. */
1421 my_encap(sc, cur_tx, m_head);
1423 if (cur_tx != start_tx)
1424 MY_TXOWN(cur_tx) = MY_OWNByNIC;
1427 * If there's a BPF listener, bounce a copy of this frame to
1430 BPF_MTAP(ifp, cur_tx->my_mbuf);
1434 * If there are no packets queued, bail.
1436 if (cur_tx == NULL) {
1440 * Place the request for the upload interrupt in the last descriptor
1441 * in the chain. This way, if we're chaining several packets at once,
1442 * we'll only get an interrupt once for the whole chain rather than
1443 * once for each packet.
1445 MY_TXCTL(cur_tx) |= MY_TXIC;
1446 cur_tx->my_ptr->my_frag[0].my_ctl |= MY_TXIC;
1447 sc->my_cdata.my_tx_tail = cur_tx;
1448 if (sc->my_cdata.my_tx_head == NULL)
1449 sc->my_cdata.my_tx_head = start_tx;
1450 MY_TXOWN(start_tx) = MY_OWNByNIC;
1451 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF); /* tx polling demand */
1454 * Set a timeout in case the chip goes out to lunch.
1463 struct my_softc *sc = xsc;
1471 my_init_locked(struct my_softc *sc)
1473 struct ifnet *ifp = sc->my_ifp;
1474 u_int16_t phy_bmcr = 0;
1477 if (sc->my_autoneg) {
1480 if (sc->my_pinfo != NULL)
1481 phy_bmcr = my_phy_readreg(sc, PHY_BMCR);
1483 * Cancel pending I/O and free all RX/TX buffers.
1489 * Set cache alignment and burst length.
1491 #if 0 /* 89/9/1 modify, */
1492 CSR_WRITE_4(sc, MY_BCR, MY_RPBLE512);
1493 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF);
1495 CSR_WRITE_4(sc, MY_BCR, MY_PBL8);
1496 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF | MY_RBLEN | MY_RPBLE512);
1498 * 89/12/29 add, for mtd891,
1500 if (sc->my_info->my_did == MTD891ID) {
1501 MY_SETBIT(sc, MY_BCR, MY_PROG);
1502 MY_SETBIT(sc, MY_TCRRCR, MY_Enhanced);
1504 my_setcfg(sc, phy_bmcr);
1505 /* Init circular RX list. */
1506 if (my_list_rx_init(sc) == ENOBUFS) {
1507 device_printf(sc->my_dev, "init failed: no memory for rx buffers\n");
1511 /* Init TX descriptors. */
1512 my_list_tx_init(sc);
1514 /* If we want promiscuous mode, set the allframes bit. */
1515 if (ifp->if_flags & IFF_PROMISC)
1516 MY_SETBIT(sc, MY_TCRRCR, MY_PROM);
1518 MY_CLRBIT(sc, MY_TCRRCR, MY_PROM);
1521 * Set capture broadcast bit to capture broadcast frames.
1523 if (ifp->if_flags & IFF_BROADCAST)
1524 MY_SETBIT(sc, MY_TCRRCR, MY_AB);
1526 MY_CLRBIT(sc, MY_TCRRCR, MY_AB);
1529 * Program the multicast filter, if necessary.
1534 * Load the address of the RX list.
1536 MY_CLRBIT(sc, MY_TCRRCR, MY_RE);
1537 CSR_WRITE_4(sc, MY_RXLBA, vtophys(&sc->my_ldata->my_rx_list[0]));
1540 * Enable interrupts.
1542 CSR_WRITE_4(sc, MY_IMR, MY_INTRS);
1543 CSR_WRITE_4(sc, MY_ISR, 0xFFFFFFFF);
1545 /* Enable receiver and transmitter. */
1546 MY_SETBIT(sc, MY_TCRRCR, MY_RE);
1547 MY_CLRBIT(sc, MY_TCRRCR, MY_TE);
1548 CSR_WRITE_4(sc, MY_TXLBA, vtophys(&sc->my_ldata->my_tx_list[0]));
1549 MY_SETBIT(sc, MY_TCRRCR, MY_TE);
1551 /* Restore state of BMCR */
1552 if (sc->my_pinfo != NULL)
1553 my_phy_writereg(sc, PHY_BMCR, phy_bmcr);
1554 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1555 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1557 callout_reset(&sc->my_watchdog, hz, my_watchdog, sc);
1562 * Set media options.
1566 my_ifmedia_upd(struct ifnet * ifp)
1568 struct my_softc *sc;
1569 struct ifmedia *ifm;
1574 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) {
1578 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO)
1579 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1);
1581 my_setmode_mii(sc, ifm->ifm_media);
1587 * Report current media status.
1591 my_ifmedia_sts(struct ifnet * ifp, struct ifmediareq * ifmr)
1593 struct my_softc *sc;
1594 u_int16_t advert = 0, ability = 0;
1598 ifmr->ifm_active = IFM_ETHER;
1599 if (!(my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) {
1600 #if 0 /* this version did not support 1000M, */
1601 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_1000)
1602 ifmr->ifm_active = IFM_ETHER | IFM_1000TX;
1604 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL)
1605 ifmr->ifm_active = IFM_ETHER | IFM_100_TX;
1607 ifmr->ifm_active = IFM_ETHER | IFM_10_T;
1608 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX)
1609 ifmr->ifm_active |= IFM_FDX;
1611 ifmr->ifm_active |= IFM_HDX;
1616 ability = my_phy_readreg(sc, PHY_LPAR);
1617 advert = my_phy_readreg(sc, PHY_ANAR);
1619 #if 0 /* this version did not support 1000M, */
1620 if (sc->my_pinfo->my_vid = MarvellPHYID0) {
1621 ability2 = my_phy_readreg(sc, PHY_1000SR);
1622 if (ability2 & PHY_1000SR_1000BTXFULL) {
1625 ifmr->ifm_active = IFM_ETHER|IFM_1000_T|IFM_FDX;
1626 } else if (ability & PHY_1000SR_1000BTXHALF) {
1629 ifmr->ifm_active = IFM_ETHER|IFM_1000_T|IFM_HDX;
1633 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4)
1634 ifmr->ifm_active = IFM_ETHER | IFM_100_T4;
1635 else if (advert & PHY_ANAR_100BTXFULL && ability & PHY_ANAR_100BTXFULL)
1636 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1637 else if (advert & PHY_ANAR_100BTXHALF && ability & PHY_ANAR_100BTXHALF)
1638 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_HDX;
1639 else if (advert & PHY_ANAR_10BTFULL && ability & PHY_ANAR_10BTFULL)
1640 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_FDX;
1641 else if (advert & PHY_ANAR_10BTHALF && ability & PHY_ANAR_10BTHALF)
1642 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_HDX;
1648 my_ioctl(struct ifnet * ifp, u_long command, caddr_t data)
1650 struct my_softc *sc = ifp->if_softc;
1651 struct ifreq *ifr = (struct ifreq *) data;
1657 if (ifp->if_flags & IFF_UP)
1659 else if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1673 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
1676 error = ether_ioctl(ifp, command, data);
1683 my_watchdog(void *arg)
1685 struct my_softc *sc;
1690 callout_reset(&sc->my_watchdog, hz, my_watchdog, sc);
1691 if (sc->my_timer == 0 || --sc->my_timer > 0)
1695 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1696 if_printf(ifp, "watchdog timeout\n");
1697 if (!(my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT))
1698 if_printf(ifp, "no carrier - transceiver cable problem?\n");
1702 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1703 my_start_locked(ifp);
1707 * Stop the adapter and free any mbufs allocated to the RX and TX lists.
1710 my_stop(struct my_softc * sc)
1718 callout_stop(&sc->my_autoneg_timer);
1719 callout_stop(&sc->my_watchdog);
1721 MY_CLRBIT(sc, MY_TCRRCR, (MY_RE | MY_TE));
1722 CSR_WRITE_4(sc, MY_IMR, 0x00000000);
1723 CSR_WRITE_4(sc, MY_TXLBA, 0x00000000);
1724 CSR_WRITE_4(sc, MY_RXLBA, 0x00000000);
1727 * Free data in the RX lists.
1729 for (i = 0; i < MY_RX_LIST_CNT; i++) {
1730 if (sc->my_cdata.my_rx_chain[i].my_mbuf != NULL) {
1731 m_freem(sc->my_cdata.my_rx_chain[i].my_mbuf);
1732 sc->my_cdata.my_rx_chain[i].my_mbuf = NULL;
1735 bzero((char *)&sc->my_ldata->my_rx_list,
1736 sizeof(sc->my_ldata->my_rx_list));
1738 * Free the TX list buffers.
1740 for (i = 0; i < MY_TX_LIST_CNT; i++) {
1741 if (sc->my_cdata.my_tx_chain[i].my_mbuf != NULL) {
1742 m_freem(sc->my_cdata.my_tx_chain[i].my_mbuf);
1743 sc->my_cdata.my_tx_chain[i].my_mbuf = NULL;
1746 bzero((char *)&sc->my_ldata->my_tx_list,
1747 sizeof(sc->my_ldata->my_tx_list));
1748 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1753 * Stop all chip I/O so that the kernel's probe routines don't get confused
1754 * by errant DMAs when rebooting.
1757 my_shutdown(device_t dev)
1759 struct my_softc *sc;
1761 sc = device_get_softc(dev);