2 * Copyright (c) 2002 Myson Technology Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions, and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. The name of the author may not be used to endorse or promote products
12 * derived from this software without specific prior written permission.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
18 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * Written by: yen_cw@myson.com.tw available at: http://www.myson.com.tw/
30 * Myson fast ethernet PCI NIC driver
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/sockio.h>
36 #include <sys/malloc.h>
37 #include <sys/kernel.h>
38 #include <sys/socket.h>
39 #include <sys/queue.h>
40 #include <sys/types.h>
42 #include <sys/module.h>
44 #include <sys/mutex.h>
49 #include <net/if_arp.h>
50 #include <net/ethernet.h>
51 #include <net/if_media.h>
52 #include <net/if_dl.h>
55 #include <vm/vm.h> /* for vtophys */
56 #include <vm/pmap.h> /* for vtophys */
57 #include <machine/clock.h> /* for DELAY */
58 #include <machine/bus_memio.h>
59 #include <machine/bus_pio.h>
60 #include <machine/bus.h>
61 #include <machine/resource.h>
65 #include <pci/pcireg.h>
66 #include <pci/pcivar.h>
68 #include <dev/mii/mii.h>
69 #include <dev/mii/miivar.h>
71 #include "miibus_if.h"
74 * #define MY_USEIOSPACE
77 static int MY_USEIOSPACE = 1;
80 #define MY_RES SYS_RES_IOPORT
81 #define MY_RID MY_PCI_LOIO
83 #define MY_RES SYS_RES_MEMORY
84 #define MY_RID MY_PCI_LOMEM
88 #include <dev/my/if_myreg.h>
91 static const char rcsid[] =
92 "$Id: if_my.c,v 1.50 2001/12/03 04:15:33 <yen_cw@myson.com.tw> wpaul Exp $";
96 * Various supported device vendors/types and their names.
98 struct my_type *my_info_tmp;
99 static struct my_type my_devs[] = {
100 {MYSONVENDORID, MTD800ID, "Myson MTD80X Based Fast Ethernet Card"},
101 {MYSONVENDORID, MTD803ID, "Myson MTD80X Based Fast Ethernet Card"},
102 {MYSONVENDORID, MTD891ID, "Myson MTD89X Based Giga Ethernet Card"},
107 * Various supported PHY vendors/types and their names. Note that this driver
108 * will work with pretty much any MII-compliant PHY, so failure to positively
109 * identify the chip is not a fatal error.
111 static struct my_type my_phys[] = {
112 {MysonPHYID0, MysonPHYID0, "<MYSON MTD981>"},
113 {SeeqPHYID0, SeeqPHYID0, "<SEEQ 80225>"},
114 {AhdocPHYID0, AhdocPHYID0, "<AHDOC 101>"},
115 {MarvellPHYID0, MarvellPHYID0, "<MARVELL 88E1000>"},
116 {LevelOnePHYID0, LevelOnePHYID0, "<LevelOne LXT1000>"},
117 {0, 0, "<MII-compliant physical interface>"}
120 static int my_probe(device_t);
121 static int my_attach(device_t);
122 static int my_detach(device_t);
123 static int my_newbuf(struct my_softc *, struct my_chain_onefrag *);
124 static int my_encap(struct my_softc *, struct my_chain *, struct mbuf *);
125 static void my_rxeof(struct my_softc *);
126 static void my_txeof(struct my_softc *);
127 static void my_txeoc(struct my_softc *);
128 static void my_intr(void *);
129 static void my_start(struct ifnet *);
130 static int my_ioctl(struct ifnet *, u_long, caddr_t);
131 static void my_init(void *);
132 static void my_stop(struct my_softc *);
133 static void my_watchdog(struct ifnet *);
134 static void my_shutdown(device_t);
135 static int my_ifmedia_upd(struct ifnet *);
136 static void my_ifmedia_sts(struct ifnet *, struct ifmediareq *);
137 static u_int16_t my_phy_readreg(struct my_softc *, int);
138 static void my_phy_writereg(struct my_softc *, int, int);
139 static void my_autoneg_xmit(struct my_softc *);
140 static void my_autoneg_mii(struct my_softc *, int, int);
141 static void my_setmode_mii(struct my_softc *, int);
142 static void my_getmode_mii(struct my_softc *);
143 static void my_setcfg(struct my_softc *, int);
144 static u_int8_t my_calchash(caddr_t);
145 static void my_setmulti(struct my_softc *);
146 static void my_reset(struct my_softc *);
147 static int my_list_rx_init(struct my_softc *);
148 static int my_list_tx_init(struct my_softc *);
149 static long my_send_cmd_to_phy(struct my_softc *, int, int);
151 #define MY_SETBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x)
152 #define MY_CLRBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x)
154 static device_method_t my_methods[] = {
155 /* Device interface */
156 DEVMETHOD(device_probe, my_probe),
157 DEVMETHOD(device_attach, my_attach),
158 DEVMETHOD(device_detach, my_detach),
159 DEVMETHOD(device_shutdown, my_shutdown),
164 static driver_t my_driver = {
167 sizeof(struct my_softc)
170 static devclass_t my_devclass;
172 DRIVER_MODULE(if_my, pci, my_driver, my_devclass, 0, 0);
175 my_send_cmd_to_phy(struct my_softc * sc, int opcode, int regad)
183 /* enable MII output */
184 miir = CSR_READ_4(sc, MY_MANAGEMENT);
187 miir |= MY_MASK_MIIR_MII_WRITE + MY_MASK_MIIR_MII_MDO;
189 /* send 32 1's preamble */
190 for (i = 0; i < 32; i++) {
191 /* low MDC; MDO is already high (miir) */
192 miir &= ~MY_MASK_MIIR_MII_MDC;
193 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
196 miir |= MY_MASK_MIIR_MII_MDC;
197 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
200 /* calculate ST+OP+PHYAD+REGAD+TA */
201 data = opcode | (sc->my_phy_addr << 7) | (regad << 2);
206 /* low MDC, prepare MDO */
207 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO);
209 miir |= MY_MASK_MIIR_MII_MDO;
211 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
213 miir |= MY_MASK_MIIR_MII_MDC;
214 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
219 if (mask == 0x2 && opcode == MY_OP_READ)
220 miir &= ~MY_MASK_MIIR_MII_WRITE;
229 my_phy_readreg(struct my_softc * sc, int reg)
236 if (sc->my_info->my_did == MTD803ID)
237 data = CSR_READ_2(sc, MY_PHYBASE + reg * 2);
239 miir = my_send_cmd_to_phy(sc, MY_OP_READ, reg);
246 miir &= ~MY_MASK_MIIR_MII_MDC;
247 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
250 miir = CSR_READ_4(sc, MY_MANAGEMENT);
251 if (miir & MY_MASK_MIIR_MII_MDI)
254 /* high MDC, and wait */
255 miir |= MY_MASK_MIIR_MII_MDC;
256 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
264 miir &= ~MY_MASK_MIIR_MII_MDC;
265 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
269 return (u_int16_t) data;
274 my_phy_writereg(struct my_softc * sc, int reg, int data)
281 if (sc->my_info->my_did == MTD803ID)
282 CSR_WRITE_2(sc, MY_PHYBASE + reg * 2, data);
284 miir = my_send_cmd_to_phy(sc, MY_OP_WRITE, reg);
289 /* low MDC, prepare MDO */
290 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO);
292 miir |= MY_MASK_MIIR_MII_MDO;
293 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
297 miir |= MY_MASK_MIIR_MII_MDC;
298 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
306 miir &= ~MY_MASK_MIIR_MII_MDC;
307 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
314 my_calchash(caddr_t addr)
316 u_int32_t crc, carry;
320 /* Compute CRC for the address value. */
321 crc = 0xFFFFFFFF; /* initial value */
323 for (i = 0; i < 6; i++) {
325 for (j = 0; j < 8; j++) {
326 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
330 crc = (crc ^ 0x04c11db6) | carry;
335 * return the filter bit position Note: I arrived at the following
336 * nonsense through experimentation. It's not the usual way to
337 * generate the bit position but it's the only thing I could come up
340 return (~(crc >> 26) & 0x0000003F);
345 * Program the 64-bit multicast hash filter.
348 my_setmulti(struct my_softc * sc)
352 u_int32_t hashes[2] = {0, 0};
353 struct ifmultiaddr *ifma;
359 ifp = &sc->arpcom.ac_if;
361 rxfilt = CSR_READ_4(sc, MY_TCRRCR);
363 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
365 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt);
366 CSR_WRITE_4(sc, MY_MAR0, 0xFFFFFFFF);
367 CSR_WRITE_4(sc, MY_MAR1, 0xFFFFFFFF);
373 /* first, zot all the existing hash bits */
374 CSR_WRITE_4(sc, MY_MAR0, 0);
375 CSR_WRITE_4(sc, MY_MAR1, 0);
377 /* now program new ones */
378 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
379 if (ifma->ifma_addr->sa_family != AF_LINK)
381 h = my_calchash(LLADDR((struct sockaddr_dl *) ifma->ifma_addr));
383 hashes[0] |= (1 << h);
385 hashes[1] |= (1 << (h - 32));
393 CSR_WRITE_4(sc, MY_MAR0, hashes[0]);
394 CSR_WRITE_4(sc, MY_MAR1, hashes[1]);
395 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt);
401 * Initiate an autonegotiation session.
404 my_autoneg_xmit(struct my_softc * sc)
406 u_int16_t phy_sts = 0;
410 my_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET);
412 while (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_RESET);
414 phy_sts = my_phy_readreg(sc, PHY_BMCR);
415 phy_sts |= PHY_BMCR_AUTONEGENBL | PHY_BMCR_AUTONEGRSTR;
416 my_phy_writereg(sc, PHY_BMCR, phy_sts);
424 * Invoke autonegotiation on a PHY.
427 my_autoneg_mii(struct my_softc * sc, int flag, int verbose)
429 u_int16_t phy_sts = 0, media, advert, ability;
430 u_int16_t ability2 = 0;
437 ifp = &sc->arpcom.ac_if;
439 ifm->ifm_media = IFM_ETHER | IFM_AUTO;
441 #ifndef FORCE_AUTONEG_TFOUR
443 * First, see if autoneg is supported. If not, there's no point in
446 phy_sts = my_phy_readreg(sc, PHY_BMSR);
447 if (!(phy_sts & PHY_BMSR_CANAUTONEG)) {
449 printf("my%d: autonegotiation not supported\n",
451 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX;
457 case MY_FLAG_FORCEDELAY:
459 * XXX Never use this option anywhere but in the probe
460 * routine: making the kernel stop dead in its tracks for
461 * three whole seconds after we've gone multi-user is really
467 case MY_FLAG_SCHEDDELAY:
469 * Wait for the transmitter to go idle before starting an
470 * autoneg session, otherwise my_start() may clobber our
471 * timeout, and we don't want to allow transmission during an
472 * autoneg session since that can screw it up.
474 if (sc->my_cdata.my_tx_head != NULL) {
475 sc->my_want_auto = 1;
482 sc->my_want_auto = 0;
485 case MY_FLAG_DELAYTIMEO:
490 printf("my%d: invalid autoneg flag: %d\n", sc->my_unit, flag);
495 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) {
497 printf("my%d: autoneg complete, ", sc->my_unit);
498 phy_sts = my_phy_readreg(sc, PHY_BMSR);
501 printf("my%d: autoneg not complete, ", sc->my_unit);
504 media = my_phy_readreg(sc, PHY_BMCR);
506 /* Link is good. Report modes and set duplex mode. */
507 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) {
509 printf("my%d: link status good. ", sc->my_unit);
510 advert = my_phy_readreg(sc, PHY_ANAR);
511 ability = my_phy_readreg(sc, PHY_LPAR);
512 if ((sc->my_pinfo->my_vid == MarvellPHYID0) ||
513 (sc->my_pinfo->my_vid == LevelOnePHYID0)) {
514 ability2 = my_phy_readreg(sc, PHY_1000SR);
515 if (ability2 & PHY_1000SR_1000BTXFULL) {
519 * this version did not support 1000M,
521 * IFM_ETHER|IFM_1000_T|IFM_FDX;
524 IFM_ETHER | IFM_100_TX | IFM_FDX;
525 media &= ~PHY_BMCR_SPEEDSEL;
526 media |= PHY_BMCR_1000;
527 media |= PHY_BMCR_DUPLEX;
528 printf("(full-duplex, 1000Mbps)\n");
529 } else if (ability2 & PHY_1000SR_1000BTXHALF) {
533 * this version did not support 1000M,
534 * ifm->ifm_media = IFM_ETHER|IFM_1000_T;
536 ifm->ifm_media = IFM_ETHER | IFM_100_TX;
537 media &= ~PHY_BMCR_SPEEDSEL;
538 media &= ~PHY_BMCR_DUPLEX;
539 media |= PHY_BMCR_1000;
540 printf("(half-duplex, 1000Mbps)\n");
543 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) {
544 ifm->ifm_media = IFM_ETHER | IFM_100_T4;
545 media |= PHY_BMCR_SPEEDSEL;
546 media &= ~PHY_BMCR_DUPLEX;
547 printf("(100baseT4)\n");
548 } else if (advert & PHY_ANAR_100BTXFULL &&
549 ability & PHY_ANAR_100BTXFULL) {
550 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX;
551 media |= PHY_BMCR_SPEEDSEL;
552 media |= PHY_BMCR_DUPLEX;
553 printf("(full-duplex, 100Mbps)\n");
554 } else if (advert & PHY_ANAR_100BTXHALF &&
555 ability & PHY_ANAR_100BTXHALF) {
556 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX;
557 media |= PHY_BMCR_SPEEDSEL;
558 media &= ~PHY_BMCR_DUPLEX;
559 printf("(half-duplex, 100Mbps)\n");
560 } else if (advert & PHY_ANAR_10BTFULL &&
561 ability & PHY_ANAR_10BTFULL) {
562 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX;
563 media &= ~PHY_BMCR_SPEEDSEL;
564 media |= PHY_BMCR_DUPLEX;
565 printf("(full-duplex, 10Mbps)\n");
567 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX;
568 media &= ~PHY_BMCR_SPEEDSEL;
569 media &= ~PHY_BMCR_DUPLEX;
570 printf("(half-duplex, 10Mbps)\n");
572 media &= ~PHY_BMCR_AUTONEGENBL;
574 /* Set ASIC's duplex mode to match the PHY. */
575 my_phy_writereg(sc, PHY_BMCR, media);
576 my_setcfg(sc, media);
579 printf("my%d: no carrier\n", sc->my_unit);
583 if (sc->my_tx_pend) {
593 * To get PHY ability.
596 my_getmode_mii(struct my_softc * sc)
602 ifp = &sc->arpcom.ac_if;
603 bmsr = my_phy_readreg(sc, PHY_BMSR);
605 printf("my%d: PHY status word: %x\n", sc->my_unit, bmsr);
608 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX;
610 if (bmsr & PHY_BMSR_10BTHALF) {
612 printf("my%d: 10Mbps half-duplex mode supported\n",
614 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_HDX,
616 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T, 0, NULL);
618 if (bmsr & PHY_BMSR_10BTFULL) {
620 printf("my%d: 10Mbps full-duplex mode supported\n",
623 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX,
625 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX;
627 if (bmsr & PHY_BMSR_100BTXHALF) {
629 printf("my%d: 100Mbps half-duplex mode supported\n",
631 ifp->if_baudrate = 100000000;
632 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL);
633 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_HDX,
635 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX;
637 if (bmsr & PHY_BMSR_100BTXFULL) {
639 printf("my%d: 100Mbps full-duplex mode supported\n",
641 ifp->if_baudrate = 100000000;
642 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX,
644 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX;
646 /* Some also support 100BaseT4. */
647 if (bmsr & PHY_BMSR_100BT4) {
649 printf("my%d: 100baseT4 mode supported\n", sc->my_unit);
650 ifp->if_baudrate = 100000000;
651 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_T4, 0, NULL);
652 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_T4;
653 #ifdef FORCE_AUTONEG_TFOUR
655 printf("my%d: forcing on autoneg support for BT4\n",
657 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0 NULL):
658 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO;
661 #if 0 /* this version did not support 1000M, */
662 if (sc->my_pinfo->my_vid == MarvellPHYID0) {
664 printf("my%d: 1000Mbps half-duplex mode supported\n",
667 ifp->if_baudrate = 1000000000;
668 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T, 0, NULL);
669 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_HDX,
672 printf("my%d: 1000Mbps full-duplex mode supported\n",
674 ifp->if_baudrate = 1000000000;
675 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_FDX,
677 sc->ifmedia.ifm_media = IFM_ETHER | IFM_1000_T | IFM_FDX;
680 if (bmsr & PHY_BMSR_CANAUTONEG) {
682 printf("my%d: autoneg supported\n", sc->my_unit);
683 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
684 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO;
691 * Set speed and duplex mode.
694 my_setmode_mii(struct my_softc * sc, int media)
700 ifp = &sc->arpcom.ac_if;
702 * If an autoneg session is in progress, stop it.
704 if (sc->my_autoneg) {
705 printf("my%d: canceling autoneg session\n", sc->my_unit);
706 ifp->if_timer = sc->my_autoneg = sc->my_want_auto = 0;
707 bmcr = my_phy_readreg(sc, PHY_BMCR);
708 bmcr &= ~PHY_BMCR_AUTONEGENBL;
709 my_phy_writereg(sc, PHY_BMCR, bmcr);
711 printf("my%d: selecting MII, ", sc->my_unit);
712 bmcr = my_phy_readreg(sc, PHY_BMCR);
713 bmcr &= ~(PHY_BMCR_AUTONEGENBL | PHY_BMCR_SPEEDSEL | PHY_BMCR_1000 |
714 PHY_BMCR_DUPLEX | PHY_BMCR_LOOPBK);
716 #if 0 /* this version did not support 1000M, */
717 if (IFM_SUBTYPE(media) == IFM_1000_T) {
718 printf("1000Mbps/T4, half-duplex\n");
719 bmcr &= ~PHY_BMCR_SPEEDSEL;
720 bmcr &= ~PHY_BMCR_DUPLEX;
721 bmcr |= PHY_BMCR_1000;
724 if (IFM_SUBTYPE(media) == IFM_100_T4) {
725 printf("100Mbps/T4, half-duplex\n");
726 bmcr |= PHY_BMCR_SPEEDSEL;
727 bmcr &= ~PHY_BMCR_DUPLEX;
729 if (IFM_SUBTYPE(media) == IFM_100_TX) {
731 bmcr |= PHY_BMCR_SPEEDSEL;
733 if (IFM_SUBTYPE(media) == IFM_10_T) {
735 bmcr &= ~PHY_BMCR_SPEEDSEL;
737 if ((media & IFM_GMASK) == IFM_FDX) {
738 printf("full duplex\n");
739 bmcr |= PHY_BMCR_DUPLEX;
741 printf("half duplex\n");
742 bmcr &= ~PHY_BMCR_DUPLEX;
744 my_phy_writereg(sc, PHY_BMCR, bmcr);
751 * The Myson manual states that in order to fiddle with the 'full-duplex' and
752 * '100Mbps' bits in the netconfig register, we first have to put the
753 * transmit and/or receive logic in the idle state.
756 my_setcfg(struct my_softc * sc, int bmcr)
761 if (CSR_READ_4(sc, MY_TCRRCR) & (MY_TE | MY_RE)) {
763 MY_CLRBIT(sc, MY_TCRRCR, (MY_TE | MY_RE));
764 for (i = 0; i < MY_TIMEOUT; i++) {
766 if (!(CSR_READ_4(sc, MY_TCRRCR) &
767 (MY_TXRUN | MY_RXRUN)))
771 printf("my%d: failed to force tx and rx to idle \n",
774 MY_CLRBIT(sc, MY_TCRRCR, MY_PS1000);
775 MY_CLRBIT(sc, MY_TCRRCR, MY_PS10);
776 if (bmcr & PHY_BMCR_1000)
777 MY_SETBIT(sc, MY_TCRRCR, MY_PS1000);
778 else if (!(bmcr & PHY_BMCR_SPEEDSEL))
779 MY_SETBIT(sc, MY_TCRRCR, MY_PS10);
780 if (bmcr & PHY_BMCR_DUPLEX)
781 MY_SETBIT(sc, MY_TCRRCR, MY_FD);
783 MY_CLRBIT(sc, MY_TCRRCR, MY_FD);
785 MY_SETBIT(sc, MY_TCRRCR, MY_TE | MY_RE);
791 my_reset(struct my_softc * sc)
796 MY_SETBIT(sc, MY_BCR, MY_SWR);
797 for (i = 0; i < MY_TIMEOUT; i++) {
799 if (!(CSR_READ_4(sc, MY_BCR) & MY_SWR))
803 printf("m0x%d: reset never completed!\n", sc->my_unit);
805 /* Wait a little while for the chip to get its brains in order. */
812 * Probe for a Myson chip. Check the PCI vendor and device IDs against our
813 * list and return a device name if we find a match.
816 my_probe(device_t dev)
821 while (t->my_name != NULL) {
822 if ((pci_get_vendor(dev) == t->my_vid) &&
823 (pci_get_device(dev) == t->my_did)) {
824 device_set_desc(dev, t->my_name);
834 * Attach the interface. Allocate softc structures, do ifmedia setup and
835 * ethernet/BPF attach.
838 my_attach(device_t dev)
841 u_char eaddr[ETHER_ADDR_LEN];
842 u_int32_t command, iobase;
845 int media = IFM_ETHER | IFM_100_TX | IFM_FDX;
849 u_int16_t phy_vid, phy_did, phy_sts = 0;
850 int rid, unit, error = 0;
853 sc = device_get_softc(dev);
854 unit = device_get_unit(dev);
856 printf("my%d: no memory for softc struct!\n", unit);
861 bzero(sc, sizeof(struct my_softc));
862 mtx_init(&sc->my_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
863 MTX_DEF | MTX_RECURSE);
867 * Map control/status registers.
870 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4);
871 command |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
872 pci_write_config(dev, PCI_COMMAND_STATUS_REG, command & 0x000000ff, 4);
873 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4);
875 command = pci_read_config(dev, PCIR_COMMAND, 4);
876 command |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
877 pci_write_config(dev, PCIR_COMMAND, command & 0x000000ff, 4);
878 command = pci_read_config(dev, PCIR_COMMAND, 4);
880 if (my_info_tmp->my_did == MTD800ID) {
881 iobase = pci_read_config(dev, MY_PCI_LOIO, 4);
886 if (!(command & PCIM_CMD_PORTEN)) {
887 printf("my%d: failed to enable I/O ports!\n", unit);
893 if (!pci_map_port(config_id, MY_PCI_LOIO, (u_int16_t *) & (sc->my_bhandle))) {
894 printf("my%d: couldn't map ports\n", unit);
899 sc->my_btag = I386_BUS_SPACE_IO;
902 if (!(command & PCIM_CMD_MEMEN)) {
903 printf("my%d: failed to enable memory mapping!\n",
909 if (!pci_map_mem(config_id, MY_PCI_LOMEM, &vbase, &pbase)) {
910 printf ("my%d: couldn't map memory\n", unit);
914 sc->my_btag = I386_BUS_SPACE_MEM;
915 sc->my_bhandle = vbase;
920 sc->my_res = bus_alloc_resource(dev, MY_RES, &rid,
921 0, ~0, 1, RF_ACTIVE);
923 if (sc->my_res == NULL) {
924 printf("my%d: couldn't map ports/memory\n", unit);
928 sc->my_btag = rman_get_bustag(sc->my_res);
929 sc->my_bhandle = rman_get_bushandle(sc->my_res);
932 sc->my_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
933 RF_SHAREABLE | RF_ACTIVE);
935 if (sc->my_irq == NULL) {
936 printf("my%d: couldn't map interrupt\n", unit);
937 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res);
941 error = bus_setup_intr(dev, sc->my_irq, INTR_TYPE_NET,
942 my_intr, sc, &sc->my_intrhand);
945 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq);
946 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res);
947 printf("my%d: couldn't set up irq\n", unit);
950 callout_handle_init(&sc->my_stat_ch);
952 sc->my_info = my_info_tmp;
954 /* Reset the adapter. */
958 * Get station address
960 for (i = 0; i < ETHER_ADDR_LEN; ++i)
961 eaddr[i] = CSR_READ_1(sc, MY_PAR0 + i);
964 * A Myson chip was detected. Inform the world.
966 printf("my%d: Ethernet address: %6D\n", unit, eaddr, ":");
969 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
971 sc->my_ldata_ptr = malloc(sizeof(struct my_list_data) + 8,
973 if (sc->my_ldata_ptr == NULL) {
975 printf("my%d: no memory for list buffers!\n", unit);
979 sc->my_ldata = (struct my_list_data *) sc->my_ldata_ptr;
980 round = (uintptr_t)sc->my_ldata_ptr & 0xF;
981 roundptr = sc->my_ldata_ptr;
982 for (i = 0; i < 8; i++) {
989 sc->my_ldata = (struct my_list_data *) roundptr;
990 bzero(sc->my_ldata, sizeof(struct my_list_data));
992 ifp = &sc->arpcom.ac_if;
996 ifp->if_mtu = ETHERMTU;
997 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
998 ifp->if_ioctl = my_ioctl;
999 ifp->if_output = ether_output;
1000 ifp->if_start = my_start;
1001 ifp->if_watchdog = my_watchdog;
1002 ifp->if_init = my_init;
1003 ifp->if_baudrate = 10000000;
1004 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN;
1006 if (sc->my_info->my_did == MTD803ID)
1007 sc->my_pinfo = my_phys;
1010 printf("my%d: probing for a PHY\n", sc->my_unit);
1011 for (i = MY_PHYADDR_MIN; i < MY_PHYADDR_MAX + 1; i++) {
1013 printf("my%d: checking address: %d\n",
1015 sc->my_phy_addr = i;
1016 phy_sts = my_phy_readreg(sc, PHY_BMSR);
1017 if ((phy_sts != 0) && (phy_sts != 0xffff))
1023 phy_vid = my_phy_readreg(sc, PHY_VENID);
1024 phy_did = my_phy_readreg(sc, PHY_DEVID);
1026 printf("my%d: found PHY at address %d, ",
1027 sc->my_unit, sc->my_phy_addr);
1028 printf("vendor id: %x device id: %x\n",
1033 if (phy_vid == p->my_vid) {
1039 if (sc->my_pinfo == NULL)
1040 sc->my_pinfo = &my_phys[PHY_UNKNOWN];
1042 printf("my%d: PHY type: %s\n",
1043 sc->my_unit, sc->my_pinfo->my_name);
1045 printf("my%d: MII without any phy!\n", sc->my_unit);
1051 /* Do ifmedia setup. */
1052 ifmedia_init(&sc->ifmedia, 0, my_ifmedia_upd, my_ifmedia_sts);
1054 my_autoneg_mii(sc, MY_FLAG_FORCEDELAY, 1);
1055 media = sc->ifmedia.ifm_media;
1057 ifmedia_set(&sc->ifmedia, media);
1059 ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
1062 at_shutdown(my_shutdown, sc, SHUTDOWN_POST_SYNC);
1063 shutdownhook_establish(my_shutdown, sc);
1071 mtx_destroy(&sc->my_mtx);
1077 my_detach(device_t dev)
1079 struct my_softc *sc;
1084 sc = device_get_softc(dev);
1086 ifp = &sc->arpcom.ac_if;
1087 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
1091 bus_generic_detach(dev);
1092 device_delete_child(dev, sc->rl_miibus);
1095 bus_teardown_intr(dev, sc->my_irq, sc->my_intrhand);
1096 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq);
1097 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res);
1099 contigfree(sc->my_cdata.my_rx_buf, MY_RXBUFLEN + 32, M_DEVBUF);
1104 mtx_destroy(&sc->my_mtx);
1110 * Initialize the transmit descriptors.
1113 my_list_tx_init(struct my_softc * sc)
1115 struct my_chain_data *cd;
1116 struct my_list_data *ld;
1122 for (i = 0; i < MY_TX_LIST_CNT; i++) {
1123 cd->my_tx_chain[i].my_ptr = &ld->my_tx_list[i];
1124 if (i == (MY_TX_LIST_CNT - 1))
1125 cd->my_tx_chain[i].my_nextdesc = &cd->my_tx_chain[0];
1127 cd->my_tx_chain[i].my_nextdesc =
1128 &cd->my_tx_chain[i + 1];
1130 cd->my_tx_free = &cd->my_tx_chain[0];
1131 cd->my_tx_tail = cd->my_tx_head = NULL;
1137 * Initialize the RX descriptors and allocate mbufs for them. Note that we
1138 * arrange the descriptors in a closed ring, so that the last descriptor
1139 * points back to the first.
1142 my_list_rx_init(struct my_softc * sc)
1144 struct my_chain_data *cd;
1145 struct my_list_data *ld;
1151 for (i = 0; i < MY_RX_LIST_CNT; i++) {
1152 cd->my_rx_chain[i].my_ptr =
1153 (struct my_desc *) & ld->my_rx_list[i];
1154 if (my_newbuf(sc, &cd->my_rx_chain[i]) == ENOBUFS) {
1158 if (i == (MY_RX_LIST_CNT - 1)) {
1159 cd->my_rx_chain[i].my_nextdesc = &cd->my_rx_chain[0];
1160 ld->my_rx_list[i].my_next = vtophys(&ld->my_rx_list[0]);
1162 cd->my_rx_chain[i].my_nextdesc =
1163 &cd->my_rx_chain[i + 1];
1164 ld->my_rx_list[i].my_next =
1165 vtophys(&ld->my_rx_list[i + 1]);
1168 cd->my_rx_head = &cd->my_rx_chain[0];
1174 * Initialize an RX descriptor and attach an MBUF cluster.
1177 my_newbuf(struct my_softc * sc, struct my_chain_onefrag * c)
1179 struct mbuf *m_new = NULL;
1182 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1183 if (m_new == NULL) {
1184 printf("my%d: no memory for rx list -- packet dropped!\n",
1189 MCLGET(m_new, M_DONTWAIT);
1190 if (!(m_new->m_flags & M_EXT)) {
1191 printf("my%d: no memory for rx list -- packet dropped!\n",
1198 c->my_ptr->my_data = vtophys(mtod(m_new, caddr_t));
1199 c->my_ptr->my_ctl = (MCLBYTES - 1) << MY_RBSShift;
1200 c->my_ptr->my_status = MY_OWNByNIC;
1206 * A frame has been uploaded: pass the resulting mbuf chain up to the higher
1210 my_rxeof(struct my_softc * sc)
1212 struct ether_header *eh;
1215 struct my_chain_onefrag *cur_rx;
1220 ifp = &sc->arpcom.ac_if;
1221 while (!((rxstat = sc->my_cdata.my_rx_head->my_ptr->my_status)
1223 cur_rx = sc->my_cdata.my_rx_head;
1224 sc->my_cdata.my_rx_head = cur_rx->my_nextdesc;
1226 if (rxstat & MY_ES) { /* error summary: give up this rx pkt */
1228 cur_rx->my_ptr->my_status = MY_OWNByNIC;
1231 /* No errors; receive the packet. */
1232 total_len = (rxstat & MY_FLNGMASK) >> MY_FLNGShift;
1233 total_len -= ETHER_CRC_LEN;
1235 if (total_len < MINCLSIZE) {
1236 m = m_devget(mtod(cur_rx->my_mbuf, char *),
1237 total_len, 0, ifp, NULL);
1238 cur_rx->my_ptr->my_status = MY_OWNByNIC;
1244 m = cur_rx->my_mbuf;
1246 * Try to conjure up a new mbuf cluster. If that
1247 * fails, it means we have an out of memory condition
1248 * and should leave the buffer in place and continue.
1249 * This will result in a lost packet, but there's
1250 * little else we can do in this situation.
1252 if (my_newbuf(sc, cur_rx) == ENOBUFS) {
1254 cur_rx->my_ptr->my_status = MY_OWNByNIC;
1257 m->m_pkthdr.rcvif = ifp;
1258 m->m_pkthdr.len = m->m_len = total_len;
1261 eh = mtod(m, struct ether_header *);
1264 * Handle BPF listeners. Let the BPF user see the packet, but
1265 * don't pass it up to the ether_input() layer unless it's a
1266 * broadcast packet, multicast packet, matches our ethernet
1267 * address or the interface is in promiscuous mode.
1271 if (ifp->if_flags & IFF_PROMISC &&
1272 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr,
1274 (eh->ether_dhost[0] & 1) == 0)) {
1280 /* Remove header from mbuf and pass it on. */
1281 m_adj(m, sizeof(struct ether_header));
1282 ether_input(ifp, eh, m);
1290 * A frame was downloaded to the chip. It's safe for us to clean up the list
1294 my_txeof(struct my_softc * sc)
1296 struct my_chain *cur_tx;
1300 ifp = &sc->arpcom.ac_if;
1301 /* Clear the timeout timer. */
1303 if (sc->my_cdata.my_tx_head == NULL) {
1308 * Go through our tx list and free mbufs for those frames that have
1311 while (sc->my_cdata.my_tx_head->my_mbuf != NULL) {
1314 cur_tx = sc->my_cdata.my_tx_head;
1315 txstat = MY_TXSTATUS(cur_tx);
1316 if ((txstat & MY_OWNByNIC) || txstat == MY_UNSENT)
1318 if (!(CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced)) {
1319 if (txstat & MY_TXERR) {
1321 if (txstat & MY_EC) /* excessive collision */
1322 ifp->if_collisions++;
1323 if (txstat & MY_LC) /* late collision */
1324 ifp->if_collisions++;
1326 ifp->if_collisions += (txstat & MY_NCRMASK) >>
1330 m_freem(cur_tx->my_mbuf);
1331 cur_tx->my_mbuf = NULL;
1332 if (sc->my_cdata.my_tx_head == sc->my_cdata.my_tx_tail) {
1333 sc->my_cdata.my_tx_head = NULL;
1334 sc->my_cdata.my_tx_tail = NULL;
1337 sc->my_cdata.my_tx_head = cur_tx->my_nextdesc;
1339 if (CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced) {
1340 ifp->if_collisions += (CSR_READ_4(sc, MY_TSR) & MY_NCRMask);
1347 * TX 'end of channel' interrupt handler.
1350 my_txeoc(struct my_softc * sc)
1355 ifp = &sc->arpcom.ac_if;
1357 if (sc->my_cdata.my_tx_head == NULL) {
1358 ifp->if_flags &= ~IFF_OACTIVE;
1359 sc->my_cdata.my_tx_tail = NULL;
1360 if (sc->my_want_auto)
1361 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1);
1363 if (MY_TXOWN(sc->my_cdata.my_tx_head) == MY_UNSENT) {
1364 MY_TXOWN(sc->my_cdata.my_tx_head) = MY_OWNByNIC;
1366 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF);
1376 struct my_softc *sc;
1382 ifp = &sc->arpcom.ac_if;
1383 if (!(ifp->if_flags & IFF_UP)) {
1387 /* Disable interrupts. */
1388 CSR_WRITE_4(sc, MY_IMR, 0x00000000);
1391 status = CSR_READ_4(sc, MY_ISR);
1394 CSR_WRITE_4(sc, MY_ISR, status);
1398 if (status & MY_RI) /* receive interrupt */
1401 if ((status & MY_RBU) || (status & MY_RxErr)) {
1402 /* rx buffer unavailable or rx error */
1410 if (status & MY_TI) /* tx interrupt */
1412 if (status & MY_ETI) /* tx early interrupt */
1414 if (status & MY_TBU) /* tx buffer unavailable */
1417 #if 0 /* 90/1/18 delete */
1418 if (status & MY_FBE) {
1426 /* Re-enable interrupts. */
1427 CSR_WRITE_4(sc, MY_IMR, MY_INTRS);
1428 if (ifp->if_snd.ifq_head != NULL)
1435 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1436 * pointers to the fragment pointers.
1439 my_encap(struct my_softc * sc, struct my_chain * c, struct mbuf * m_head)
1441 struct my_desc *f = NULL;
1443 struct mbuf *m, *m_new = NULL;
1446 /* calculate the total tx pkt length */
1448 for (m = m_head; m != NULL; m = m->m_next)
1449 total_len += m->m_len;
1451 * Start packing the mbufs in this chain into the fragment pointers.
1452 * Stop when we run out of fragments or hit the end of the mbuf
1456 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1457 if (m_new == NULL) {
1458 printf("my%d: no memory for tx list", sc->my_unit);
1462 if (m_head->m_pkthdr.len > MHLEN) {
1463 MCLGET(m_new, M_DONTWAIT);
1464 if (!(m_new->m_flags & M_EXT)) {
1466 printf("my%d: no memory for tx list", sc->my_unit);
1471 m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t));
1472 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1475 f = &c->my_ptr->my_frag[0];
1477 f->my_data = vtophys(mtod(m_new, caddr_t));
1478 total_len = m_new->m_len;
1479 f->my_ctl = MY_TXFD | MY_TXLD | MY_CRCEnable | MY_PADEnable;
1480 f->my_ctl |= total_len << MY_PKTShift; /* pkt size */
1481 f->my_ctl |= total_len; /* buffer size */
1482 /* 89/12/29 add, for mtd891 *//* [ 89? ] */
1483 if (sc->my_info->my_did == MTD891ID)
1484 f->my_ctl |= MY_ETIControl | MY_RetryTxLC;
1485 c->my_mbuf = m_head;
1487 MY_TXNEXT(c) = vtophys(&c->my_nextdesc->my_ptr->my_frag[0]);
1493 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1494 * to the mbuf data regions directly in the transmit lists. We also save a
1495 * copy of the pointers since the transmit list fragment pointers are
1496 * physical addresses.
1499 my_start(struct ifnet * ifp)
1501 struct my_softc *sc;
1502 struct mbuf *m_head = NULL;
1503 struct my_chain *cur_tx = NULL, *start_tx;
1507 if (sc->my_autoneg) {
1513 * Check for an available queue slot. If there are none, punt.
1515 if (sc->my_cdata.my_tx_free->my_mbuf != NULL) {
1516 ifp->if_flags |= IFF_OACTIVE;
1520 start_tx = sc->my_cdata.my_tx_free;
1521 while (sc->my_cdata.my_tx_free->my_mbuf == NULL) {
1522 IF_DEQUEUE(&ifp->if_snd, m_head);
1526 /* Pick a descriptor off the free list. */
1527 cur_tx = sc->my_cdata.my_tx_free;
1528 sc->my_cdata.my_tx_free = cur_tx->my_nextdesc;
1530 /* Pack the data into the descriptor. */
1531 my_encap(sc, cur_tx, m_head);
1533 if (cur_tx != start_tx)
1534 MY_TXOWN(cur_tx) = MY_OWNByNIC;
1537 * If there's a BPF listener, bounce a copy of this frame to
1541 bpf_mtap(ifp, cur_tx->my_mbuf);
1545 * If there are no packets queued, bail.
1547 if (cur_tx == NULL) {
1552 * Place the request for the upload interrupt in the last descriptor
1553 * in the chain. This way, if we're chaining several packets at once,
1554 * we'll only get an interupt once for the whole chain rather than
1555 * once for each packet.
1557 MY_TXCTL(cur_tx) |= MY_TXIC;
1558 cur_tx->my_ptr->my_frag[0].my_ctl |= MY_TXIC;
1559 sc->my_cdata.my_tx_tail = cur_tx;
1560 if (sc->my_cdata.my_tx_head == NULL)
1561 sc->my_cdata.my_tx_head = start_tx;
1562 MY_TXOWN(start_tx) = MY_OWNByNIC;
1563 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF); /* tx polling demand */
1566 * Set a timeout in case the chip goes out to lunch.
1576 struct my_softc *sc = xsc;
1577 struct ifnet *ifp = &sc->arpcom.ac_if;
1579 u_int16_t phy_bmcr = 0;
1582 if (sc->my_autoneg) {
1587 if (sc->my_pinfo != NULL)
1588 phy_bmcr = my_phy_readreg(sc, PHY_BMCR);
1590 * Cancel pending I/O and free all RX/TX buffers.
1596 * Set cache alignment and burst length.
1598 #if 0 /* 89/9/1 modify, */
1599 CSR_WRITE_4(sc, MY_BCR, MY_RPBLE512);
1600 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF);
1602 CSR_WRITE_4(sc, MY_BCR, MY_PBL8);
1603 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF | MY_RBLEN | MY_RPBLE512);
1605 * 89/12/29 add, for mtd891,
1607 if (sc->my_info->my_did == MTD891ID) {
1608 MY_SETBIT(sc, MY_BCR, MY_PROG);
1609 MY_SETBIT(sc, MY_TCRRCR, MY_Enhanced);
1611 my_setcfg(sc, phy_bmcr);
1612 /* Init circular RX list. */
1613 if (my_list_rx_init(sc) == ENOBUFS) {
1614 printf("my%d: init failed: no memory for rx buffers\n",
1621 /* Init TX descriptors. */
1622 my_list_tx_init(sc);
1624 /* If we want promiscuous mode, set the allframes bit. */
1625 if (ifp->if_flags & IFF_PROMISC)
1626 MY_SETBIT(sc, MY_TCRRCR, MY_PROM);
1628 MY_CLRBIT(sc, MY_TCRRCR, MY_PROM);
1631 * Set capture broadcast bit to capture broadcast frames.
1633 if (ifp->if_flags & IFF_BROADCAST)
1634 MY_SETBIT(sc, MY_TCRRCR, MY_AB);
1636 MY_CLRBIT(sc, MY_TCRRCR, MY_AB);
1639 * Program the multicast filter, if necessary.
1644 * Load the address of the RX list.
1646 MY_CLRBIT(sc, MY_TCRRCR, MY_RE);
1647 CSR_WRITE_4(sc, MY_RXLBA, vtophys(&sc->my_ldata->my_rx_list[0]));
1650 * Enable interrupts.
1652 CSR_WRITE_4(sc, MY_IMR, MY_INTRS);
1653 CSR_WRITE_4(sc, MY_ISR, 0xFFFFFFFF);
1655 /* Enable receiver and transmitter. */
1656 MY_SETBIT(sc, MY_TCRRCR, MY_RE);
1657 MY_CLRBIT(sc, MY_TCRRCR, MY_TE);
1658 CSR_WRITE_4(sc, MY_TXLBA, vtophys(&sc->my_ldata->my_tx_list[0]));
1659 MY_SETBIT(sc, MY_TCRRCR, MY_TE);
1661 /* Restore state of BMCR */
1662 if (sc->my_pinfo != NULL)
1663 my_phy_writereg(sc, PHY_BMCR, phy_bmcr);
1664 ifp->if_flags |= IFF_RUNNING;
1665 ifp->if_flags &= ~IFF_OACTIVE;
1672 * Set media options.
1676 my_ifmedia_upd(struct ifnet * ifp)
1678 struct my_softc *sc;
1679 struct ifmedia *ifm;
1684 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) {
1688 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO)
1689 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1);
1691 my_setmode_mii(sc, ifm->ifm_media);
1697 * Report current media status.
1701 my_ifmedia_sts(struct ifnet * ifp, struct ifmediareq * ifmr)
1703 struct my_softc *sc;
1704 u_int16_t advert = 0, ability = 0;
1708 ifmr->ifm_active = IFM_ETHER;
1709 if (!(my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) {
1710 #if 0 /* this version did not support 1000M, */
1711 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_1000)
1712 ifmr->ifm_active = IFM_ETHER | IFM_1000TX;
1714 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL)
1715 ifmr->ifm_active = IFM_ETHER | IFM_100_TX;
1717 ifmr->ifm_active = IFM_ETHER | IFM_10_T;
1718 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX)
1719 ifmr->ifm_active |= IFM_FDX;
1721 ifmr->ifm_active |= IFM_HDX;
1726 ability = my_phy_readreg(sc, PHY_LPAR);
1727 advert = my_phy_readreg(sc, PHY_ANAR);
1729 #if 0 /* this version did not support 1000M, */
1730 if (sc->my_pinfo->my_vid = MarvellPHYID0) {
1731 ability2 = my_phy_readreg(sc, PHY_1000SR);
1732 if (ability2 & PHY_1000SR_1000BTXFULL) {
1735 ifmr->ifm_active = IFM_ETHER|IFM_1000_T|IFM_FDX;
1736 } else if (ability & PHY_1000SR_1000BTXHALF) {
1739 ifmr->ifm_active = IFM_ETHER|IFM_1000_T|IFM_HDX;
1743 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4)
1744 ifmr->ifm_active = IFM_ETHER | IFM_100_T4;
1745 else if (advert & PHY_ANAR_100BTXFULL && ability & PHY_ANAR_100BTXFULL)
1746 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1747 else if (advert & PHY_ANAR_100BTXHALF && ability & PHY_ANAR_100BTXHALF)
1748 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_HDX;
1749 else if (advert & PHY_ANAR_10BTFULL && ability & PHY_ANAR_10BTFULL)
1750 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_FDX;
1751 else if (advert & PHY_ANAR_10BTHALF && ability & PHY_ANAR_10BTHALF)
1752 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_HDX;
1758 my_ioctl(struct ifnet * ifp, u_long command, caddr_t data)
1760 struct my_softc *sc = ifp->if_softc;
1761 struct ifreq *ifr = (struct ifreq *) data;
1770 error = ether_ioctl(ifp, command, data);
1773 if (ifp->if_flags & IFF_UP)
1775 else if (ifp->if_flags & IFF_RUNNING)
1786 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
1798 my_watchdog(struct ifnet * ifp)
1800 struct my_softc *sc;
1804 if (sc->my_autoneg) {
1805 my_autoneg_mii(sc, MY_FLAG_DELAYTIMEO, 1);
1810 printf("my%d: watchdog timeout\n", sc->my_unit);
1811 if (!(my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT))
1812 printf("my%d: no carrier - transceiver cable problem?\n",
1817 if (ifp->if_snd.ifq_head != NULL)
1825 * Stop the adapter and free any mbufs allocated to the RX and TX lists.
1828 my_stop(struct my_softc * sc)
1834 ifp = &sc->arpcom.ac_if;
1837 MY_CLRBIT(sc, MY_TCRRCR, (MY_RE | MY_TE));
1838 CSR_WRITE_4(sc, MY_IMR, 0x00000000);
1839 CSR_WRITE_4(sc, MY_TXLBA, 0x00000000);
1840 CSR_WRITE_4(sc, MY_RXLBA, 0x00000000);
1843 * Free data in the RX lists.
1845 for (i = 0; i < MY_RX_LIST_CNT; i++) {
1846 if (sc->my_cdata.my_rx_chain[i].my_mbuf != NULL) {
1847 m_freem(sc->my_cdata.my_rx_chain[i].my_mbuf);
1848 sc->my_cdata.my_rx_chain[i].my_mbuf = NULL;
1851 bzero((char *)&sc->my_ldata->my_rx_list,
1852 sizeof(sc->my_ldata->my_rx_list));
1854 * Free the TX list buffers.
1856 for (i = 0; i < MY_TX_LIST_CNT; i++) {
1857 if (sc->my_cdata.my_tx_chain[i].my_mbuf != NULL) {
1858 m_freem(sc->my_cdata.my_tx_chain[i].my_mbuf);
1859 sc->my_cdata.my_tx_chain[i].my_mbuf = NULL;
1862 bzero((char *)&sc->my_ldata->my_tx_list,
1863 sizeof(sc->my_ldata->my_tx_list));
1864 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1870 * Stop all chip I/O so that the kernel's probe routines don't get confused
1871 * by errant DMAs when rebooting.
1874 my_shutdown(device_t dev)
1876 struct my_softc *sc;
1878 sc = device_get_softc(dev);