2 * Written by: yen_cw@myson.com.tw
3 * Copyright (c) 2002 Myson Technology Inc.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions, and the following disclaimer,
11 * without modification, immediately at the beginning of the file.
12 * 2. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
19 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * Myson fast ethernet PCI NIC driver, available at: http://www.myson.com.tw/
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/sockio.h>
37 #include <sys/malloc.h>
38 #include <sys/kernel.h>
39 #include <sys/socket.h>
40 #include <sys/queue.h>
41 #include <sys/types.h>
42 #include <sys/module.h>
44 #include <sys/mutex.h>
49 #include <net/if_var.h>
50 #include <net/if_arp.h>
51 #include <net/ethernet.h>
52 #include <net/if_media.h>
53 #include <net/if_types.h>
54 #include <net/if_dl.h>
57 #include <vm/vm.h> /* for vtophys */
58 #include <vm/pmap.h> /* for vtophys */
59 #include <machine/bus.h>
60 #include <machine/resource.h>
64 #include <dev/pci/pcireg.h>
65 #include <dev/pci/pcivar.h>
68 * #define MY_USEIOSPACE
71 static int MY_USEIOSPACE = 1;
74 #define MY_RES SYS_RES_IOPORT
75 #define MY_RID MY_PCI_LOIO
77 #define MY_RES SYS_RES_MEMORY
78 #define MY_RID MY_PCI_LOMEM
82 #include <dev/my/if_myreg.h>
85 * Various supported device vendors/types and their names.
87 struct my_type *my_info_tmp;
88 static struct my_type my_devs[] = {
89 {MYSONVENDORID, MTD800ID, "Myson MTD80X Based Fast Ethernet Card"},
90 {MYSONVENDORID, MTD803ID, "Myson MTD80X Based Fast Ethernet Card"},
91 {MYSONVENDORID, MTD891ID, "Myson MTD89X Based Giga Ethernet Card"},
96 * Various supported PHY vendors/types and their names. Note that this driver
97 * will work with pretty much any MII-compliant PHY, so failure to positively
98 * identify the chip is not a fatal error.
100 static struct my_type my_phys[] = {
101 {MysonPHYID0, MysonPHYID0, "<MYSON MTD981>"},
102 {SeeqPHYID0, SeeqPHYID0, "<SEEQ 80225>"},
103 {AhdocPHYID0, AhdocPHYID0, "<AHDOC 101>"},
104 {MarvellPHYID0, MarvellPHYID0, "<MARVELL 88E1000>"},
105 {LevelOnePHYID0, LevelOnePHYID0, "<LevelOne LXT1000>"},
106 {0, 0, "<MII-compliant physical interface>"}
109 static int my_probe(device_t);
110 static int my_attach(device_t);
111 static int my_detach(device_t);
112 static int my_newbuf(struct my_softc *, struct my_chain_onefrag *);
113 static int my_encap(struct my_softc *, struct my_chain *, struct mbuf *);
114 static void my_rxeof(struct my_softc *);
115 static void my_txeof(struct my_softc *);
116 static void my_txeoc(struct my_softc *);
117 static void my_intr(void *);
118 static void my_start(struct ifnet *);
119 static void my_start_locked(struct ifnet *);
120 static int my_ioctl(struct ifnet *, u_long, caddr_t);
121 static void my_init(void *);
122 static void my_init_locked(struct my_softc *);
123 static void my_stop(struct my_softc *);
124 static void my_autoneg_timeout(void *);
125 static void my_watchdog(void *);
126 static int my_shutdown(device_t);
127 static int my_ifmedia_upd(struct ifnet *);
128 static void my_ifmedia_sts(struct ifnet *, struct ifmediareq *);
129 static u_int16_t my_phy_readreg(struct my_softc *, int);
130 static void my_phy_writereg(struct my_softc *, int, int);
131 static void my_autoneg_xmit(struct my_softc *);
132 static void my_autoneg_mii(struct my_softc *, int, int);
133 static void my_setmode_mii(struct my_softc *, int);
134 static void my_getmode_mii(struct my_softc *);
135 static void my_setcfg(struct my_softc *, int);
136 static void my_setmulti(struct my_softc *);
137 static void my_reset(struct my_softc *);
138 static int my_list_rx_init(struct my_softc *);
139 static int my_list_tx_init(struct my_softc *);
140 static long my_send_cmd_to_phy(struct my_softc *, int, int);
142 #define MY_SETBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
143 #define MY_CLRBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
145 static device_method_t my_methods[] = {
146 /* Device interface */
147 DEVMETHOD(device_probe, my_probe),
148 DEVMETHOD(device_attach, my_attach),
149 DEVMETHOD(device_detach, my_detach),
150 DEVMETHOD(device_shutdown, my_shutdown),
155 static driver_t my_driver = {
158 sizeof(struct my_softc)
161 static devclass_t my_devclass;
163 DRIVER_MODULE(my, pci, my_driver, my_devclass, 0, 0);
164 MODULE_DEPEND(my, pci, 1, 1, 1);
165 MODULE_DEPEND(my, ether, 1, 1, 1);
168 my_send_cmd_to_phy(struct my_softc * sc, int opcode, int regad)
176 /* enable MII output */
177 miir = CSR_READ_4(sc, MY_MANAGEMENT);
180 miir |= MY_MASK_MIIR_MII_WRITE + MY_MASK_MIIR_MII_MDO;
182 /* send 32 1's preamble */
183 for (i = 0; i < 32; i++) {
184 /* low MDC; MDO is already high (miir) */
185 miir &= ~MY_MASK_MIIR_MII_MDC;
186 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
189 miir |= MY_MASK_MIIR_MII_MDC;
190 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
193 /* calculate ST+OP+PHYAD+REGAD+TA */
194 data = opcode | (sc->my_phy_addr << 7) | (regad << 2);
199 /* low MDC, prepare MDO */
200 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO);
202 miir |= MY_MASK_MIIR_MII_MDO;
204 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
206 miir |= MY_MASK_MIIR_MII_MDC;
207 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
212 if (mask == 0x2 && opcode == MY_OP_READ)
213 miir &= ~MY_MASK_MIIR_MII_WRITE;
221 my_phy_readreg(struct my_softc * sc, int reg)
228 if (sc->my_info->my_did == MTD803ID)
229 data = CSR_READ_2(sc, MY_PHYBASE + reg * 2);
231 miir = my_send_cmd_to_phy(sc, MY_OP_READ, reg);
238 miir &= ~MY_MASK_MIIR_MII_MDC;
239 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
242 miir = CSR_READ_4(sc, MY_MANAGEMENT);
243 if (miir & MY_MASK_MIIR_MII_MDI)
246 /* high MDC, and wait */
247 miir |= MY_MASK_MIIR_MII_MDC;
248 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
256 miir &= ~MY_MASK_MIIR_MII_MDC;
257 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
260 return (u_int16_t) data;
265 my_phy_writereg(struct my_softc * sc, int reg, int data)
272 if (sc->my_info->my_did == MTD803ID)
273 CSR_WRITE_2(sc, MY_PHYBASE + reg * 2, data);
275 miir = my_send_cmd_to_phy(sc, MY_OP_WRITE, reg);
280 /* low MDC, prepare MDO */
281 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO);
283 miir |= MY_MASK_MIIR_MII_MDO;
284 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
288 miir |= MY_MASK_MIIR_MII_MDC;
289 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
297 miir &= ~MY_MASK_MIIR_MII_MDC;
298 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
305 * Program the 64-bit multicast hash filter.
308 my_setmulti(struct my_softc * sc)
312 u_int32_t hashes[2] = {0, 0};
313 struct ifmultiaddr *ifma;
321 rxfilt = CSR_READ_4(sc, MY_TCRRCR);
323 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
325 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt);
326 CSR_WRITE_4(sc, MY_MAR0, 0xFFFFFFFF);
327 CSR_WRITE_4(sc, MY_MAR1, 0xFFFFFFFF);
331 /* first, zot all the existing hash bits */
332 CSR_WRITE_4(sc, MY_MAR0, 0);
333 CSR_WRITE_4(sc, MY_MAR1, 0);
335 /* now program new ones */
337 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
338 if (ifma->ifma_addr->sa_family != AF_LINK)
340 h = ~ether_crc32_be(LLADDR((struct sockaddr_dl *)
341 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
343 hashes[0] |= (1 << h);
345 hashes[1] |= (1 << (h - 32));
348 if_maddr_runlock(ifp);
354 CSR_WRITE_4(sc, MY_MAR0, hashes[0]);
355 CSR_WRITE_4(sc, MY_MAR1, hashes[1]);
356 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt);
361 * Initiate an autonegotiation session.
364 my_autoneg_xmit(struct my_softc * sc)
366 u_int16_t phy_sts = 0;
370 my_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET);
372 while (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_RESET);
374 phy_sts = my_phy_readreg(sc, PHY_BMCR);
375 phy_sts |= PHY_BMCR_AUTONEGENBL | PHY_BMCR_AUTONEGRSTR;
376 my_phy_writereg(sc, PHY_BMCR, phy_sts);
382 my_autoneg_timeout(void *arg)
388 my_autoneg_mii(sc, MY_FLAG_DELAYTIMEO, 1);
392 * Invoke autonegotiation on a PHY.
395 my_autoneg_mii(struct my_softc * sc, int flag, int verbose)
397 u_int16_t phy_sts = 0, media, advert, ability;
398 u_int16_t ability2 = 0;
407 ifm->ifm_media = IFM_ETHER | IFM_AUTO;
409 #ifndef FORCE_AUTONEG_TFOUR
411 * First, see if autoneg is supported. If not, there's no point in
414 phy_sts = my_phy_readreg(sc, PHY_BMSR);
415 if (!(phy_sts & PHY_BMSR_CANAUTONEG)) {
417 device_printf(sc->my_dev,
418 "autonegotiation not supported\n");
419 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX;
424 case MY_FLAG_FORCEDELAY:
426 * XXX Never use this option anywhere but in the probe
427 * routine: making the kernel stop dead in its tracks for
428 * three whole seconds after we've gone multi-user is really
434 case MY_FLAG_SCHEDDELAY:
436 * Wait for the transmitter to go idle before starting an
437 * autoneg session, otherwise my_start() may clobber our
438 * timeout, and we don't want to allow transmission during an
439 * autoneg session since that can screw it up.
441 if (sc->my_cdata.my_tx_head != NULL) {
442 sc->my_want_auto = 1;
447 callout_reset(&sc->my_autoneg_timer, hz * 5, my_autoneg_timeout,
450 sc->my_want_auto = 0;
452 case MY_FLAG_DELAYTIMEO:
453 callout_stop(&sc->my_autoneg_timer);
457 device_printf(sc->my_dev, "invalid autoneg flag: %d\n", flag);
461 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) {
463 device_printf(sc->my_dev, "autoneg complete, ");
464 phy_sts = my_phy_readreg(sc, PHY_BMSR);
467 device_printf(sc->my_dev, "autoneg not complete, ");
470 media = my_phy_readreg(sc, PHY_BMCR);
472 /* Link is good. Report modes and set duplex mode. */
473 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) {
475 device_printf(sc->my_dev, "link status good. ");
476 advert = my_phy_readreg(sc, PHY_ANAR);
477 ability = my_phy_readreg(sc, PHY_LPAR);
478 if ((sc->my_pinfo->my_vid == MarvellPHYID0) ||
479 (sc->my_pinfo->my_vid == LevelOnePHYID0)) {
480 ability2 = my_phy_readreg(sc, PHY_1000SR);
481 if (ability2 & PHY_1000SR_1000BTXFULL) {
485 * this version did not support 1000M,
487 * IFM_ETHER|IFM_1000_T|IFM_FDX;
490 IFM_ETHER | IFM_100_TX | IFM_FDX;
491 media &= ~PHY_BMCR_SPEEDSEL;
492 media |= PHY_BMCR_1000;
493 media |= PHY_BMCR_DUPLEX;
494 printf("(full-duplex, 1000Mbps)\n");
495 } else if (ability2 & PHY_1000SR_1000BTXHALF) {
499 * this version did not support 1000M,
500 * ifm->ifm_media = IFM_ETHER|IFM_1000_T;
502 ifm->ifm_media = IFM_ETHER | IFM_100_TX;
503 media &= ~PHY_BMCR_SPEEDSEL;
504 media &= ~PHY_BMCR_DUPLEX;
505 media |= PHY_BMCR_1000;
506 printf("(half-duplex, 1000Mbps)\n");
509 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) {
510 ifm->ifm_media = IFM_ETHER | IFM_100_T4;
511 media |= PHY_BMCR_SPEEDSEL;
512 media &= ~PHY_BMCR_DUPLEX;
513 printf("(100baseT4)\n");
514 } else if (advert & PHY_ANAR_100BTXFULL &&
515 ability & PHY_ANAR_100BTXFULL) {
516 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX;
517 media |= PHY_BMCR_SPEEDSEL;
518 media |= PHY_BMCR_DUPLEX;
519 printf("(full-duplex, 100Mbps)\n");
520 } else if (advert & PHY_ANAR_100BTXHALF &&
521 ability & PHY_ANAR_100BTXHALF) {
522 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX;
523 media |= PHY_BMCR_SPEEDSEL;
524 media &= ~PHY_BMCR_DUPLEX;
525 printf("(half-duplex, 100Mbps)\n");
526 } else if (advert & PHY_ANAR_10BTFULL &&
527 ability & PHY_ANAR_10BTFULL) {
528 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX;
529 media &= ~PHY_BMCR_SPEEDSEL;
530 media |= PHY_BMCR_DUPLEX;
531 printf("(full-duplex, 10Mbps)\n");
533 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX;
534 media &= ~PHY_BMCR_SPEEDSEL;
535 media &= ~PHY_BMCR_DUPLEX;
536 printf("(half-duplex, 10Mbps)\n");
538 media &= ~PHY_BMCR_AUTONEGENBL;
540 /* Set ASIC's duplex mode to match the PHY. */
541 my_phy_writereg(sc, PHY_BMCR, media);
542 my_setcfg(sc, media);
545 device_printf(sc->my_dev, "no carrier\n");
549 if (sc->my_tx_pend) {
552 my_start_locked(ifp);
558 * To get PHY ability.
561 my_getmode_mii(struct my_softc * sc)
568 bmsr = my_phy_readreg(sc, PHY_BMSR);
570 device_printf(sc->my_dev, "PHY status word: %x\n", bmsr);
573 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX;
575 if (bmsr & PHY_BMSR_10BTHALF) {
577 device_printf(sc->my_dev,
578 "10Mbps half-duplex mode supported\n");
579 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_HDX,
581 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T, 0, NULL);
583 if (bmsr & PHY_BMSR_10BTFULL) {
585 device_printf(sc->my_dev,
586 "10Mbps full-duplex mode supported\n");
588 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX,
590 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX;
592 if (bmsr & PHY_BMSR_100BTXHALF) {
594 device_printf(sc->my_dev,
595 "100Mbps half-duplex mode supported\n");
596 ifp->if_baudrate = 100000000;
597 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL);
598 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_HDX,
600 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX;
602 if (bmsr & PHY_BMSR_100BTXFULL) {
604 device_printf(sc->my_dev,
605 "100Mbps full-duplex mode supported\n");
606 ifp->if_baudrate = 100000000;
607 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX,
609 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX;
611 /* Some also support 100BaseT4. */
612 if (bmsr & PHY_BMSR_100BT4) {
614 device_printf(sc->my_dev, "100baseT4 mode supported\n");
615 ifp->if_baudrate = 100000000;
616 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_T4, 0, NULL);
617 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_T4;
618 #ifdef FORCE_AUTONEG_TFOUR
620 device_printf(sc->my_dev,
621 "forcing on autoneg support for BT4\n");
622 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0 NULL):
623 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO;
626 #if 0 /* this version did not support 1000M, */
627 if (sc->my_pinfo->my_vid == MarvellPHYID0) {
629 device_printf(sc->my_dev,
630 "1000Mbps half-duplex mode supported\n");
632 ifp->if_baudrate = 1000000000;
633 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T, 0, NULL);
634 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_HDX,
637 device_printf(sc->my_dev,
638 "1000Mbps full-duplex mode supported\n");
639 ifp->if_baudrate = 1000000000;
640 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_FDX,
642 sc->ifmedia.ifm_media = IFM_ETHER | IFM_1000_T | IFM_FDX;
645 if (bmsr & PHY_BMSR_CANAUTONEG) {
647 device_printf(sc->my_dev, "autoneg supported\n");
648 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
649 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO;
655 * Set speed and duplex mode.
658 my_setmode_mii(struct my_softc * sc, int media)
664 * If an autoneg session is in progress, stop it.
666 if (sc->my_autoneg) {
667 device_printf(sc->my_dev, "canceling autoneg session\n");
668 callout_stop(&sc->my_autoneg_timer);
669 sc->my_autoneg = sc->my_want_auto = 0;
670 bmcr = my_phy_readreg(sc, PHY_BMCR);
671 bmcr &= ~PHY_BMCR_AUTONEGENBL;
672 my_phy_writereg(sc, PHY_BMCR, bmcr);
674 device_printf(sc->my_dev, "selecting MII, ");
675 bmcr = my_phy_readreg(sc, PHY_BMCR);
676 bmcr &= ~(PHY_BMCR_AUTONEGENBL | PHY_BMCR_SPEEDSEL | PHY_BMCR_1000 |
677 PHY_BMCR_DUPLEX | PHY_BMCR_LOOPBK);
679 #if 0 /* this version did not support 1000M, */
680 if (IFM_SUBTYPE(media) == IFM_1000_T) {
681 printf("1000Mbps/T4, half-duplex\n");
682 bmcr &= ~PHY_BMCR_SPEEDSEL;
683 bmcr &= ~PHY_BMCR_DUPLEX;
684 bmcr |= PHY_BMCR_1000;
687 if (IFM_SUBTYPE(media) == IFM_100_T4) {
688 printf("100Mbps/T4, half-duplex\n");
689 bmcr |= PHY_BMCR_SPEEDSEL;
690 bmcr &= ~PHY_BMCR_DUPLEX;
692 if (IFM_SUBTYPE(media) == IFM_100_TX) {
694 bmcr |= PHY_BMCR_SPEEDSEL;
696 if (IFM_SUBTYPE(media) == IFM_10_T) {
698 bmcr &= ~PHY_BMCR_SPEEDSEL;
700 if ((media & IFM_GMASK) == IFM_FDX) {
701 printf("full duplex\n");
702 bmcr |= PHY_BMCR_DUPLEX;
704 printf("half duplex\n");
705 bmcr &= ~PHY_BMCR_DUPLEX;
707 my_phy_writereg(sc, PHY_BMCR, bmcr);
713 * The Myson manual states that in order to fiddle with the 'full-duplex' and
714 * '100Mbps' bits in the netconfig register, we first have to put the
715 * transmit and/or receive logic in the idle state.
718 my_setcfg(struct my_softc * sc, int bmcr)
723 if (CSR_READ_4(sc, MY_TCRRCR) & (MY_TE | MY_RE)) {
725 MY_CLRBIT(sc, MY_TCRRCR, (MY_TE | MY_RE));
726 for (i = 0; i < MY_TIMEOUT; i++) {
728 if (!(CSR_READ_4(sc, MY_TCRRCR) &
729 (MY_TXRUN | MY_RXRUN)))
733 device_printf(sc->my_dev,
734 "failed to force tx and rx to idle \n");
736 MY_CLRBIT(sc, MY_TCRRCR, MY_PS1000);
737 MY_CLRBIT(sc, MY_TCRRCR, MY_PS10);
738 if (bmcr & PHY_BMCR_1000)
739 MY_SETBIT(sc, MY_TCRRCR, MY_PS1000);
740 else if (!(bmcr & PHY_BMCR_SPEEDSEL))
741 MY_SETBIT(sc, MY_TCRRCR, MY_PS10);
742 if (bmcr & PHY_BMCR_DUPLEX)
743 MY_SETBIT(sc, MY_TCRRCR, MY_FD);
745 MY_CLRBIT(sc, MY_TCRRCR, MY_FD);
747 MY_SETBIT(sc, MY_TCRRCR, MY_TE | MY_RE);
752 my_reset(struct my_softc * sc)
757 MY_SETBIT(sc, MY_BCR, MY_SWR);
758 for (i = 0; i < MY_TIMEOUT; i++) {
760 if (!(CSR_READ_4(sc, MY_BCR) & MY_SWR))
764 device_printf(sc->my_dev, "reset never completed!\n");
766 /* Wait a little while for the chip to get its brains in order. */
772 * Probe for a Myson chip. Check the PCI vendor and device IDs against our
773 * list and return a device name if we find a match.
776 my_probe(device_t dev)
781 while (t->my_name != NULL) {
782 if ((pci_get_vendor(dev) == t->my_vid) &&
783 (pci_get_device(dev) == t->my_did)) {
784 device_set_desc(dev, t->my_name);
786 return (BUS_PROBE_DEFAULT);
794 * Attach the interface. Allocate softc structures, do ifmedia setup and
795 * ethernet/BPF attach.
798 my_attach(device_t dev)
801 u_char eaddr[ETHER_ADDR_LEN];
805 int media = IFM_ETHER | IFM_100_TX | IFM_FDX;
809 u_int16_t phy_vid, phy_did, phy_sts = 0;
812 sc = device_get_softc(dev);
814 mtx_init(&sc->my_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
816 callout_init_mtx(&sc->my_autoneg_timer, &sc->my_mtx, 0);
817 callout_init_mtx(&sc->my_watchdog, &sc->my_mtx, 0);
820 * Map control/status registers.
822 pci_enable_busmaster(dev);
824 if (my_info_tmp->my_did == MTD800ID) {
825 iobase = pci_read_config(dev, MY_PCI_LOIO, 4);
831 sc->my_res = bus_alloc_resource_any(dev, MY_RES, &rid, RF_ACTIVE);
833 if (sc->my_res == NULL) {
834 device_printf(dev, "couldn't map ports/memory\n");
838 sc->my_btag = rman_get_bustag(sc->my_res);
839 sc->my_bhandle = rman_get_bushandle(sc->my_res);
842 sc->my_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
843 RF_SHAREABLE | RF_ACTIVE);
845 if (sc->my_irq == NULL) {
846 device_printf(dev, "couldn't map interrupt\n");
851 sc->my_info = my_info_tmp;
853 /* Reset the adapter. */
859 * Get station address
861 for (i = 0; i < ETHER_ADDR_LEN; ++i)
862 eaddr[i] = CSR_READ_1(sc, MY_PAR0 + i);
864 sc->my_ldata_ptr = malloc(sizeof(struct my_list_data) + 8,
866 if (sc->my_ldata_ptr == NULL) {
867 device_printf(dev, "no memory for list buffers!\n");
871 sc->my_ldata = (struct my_list_data *) sc->my_ldata_ptr;
872 round = (uintptr_t)sc->my_ldata_ptr & 0xF;
873 roundptr = sc->my_ldata_ptr;
874 for (i = 0; i < 8; i++) {
881 sc->my_ldata = (struct my_list_data *) roundptr;
882 bzero(sc->my_ldata, sizeof(struct my_list_data));
884 ifp = sc->my_ifp = if_alloc(IFT_ETHER);
886 device_printf(dev, "can not if_alloc()\n");
891 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
892 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
893 ifp->if_ioctl = my_ioctl;
894 ifp->if_start = my_start;
895 ifp->if_init = my_init;
896 ifp->if_baudrate = 10000000;
897 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
898 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen;
899 IFQ_SET_READY(&ifp->if_snd);
901 if (sc->my_info->my_did == MTD803ID)
902 sc->my_pinfo = my_phys;
905 device_printf(dev, "probing for a PHY\n");
907 for (i = MY_PHYADDR_MIN; i < MY_PHYADDR_MAX + 1; i++) {
909 device_printf(dev, "checking address: %d\n", i);
911 phy_sts = my_phy_readreg(sc, PHY_BMSR);
912 if ((phy_sts != 0) && (phy_sts != 0xffff))
918 phy_vid = my_phy_readreg(sc, PHY_VENID);
919 phy_did = my_phy_readreg(sc, PHY_DEVID);
921 device_printf(dev, "found PHY at address %d, ",
923 printf("vendor id: %x device id: %x\n",
928 if (phy_vid == p->my_vid) {
934 if (sc->my_pinfo == NULL)
935 sc->my_pinfo = &my_phys[PHY_UNKNOWN];
937 device_printf(dev, "PHY type: %s\n",
938 sc->my_pinfo->my_name);
941 device_printf(dev, "MII without any phy!\n");
948 /* Do ifmedia setup. */
949 ifmedia_init(&sc->ifmedia, 0, my_ifmedia_upd, my_ifmedia_sts);
952 my_autoneg_mii(sc, MY_FLAG_FORCEDELAY, 1);
953 media = sc->ifmedia.ifm_media;
956 ifmedia_set(&sc->ifmedia, media);
958 ether_ifattach(ifp, eaddr);
960 error = bus_setup_intr(dev, sc->my_irq, INTR_TYPE_NET | INTR_MPSAFE,
961 NULL, my_intr, sc, &sc->my_intrhand);
964 device_printf(dev, "couldn't set up irq\n");
975 free(sc->my_ldata_ptr, M_DEVBUF);
977 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq);
979 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res);
981 mtx_destroy(&sc->my_mtx);
986 my_detach(device_t dev)
991 sc = device_get_softc(dev);
997 bus_teardown_intr(dev, sc->my_irq, sc->my_intrhand);
998 callout_drain(&sc->my_watchdog);
999 callout_drain(&sc->my_autoneg_timer);
1002 free(sc->my_ldata_ptr, M_DEVBUF);
1004 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq);
1005 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res);
1006 mtx_destroy(&sc->my_mtx);
1012 * Initialize the transmit descriptors.
1015 my_list_tx_init(struct my_softc * sc)
1017 struct my_chain_data *cd;
1018 struct my_list_data *ld;
1024 for (i = 0; i < MY_TX_LIST_CNT; i++) {
1025 cd->my_tx_chain[i].my_ptr = &ld->my_tx_list[i];
1026 if (i == (MY_TX_LIST_CNT - 1))
1027 cd->my_tx_chain[i].my_nextdesc = &cd->my_tx_chain[0];
1029 cd->my_tx_chain[i].my_nextdesc =
1030 &cd->my_tx_chain[i + 1];
1032 cd->my_tx_free = &cd->my_tx_chain[0];
1033 cd->my_tx_tail = cd->my_tx_head = NULL;
1038 * Initialize the RX descriptors and allocate mbufs for them. Note that we
1039 * arrange the descriptors in a closed ring, so that the last descriptor
1040 * points back to the first.
1043 my_list_rx_init(struct my_softc * sc)
1045 struct my_chain_data *cd;
1046 struct my_list_data *ld;
1052 for (i = 0; i < MY_RX_LIST_CNT; i++) {
1053 cd->my_rx_chain[i].my_ptr =
1054 (struct my_desc *) & ld->my_rx_list[i];
1055 if (my_newbuf(sc, &cd->my_rx_chain[i]) == ENOBUFS) {
1059 if (i == (MY_RX_LIST_CNT - 1)) {
1060 cd->my_rx_chain[i].my_nextdesc = &cd->my_rx_chain[0];
1061 ld->my_rx_list[i].my_next = vtophys(&ld->my_rx_list[0]);
1063 cd->my_rx_chain[i].my_nextdesc =
1064 &cd->my_rx_chain[i + 1];
1065 ld->my_rx_list[i].my_next =
1066 vtophys(&ld->my_rx_list[i + 1]);
1069 cd->my_rx_head = &cd->my_rx_chain[0];
1074 * Initialize an RX descriptor and attach an MBUF cluster.
1077 my_newbuf(struct my_softc * sc, struct my_chain_onefrag * c)
1079 struct mbuf *m_new = NULL;
1082 MGETHDR(m_new, M_NOWAIT, MT_DATA);
1083 if (m_new == NULL) {
1084 device_printf(sc->my_dev,
1085 "no memory for rx list -- packet dropped!\n");
1088 if (!(MCLGET(m_new, M_NOWAIT))) {
1089 device_printf(sc->my_dev,
1090 "no memory for rx list -- packet dropped!\n");
1095 c->my_ptr->my_data = vtophys(mtod(m_new, caddr_t));
1096 c->my_ptr->my_ctl = (MCLBYTES - 1) << MY_RBSShift;
1097 c->my_ptr->my_status = MY_OWNByNIC;
1102 * A frame has been uploaded: pass the resulting mbuf chain up to the higher
1106 my_rxeof(struct my_softc * sc)
1108 struct ether_header *eh;
1111 struct my_chain_onefrag *cur_rx;
1117 while (!((rxstat = sc->my_cdata.my_rx_head->my_ptr->my_status)
1119 cur_rx = sc->my_cdata.my_rx_head;
1120 sc->my_cdata.my_rx_head = cur_rx->my_nextdesc;
1122 if (rxstat & MY_ES) { /* error summary: give up this rx pkt */
1123 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1124 cur_rx->my_ptr->my_status = MY_OWNByNIC;
1127 /* No errors; receive the packet. */
1128 total_len = (rxstat & MY_FLNGMASK) >> MY_FLNGShift;
1129 total_len -= ETHER_CRC_LEN;
1131 if (total_len < MINCLSIZE) {
1132 m = m_devget(mtod(cur_rx->my_mbuf, char *),
1133 total_len, 0, ifp, NULL);
1134 cur_rx->my_ptr->my_status = MY_OWNByNIC;
1136 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1140 m = cur_rx->my_mbuf;
1142 * Try to conjure up a new mbuf cluster. If that
1143 * fails, it means we have an out of memory condition
1144 * and should leave the buffer in place and continue.
1145 * This will result in a lost packet, but there's
1146 * little else we can do in this situation.
1148 if (my_newbuf(sc, cur_rx) == ENOBUFS) {
1149 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1150 cur_rx->my_ptr->my_status = MY_OWNByNIC;
1153 m->m_pkthdr.rcvif = ifp;
1154 m->m_pkthdr.len = m->m_len = total_len;
1156 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
1157 eh = mtod(m, struct ether_header *);
1160 * Handle BPF listeners. Let the BPF user see the packet, but
1161 * don't pass it up to the ether_input() layer unless it's a
1162 * broadcast packet, multicast packet, matches our ethernet
1163 * address or the interface is in promiscuous mode.
1165 if (bpf_peers_present(ifp->if_bpf)) {
1166 bpf_mtap(ifp->if_bpf, m);
1167 if (ifp->if_flags & IFF_PROMISC &&
1168 (bcmp(eh->ether_dhost, IF_LLADDR(sc->my_ifp),
1170 (eh->ether_dhost[0] & 1) == 0)) {
1177 (*ifp->if_input)(ifp, m);
1185 * A frame was downloaded to the chip. It's safe for us to clean up the list
1189 my_txeof(struct my_softc * sc)
1191 struct my_chain *cur_tx;
1196 /* Clear the timeout timer. */
1198 if (sc->my_cdata.my_tx_head == NULL) {
1202 * Go through our tx list and free mbufs for those frames that have
1205 while (sc->my_cdata.my_tx_head->my_mbuf != NULL) {
1208 cur_tx = sc->my_cdata.my_tx_head;
1209 txstat = MY_TXSTATUS(cur_tx);
1210 if ((txstat & MY_OWNByNIC) || txstat == MY_UNSENT)
1212 if (!(CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced)) {
1213 if (txstat & MY_TXERR) {
1214 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1215 if (txstat & MY_EC) /* excessive collision */
1216 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
1217 if (txstat & MY_LC) /* late collision */
1218 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
1220 if_inc_counter(ifp, IFCOUNTER_COLLISIONS,
1221 (txstat & MY_NCRMASK) >> MY_NCRShift);
1223 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
1224 m_freem(cur_tx->my_mbuf);
1225 cur_tx->my_mbuf = NULL;
1226 if (sc->my_cdata.my_tx_head == sc->my_cdata.my_tx_tail) {
1227 sc->my_cdata.my_tx_head = NULL;
1228 sc->my_cdata.my_tx_tail = NULL;
1231 sc->my_cdata.my_tx_head = cur_tx->my_nextdesc;
1233 if (CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced) {
1234 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, (CSR_READ_4(sc, MY_TSR) & MY_NCRMask));
1240 * TX 'end of channel' interrupt handler.
1243 my_txeoc(struct my_softc * sc)
1250 if (sc->my_cdata.my_tx_head == NULL) {
1251 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1252 sc->my_cdata.my_tx_tail = NULL;
1253 if (sc->my_want_auto)
1254 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1);
1256 if (MY_TXOWN(sc->my_cdata.my_tx_head) == MY_UNSENT) {
1257 MY_TXOWN(sc->my_cdata.my_tx_head) = MY_OWNByNIC;
1259 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF);
1268 struct my_softc *sc;
1275 if (!(ifp->if_flags & IFF_UP)) {
1279 /* Disable interrupts. */
1280 CSR_WRITE_4(sc, MY_IMR, 0x00000000);
1283 status = CSR_READ_4(sc, MY_ISR);
1286 CSR_WRITE_4(sc, MY_ISR, status);
1290 if (status & MY_RI) /* receive interrupt */
1293 if ((status & MY_RBU) || (status & MY_RxErr)) {
1294 /* rx buffer unavailable or rx error */
1295 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1302 if (status & MY_TI) /* tx interrupt */
1304 if (status & MY_ETI) /* tx early interrupt */
1306 if (status & MY_TBU) /* tx buffer unavailable */
1309 #if 0 /* 90/1/18 delete */
1310 if (status & MY_FBE) {
1318 /* Re-enable interrupts. */
1319 CSR_WRITE_4(sc, MY_IMR, MY_INTRS);
1320 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1321 my_start_locked(ifp);
1327 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1328 * pointers to the fragment pointers.
1331 my_encap(struct my_softc * sc, struct my_chain * c, struct mbuf * m_head)
1333 struct my_desc *f = NULL;
1335 struct mbuf *m, *m_new = NULL;
1338 /* calculate the total tx pkt length */
1340 for (m = m_head; m != NULL; m = m->m_next)
1341 total_len += m->m_len;
1343 * Start packing the mbufs in this chain into the fragment pointers.
1344 * Stop when we run out of fragments or hit the end of the mbuf
1348 MGETHDR(m_new, M_NOWAIT, MT_DATA);
1349 if (m_new == NULL) {
1350 device_printf(sc->my_dev, "no memory for tx list");
1353 if (m_head->m_pkthdr.len > MHLEN) {
1354 if (!(MCLGET(m_new, M_NOWAIT))) {
1356 device_printf(sc->my_dev, "no memory for tx list");
1360 m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t));
1361 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1364 f = &c->my_ptr->my_frag[0];
1366 f->my_data = vtophys(mtod(m_new, caddr_t));
1367 total_len = m_new->m_len;
1368 f->my_ctl = MY_TXFD | MY_TXLD | MY_CRCEnable | MY_PADEnable;
1369 f->my_ctl |= total_len << MY_PKTShift; /* pkt size */
1370 f->my_ctl |= total_len; /* buffer size */
1371 /* 89/12/29 add, for mtd891 *//* [ 89? ] */
1372 if (sc->my_info->my_did == MTD891ID)
1373 f->my_ctl |= MY_ETIControl | MY_RetryTxLC;
1374 c->my_mbuf = m_head;
1376 MY_TXNEXT(c) = vtophys(&c->my_nextdesc->my_ptr->my_frag[0]);
1381 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1382 * to the mbuf data regions directly in the transmit lists. We also save a
1383 * copy of the pointers since the transmit list fragment pointers are
1384 * physical addresses.
1387 my_start(struct ifnet * ifp)
1389 struct my_softc *sc;
1393 my_start_locked(ifp);
1398 my_start_locked(struct ifnet * ifp)
1400 struct my_softc *sc;
1401 struct mbuf *m_head = NULL;
1402 struct my_chain *cur_tx = NULL, *start_tx;
1406 if (sc->my_autoneg) {
1411 * Check for an available queue slot. If there are none, punt.
1413 if (sc->my_cdata.my_tx_free->my_mbuf != NULL) {
1414 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1417 start_tx = sc->my_cdata.my_tx_free;
1418 while (sc->my_cdata.my_tx_free->my_mbuf == NULL) {
1419 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1423 /* Pick a descriptor off the free list. */
1424 cur_tx = sc->my_cdata.my_tx_free;
1425 sc->my_cdata.my_tx_free = cur_tx->my_nextdesc;
1427 /* Pack the data into the descriptor. */
1428 my_encap(sc, cur_tx, m_head);
1430 if (cur_tx != start_tx)
1431 MY_TXOWN(cur_tx) = MY_OWNByNIC;
1434 * If there's a BPF listener, bounce a copy of this frame to
1437 BPF_MTAP(ifp, cur_tx->my_mbuf);
1441 * If there are no packets queued, bail.
1443 if (cur_tx == NULL) {
1447 * Place the request for the upload interrupt in the last descriptor
1448 * in the chain. This way, if we're chaining several packets at once,
1449 * we'll only get an interrupt once for the whole chain rather than
1450 * once for each packet.
1452 MY_TXCTL(cur_tx) |= MY_TXIC;
1453 cur_tx->my_ptr->my_frag[0].my_ctl |= MY_TXIC;
1454 sc->my_cdata.my_tx_tail = cur_tx;
1455 if (sc->my_cdata.my_tx_head == NULL)
1456 sc->my_cdata.my_tx_head = start_tx;
1457 MY_TXOWN(start_tx) = MY_OWNByNIC;
1458 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF); /* tx polling demand */
1461 * Set a timeout in case the chip goes out to lunch.
1470 struct my_softc *sc = xsc;
1478 my_init_locked(struct my_softc *sc)
1480 struct ifnet *ifp = sc->my_ifp;
1481 u_int16_t phy_bmcr = 0;
1484 if (sc->my_autoneg) {
1487 if (sc->my_pinfo != NULL)
1488 phy_bmcr = my_phy_readreg(sc, PHY_BMCR);
1490 * Cancel pending I/O and free all RX/TX buffers.
1496 * Set cache alignment and burst length.
1498 #if 0 /* 89/9/1 modify, */
1499 CSR_WRITE_4(sc, MY_BCR, MY_RPBLE512);
1500 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF);
1502 CSR_WRITE_4(sc, MY_BCR, MY_PBL8);
1503 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF | MY_RBLEN | MY_RPBLE512);
1505 * 89/12/29 add, for mtd891,
1507 if (sc->my_info->my_did == MTD891ID) {
1508 MY_SETBIT(sc, MY_BCR, MY_PROG);
1509 MY_SETBIT(sc, MY_TCRRCR, MY_Enhanced);
1511 my_setcfg(sc, phy_bmcr);
1512 /* Init circular RX list. */
1513 if (my_list_rx_init(sc) == ENOBUFS) {
1514 device_printf(sc->my_dev, "init failed: no memory for rx buffers\n");
1518 /* Init TX descriptors. */
1519 my_list_tx_init(sc);
1521 /* If we want promiscuous mode, set the allframes bit. */
1522 if (ifp->if_flags & IFF_PROMISC)
1523 MY_SETBIT(sc, MY_TCRRCR, MY_PROM);
1525 MY_CLRBIT(sc, MY_TCRRCR, MY_PROM);
1528 * Set capture broadcast bit to capture broadcast frames.
1530 if (ifp->if_flags & IFF_BROADCAST)
1531 MY_SETBIT(sc, MY_TCRRCR, MY_AB);
1533 MY_CLRBIT(sc, MY_TCRRCR, MY_AB);
1536 * Program the multicast filter, if necessary.
1541 * Load the address of the RX list.
1543 MY_CLRBIT(sc, MY_TCRRCR, MY_RE);
1544 CSR_WRITE_4(sc, MY_RXLBA, vtophys(&sc->my_ldata->my_rx_list[0]));
1547 * Enable interrupts.
1549 CSR_WRITE_4(sc, MY_IMR, MY_INTRS);
1550 CSR_WRITE_4(sc, MY_ISR, 0xFFFFFFFF);
1552 /* Enable receiver and transmitter. */
1553 MY_SETBIT(sc, MY_TCRRCR, MY_RE);
1554 MY_CLRBIT(sc, MY_TCRRCR, MY_TE);
1555 CSR_WRITE_4(sc, MY_TXLBA, vtophys(&sc->my_ldata->my_tx_list[0]));
1556 MY_SETBIT(sc, MY_TCRRCR, MY_TE);
1558 /* Restore state of BMCR */
1559 if (sc->my_pinfo != NULL)
1560 my_phy_writereg(sc, PHY_BMCR, phy_bmcr);
1561 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1562 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1564 callout_reset(&sc->my_watchdog, hz, my_watchdog, sc);
1569 * Set media options.
1573 my_ifmedia_upd(struct ifnet * ifp)
1575 struct my_softc *sc;
1576 struct ifmedia *ifm;
1581 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) {
1585 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO)
1586 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1);
1588 my_setmode_mii(sc, ifm->ifm_media);
1594 * Report current media status.
1598 my_ifmedia_sts(struct ifnet * ifp, struct ifmediareq * ifmr)
1600 struct my_softc *sc;
1601 u_int16_t advert = 0, ability = 0;
1605 ifmr->ifm_active = IFM_ETHER;
1606 if (!(my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) {
1607 #if 0 /* this version did not support 1000M, */
1608 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_1000)
1609 ifmr->ifm_active = IFM_ETHER | IFM_1000TX;
1611 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL)
1612 ifmr->ifm_active = IFM_ETHER | IFM_100_TX;
1614 ifmr->ifm_active = IFM_ETHER | IFM_10_T;
1615 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX)
1616 ifmr->ifm_active |= IFM_FDX;
1618 ifmr->ifm_active |= IFM_HDX;
1623 ability = my_phy_readreg(sc, PHY_LPAR);
1624 advert = my_phy_readreg(sc, PHY_ANAR);
1626 #if 0 /* this version did not support 1000M, */
1627 if (sc->my_pinfo->my_vid = MarvellPHYID0) {
1628 ability2 = my_phy_readreg(sc, PHY_1000SR);
1629 if (ability2 & PHY_1000SR_1000BTXFULL) {
1632 ifmr->ifm_active = IFM_ETHER|IFM_1000_T|IFM_FDX;
1633 } else if (ability & PHY_1000SR_1000BTXHALF) {
1636 ifmr->ifm_active = IFM_ETHER|IFM_1000_T|IFM_HDX;
1640 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4)
1641 ifmr->ifm_active = IFM_ETHER | IFM_100_T4;
1642 else if (advert & PHY_ANAR_100BTXFULL && ability & PHY_ANAR_100BTXFULL)
1643 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1644 else if (advert & PHY_ANAR_100BTXHALF && ability & PHY_ANAR_100BTXHALF)
1645 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_HDX;
1646 else if (advert & PHY_ANAR_10BTFULL && ability & PHY_ANAR_10BTFULL)
1647 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_FDX;
1648 else if (advert & PHY_ANAR_10BTHALF && ability & PHY_ANAR_10BTHALF)
1649 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_HDX;
1655 my_ioctl(struct ifnet * ifp, u_long command, caddr_t data)
1657 struct my_softc *sc = ifp->if_softc;
1658 struct ifreq *ifr = (struct ifreq *) data;
1664 if (ifp->if_flags & IFF_UP)
1666 else if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1680 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
1683 error = ether_ioctl(ifp, command, data);
1690 my_watchdog(void *arg)
1692 struct my_softc *sc;
1697 callout_reset(&sc->my_watchdog, hz, my_watchdog, sc);
1698 if (sc->my_timer == 0 || --sc->my_timer > 0)
1702 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1703 if_printf(ifp, "watchdog timeout\n");
1704 if (!(my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT))
1705 if_printf(ifp, "no carrier - transceiver cable problem?\n");
1709 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1710 my_start_locked(ifp);
1715 * Stop the adapter and free any mbufs allocated to the RX and TX lists.
1718 my_stop(struct my_softc * sc)
1726 callout_stop(&sc->my_autoneg_timer);
1727 callout_stop(&sc->my_watchdog);
1729 MY_CLRBIT(sc, MY_TCRRCR, (MY_RE | MY_TE));
1730 CSR_WRITE_4(sc, MY_IMR, 0x00000000);
1731 CSR_WRITE_4(sc, MY_TXLBA, 0x00000000);
1732 CSR_WRITE_4(sc, MY_RXLBA, 0x00000000);
1735 * Free data in the RX lists.
1737 for (i = 0; i < MY_RX_LIST_CNT; i++) {
1738 if (sc->my_cdata.my_rx_chain[i].my_mbuf != NULL) {
1739 m_freem(sc->my_cdata.my_rx_chain[i].my_mbuf);
1740 sc->my_cdata.my_rx_chain[i].my_mbuf = NULL;
1743 bzero((char *)&sc->my_ldata->my_rx_list,
1744 sizeof(sc->my_ldata->my_rx_list));
1746 * Free the TX list buffers.
1748 for (i = 0; i < MY_TX_LIST_CNT; i++) {
1749 if (sc->my_cdata.my_tx_chain[i].my_mbuf != NULL) {
1750 m_freem(sc->my_cdata.my_tx_chain[i].my_mbuf);
1751 sc->my_cdata.my_tx_chain[i].my_mbuf = NULL;
1754 bzero((char *)&sc->my_ldata->my_tx_list,
1755 sizeof(sc->my_ldata->my_tx_list));
1756 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1761 * Stop all chip I/O so that the kernel's probe routines don't get confused
1762 * by errant DMAs when rebooting.
1765 my_shutdown(device_t dev)
1767 struct my_softc *sc;
1769 sc = device_get_softc(dev);