2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Written by: yen_cw@myson.com.tw
5 * Copyright (c) 2002 Myson Technology Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification, immediately at the beginning of the file.
14 * 2. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
21 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * Myson fast ethernet PCI NIC driver, available at: http://www.myson.com.tw/
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/sockio.h>
39 #include <sys/malloc.h>
40 #include <sys/kernel.h>
41 #include <sys/socket.h>
42 #include <sys/queue.h>
43 #include <sys/types.h>
44 #include <sys/module.h>
46 #include <sys/mutex.h>
51 #include <net/if_var.h>
52 #include <net/if_arp.h>
53 #include <net/ethernet.h>
54 #include <net/if_media.h>
55 #include <net/if_types.h>
56 #include <net/if_dl.h>
59 #include <vm/vm.h> /* for vtophys */
60 #include <vm/pmap.h> /* for vtophys */
61 #include <machine/bus.h>
62 #include <machine/resource.h>
66 #include <dev/pci/pcireg.h>
67 #include <dev/pci/pcivar.h>
70 * #define MY_USEIOSPACE
73 static int MY_USEIOSPACE = 1;
76 #define MY_RES SYS_RES_IOPORT
77 #define MY_RID MY_PCI_LOIO
79 #define MY_RES SYS_RES_MEMORY
80 #define MY_RID MY_PCI_LOMEM
84 #include <dev/my/if_myreg.h>
87 * Various supported device vendors/types and their names.
89 struct my_type *my_info_tmp;
90 static struct my_type my_devs[] = {
91 {MYSONVENDORID, MTD800ID, "Myson MTD80X Based Fast Ethernet Card"},
92 {MYSONVENDORID, MTD803ID, "Myson MTD80X Based Fast Ethernet Card"},
93 {MYSONVENDORID, MTD891ID, "Myson MTD89X Based Giga Ethernet Card"},
98 * Various supported PHY vendors/types and their names. Note that this driver
99 * will work with pretty much any MII-compliant PHY, so failure to positively
100 * identify the chip is not a fatal error.
102 static struct my_type my_phys[] = {
103 {MysonPHYID0, MysonPHYID0, "<MYSON MTD981>"},
104 {SeeqPHYID0, SeeqPHYID0, "<SEEQ 80225>"},
105 {AhdocPHYID0, AhdocPHYID0, "<AHDOC 101>"},
106 {MarvellPHYID0, MarvellPHYID0, "<MARVELL 88E1000>"},
107 {LevelOnePHYID0, LevelOnePHYID0, "<LevelOne LXT1000>"},
108 {0, 0, "<MII-compliant physical interface>"}
111 static int my_probe(device_t);
112 static int my_attach(device_t);
113 static int my_detach(device_t);
114 static int my_newbuf(struct my_softc *, struct my_chain_onefrag *);
115 static int my_encap(struct my_softc *, struct my_chain *, struct mbuf *);
116 static void my_rxeof(struct my_softc *);
117 static void my_txeof(struct my_softc *);
118 static void my_txeoc(struct my_softc *);
119 static void my_intr(void *);
120 static void my_start(struct ifnet *);
121 static void my_start_locked(struct ifnet *);
122 static int my_ioctl(struct ifnet *, u_long, caddr_t);
123 static void my_init(void *);
124 static void my_init_locked(struct my_softc *);
125 static void my_stop(struct my_softc *);
126 static void my_autoneg_timeout(void *);
127 static void my_watchdog(void *);
128 static int my_shutdown(device_t);
129 static int my_ifmedia_upd(struct ifnet *);
130 static void my_ifmedia_sts(struct ifnet *, struct ifmediareq *);
131 static u_int16_t my_phy_readreg(struct my_softc *, int);
132 static void my_phy_writereg(struct my_softc *, int, int);
133 static void my_autoneg_xmit(struct my_softc *);
134 static void my_autoneg_mii(struct my_softc *, int, int);
135 static void my_setmode_mii(struct my_softc *, int);
136 static void my_getmode_mii(struct my_softc *);
137 static void my_setcfg(struct my_softc *, int);
138 static void my_setmulti(struct my_softc *);
139 static void my_reset(struct my_softc *);
140 static int my_list_rx_init(struct my_softc *);
141 static int my_list_tx_init(struct my_softc *);
142 static long my_send_cmd_to_phy(struct my_softc *, int, int);
144 #define MY_SETBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
145 #define MY_CLRBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
147 static device_method_t my_methods[] = {
148 /* Device interface */
149 DEVMETHOD(device_probe, my_probe),
150 DEVMETHOD(device_attach, my_attach),
151 DEVMETHOD(device_detach, my_detach),
152 DEVMETHOD(device_shutdown, my_shutdown),
157 static driver_t my_driver = {
160 sizeof(struct my_softc)
163 static devclass_t my_devclass;
165 DRIVER_MODULE(my, pci, my_driver, my_devclass, 0, 0);
166 MODULE_DEPEND(my, pci, 1, 1, 1);
167 MODULE_DEPEND(my, ether, 1, 1, 1);
170 my_send_cmd_to_phy(struct my_softc * sc, int opcode, int regad)
178 /* enable MII output */
179 miir = CSR_READ_4(sc, MY_MANAGEMENT);
182 miir |= MY_MASK_MIIR_MII_WRITE + MY_MASK_MIIR_MII_MDO;
184 /* send 32 1's preamble */
185 for (i = 0; i < 32; i++) {
186 /* low MDC; MDO is already high (miir) */
187 miir &= ~MY_MASK_MIIR_MII_MDC;
188 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
191 miir |= MY_MASK_MIIR_MII_MDC;
192 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
195 /* calculate ST+OP+PHYAD+REGAD+TA */
196 data = opcode | (sc->my_phy_addr << 7) | (regad << 2);
201 /* low MDC, prepare MDO */
202 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO);
204 miir |= MY_MASK_MIIR_MII_MDO;
206 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
208 miir |= MY_MASK_MIIR_MII_MDC;
209 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
214 if (mask == 0x2 && opcode == MY_OP_READ)
215 miir &= ~MY_MASK_MIIR_MII_WRITE;
223 my_phy_readreg(struct my_softc * sc, int reg)
230 if (sc->my_info->my_did == MTD803ID)
231 data = CSR_READ_2(sc, MY_PHYBASE + reg * 2);
233 miir = my_send_cmd_to_phy(sc, MY_OP_READ, reg);
240 miir &= ~MY_MASK_MIIR_MII_MDC;
241 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
244 miir = CSR_READ_4(sc, MY_MANAGEMENT);
245 if (miir & MY_MASK_MIIR_MII_MDI)
248 /* high MDC, and wait */
249 miir |= MY_MASK_MIIR_MII_MDC;
250 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
258 miir &= ~MY_MASK_MIIR_MII_MDC;
259 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
262 return (u_int16_t) data;
267 my_phy_writereg(struct my_softc * sc, int reg, int data)
274 if (sc->my_info->my_did == MTD803ID)
275 CSR_WRITE_2(sc, MY_PHYBASE + reg * 2, data);
277 miir = my_send_cmd_to_phy(sc, MY_OP_WRITE, reg);
282 /* low MDC, prepare MDO */
283 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO);
285 miir |= MY_MASK_MIIR_MII_MDO;
286 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
290 miir |= MY_MASK_MIIR_MII_MDC;
291 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
299 miir &= ~MY_MASK_MIIR_MII_MDC;
300 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
307 * Program the 64-bit multicast hash filter.
310 my_setmulti(struct my_softc * sc)
314 u_int32_t hashes[2] = {0, 0};
315 struct ifmultiaddr *ifma;
323 rxfilt = CSR_READ_4(sc, MY_TCRRCR);
325 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
327 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt);
328 CSR_WRITE_4(sc, MY_MAR0, 0xFFFFFFFF);
329 CSR_WRITE_4(sc, MY_MAR1, 0xFFFFFFFF);
333 /* first, zot all the existing hash bits */
334 CSR_WRITE_4(sc, MY_MAR0, 0);
335 CSR_WRITE_4(sc, MY_MAR1, 0);
337 /* now program new ones */
339 CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
340 if (ifma->ifma_addr->sa_family != AF_LINK)
342 h = ~ether_crc32_be(LLADDR((struct sockaddr_dl *)
343 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
345 hashes[0] |= (1 << h);
347 hashes[1] |= (1 << (h - 32));
350 if_maddr_runlock(ifp);
356 CSR_WRITE_4(sc, MY_MAR0, hashes[0]);
357 CSR_WRITE_4(sc, MY_MAR1, hashes[1]);
358 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt);
363 * Initiate an autonegotiation session.
366 my_autoneg_xmit(struct my_softc * sc)
368 u_int16_t phy_sts = 0;
372 my_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET);
374 while (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_RESET);
376 phy_sts = my_phy_readreg(sc, PHY_BMCR);
377 phy_sts |= PHY_BMCR_AUTONEGENBL | PHY_BMCR_AUTONEGRSTR;
378 my_phy_writereg(sc, PHY_BMCR, phy_sts);
384 my_autoneg_timeout(void *arg)
390 my_autoneg_mii(sc, MY_FLAG_DELAYTIMEO, 1);
394 * Invoke autonegotiation on a PHY.
397 my_autoneg_mii(struct my_softc * sc, int flag, int verbose)
399 u_int16_t phy_sts = 0, media, advert, ability;
400 u_int16_t ability2 = 0;
409 ifm->ifm_media = IFM_ETHER | IFM_AUTO;
411 #ifndef FORCE_AUTONEG_TFOUR
413 * First, see if autoneg is supported. If not, there's no point in
416 phy_sts = my_phy_readreg(sc, PHY_BMSR);
417 if (!(phy_sts & PHY_BMSR_CANAUTONEG)) {
419 device_printf(sc->my_dev,
420 "autonegotiation not supported\n");
421 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX;
426 case MY_FLAG_FORCEDELAY:
428 * XXX Never use this option anywhere but in the probe
429 * routine: making the kernel stop dead in its tracks for
430 * three whole seconds after we've gone multi-user is really
436 case MY_FLAG_SCHEDDELAY:
438 * Wait for the transmitter to go idle before starting an
439 * autoneg session, otherwise my_start() may clobber our
440 * timeout, and we don't want to allow transmission during an
441 * autoneg session since that can screw it up.
443 if (sc->my_cdata.my_tx_head != NULL) {
444 sc->my_want_auto = 1;
449 callout_reset(&sc->my_autoneg_timer, hz * 5, my_autoneg_timeout,
452 sc->my_want_auto = 0;
454 case MY_FLAG_DELAYTIMEO:
455 callout_stop(&sc->my_autoneg_timer);
459 device_printf(sc->my_dev, "invalid autoneg flag: %d\n", flag);
463 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) {
465 device_printf(sc->my_dev, "autoneg complete, ");
466 phy_sts = my_phy_readreg(sc, PHY_BMSR);
469 device_printf(sc->my_dev, "autoneg not complete, ");
472 media = my_phy_readreg(sc, PHY_BMCR);
474 /* Link is good. Report modes and set duplex mode. */
475 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) {
477 device_printf(sc->my_dev, "link status good. ");
478 advert = my_phy_readreg(sc, PHY_ANAR);
479 ability = my_phy_readreg(sc, PHY_LPAR);
480 if ((sc->my_pinfo->my_vid == MarvellPHYID0) ||
481 (sc->my_pinfo->my_vid == LevelOnePHYID0)) {
482 ability2 = my_phy_readreg(sc, PHY_1000SR);
483 if (ability2 & PHY_1000SR_1000BTXFULL) {
487 * this version did not support 1000M,
489 * IFM_ETHER|IFM_1000_T|IFM_FDX;
492 IFM_ETHER | IFM_100_TX | IFM_FDX;
493 media &= ~PHY_BMCR_SPEEDSEL;
494 media |= PHY_BMCR_1000;
495 media |= PHY_BMCR_DUPLEX;
496 printf("(full-duplex, 1000Mbps)\n");
497 } else if (ability2 & PHY_1000SR_1000BTXHALF) {
501 * this version did not support 1000M,
502 * ifm->ifm_media = IFM_ETHER|IFM_1000_T;
504 ifm->ifm_media = IFM_ETHER | IFM_100_TX;
505 media &= ~PHY_BMCR_SPEEDSEL;
506 media &= ~PHY_BMCR_DUPLEX;
507 media |= PHY_BMCR_1000;
508 printf("(half-duplex, 1000Mbps)\n");
511 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) {
512 ifm->ifm_media = IFM_ETHER | IFM_100_T4;
513 media |= PHY_BMCR_SPEEDSEL;
514 media &= ~PHY_BMCR_DUPLEX;
515 printf("(100baseT4)\n");
516 } else if (advert & PHY_ANAR_100BTXFULL &&
517 ability & PHY_ANAR_100BTXFULL) {
518 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX;
519 media |= PHY_BMCR_SPEEDSEL;
520 media |= PHY_BMCR_DUPLEX;
521 printf("(full-duplex, 100Mbps)\n");
522 } else if (advert & PHY_ANAR_100BTXHALF &&
523 ability & PHY_ANAR_100BTXHALF) {
524 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX;
525 media |= PHY_BMCR_SPEEDSEL;
526 media &= ~PHY_BMCR_DUPLEX;
527 printf("(half-duplex, 100Mbps)\n");
528 } else if (advert & PHY_ANAR_10BTFULL &&
529 ability & PHY_ANAR_10BTFULL) {
530 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX;
531 media &= ~PHY_BMCR_SPEEDSEL;
532 media |= PHY_BMCR_DUPLEX;
533 printf("(full-duplex, 10Mbps)\n");
535 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX;
536 media &= ~PHY_BMCR_SPEEDSEL;
537 media &= ~PHY_BMCR_DUPLEX;
538 printf("(half-duplex, 10Mbps)\n");
540 media &= ~PHY_BMCR_AUTONEGENBL;
542 /* Set ASIC's duplex mode to match the PHY. */
543 my_phy_writereg(sc, PHY_BMCR, media);
544 my_setcfg(sc, media);
547 device_printf(sc->my_dev, "no carrier\n");
551 if (sc->my_tx_pend) {
554 my_start_locked(ifp);
560 * To get PHY ability.
563 my_getmode_mii(struct my_softc * sc)
570 bmsr = my_phy_readreg(sc, PHY_BMSR);
572 device_printf(sc->my_dev, "PHY status word: %x\n", bmsr);
575 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX;
577 if (bmsr & PHY_BMSR_10BTHALF) {
579 device_printf(sc->my_dev,
580 "10Mbps half-duplex mode supported\n");
581 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_HDX,
583 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T, 0, NULL);
585 if (bmsr & PHY_BMSR_10BTFULL) {
587 device_printf(sc->my_dev,
588 "10Mbps full-duplex mode supported\n");
590 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX,
592 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX;
594 if (bmsr & PHY_BMSR_100BTXHALF) {
596 device_printf(sc->my_dev,
597 "100Mbps half-duplex mode supported\n");
598 ifp->if_baudrate = 100000000;
599 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL);
600 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_HDX,
602 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX;
604 if (bmsr & PHY_BMSR_100BTXFULL) {
606 device_printf(sc->my_dev,
607 "100Mbps full-duplex mode supported\n");
608 ifp->if_baudrate = 100000000;
609 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX,
611 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX;
613 /* Some also support 100BaseT4. */
614 if (bmsr & PHY_BMSR_100BT4) {
616 device_printf(sc->my_dev, "100baseT4 mode supported\n");
617 ifp->if_baudrate = 100000000;
618 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_T4, 0, NULL);
619 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_T4;
620 #ifdef FORCE_AUTONEG_TFOUR
622 device_printf(sc->my_dev,
623 "forcing on autoneg support for BT4\n");
624 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0 NULL):
625 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO;
628 #if 0 /* this version did not support 1000M, */
629 if (sc->my_pinfo->my_vid == MarvellPHYID0) {
631 device_printf(sc->my_dev,
632 "1000Mbps half-duplex mode supported\n");
634 ifp->if_baudrate = 1000000000;
635 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T, 0, NULL);
636 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_HDX,
639 device_printf(sc->my_dev,
640 "1000Mbps full-duplex mode supported\n");
641 ifp->if_baudrate = 1000000000;
642 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_FDX,
644 sc->ifmedia.ifm_media = IFM_ETHER | IFM_1000_T | IFM_FDX;
647 if (bmsr & PHY_BMSR_CANAUTONEG) {
649 device_printf(sc->my_dev, "autoneg supported\n");
650 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
651 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO;
657 * Set speed and duplex mode.
660 my_setmode_mii(struct my_softc * sc, int media)
666 * If an autoneg session is in progress, stop it.
668 if (sc->my_autoneg) {
669 device_printf(sc->my_dev, "canceling autoneg session\n");
670 callout_stop(&sc->my_autoneg_timer);
671 sc->my_autoneg = sc->my_want_auto = 0;
672 bmcr = my_phy_readreg(sc, PHY_BMCR);
673 bmcr &= ~PHY_BMCR_AUTONEGENBL;
674 my_phy_writereg(sc, PHY_BMCR, bmcr);
676 device_printf(sc->my_dev, "selecting MII, ");
677 bmcr = my_phy_readreg(sc, PHY_BMCR);
678 bmcr &= ~(PHY_BMCR_AUTONEGENBL | PHY_BMCR_SPEEDSEL | PHY_BMCR_1000 |
679 PHY_BMCR_DUPLEX | PHY_BMCR_LOOPBK);
681 #if 0 /* this version did not support 1000M, */
682 if (IFM_SUBTYPE(media) == IFM_1000_T) {
683 printf("1000Mbps/T4, half-duplex\n");
684 bmcr &= ~PHY_BMCR_SPEEDSEL;
685 bmcr &= ~PHY_BMCR_DUPLEX;
686 bmcr |= PHY_BMCR_1000;
689 if (IFM_SUBTYPE(media) == IFM_100_T4) {
690 printf("100Mbps/T4, half-duplex\n");
691 bmcr |= PHY_BMCR_SPEEDSEL;
692 bmcr &= ~PHY_BMCR_DUPLEX;
694 if (IFM_SUBTYPE(media) == IFM_100_TX) {
696 bmcr |= PHY_BMCR_SPEEDSEL;
698 if (IFM_SUBTYPE(media) == IFM_10_T) {
700 bmcr &= ~PHY_BMCR_SPEEDSEL;
702 if ((media & IFM_GMASK) == IFM_FDX) {
703 printf("full duplex\n");
704 bmcr |= PHY_BMCR_DUPLEX;
706 printf("half duplex\n");
707 bmcr &= ~PHY_BMCR_DUPLEX;
709 my_phy_writereg(sc, PHY_BMCR, bmcr);
715 * The Myson manual states that in order to fiddle with the 'full-duplex' and
716 * '100Mbps' bits in the netconfig register, we first have to put the
717 * transmit and/or receive logic in the idle state.
720 my_setcfg(struct my_softc * sc, int bmcr)
725 if (CSR_READ_4(sc, MY_TCRRCR) & (MY_TE | MY_RE)) {
727 MY_CLRBIT(sc, MY_TCRRCR, (MY_TE | MY_RE));
728 for (i = 0; i < MY_TIMEOUT; i++) {
730 if (!(CSR_READ_4(sc, MY_TCRRCR) &
731 (MY_TXRUN | MY_RXRUN)))
735 device_printf(sc->my_dev,
736 "failed to force tx and rx to idle \n");
738 MY_CLRBIT(sc, MY_TCRRCR, MY_PS1000);
739 MY_CLRBIT(sc, MY_TCRRCR, MY_PS10);
740 if (bmcr & PHY_BMCR_1000)
741 MY_SETBIT(sc, MY_TCRRCR, MY_PS1000);
742 else if (!(bmcr & PHY_BMCR_SPEEDSEL))
743 MY_SETBIT(sc, MY_TCRRCR, MY_PS10);
744 if (bmcr & PHY_BMCR_DUPLEX)
745 MY_SETBIT(sc, MY_TCRRCR, MY_FD);
747 MY_CLRBIT(sc, MY_TCRRCR, MY_FD);
749 MY_SETBIT(sc, MY_TCRRCR, MY_TE | MY_RE);
754 my_reset(struct my_softc * sc)
759 MY_SETBIT(sc, MY_BCR, MY_SWR);
760 for (i = 0; i < MY_TIMEOUT; i++) {
762 if (!(CSR_READ_4(sc, MY_BCR) & MY_SWR))
766 device_printf(sc->my_dev, "reset never completed!\n");
768 /* Wait a little while for the chip to get its brains in order. */
774 * Probe for a Myson chip. Check the PCI vendor and device IDs against our
775 * list and return a device name if we find a match.
778 my_probe(device_t dev)
783 while (t->my_name != NULL) {
784 if ((pci_get_vendor(dev) == t->my_vid) &&
785 (pci_get_device(dev) == t->my_did)) {
786 device_set_desc(dev, t->my_name);
788 return (BUS_PROBE_DEFAULT);
796 * Attach the interface. Allocate softc structures, do ifmedia setup and
797 * ethernet/BPF attach.
800 my_attach(device_t dev)
803 u_char eaddr[ETHER_ADDR_LEN];
807 int media = IFM_ETHER | IFM_100_TX | IFM_FDX;
811 u_int16_t phy_vid, phy_did, phy_sts = 0;
814 sc = device_get_softc(dev);
816 mtx_init(&sc->my_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
818 callout_init_mtx(&sc->my_autoneg_timer, &sc->my_mtx, 0);
819 callout_init_mtx(&sc->my_watchdog, &sc->my_mtx, 0);
822 * Map control/status registers.
824 pci_enable_busmaster(dev);
826 if (my_info_tmp->my_did == MTD800ID) {
827 iobase = pci_read_config(dev, MY_PCI_LOIO, 4);
833 sc->my_res = bus_alloc_resource_any(dev, MY_RES, &rid, RF_ACTIVE);
835 if (sc->my_res == NULL) {
836 device_printf(dev, "couldn't map ports/memory\n");
840 sc->my_btag = rman_get_bustag(sc->my_res);
841 sc->my_bhandle = rman_get_bushandle(sc->my_res);
844 sc->my_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
845 RF_SHAREABLE | RF_ACTIVE);
847 if (sc->my_irq == NULL) {
848 device_printf(dev, "couldn't map interrupt\n");
853 sc->my_info = my_info_tmp;
855 /* Reset the adapter. */
861 * Get station address
863 for (i = 0; i < ETHER_ADDR_LEN; ++i)
864 eaddr[i] = CSR_READ_1(sc, MY_PAR0 + i);
866 sc->my_ldata_ptr = malloc(sizeof(struct my_list_data) + 8,
868 if (sc->my_ldata_ptr == NULL) {
869 device_printf(dev, "no memory for list buffers!\n");
873 sc->my_ldata = (struct my_list_data *) sc->my_ldata_ptr;
874 round = (uintptr_t)sc->my_ldata_ptr & 0xF;
875 roundptr = sc->my_ldata_ptr;
876 for (i = 0; i < 8; i++) {
883 sc->my_ldata = (struct my_list_data *) roundptr;
884 bzero(sc->my_ldata, sizeof(struct my_list_data));
886 ifp = sc->my_ifp = if_alloc(IFT_ETHER);
888 device_printf(dev, "can not if_alloc()\n");
893 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
894 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
895 ifp->if_ioctl = my_ioctl;
896 ifp->if_start = my_start;
897 ifp->if_init = my_init;
898 ifp->if_baudrate = 10000000;
899 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
900 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen;
901 IFQ_SET_READY(&ifp->if_snd);
903 if (sc->my_info->my_did == MTD803ID)
904 sc->my_pinfo = my_phys;
907 device_printf(dev, "probing for a PHY\n");
909 for (i = MY_PHYADDR_MIN; i < MY_PHYADDR_MAX + 1; i++) {
911 device_printf(dev, "checking address: %d\n", i);
913 phy_sts = my_phy_readreg(sc, PHY_BMSR);
914 if ((phy_sts != 0) && (phy_sts != 0xffff))
920 phy_vid = my_phy_readreg(sc, PHY_VENID);
921 phy_did = my_phy_readreg(sc, PHY_DEVID);
923 device_printf(dev, "found PHY at address %d, ",
925 printf("vendor id: %x device id: %x\n",
930 if (phy_vid == p->my_vid) {
936 if (sc->my_pinfo == NULL)
937 sc->my_pinfo = &my_phys[PHY_UNKNOWN];
939 device_printf(dev, "PHY type: %s\n",
940 sc->my_pinfo->my_name);
943 device_printf(dev, "MII without any phy!\n");
950 /* Do ifmedia setup. */
951 ifmedia_init(&sc->ifmedia, 0, my_ifmedia_upd, my_ifmedia_sts);
954 my_autoneg_mii(sc, MY_FLAG_FORCEDELAY, 1);
955 media = sc->ifmedia.ifm_media;
958 ifmedia_set(&sc->ifmedia, media);
960 ether_ifattach(ifp, eaddr);
962 error = bus_setup_intr(dev, sc->my_irq, INTR_TYPE_NET | INTR_MPSAFE,
963 NULL, my_intr, sc, &sc->my_intrhand);
966 device_printf(dev, "couldn't set up irq\n");
977 free(sc->my_ldata_ptr, M_DEVBUF);
979 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq);
981 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res);
983 mtx_destroy(&sc->my_mtx);
988 my_detach(device_t dev)
993 sc = device_get_softc(dev);
999 bus_teardown_intr(dev, sc->my_irq, sc->my_intrhand);
1000 callout_drain(&sc->my_watchdog);
1001 callout_drain(&sc->my_autoneg_timer);
1004 free(sc->my_ldata_ptr, M_DEVBUF);
1006 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq);
1007 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res);
1008 mtx_destroy(&sc->my_mtx);
1014 * Initialize the transmit descriptors.
1017 my_list_tx_init(struct my_softc * sc)
1019 struct my_chain_data *cd;
1020 struct my_list_data *ld;
1026 for (i = 0; i < MY_TX_LIST_CNT; i++) {
1027 cd->my_tx_chain[i].my_ptr = &ld->my_tx_list[i];
1028 if (i == (MY_TX_LIST_CNT - 1))
1029 cd->my_tx_chain[i].my_nextdesc = &cd->my_tx_chain[0];
1031 cd->my_tx_chain[i].my_nextdesc =
1032 &cd->my_tx_chain[i + 1];
1034 cd->my_tx_free = &cd->my_tx_chain[0];
1035 cd->my_tx_tail = cd->my_tx_head = NULL;
1040 * Initialize the RX descriptors and allocate mbufs for them. Note that we
1041 * arrange the descriptors in a closed ring, so that the last descriptor
1042 * points back to the first.
1045 my_list_rx_init(struct my_softc * sc)
1047 struct my_chain_data *cd;
1048 struct my_list_data *ld;
1054 for (i = 0; i < MY_RX_LIST_CNT; i++) {
1055 cd->my_rx_chain[i].my_ptr =
1056 (struct my_desc *) & ld->my_rx_list[i];
1057 if (my_newbuf(sc, &cd->my_rx_chain[i]) == ENOBUFS) {
1061 if (i == (MY_RX_LIST_CNT - 1)) {
1062 cd->my_rx_chain[i].my_nextdesc = &cd->my_rx_chain[0];
1063 ld->my_rx_list[i].my_next = vtophys(&ld->my_rx_list[0]);
1065 cd->my_rx_chain[i].my_nextdesc =
1066 &cd->my_rx_chain[i + 1];
1067 ld->my_rx_list[i].my_next =
1068 vtophys(&ld->my_rx_list[i + 1]);
1071 cd->my_rx_head = &cd->my_rx_chain[0];
1076 * Initialize an RX descriptor and attach an MBUF cluster.
1079 my_newbuf(struct my_softc * sc, struct my_chain_onefrag * c)
1081 struct mbuf *m_new = NULL;
1084 MGETHDR(m_new, M_NOWAIT, MT_DATA);
1085 if (m_new == NULL) {
1086 device_printf(sc->my_dev,
1087 "no memory for rx list -- packet dropped!\n");
1090 if (!(MCLGET(m_new, M_NOWAIT))) {
1091 device_printf(sc->my_dev,
1092 "no memory for rx list -- packet dropped!\n");
1097 c->my_ptr->my_data = vtophys(mtod(m_new, caddr_t));
1098 c->my_ptr->my_ctl = (MCLBYTES - 1) << MY_RBSShift;
1099 c->my_ptr->my_status = MY_OWNByNIC;
1104 * A frame has been uploaded: pass the resulting mbuf chain up to the higher
1108 my_rxeof(struct my_softc * sc)
1110 struct ether_header *eh;
1113 struct my_chain_onefrag *cur_rx;
1119 while (!((rxstat = sc->my_cdata.my_rx_head->my_ptr->my_status)
1121 cur_rx = sc->my_cdata.my_rx_head;
1122 sc->my_cdata.my_rx_head = cur_rx->my_nextdesc;
1124 if (rxstat & MY_ES) { /* error summary: give up this rx pkt */
1125 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1126 cur_rx->my_ptr->my_status = MY_OWNByNIC;
1129 /* No errors; receive the packet. */
1130 total_len = (rxstat & MY_FLNGMASK) >> MY_FLNGShift;
1131 total_len -= ETHER_CRC_LEN;
1133 if (total_len < MINCLSIZE) {
1134 m = m_devget(mtod(cur_rx->my_mbuf, char *),
1135 total_len, 0, ifp, NULL);
1136 cur_rx->my_ptr->my_status = MY_OWNByNIC;
1138 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1142 m = cur_rx->my_mbuf;
1144 * Try to conjure up a new mbuf cluster. If that
1145 * fails, it means we have an out of memory condition
1146 * and should leave the buffer in place and continue.
1147 * This will result in a lost packet, but there's
1148 * little else we can do in this situation.
1150 if (my_newbuf(sc, cur_rx) == ENOBUFS) {
1151 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1152 cur_rx->my_ptr->my_status = MY_OWNByNIC;
1155 m->m_pkthdr.rcvif = ifp;
1156 m->m_pkthdr.len = m->m_len = total_len;
1158 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
1159 eh = mtod(m, struct ether_header *);
1162 * Handle BPF listeners. Let the BPF user see the packet, but
1163 * don't pass it up to the ether_input() layer unless it's a
1164 * broadcast packet, multicast packet, matches our ethernet
1165 * address or the interface is in promiscuous mode.
1167 if (bpf_peers_present(ifp->if_bpf)) {
1168 bpf_mtap(ifp->if_bpf, m);
1169 if (ifp->if_flags & IFF_PROMISC &&
1170 (bcmp(eh->ether_dhost, IF_LLADDR(sc->my_ifp),
1172 (eh->ether_dhost[0] & 1) == 0)) {
1179 (*ifp->if_input)(ifp, m);
1187 * A frame was downloaded to the chip. It's safe for us to clean up the list
1191 my_txeof(struct my_softc * sc)
1193 struct my_chain *cur_tx;
1198 /* Clear the timeout timer. */
1200 if (sc->my_cdata.my_tx_head == NULL) {
1204 * Go through our tx list and free mbufs for those frames that have
1207 while (sc->my_cdata.my_tx_head->my_mbuf != NULL) {
1210 cur_tx = sc->my_cdata.my_tx_head;
1211 txstat = MY_TXSTATUS(cur_tx);
1212 if ((txstat & MY_OWNByNIC) || txstat == MY_UNSENT)
1214 if (!(CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced)) {
1215 if (txstat & MY_TXERR) {
1216 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1217 if (txstat & MY_EC) /* excessive collision */
1218 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
1219 if (txstat & MY_LC) /* late collision */
1220 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
1222 if_inc_counter(ifp, IFCOUNTER_COLLISIONS,
1223 (txstat & MY_NCRMASK) >> MY_NCRShift);
1225 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
1226 m_freem(cur_tx->my_mbuf);
1227 cur_tx->my_mbuf = NULL;
1228 if (sc->my_cdata.my_tx_head == sc->my_cdata.my_tx_tail) {
1229 sc->my_cdata.my_tx_head = NULL;
1230 sc->my_cdata.my_tx_tail = NULL;
1233 sc->my_cdata.my_tx_head = cur_tx->my_nextdesc;
1235 if (CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced) {
1236 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, (CSR_READ_4(sc, MY_TSR) & MY_NCRMask));
1242 * TX 'end of channel' interrupt handler.
1245 my_txeoc(struct my_softc * sc)
1252 if (sc->my_cdata.my_tx_head == NULL) {
1253 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1254 sc->my_cdata.my_tx_tail = NULL;
1255 if (sc->my_want_auto)
1256 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1);
1258 if (MY_TXOWN(sc->my_cdata.my_tx_head) == MY_UNSENT) {
1259 MY_TXOWN(sc->my_cdata.my_tx_head) = MY_OWNByNIC;
1261 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF);
1270 struct my_softc *sc;
1277 if (!(ifp->if_flags & IFF_UP)) {
1281 /* Disable interrupts. */
1282 CSR_WRITE_4(sc, MY_IMR, 0x00000000);
1285 status = CSR_READ_4(sc, MY_ISR);
1288 CSR_WRITE_4(sc, MY_ISR, status);
1292 if (status & MY_RI) /* receive interrupt */
1295 if ((status & MY_RBU) || (status & MY_RxErr)) {
1296 /* rx buffer unavailable or rx error */
1297 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1304 if (status & MY_TI) /* tx interrupt */
1306 if (status & MY_ETI) /* tx early interrupt */
1308 if (status & MY_TBU) /* tx buffer unavailable */
1311 #if 0 /* 90/1/18 delete */
1312 if (status & MY_FBE) {
1320 /* Re-enable interrupts. */
1321 CSR_WRITE_4(sc, MY_IMR, MY_INTRS);
1322 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1323 my_start_locked(ifp);
1329 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1330 * pointers to the fragment pointers.
1333 my_encap(struct my_softc * sc, struct my_chain * c, struct mbuf * m_head)
1335 struct my_desc *f = NULL;
1337 struct mbuf *m, *m_new = NULL;
1340 /* calculate the total tx pkt length */
1342 for (m = m_head; m != NULL; m = m->m_next)
1343 total_len += m->m_len;
1345 * Start packing the mbufs in this chain into the fragment pointers.
1346 * Stop when we run out of fragments or hit the end of the mbuf
1350 MGETHDR(m_new, M_NOWAIT, MT_DATA);
1351 if (m_new == NULL) {
1352 device_printf(sc->my_dev, "no memory for tx list");
1355 if (m_head->m_pkthdr.len > MHLEN) {
1356 if (!(MCLGET(m_new, M_NOWAIT))) {
1358 device_printf(sc->my_dev, "no memory for tx list");
1362 m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t));
1363 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1366 f = &c->my_ptr->my_frag[0];
1368 f->my_data = vtophys(mtod(m_new, caddr_t));
1369 total_len = m_new->m_len;
1370 f->my_ctl = MY_TXFD | MY_TXLD | MY_CRCEnable | MY_PADEnable;
1371 f->my_ctl |= total_len << MY_PKTShift; /* pkt size */
1372 f->my_ctl |= total_len; /* buffer size */
1373 /* 89/12/29 add, for mtd891 *//* [ 89? ] */
1374 if (sc->my_info->my_did == MTD891ID)
1375 f->my_ctl |= MY_ETIControl | MY_RetryTxLC;
1376 c->my_mbuf = m_head;
1378 MY_TXNEXT(c) = vtophys(&c->my_nextdesc->my_ptr->my_frag[0]);
1383 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1384 * to the mbuf data regions directly in the transmit lists. We also save a
1385 * copy of the pointers since the transmit list fragment pointers are
1386 * physical addresses.
1389 my_start(struct ifnet * ifp)
1391 struct my_softc *sc;
1395 my_start_locked(ifp);
1400 my_start_locked(struct ifnet * ifp)
1402 struct my_softc *sc;
1403 struct mbuf *m_head = NULL;
1404 struct my_chain *cur_tx = NULL, *start_tx;
1408 if (sc->my_autoneg) {
1413 * Check for an available queue slot. If there are none, punt.
1415 if (sc->my_cdata.my_tx_free->my_mbuf != NULL) {
1416 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1419 start_tx = sc->my_cdata.my_tx_free;
1420 while (sc->my_cdata.my_tx_free->my_mbuf == NULL) {
1421 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1425 /* Pick a descriptor off the free list. */
1426 cur_tx = sc->my_cdata.my_tx_free;
1427 sc->my_cdata.my_tx_free = cur_tx->my_nextdesc;
1429 /* Pack the data into the descriptor. */
1430 my_encap(sc, cur_tx, m_head);
1432 if (cur_tx != start_tx)
1433 MY_TXOWN(cur_tx) = MY_OWNByNIC;
1436 * If there's a BPF listener, bounce a copy of this frame to
1439 BPF_MTAP(ifp, cur_tx->my_mbuf);
1443 * If there are no packets queued, bail.
1445 if (cur_tx == NULL) {
1449 * Place the request for the upload interrupt in the last descriptor
1450 * in the chain. This way, if we're chaining several packets at once,
1451 * we'll only get an interrupt once for the whole chain rather than
1452 * once for each packet.
1454 MY_TXCTL(cur_tx) |= MY_TXIC;
1455 cur_tx->my_ptr->my_frag[0].my_ctl |= MY_TXIC;
1456 sc->my_cdata.my_tx_tail = cur_tx;
1457 if (sc->my_cdata.my_tx_head == NULL)
1458 sc->my_cdata.my_tx_head = start_tx;
1459 MY_TXOWN(start_tx) = MY_OWNByNIC;
1460 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF); /* tx polling demand */
1463 * Set a timeout in case the chip goes out to lunch.
1472 struct my_softc *sc = xsc;
1480 my_init_locked(struct my_softc *sc)
1482 struct ifnet *ifp = sc->my_ifp;
1483 u_int16_t phy_bmcr = 0;
1486 if (sc->my_autoneg) {
1489 if (sc->my_pinfo != NULL)
1490 phy_bmcr = my_phy_readreg(sc, PHY_BMCR);
1492 * Cancel pending I/O and free all RX/TX buffers.
1498 * Set cache alignment and burst length.
1500 #if 0 /* 89/9/1 modify, */
1501 CSR_WRITE_4(sc, MY_BCR, MY_RPBLE512);
1502 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF);
1504 CSR_WRITE_4(sc, MY_BCR, MY_PBL8);
1505 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF | MY_RBLEN | MY_RPBLE512);
1507 * 89/12/29 add, for mtd891,
1509 if (sc->my_info->my_did == MTD891ID) {
1510 MY_SETBIT(sc, MY_BCR, MY_PROG);
1511 MY_SETBIT(sc, MY_TCRRCR, MY_Enhanced);
1513 my_setcfg(sc, phy_bmcr);
1514 /* Init circular RX list. */
1515 if (my_list_rx_init(sc) == ENOBUFS) {
1516 device_printf(sc->my_dev, "init failed: no memory for rx buffers\n");
1520 /* Init TX descriptors. */
1521 my_list_tx_init(sc);
1523 /* If we want promiscuous mode, set the allframes bit. */
1524 if (ifp->if_flags & IFF_PROMISC)
1525 MY_SETBIT(sc, MY_TCRRCR, MY_PROM);
1527 MY_CLRBIT(sc, MY_TCRRCR, MY_PROM);
1530 * Set capture broadcast bit to capture broadcast frames.
1532 if (ifp->if_flags & IFF_BROADCAST)
1533 MY_SETBIT(sc, MY_TCRRCR, MY_AB);
1535 MY_CLRBIT(sc, MY_TCRRCR, MY_AB);
1538 * Program the multicast filter, if necessary.
1543 * Load the address of the RX list.
1545 MY_CLRBIT(sc, MY_TCRRCR, MY_RE);
1546 CSR_WRITE_4(sc, MY_RXLBA, vtophys(&sc->my_ldata->my_rx_list[0]));
1549 * Enable interrupts.
1551 CSR_WRITE_4(sc, MY_IMR, MY_INTRS);
1552 CSR_WRITE_4(sc, MY_ISR, 0xFFFFFFFF);
1554 /* Enable receiver and transmitter. */
1555 MY_SETBIT(sc, MY_TCRRCR, MY_RE);
1556 MY_CLRBIT(sc, MY_TCRRCR, MY_TE);
1557 CSR_WRITE_4(sc, MY_TXLBA, vtophys(&sc->my_ldata->my_tx_list[0]));
1558 MY_SETBIT(sc, MY_TCRRCR, MY_TE);
1560 /* Restore state of BMCR */
1561 if (sc->my_pinfo != NULL)
1562 my_phy_writereg(sc, PHY_BMCR, phy_bmcr);
1563 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1564 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1566 callout_reset(&sc->my_watchdog, hz, my_watchdog, sc);
1571 * Set media options.
1575 my_ifmedia_upd(struct ifnet * ifp)
1577 struct my_softc *sc;
1578 struct ifmedia *ifm;
1583 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) {
1587 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO)
1588 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1);
1590 my_setmode_mii(sc, ifm->ifm_media);
1596 * Report current media status.
1600 my_ifmedia_sts(struct ifnet * ifp, struct ifmediareq * ifmr)
1602 struct my_softc *sc;
1603 u_int16_t advert = 0, ability = 0;
1607 ifmr->ifm_active = IFM_ETHER;
1608 if (!(my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) {
1609 #if 0 /* this version did not support 1000M, */
1610 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_1000)
1611 ifmr->ifm_active = IFM_ETHER | IFM_1000TX;
1613 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL)
1614 ifmr->ifm_active = IFM_ETHER | IFM_100_TX;
1616 ifmr->ifm_active = IFM_ETHER | IFM_10_T;
1617 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX)
1618 ifmr->ifm_active |= IFM_FDX;
1620 ifmr->ifm_active |= IFM_HDX;
1625 ability = my_phy_readreg(sc, PHY_LPAR);
1626 advert = my_phy_readreg(sc, PHY_ANAR);
1628 #if 0 /* this version did not support 1000M, */
1629 if (sc->my_pinfo->my_vid = MarvellPHYID0) {
1630 ability2 = my_phy_readreg(sc, PHY_1000SR);
1631 if (ability2 & PHY_1000SR_1000BTXFULL) {
1634 ifmr->ifm_active = IFM_ETHER|IFM_1000_T|IFM_FDX;
1635 } else if (ability & PHY_1000SR_1000BTXHALF) {
1638 ifmr->ifm_active = IFM_ETHER|IFM_1000_T|IFM_HDX;
1642 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4)
1643 ifmr->ifm_active = IFM_ETHER | IFM_100_T4;
1644 else if (advert & PHY_ANAR_100BTXFULL && ability & PHY_ANAR_100BTXFULL)
1645 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1646 else if (advert & PHY_ANAR_100BTXHALF && ability & PHY_ANAR_100BTXHALF)
1647 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_HDX;
1648 else if (advert & PHY_ANAR_10BTFULL && ability & PHY_ANAR_10BTFULL)
1649 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_FDX;
1650 else if (advert & PHY_ANAR_10BTHALF && ability & PHY_ANAR_10BTHALF)
1651 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_HDX;
1657 my_ioctl(struct ifnet * ifp, u_long command, caddr_t data)
1659 struct my_softc *sc = ifp->if_softc;
1660 struct ifreq *ifr = (struct ifreq *) data;
1666 if (ifp->if_flags & IFF_UP)
1668 else if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1682 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
1685 error = ether_ioctl(ifp, command, data);
1692 my_watchdog(void *arg)
1694 struct my_softc *sc;
1699 callout_reset(&sc->my_watchdog, hz, my_watchdog, sc);
1700 if (sc->my_timer == 0 || --sc->my_timer > 0)
1704 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1705 if_printf(ifp, "watchdog timeout\n");
1706 if (!(my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT))
1707 if_printf(ifp, "no carrier - transceiver cable problem?\n");
1711 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1712 my_start_locked(ifp);
1717 * Stop the adapter and free any mbufs allocated to the RX and TX lists.
1720 my_stop(struct my_softc * sc)
1728 callout_stop(&sc->my_autoneg_timer);
1729 callout_stop(&sc->my_watchdog);
1731 MY_CLRBIT(sc, MY_TCRRCR, (MY_RE | MY_TE));
1732 CSR_WRITE_4(sc, MY_IMR, 0x00000000);
1733 CSR_WRITE_4(sc, MY_TXLBA, 0x00000000);
1734 CSR_WRITE_4(sc, MY_RXLBA, 0x00000000);
1737 * Free data in the RX lists.
1739 for (i = 0; i < MY_RX_LIST_CNT; i++) {
1740 if (sc->my_cdata.my_rx_chain[i].my_mbuf != NULL) {
1741 m_freem(sc->my_cdata.my_rx_chain[i].my_mbuf);
1742 sc->my_cdata.my_rx_chain[i].my_mbuf = NULL;
1745 bzero((char *)&sc->my_ldata->my_rx_list,
1746 sizeof(sc->my_ldata->my_rx_list));
1748 * Free the TX list buffers.
1750 for (i = 0; i < MY_TX_LIST_CNT; i++) {
1751 if (sc->my_cdata.my_tx_chain[i].my_mbuf != NULL) {
1752 m_freem(sc->my_cdata.my_tx_chain[i].my_mbuf);
1753 sc->my_cdata.my_tx_chain[i].my_mbuf = NULL;
1756 bzero((char *)&sc->my_ldata->my_tx_list,
1757 sizeof(sc->my_ldata->my_tx_list));
1758 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1763 * Stop all chip I/O so that the kernel's probe routines don't get confused
1764 * by errant DMAs when rebooting.
1767 my_shutdown(device_t dev)
1769 struct my_softc *sc;
1771 sc = device_get_softc(dev);