2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2002 Myson Technology Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification, immediately at the beginning of the file.
13 * 2. The name of the author may not be used to endorse or promote products
14 * derived from this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
20 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * Written by: yen_cw@myson.com.tw available at: http://www.myson.com.tw/
32 * Myson MTD80x register definitions.
35 #define MY_PAR0 0x0 /* physical address 0-3 */
36 #define MY_PAR1 0x04 /* physical address 4-5 */
37 #define MY_MAR0 0x08 /* multicast address 0-3 */
38 #define MY_MAR1 0x0C /* multicast address 4-7 */
39 #define MY_FAR0 0x10 /* flow-control address 0-3 */
40 #define MY_FAR1 0x14 /* flow-control address 4-5 */
41 #define MY_TCRRCR 0x18 /* receive & transmit configuration */
42 #define MY_BCR 0x1C /* bus command */
43 #define MY_TXPDR 0x20 /* transmit polling demand */
44 #define MY_RXPDR 0x24 /* receive polling demand */
45 #define MY_RXCWP 0x28 /* receive current word pointer */
46 #define MY_TXLBA 0x2C /* transmit list base address */
47 #define MY_RXLBA 0x30 /* receive list base address */
48 #define MY_ISR 0x34 /* interrupt status */
49 #define MY_IMR 0x38 /* interrupt mask */
50 #define MY_FTH 0x3C /* flow control high/low threshold */
51 #define MY_MANAGEMENT 0x40 /* bootrom/eeprom and mii management */
52 #define MY_TALLY 0x44 /* tally counters for crc and mpa */
53 #define MY_TSR 0x48 /* tally counter for transmit status */
54 #define MY_PHYBASE 0x4c
57 * Receive Configuration Register
59 #define MY_RXRUN 0x00008000 /* receive running status */
60 #define MY_EIEN 0x00004000 /* early interrupt enable */
61 #define MY_RFCEN 0x00002000 /* receive flow control packet enable */
62 #define MY_NDFA 0x00001000 /* not defined flow control address */
63 #define MY_RBLEN 0x00000800 /* receive burst length enable */
64 #define MY_RPBLE1 0x00000000 /* 1 word */
65 #define MY_RPBLE4 0x00000100 /* 4 words */
66 #define MY_RPBLE8 0x00000200 /* 8 words */
67 #define MY_RPBLE16 0x00000300 /* 16 words */
68 #define MY_RPBLE32 0x00000400 /* 32 words */
69 #define MY_RPBLE64 0x00000500 /* 64 words */
70 #define MY_RPBLE128 0x00000600 /* 128 words */
71 #define MY_RPBLE512 0x00000700 /* 512 words */
72 #define MY_PROM 0x000000080 /* promiscuous mode */
73 #define MY_AB 0x000000040 /* accept broadcast */
74 #define MY_AM 0x000000020 /* accept mutlicast */
75 #define MY_ARP 0x000000008 /* receive runt pkt */
76 #define MY_ALP 0x000000004 /* receive long pkt */
77 #define MY_SEP 0x000000002 /* receive error pkt */
78 #define MY_RE 0x000000001 /* receive enable */
81 * Transmit Configuration Register
83 #define MY_TXRUN 0x04000000 /* transmit running status */
84 #define MY_Enhanced 0x02000000 /* transmit enhanced mode */
85 #define MY_TFCEN 0x01000000 /* tx flow control packet enable */
86 #define MY_TFT64 0x00000000 /* 64 bytes */
87 #define MY_TFT32 0x00200000 /* 32 bytes */
88 #define MY_TFT128 0x00400000 /* 128 bytes */
89 #define MY_TFT256 0x00600000 /* 256 bytes */
90 #define MY_TFT512 0x00800000 /* 512 bytes */
91 #define MY_TFT768 0x00A00000 /* 768 bytes */
92 #define MY_TFT1024 0x00C00000 /* 1024 bytes */
93 #define MY_TFTSF 0x00E00000 /* store and forward */
94 #define MY_FD 0x00100000 /* full duplex mode */
95 #define MY_PS10 0x00080000 /* port speed is 10M */
96 #define MY_TE 0x00040000 /* transmit enable */
97 #define MY_PS1000 0x00010000 /* port speed is 1000M */
99 * Bus Command Register
101 #define MY_PROG 0x00000200 /* programming */
102 #define MY_RLE 0x00000100 /* read line command enable */
103 #define MY_RME 0x00000080 /* read multiple command enable */
104 #define MY_WIE 0x00000040 /* write and invalidate cmd enable */
105 #define MY_PBL1 0x00000000 /* 1 dword */
106 #define MY_PBL4 0x00000008 /* 4 dwords */
107 #define MY_PBL8 0x00000010 /* 8 dwords */
108 #define MY_PBL16 0x00000018 /* 16 dwords */
109 #define MY_PBL32 0x00000020 /* 32 dwords */
110 #define MY_PBL64 0x00000028 /* 64 dwords */
111 #define MY_PBL128 0x00000030 /* 128 dwords */
112 #define MY_PBL512 0x00000038 /* 512 dwords */
113 #define MY_ABR 0x00000004 /* arbitration rule */
114 #define MY_BLS 0x00000002 /* big/little endian select */
115 #define MY_SWR 0x00000001 /* software reset */
118 * Transmit Poll Demand Register
120 #define MY_TxPollDemand 0x1
123 * Receive Poll Demand Register
125 #define MY_RxPollDemand 0x01
128 * Interrupt Status Register
130 #define MY_RFCON 0x00020000 /* receive flow control xon packet */
131 #define MY_RFCOFF 0x00010000 /* receive flow control xoff packet */
132 #define MY_LSCStatus 0x00008000 /* link status change */
133 #define MY_ANCStatus 0x00004000 /* autonegotiation completed */
134 #define MY_FBE 0x00002000 /* fatal bus error */
135 #define MY_FBEMask 0x00001800
136 #define MY_ParityErr 0x00000000 /* parity error */
137 #define MY_MasterErr 0x00000800 /* master error */
138 #define MY_TargetErr 0x00001000 /* target abort */
139 #define MY_TUNF 0x00000400 /* transmit underflow */
140 #define MY_ROVF 0x00000200 /* receive overflow */
141 #define MY_ETI 0x00000100 /* transmit early int */
142 #define MY_ERI 0x00000080 /* receive early int */
143 #define MY_CNTOVF 0x00000040 /* counter overflow */
144 #define MY_RBU 0x00000020 /* receive buffer unavailable */
145 #define MY_TBU 0x00000010 /* transmit buffer unavilable */
146 #define MY_TI 0x00000008 /* transmit interrupt */
147 #define MY_RI 0x00000004 /* receive interrupt */
148 #define MY_RxErr 0x00000002 /* receive error */
151 * Interrupt Mask Register
153 #define MY_MRFCON 0x00020000 /* receive flow control xon packet */
154 #define MY_MRFCOFF 0x00010000 /* receive flow control xoff packet */
155 #define MY_MLSCStatus 0x00008000 /* link status change */
156 #define MY_MANCStatus 0x00004000 /* autonegotiation completed */
157 #define MY_MFBE 0x00002000 /* fatal bus error */
158 #define MY_MFBEMask 0x00001800
159 #define MY_MTUNF 0x00000400 /* transmit underflow */
160 #define MY_MROVF 0x00000200 /* receive overflow */
161 #define MY_METI 0x00000100 /* transmit early int */
162 #define MY_MERI 0x00000080 /* receive early int */
163 #define MY_MCNTOVF 0x00000040 /* counter overflow */
164 #define MY_MRBU 0x00000020 /* receive buffer unavailable */
165 #define MY_MTBU 0x00000010 /* transmit buffer unavilable */
166 #define MY_MTI 0x00000008 /* transmit interrupt */
167 #define MY_MRI 0x00000004 /* receive interrupt */
168 #define MY_MRxErr 0x00000002 /* receive error */
171 /* #define MY_INTRS MY_FBE|MY_MRBU|MY_TBU|MY_MTI|MY_MRI|MY_METI */
172 #define MY_INTRS MY_MRBU|MY_TBU|MY_MTI|MY_MRI|MY_METI
175 * Flow Control High/Low Threshold Register
177 #define MY_FCHTShift 16 /* flow control high threshold */
178 #define MY_FCLTShift 0 /* flow control low threshold */
181 * BootROM/EEPROM/MII Management Register
183 #define MY_MASK_MIIR_MII_READ 0x00000000
184 #define MY_MASK_MIIR_MII_WRITE 0x00000008
185 #define MY_MASK_MIIR_MII_MDO 0x00000004
186 #define MY_MASK_MIIR_MII_MDI 0x00000002
187 #define MY_MASK_MIIR_MII_MDC 0x00000001
190 * Tally Counter for CRC and MPA
192 #define MY_TCOVF 0x80000000 /* crc tally counter overflow */
193 #define MY_CRCMask 0x7fff0000 /* crc number: bit 16-30 */
194 #define MY_CRCShift 16
195 #define MY_TMOVF 0x00008000 /* mpa tally counter overflow */
196 #define MY_MPAMask 0x00007fff /* mpa number: bit 0-14 */
197 #define MY_MPAShift 0
200 * Tally Counters for transmit status
202 #define MY_AbortMask 0xff000000 /* transmit abort number */
203 #define MY_AbortShift 24
204 #define MY_LColMask 0x00ff0000 /* transmit late collisions */
205 #define MY_LColShift 16
206 #define MY_NCRMask 0x0000ffff /* transmit retry number */
207 #define MY_NCRShift 0
210 * Myson TX/RX descriptor structure.
221 * for tx/rx descriptors
223 #define MY_OWNByNIC 0x80000000
224 #define MY_OWNByDriver 0x0
227 * receive descriptor 0
229 #define MY_RXOWN 0x80000000 /* own bit */
230 #define MY_FLNGMASK 0x0fff0000 /* frame length */
231 #define MY_FLNGShift 16
232 #define MY_MARSTATUS 0x00004000 /* multicast address received */
233 #define MY_BARSTATUS 0x00002000 /* broadcast address received */
234 #define MY_PHYSTATUS 0x00001000 /* physical address received */
235 #define MY_RXFSD 0x00000800 /* first descriptor */
236 #define MY_RXLSD 0x00000400 /* last descriptor */
237 #define MY_ES 0x00000080 /* error summary */
238 #define MY_RUNT 0x00000040 /* runt packet received */
239 #define MY_LONG 0x00000020 /* long packet received */
240 #define MY_FAE 0x00000010 /* frame align error */
241 #define MY_CRC 0x00000008 /* crc error */
242 #define MY_RXER 0x00000004 /* receive error */
243 #define MY_RDES0CHECK 0x000078fc /* only check MAR, BAR, PHY, ES, RUNT,
244 LONG, FAE, CRC and RXER bits */
247 * receive descriptor 1
249 #define MY_RXIC 0x00800000 /* interrupt control */
250 #define MY_RBSMASK 0x000007ff /* receive buffer size */
251 #define MY_RBSShift 0
254 * transmit descriptor 0
256 #define MY_TXERR 0x00008000 /* transmit error */
257 #define MY_JABTO 0x00004000 /* jabber timeout */
258 #define MY_CSL 0x00002000 /* carrier sense lost */
259 #define MY_LC 0x00001000 /* late collision */
260 #define MY_EC 0x00000800 /* excessive collision */
261 #define MY_UDF 0x00000400 /* fifo underflow */
262 #define MY_DFR 0x00000200 /* deferred */
263 #define MY_HF 0x00000100 /* heartbeat fail */
264 #define MY_NCRMASK 0x000000ff /* collision retry count */
265 #define MY_NCRShift 0
270 #define MY_TXIC 0x80000000 /* interrupt control */
271 #define MY_ETIControl 0x40000000 /* early transmit interrupt */
272 #define MY_TXLD 0x20000000 /* last descriptor */
273 #define MY_TXFD 0x10000000 /* first descriptor */
274 #define MY_CRCDisable 0x00000000 /* crc control */
275 #define MY_CRCEnable 0x08000000
276 #define MY_PADDisable 0x00000000 /* padding control */
277 #define MY_PADEnable 0x04000000
278 #define MY_RetryTxLC 0x02000000 /* retry late collision */
279 #define MY_PKTShift 11 /* transmit pkt size */
280 #define MY_TBSMASK 0x000007ff
281 #define MY_TBSShift 0 /* transmit buffer size */
283 #define MY_MAXFRAGS 1
284 #define MY_RX_LIST_CNT 64
285 #define MY_TX_LIST_CNT 64
286 #define MY_MIN_FRAMELEN 60
289 * A transmit 'super descriptor' is actually MY_MAXFRAGS regular
290 * descriptors clumped together. The idea here is to emulate the
291 * multi-fragment descriptor layout found in devices such as the
292 * Texas Instruments ThunderLAN and 3Com boomerang and cylone chips.
293 * The advantage to using this scheme is that it avoids buffer copies.
294 * The disadvantage is that there's a certain amount of overhead due
295 * to the fact that each 'fragment' is 16 bytes long. In my tests,
296 * this limits top speed to about 10.5MB/sec. It should be more like
297 * 11.5MB/sec. However, the upshot is that you can achieve better
298 * results on slower machines: a Pentium 200 can pump out packets at
299 * same speed as a PII 400.
302 struct my_desc my_frag[MY_MAXFRAGS];
305 #define MY_TXSTATUS(x) x->my_ptr->my_frag[x->my_lastdesc].my_status
306 #define MY_TXCTL(x) x->my_ptr->my_frag[x->my_lastdesc].my_ctl
307 #define MY_TXDATA(x) x->my_ptr->my_frag[x->my_lastdesc].my_data
308 #define MY_TXNEXT(x) x->my_ptr->my_frag[x->my_lastdesc].my_next
310 #define MY_TXOWN(x) x->my_ptr->my_frag[0].my_status
312 #define MY_UNSENT 0x1234
314 struct my_list_data {
315 struct my_desc my_rx_list[MY_RX_LIST_CNT];
316 struct my_txdesc my_tx_list[MY_TX_LIST_CNT];
320 struct my_txdesc *my_ptr;
321 struct mbuf *my_mbuf;
322 struct my_chain *my_nextdesc;
323 u_int8_t my_lastdesc;
326 struct my_chain_onefrag {
327 struct my_desc *my_ptr;
328 struct mbuf *my_mbuf;
329 struct my_chain_onefrag *my_nextdesc;
333 struct my_chain_data {
334 struct my_chain_onefrag my_rx_chain[MY_RX_LIST_CNT];
335 struct my_chain my_tx_chain[MY_TX_LIST_CNT];
337 struct my_chain_onefrag *my_rx_head;
339 struct my_chain *my_tx_head;
340 struct my_chain *my_tx_tail;
341 struct my_chain *my_tx_free;
350 #define MY_FLAG_FORCEDELAY 1
351 #define MY_FLAG_SCHEDDELAY 2
352 #define MY_FLAG_DELAYTIMEO 3
355 struct ifnet *my_ifp;
357 struct ifmedia ifmedia; /* media info */
358 bus_space_handle_t my_bhandle;
359 bus_space_tag_t my_btag;
360 struct my_type *my_info; /* adapter info */
361 struct my_type *my_pinfo; /* phy info */
362 struct resource *my_res;
363 struct resource *my_irq;
365 u_int8_t my_phy_addr; /* PHY address */
366 u_int8_t my_tx_pend; /* TX pending */
367 u_int8_t my_want_auto;
369 u_int16_t my_txthresh;
370 u_int8_t my_stats_no_timeout;
371 caddr_t my_ldata_ptr;
372 struct my_list_data *my_ldata;
373 struct my_chain_data my_cdata;
375 /* Add by Surfer 2001/12/2 */
377 struct callout my_autoneg_timer;
378 struct callout my_watchdog;
382 /* Add by Surfer 2001/12/2 */
383 #define MY_LOCK(_sc) mtx_lock(&(_sc)->my_mtx)
384 #define MY_UNLOCK(_sc) mtx_unlock(&(_sc)->my_mtx)
385 #define MY_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->my_mtx, MA_OWNED)
388 * register space access macros
390 #define CSR_WRITE_4(sc, reg, val) \
391 bus_space_write_4(sc->my_btag, sc->my_bhandle, reg, val)
392 #define CSR_WRITE_2(sc, reg, val) \
393 bus_space_write_2(sc->my_btag, sc->my_bhandle, reg, val)
394 #define CSR_WRITE_1(sc, reg, val) \
395 bus_space_write_1(sc->my_btag, sc->my_bhandle, reg, val)
397 #define CSR_READ_4(sc, reg) \
398 bus_space_read_4(sc->my_btag, sc->my_bhandle, reg)
399 #define CSR_READ_2(sc, reg) \
400 bus_space_read_2(sc->my_btag, sc->my_bhandle, reg)
401 #define CSR_READ_1(sc, reg) \
402 bus_space_read_1(sc->my_btag, sc->my_bhandle, reg)
404 #define MY_TIMEOUT 1000
407 * General constants that are fun to know.
409 * MYSON PCI vendor ID
411 #define MYSONVENDORID 0x1516
416 #define MTD800ID 0x0800
417 #define MTD803ID 0x0803
418 #define MTD891ID 0x0891
421 * ST+OP+PHYAD+REGAD+TA
423 #define MY_OP_READ 0x6000 /* ST:01+OP:10+PHYAD+REGAD+TA:Z0 */
424 #define MY_OP_WRITE 0x5002 /* ST:01+OP:01+PHYAD+REGAD+TA:10 */
427 * Constansts for Myson PHY
429 #define MysonPHYID0 0x0300
432 * Constansts for Seeq 80225 PHY
434 #define SeeqPHYID0 0x0016
436 #define SEEQ_MIIRegister18 18
437 #define SEEQ_SPD_DET_100 0x80
438 #define SEEQ_DPLX_DET_FULL 0x40
441 * Constansts for Ahdoc 101 PHY
443 #define AhdocPHYID0 0x0022
445 #define AHDOC_DiagnosticReg 18
446 #define AHDOC_DPLX_FULL 0x0800
447 #define AHDOC_Speed_100 0x0400
450 * Constansts for Marvell 88E1000/88E1000S PHY and LevelOne PHY
452 #define MarvellPHYID0 0x0141
453 #define LevelOnePHYID0 0x0013
455 #define Marvell_SpecificStatus 17
456 #define Marvell_Speed1000 0x8000
457 #define Marvell_Speed100 0x4000
458 #define Marvell_FullDuplex 0x2000
461 * PCI low memory base and low I/O base register, and
462 * other PCI registers. Note: some are only available on
463 * the 3c905B, in particular those that related to power management.
465 #define MY_PCI_VENDOR_ID 0x00
466 #define MY_PCI_DEVICE_ID 0x02
467 #define MY_PCI_COMMAND 0x04
468 #define MY_PCI_STATUS 0x06
469 #define MY_PCI_CLASSCODE 0x09
470 #define MY_PCI_LATENCY_TIMER 0x0D
471 #define MY_PCI_HEADER_TYPE 0x0E
472 #define MY_PCI_LOIO 0x10
473 #define MY_PCI_LOMEM 0x14
474 #define MY_PCI_BIOSROM 0x30
475 #define MY_PCI_INTLINE 0x3C
476 #define MY_PCI_INTPIN 0x3D
477 #define MY_PCI_MINGNT 0x3E
478 #define MY_PCI_MINLAT 0x0F
479 #define MY_PCI_RESETOPT 0x48
480 #define MY_PCI_EEPROM_DATA 0x4C
482 #define PHY_UNKNOWN 3
484 #define MY_PHYADDR_MIN 0x00
485 #define MY_PHYADDR_MAX 0x1F
487 #define PHY_BMCR 0x00
488 #define PHY_BMSR 0x01
489 #define PHY_VENID 0x02
490 #define PHY_DEVID 0x03
491 #define PHY_ANAR 0x04
492 #define PHY_LPAR 0x05
493 #define PHY_ANEXP 0x06
494 #define PHY_NPTR 0x07
495 #define PHY_LPNPR 0x08
496 #define PHY_1000CR 0x09
497 #define PHY_1000SR 0x0a
499 #define PHY_ANAR_NEXTPAGE 0x8000
500 #define PHY_ANAR_RSVD0 0x4000
501 #define PHY_ANAR_TLRFLT 0x2000
502 #define PHY_ANAR_RSVD1 0x1000
503 #define PHY_ANAR_RSVD2 0x0800
504 #define PHY_ANAR_RSVD3 0x0400
505 #define PHY_ANAR_100BT4 0x0200L
506 #define PHY_ANAR_100BTXFULL 0x0100
507 #define PHY_ANAR_100BTXHALF 0x0080
508 #define PHY_ANAR_10BTFULL 0x0040
509 #define PHY_ANAR_10BTHALF 0x0020
510 #define PHY_ANAR_PROTO4 0x0010
511 #define PHY_ANAR_PROTO3 0x0008
512 #define PHY_ANAR_PROTO2 0x0004
513 #define PHY_ANAR_PROTO1 0x0002
514 #define PHY_ANAR_PROTO0 0x0001
516 #define PHY_1000SR_1000BTXFULL 0x0800
517 #define PHY_1000SR_1000BTXHALF 0x0400
520 * These are the register definitions for the PHY (physical layer
524 * PHY BMCR Basic Mode Control Register
526 #define PHY_BMCR_RESET 0x8000
527 #define PHY_BMCR_LOOPBK 0x4000
528 #define PHY_BMCR_SPEEDSEL 0x2000
529 #define PHY_BMCR_AUTONEGENBL 0x1000
530 #define PHY_BMCR_RSVD0 0x0800 /* write as zero */
531 #define PHY_BMCR_ISOLATE 0x0400
532 #define PHY_BMCR_AUTONEGRSTR 0x0200
533 #define PHY_BMCR_DUPLEX 0x0100
534 #define PHY_BMCR_COLLTEST 0x0080
535 #define PHY_BMCR_1000 0x0040 /* only used for Marvell PHY */
536 #define PHY_BMCR_RSVD2 0x0020 /* write as zero, don't care */
537 #define PHY_BMCR_RSVD3 0x0010 /* write as zero, don't care */
538 #define PHY_BMCR_RSVD4 0x0008 /* write as zero, don't care */
539 #define PHY_BMCR_RSVD5 0x0004 /* write as zero, don't care */
540 #define PHY_BMCR_RSVD6 0x0002 /* write as zero, don't care */
541 #define PHY_BMCR_RSVD7 0x0001 /* write as zero, don't care */
544 * RESET: 1 == software reset, 0 == normal operation
545 * Resets status and control registers to default values.
546 * Relatches all hardware config values.
548 * LOOPBK: 1 == loopback operation enabled, 0 == normal operation
550 * SPEEDSEL: 1 == 100Mb/s, 0 == 10Mb/s
551 * Link speed is selected byt his bit or if auto-negotiation if bit
552 * 12 (AUTONEGENBL) is set (in which case the value of this register
555 * AUTONEGENBL: 1 == Autonegotiation enabled, 0 == Autonegotiation disabled
556 * Bits 8 and 13 are ignored when autoneg is set, otherwise bits 8 and 13
557 * determine speed and mode. Should be cleared and then set if PHY configured
558 * for no autoneg on startup.
560 * ISOLATE: 1 == isolate PHY from MII, 0 == normal operation
562 * AUTONEGRSTR: 1 == restart autonegotiation, 0 = normal operation
564 * DUPLEX: 1 == full duplex mode, 0 == half duplex mode
566 * COLLTEST: 1 == collision test enabled, 0 == normal operation
570 * PHY, BMSR Basic Mode Status Register
572 #define PHY_BMSR_100BT4 0x8000
573 #define PHY_BMSR_100BTXFULL 0x4000
574 #define PHY_BMSR_100BTXHALF 0x2000
575 #define PHY_BMSR_10BTFULL 0x1000
576 #define PHY_BMSR_10BTHALF 0x0800
577 #define PHY_BMSR_RSVD1 0x0400 /* write as zero, don't care */
578 #define PHY_BMSR_RSVD2 0x0200 /* write as zero, don't care */
579 #define PHY_BMSR_RSVD3 0x0100 /* write as zero, don't care */
580 #define PHY_BMSR_RSVD4 0x0080 /* write as zero, don't care */
581 #define PHY_BMSR_MFPRESUP 0x0040
582 #define PHY_BMSR_AUTONEGCOMP 0x0020
583 #define PHY_BMSR_REMFAULT 0x0010
584 #define PHY_BMSR_CANAUTONEG 0x0008
585 #define PHY_BMSR_LINKSTAT 0x0004
586 #define PHY_BMSR_JABBER 0x0002
587 #define PHY_BMSR_EXTENDED 0x0001