2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (C) 2009-2012 Semihalf
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 #include <sys/param.h>
36 #include <sys/systm.h>
39 #include <sys/taskqueue.h>
40 #include <sys/queue.h>
43 #include <sys/mutex.h>
44 #include <sys/malloc.h>
46 #include <dev/nand/nand_dev.h>
48 MALLOC_DECLARE(M_NAND);
51 #define NAND_CMD_READ 0x00
52 #define NAND_CMD_CHNG_READ_COL 0x05
53 #define NAND_CMD_READ_END 0x30
54 #define NAND_CMD_READ_CACHE 0x31
55 #define NAND_CMD_READ_CPBK 0x35
56 #define NAND_CMD_READ_CACHE_END 0x3F
57 #define NAND_CMD_CHNG_READ_COL_END 0xE0
60 #define NAND_CMD_ERASE 0x60
61 #define NAND_CMD_ERASE_END 0xD0
62 #define NAND_CMD_ERASE_INTLV 0xD1
64 /* Program commands */
65 #define NAND_CMD_PROG 0x80
66 #define NAND_CMD_CHNG_WRITE_COL 0x85
67 #define NAND_CMD_PROG_END 0x10
68 #define NAND_CMD_PROG_INTLV 0x11
69 #define NAND_CMD_PROG_CACHE 0x15
72 #define NAND_CMD_STATUS 0x70
73 #define NAND_CMD_STATUS_ENH 0x78
74 #define NAND_CMD_READ_ID 0x90
75 #define NAND_CMD_READ_PARAMETER 0xec
76 #define NAND_CMD_READ_UNIQUE_ID 0xed
77 #define NAND_CMD_GET_FEATURE 0xee
78 #define NAND_CMD_SET_FEATURE 0xef
81 #define NAND_CMD_SYNCH_RESET 0xfc
82 #define NAND_CMD_RESET 0xff
84 /* Small page flash commands */
85 #define NAND_CMD_SMALLA 0x00
86 #define NAND_CMD_SMALLB 0x01
87 #define NAND_CMD_SMALLOOB 0x50
89 #define NAND_STATUS_FAIL 0x1
90 #define NAND_STATUS_FAILC 0x2
91 #define NAND_STATUS_ARDY 0x20
92 #define NAND_STATUS_RDY 0x40
93 #define NAND_STATUS_WP 0x80
95 #define NAND_LP_OOB_COLUMN_START 0x800
96 #define NAND_LP_OOBSZ 0x40
97 #define NAND_SP_OOB_COLUMN_START 0x200
98 #define NAND_SP_OOBSZ 0x10
100 #define PAGE_PARAM_LENGTH 0x100
101 #define PAGE_PARAMETER_DEF 0x0
102 #define PAGE_PARAMETER_RED_1 0x100
103 #define PAGE_PARAMETER_RED_2 0x200
105 #define ONFI_SIG_ADDR 0x20
107 #define NAND_MAX_CHIPS 0x4
108 #define NAND_MAX_OOBSZ 512
109 #define NAND_MAX_PAGESZ 16384
111 #define NAND_SMALL_PAGE_SIZE 0x200
113 #define NAND_16_BIT 0x00000001
115 #define NAND_ECC_NONE 0x0
116 #define NAND_ECC_SOFT 0x1
117 #define NAND_ECC_FULLHW 0x2
118 #define NAND_ECC_PARTHW 0x4
119 #define NAND_ECC_MODE_MASK 0x7
122 #define ECC_CORRECTABLE 1
123 #define ECC_ERROR_ECC (-1)
124 #define ECC_UNCORRECTABLE (-2)
126 #define NAND_MAN_SAMSUNG 0xec
127 #define NAND_MAN_HYNIX 0xad
128 #define NAND_MAN_STMICRO 0x20
129 #define NAND_MAN_MICRON 0x2c
142 uint32_t pages_per_block;
146 /* nand debug levels */
147 #define NDBG_NAND 0x01
148 #define NDBG_CDEV 0x02
149 #define NDBG_GEN 0x04
150 #define NDBG_GEOM 0x08
151 #define NDBG_BUS 0x10
152 #define NDBG_SIM 0x20
153 #define NDBG_CTRL 0x40
154 #define NDBG_DRV 0x80
155 #define NDBG_ECC 0x100
157 /* nand_debug_function */
158 void nand_debug(int level, const char *fmt, ...);
159 extern int nand_debug_flag;
161 /* ONFI features bit*/
162 #define ONFI_FEAT_16BIT 0x01
163 #define ONFI_FEAT_MULT_LUN 0x02
164 #define ONFI_FEAT_INTLV_OPS 0x04
165 #define ONFI_FEAT_CPBK_RESTRICT 0x08
166 #define ONFI_FEAT_SRC_SYNCH 0x10
168 /* ONFI optional commands bits */
169 #define ONFI_OPTCOM_PROG_CACHE 0x01
170 #define ONFI_OPTCOM_READ_CACHE 0x02
171 #define ONFI_OPTCOM_GETSET_FEAT 0x04
172 #define ONFI_OPTCOM_STATUS_ENH 0x08
173 #define ONFI_OPTCOM_COPYBACK 0x10
174 #define ONFI_OPTCOM_UNIQUE_ID 0x20
177 /* Layout of parameter page is defined in ONFI */
182 uint16_t optional_commands;
183 uint8_t primary_advanced_command;
185 uint16_t extended_parameter_page_length;
186 uint8_t parameter_page_count;
188 char manufacturer_name[12];
189 char device_model[20];
190 uint8_t manufacturer_id;
191 uint8_t manufacture_date_yy;
192 uint8_t manufacture_date_ww;
194 uint32_t bytes_per_page;
195 uint16_t spare_bytes_per_page;
196 uint32_t bytes_per_partial_page;
197 uint16_t spare_bytes_per_partial_page;
198 uint32_t pages_per_block;
199 uint32_t blocks_per_lun;
201 uint8_t address_cycles;
202 uint8_t bits_per_cell;
203 uint16_t max_bad_block_per_lun;
204 uint16_t block_endurance;
205 uint8_t guaranteed_valid_blocks;
206 uint16_t valid_block_endurance;
207 uint8_t programs_per_page;
208 uint8_t partial_prog_attr;
210 uint8_t interleaved_addr_bits;
211 uint8_t interleaved_oper_attr;
212 uint8_t eznand_support;
214 uint8_t pin_capacitance;
215 uint16_t asynch_timing_mode_support;
216 uint16_t asynch_prog_cache_timing_mode_support;
217 uint16_t t_prog; /* us, max page program time */
218 uint16_t t_bers; /* us, max block erase time */
219 uint16_t t_r; /* us, max page read time */
220 uint16_t t_ccs; /* ns, min change column setup time */
221 uint16_t source_synch_timing_mode_support;
222 uint8_t source_synch_feat;
223 uint16_t clk_input_capacitance;
224 uint16_t io_capacitance;
225 uint16_t input_capacitance;
226 uint8_t input_capacitance_max;
227 uint8_t driver_strength_support;
228 uint16_t t_r_interleaved;
231 uint8_t nv_ddr2_features;
232 uint8_t nv_ddr2_warmup_cycles;
235 uint8_t vendor_spec[88];
237 }__attribute__((packed));
238 CTASSERT(sizeof(struct onfi_params) == 256);
240 struct onfi_chip_params {
241 uint32_t blocks_per_lun;
242 uint32_t pages_per_block;
243 uint32_t bytes_per_page;
244 uint32_t spare_bytes_per_page;
250 uint8_t address_cycles;
254 struct nand_ecc_data {
255 int eccsize; /* Number of data bytes per ECC step */
257 int eccbytes; /* Number of ECC bytes per step */
259 uint16_t *eccpositions; /* Positions of ecc bytes */
260 uint8_t ecccalculated[NAND_MAX_OOBSZ];
261 uint8_t eccread[NAND_MAX_OOBSZ];
265 uint32_t ecc_succeded;
266 uint32_t ecc_corrected;
271 struct ecc_stat ecc_stat;
273 uint32_t page_raw_read;
274 uint32_t page_written;
275 uint32_t page_raw_written;
279 uint32_t block_erased;
289 uint32_t blks_per_lun;
290 uint32_t blks_per_chip;
291 uint32_t pgs_per_blk;
303 struct chip_geom chip_geom;
305 uint16_t t_prog; /* us, max page program time */
306 uint16_t t_bers; /* us, max block erase time */
307 uint16_t t_r; /* us, max page read time */
308 uint16_t t_ccs; /* ns, min change column setup time */
312 struct page_stat *pg_stat;
313 struct block_stat *blk_stat;
314 struct nand_softc *nand;
315 struct nand_bbt *bbt;
316 struct nand_ops *ops;
321 struct bio_queue_head bioq; /* bio queue */
322 struct mtx qlock; /* bioq lock */
323 struct taskqueue *tq; /* private task queue for i/o request */
324 struct task iotask; /* i/o processing */
331 char *chip_cdev_name;
332 struct nand_ecc_data ecc;
336 int nand_erase_blocks(struct nand_chip *chip, off_t offset, size_t len);
337 int nand_prog_pages(struct nand_chip *chip, uint32_t offset, uint8_t *buf,
339 int nand_read_pages(struct nand_chip *chip, uint32_t offset, void *buf,
341 int nand_read_pages_raw(struct nand_chip *chip, uint32_t offset, void *buf,
343 int nand_prog_pages_raw(struct nand_chip *chip, uint32_t offset, void *buf,
345 int nand_read_oob(struct nand_chip *chip, uint32_t page, void *buf,
347 int nand_prog_oob(struct nand_chip *chip, uint32_t page, void *buf,
350 int nand_select_cs(device_t dev, uint8_t cs);
352 int nand_read_parameter(struct nand_softc *nand, struct onfi_params *param);
353 int nand_synch_reset(struct nand_softc *nand);
354 int nand_chng_read_col(device_t dev, uint32_t col, void *buf, size_t len);
355 int nand_chng_write_col(device_t dev, uint32_t col, void *buf, size_t len);
356 int nand_get_feature(device_t dev, uint8_t feat, void* buf);
357 int nand_set_feature(device_t dev, uint8_t feat, void* buf);
360 int nand_erase_block_intlv(device_t dev, uint32_t block);
361 int nand_copyback_read(device_t dev, uint32_t page, uint32_t col,
362 void *buf, size_t len);
363 int nand_copyback_prog(device_t dev, uint32_t page, uint32_t col,
364 void *buf, size_t len);
365 int nand_copyback_prog_intlv(device_t dev, uint32_t page);
366 int nand_prog_cache(device_t dev, uint32_t page, uint32_t col,
367 void *buf, size_t len, uint8_t end);
368 int nand_prog_intlv(device_t dev, uint32_t page, uint32_t col,
369 void *buf, size_t len);
370 int nand_read_cache(device_t dev, uint32_t page, uint32_t col,
371 void *buf, size_t len, uint8_t end);
373 int nand_write_ecc(struct nand_softc *nand, uint32_t page, uint8_t *data);
374 int nand_read_ecc(struct nand_softc *nand, uint32_t page, uint8_t *data);
376 int nand_softecc_get(device_t dev, uint8_t *buf, int pagesize, uint8_t *ecc);
377 int nand_softecc_correct(device_t dev, uint8_t *buf, int pagesize,
378 uint8_t *readecc, uint8_t *calcecc);
380 /* Chip initialization */
381 void nand_init(struct nand_softc *nand, device_t dev, int ecc_mode,
382 int ecc_bytes, int ecc_size, uint16_t* eccposition, char* cdev_name);
383 void nand_detach(struct nand_softc *nand);
384 struct nand_params *nand_get_params(struct nand_id *id);
386 void nand_onfi_set_params(struct nand_chip *chip, struct onfi_chip_params *params);
387 void nand_set_params(struct nand_chip *chip, struct nand_params *params);
388 int nand_init_stat(struct nand_chip *chip);
389 void nand_destroy_stat(struct nand_chip *chip);
392 int nand_init_bbt(struct nand_chip *chip);
393 void nand_destroy_bbt(struct nand_chip *chip);
394 int nand_update_bbt(struct nand_chip *chip);
395 int nand_mark_bad_block(struct nand_chip* chip, uint32_t block_num);
396 int nand_check_bad_block(struct nand_chip* chip, uint32_t block_num);
398 /* cdev creation/removal */
399 int nand_make_dev(struct nand_chip* chip);
400 void nand_destroy_dev(struct nand_chip *chip);
402 int create_geom_disk(struct nand_chip* chip);
403 int create_geom_raw_disk(struct nand_chip *chip);
404 void destroy_geom_disk(struct nand_chip *chip);
405 void destroy_geom_raw_disk(struct nand_chip *chip);
407 int init_chip_geom(struct chip_geom* cg, uint32_t luns, uint32_t blks_per_lun,
408 uint32_t pgs_per_blk, uint32_t pg_size, uint32_t oob_size);
409 int nand_row_to_blkpg(struct chip_geom *cg, uint32_t row, uint32_t *lun,
410 uint32_t *blk, uint32_t *pg);
411 int page_to_row(struct chip_geom *cg, uint32_t page, uint32_t *row);
412 int nand_check_page_boundary(struct nand_chip *chip, uint32_t page);
413 void nand_get_chip_param(struct nand_chip *chip, struct chip_param_io *param);
415 #endif /* _DEV_NAND_H_ */