sys/dev/nand/nand_generic.c

   1 /*-
   2  * Copyright (C) 2009-2012 Semihalf
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  */
  26
  27 /* Generic NAND driver */
  28
  29 #include <sys/cdefs.h>
  30 __FBSDID("$FreeBSD$");
  31
  32 #include <sys/param.h>
  33 #include <sys/systm.h>
  34 #include <sys/proc.h>
  35 #include <sys/bus.h>
  36 #include <sys/conf.h>
  37 #include <sys/endian.h>
  38 #include <sys/kernel.h>
  39 #include <sys/module.h>
  40 #include <sys/rman.h>
  41 #include <sys/lock.h>
  42 #include <sys/mutex.h>
  43 #include <sys/time.h>
  44 #include <sys/malloc.h>
  45
  46 #include <dev/nand/nand.h>
  47 #include <dev/nand/nandbus.h>
  48 #include "nfc_if.h"
  49 #include "nand_if.h"
  50 #include "nandbus_if.h"
  51
  52
  53 static int onfi_nand_probe(device_t dev);
  54 static int large_nand_probe(device_t dev);
  55 static int small_nand_probe(device_t dev);
  56 static int generic_nand_attach(device_t dev);
  57 static int generic_nand_detach(device_t dev);
  58
  59 static int generic_erase_block(device_t, uint32_t);
  60 static int generic_erase_block_intlv(device_t, uint32_t);
  61 static int generic_read_page (device_t, uint32_t, void *, uint32_t, uint32_t);
  62 static int generic_read_oob(device_t, uint32_t, void *, uint32_t, uint32_t);
  63 static int generic_program_page(device_t, uint32_t, void *, uint32_t, uint32_t);
  64 static int generic_program_page_intlv(device_t, uint32_t, void *, uint32_t,
  65     uint32_t);
  66 static int generic_program_oob(device_t, uint32_t, void *, uint32_t, uint32_t);
  67 static int generic_is_blk_bad(device_t, uint32_t, uint8_t *);
  68 static int generic_get_ecc(device_t, void *, void *, int *);
  69 static int generic_correct_ecc(device_t, void *, void *, void *);
  70
  71 static int small_read_page(device_t, uint32_t, void *, uint32_t, uint32_t);
  72 static int small_read_oob(device_t, uint32_t, void *, uint32_t, uint32_t);
  73 static int small_program_page(device_t, uint32_t, void *, uint32_t, uint32_t);
  74 static int small_program_oob(device_t, uint32_t, void *, uint32_t, uint32_t);
  75
  76 static int onfi_is_blk_bad(device_t, uint32_t, uint8_t *);
  77 static int onfi_read_parameter(struct nand_chip *, struct onfi_chip_params *);
  78
  79 static int nand_send_address(device_t, int32_t, int32_t, int8_t);
  80
  81 static device_method_t onand_methods[] = {
  82         /* Device interface */
  83         DEVMETHOD(device_probe,                 onfi_nand_probe),
  84         DEVMETHOD(device_attach,                generic_nand_attach),
  85         DEVMETHOD(device_detach,                generic_nand_detach),
  86
  87         DEVMETHOD(nand_read_page,               generic_read_page),
  88         DEVMETHOD(nand_program_page,            generic_program_page),
  89         DEVMETHOD(nand_program_page_intlv,      generic_program_page_intlv),
  90         DEVMETHOD(nand_read_oob,                generic_read_oob),
  91         DEVMETHOD(nand_program_oob,             generic_program_oob),
  92         DEVMETHOD(nand_erase_block,             generic_erase_block),
  93         DEVMETHOD(nand_erase_block_intlv,       generic_erase_block_intlv),
  94
  95         DEVMETHOD(nand_is_blk_bad,              onfi_is_blk_bad),
  96         DEVMETHOD(nand_get_ecc,                 generic_get_ecc),
  97         DEVMETHOD(nand_correct_ecc,             generic_correct_ecc),
  98         { 0, 0 }
  99 };
 100
 101 static device_method_t lnand_methods[] = {
 102         /* Device interface */
 103         DEVMETHOD(device_probe,         large_nand_probe),
 104         DEVMETHOD(device_attach,        generic_nand_attach),
 105         DEVMETHOD(device_detach,        generic_nand_detach),
 106
 107         DEVMETHOD(nand_read_page,       generic_read_page),
 108         DEVMETHOD(nand_program_page,    generic_program_page),
 109         DEVMETHOD(nand_read_oob,        generic_read_oob),
 110         DEVMETHOD(nand_program_oob,     generic_program_oob),
 111         DEVMETHOD(nand_erase_block,     generic_erase_block),
 112
 113         DEVMETHOD(nand_is_blk_bad,      generic_is_blk_bad),
 114         DEVMETHOD(nand_get_ecc,         generic_get_ecc),
 115         DEVMETHOD(nand_correct_ecc,     generic_correct_ecc),
 116         { 0, 0 }
 117 };
 118
 119 static device_method_t snand_methods[] = {
 120         /* Device interface */
 121         DEVMETHOD(device_probe,         small_nand_probe),
 122         DEVMETHOD(device_attach,        generic_nand_attach),
 123         DEVMETHOD(device_detach,        generic_nand_detach),
 124
 125         DEVMETHOD(nand_read_page,       small_read_page),
 126         DEVMETHOD(nand_program_page,    small_program_page),
 127         DEVMETHOD(nand_read_oob,        small_read_oob),
 128         DEVMETHOD(nand_program_oob,     small_program_oob),
 129         DEVMETHOD(nand_erase_block,     generic_erase_block),
 130
 131         DEVMETHOD(nand_is_blk_bad,      generic_is_blk_bad),
 132         DEVMETHOD(nand_get_ecc,         generic_get_ecc),
 133         DEVMETHOD(nand_correct_ecc,     generic_correct_ecc),
 134         { 0, 0 }
 135 };
 136
 137 devclass_t onand_devclass;
 138 devclass_t lnand_devclass;
 139 devclass_t snand_devclass;
 140
 141 driver_t onand_driver = {
 142         "onand",
 143         onand_methods,
 144         sizeof(struct nand_chip)
 145 };
 146
 147 driver_t lnand_driver = {
 148         "lnand",
 149         lnand_methods,
 150         sizeof(struct nand_chip)
 151 };
 152
 153 driver_t snand_driver = {
 154         "snand",
 155         snand_methods,
 156         sizeof(struct nand_chip)
 157 };
 158
 159 DRIVER_MODULE(onand, nandbus, onand_driver, onand_devclass, 0, 0);
 160 DRIVER_MODULE(lnand, nandbus, lnand_driver, lnand_devclass, 0, 0);
 161 DRIVER_MODULE(snand, nandbus, snand_driver, snand_devclass, 0, 0);
 162
 163 static int
 164 onfi_nand_probe(device_t dev)
 165 {
 166         struct nandbus_ivar *ivar;
 167
 168         ivar = device_get_ivars(dev);
 169         if (ivar && ivar->is_onfi) {
 170                 device_set_desc(dev, "ONFI compliant NAND");
 171                 return (BUS_PROBE_DEFAULT);
 172         }
 173
 174         return (ENODEV);
 175 }
 176
 177 static int
 178 large_nand_probe(device_t dev)
 179 {
 180         struct nandbus_ivar *ivar;
 181
 182         ivar = device_get_ivars(dev);
 183         if (ivar && !ivar->is_onfi && ivar->params->page_size >= 512) {
 184                 device_set_desc(dev, ivar->params->name);
 185                 return (BUS_PROBE_DEFAULT);
 186         }
 187
 188         return (ENODEV);
 189 }
 190
 191 static int
 192 small_nand_probe(device_t dev)
 193 {
 194         struct nandbus_ivar *ivar;
 195
 196         ivar = device_get_ivars(dev);
 197         if (ivar && !ivar->is_onfi && ivar->params->page_size == 512) {
 198                 device_set_desc(dev, ivar->params->name);
 199                 return (BUS_PROBE_DEFAULT);
 200         }
 201
 202         return (ENODEV);
 203 }
 204
 205 static int
 206 generic_nand_attach(device_t dev)
 207 {
 208         struct nand_chip *chip;
 209         struct nandbus_ivar *ivar;
 210         struct onfi_chip_params *onfi_chip_params;
 211         device_t nandbus, nfc;
 212         int err;
 213
 214         chip = device_get_softc(dev);
 215         chip->dev = dev;
 216
 217         ivar = device_get_ivars(dev);
 218         chip->id.man_id = ivar->man_id;
 219         chip->id.dev_id = ivar->dev_id;
 220         chip->num = ivar->cs;
 221
 222         /* TODO remove when HW ECC supported */
 223         nandbus = device_get_parent(dev);
 224         nfc = device_get_parent(nandbus);
 225
 226         chip->nand = device_get_softc(nfc);
 227
 228         if (ivar->is_onfi) {
 229                 onfi_chip_params = malloc(sizeof(struct onfi_chip_params),
 230                     M_NAND, M_WAITOK | M_ZERO);
 231
 232                 if (onfi_read_parameter(chip, onfi_chip_params)) {
 233                         nand_debug(NDBG_GEN,"Could not read parameter page!\n");
 234                         free(onfi_chip_params, M_NAND);
 235                         return (ENXIO);
 236                 }
 237
 238                 nand_onfi_set_params(chip, onfi_chip_params);
 239                 /* Set proper column and row cycles */
 240                 ivar->cols = (onfi_chip_params->address_cycles >> 4) & 0xf;
 241                 ivar->rows = onfi_chip_params->address_cycles & 0xf;
 242                 free(onfi_chip_params, M_NAND);
 243
 244         } else {
 245                 nand_set_params(chip, ivar->params);
 246         }
 247
 248         err = nand_init_stat(chip);
 249         if (err) {
 250                 generic_nand_detach(dev);
 251                 return (err);
 252         }
 253
 254         err = nand_init_bbt(chip);
 255         if (err) {
 256                 generic_nand_detach(dev);
 257                 return (err);
 258         }
 259
 260         err = nand_make_dev(chip);
 261         if (err) {
 262                 generic_nand_detach(dev);
 263                 return (err);
 264         }
 265
 266         err = create_geom_disk(chip);
 267         if (err) {
 268                 generic_nand_detach(dev);
 269                 return (err);
 270         }
 271
 272         return (0);
 273 }
 274
 275 static int
 276 generic_nand_detach(device_t dev)
 277 {
 278         struct nand_chip *chip;
 279
 280         chip = device_get_softc(dev);
 281
 282         nand_destroy_bbt(chip);
 283         destroy_geom_disk(chip);
 284         nand_destroy_dev(chip);
 285         nand_destroy_stat(chip);
 286
 287         return (0);
 288 }
 289
 290 static int
 291 can_write(device_t nandbus)
 292 {
 293         uint8_t status;
 294
 295         if (NANDBUS_WAIT_READY(nandbus, &status))
 296                 return (0);
 297
 298         if (!(status & NAND_STATUS_WP)) {
 299                 nand_debug(NDBG_GEN,"Chip is write-protected");
 300                 return (0);
 301         }
 302
 303         return (1);
 304 }
 305
 306 static int
 307 check_fail(device_t nandbus)
 308 {
 309         uint8_t status;
 310
 311         NANDBUS_WAIT_READY(nandbus, &status);
 312         if (status & NAND_STATUS_FAIL) {
 313                 nand_debug(NDBG_GEN,"Status failed %x", status);
 314                 return (ENXIO);
 315         }
 316
 317         return (0);
 318 }
 319
 320 static uint16_t
 321 onfi_crc(const void *buf, size_t buflen)
 322 {
 323         int i, j;
 324         uint16_t crc;
 325         const uint8_t *bufptr;
 326
 327         bufptr = buf;
 328         crc = 0x4f4e;
 329         for (j = 0; j < buflen; j++) {
 330                 crc ^= *bufptr++ << 8;
 331                 for (i = 0; i < 8; i++)
 332                         if (crc & 0x8000)
 333                                 crc = (crc << 1) ^ 0x8005;
 334                         else
 335                                 crc <<= 1;
 336         }
 337        return crc;
 338 }
 339
 340 static int
 341 onfi_read_parameter(struct nand_chip *chip, struct onfi_chip_params *chip_params)
 342 {
 343         device_t nandbus;
 344         struct onfi_params params;
 345         int found, sigcount, trycopy;
 346
 347         nand_debug(NDBG_GEN,"read parameter");
 348
 349         nandbus = device_get_parent(chip->dev);
 350
 351         NANDBUS_SELECT_CS(nandbus, chip->num);
 352
 353         if (NANDBUS_SEND_COMMAND(nandbus, NAND_CMD_READ_PARAMETER))
 354                 return (ENXIO);
 355
 356         if (nand_send_address(chip->dev, -1, -1, PAGE_PARAMETER_DEF))
 357                 return (ENXIO);
 358
 359         if (NANDBUS_START_COMMAND(nandbus))
 360                 return (ENXIO);
 361
 362         /*
 363          * XXX Bogus DELAY, we really need a nandbus_wait_ready() here, but it's
 364          * not accessible from here (static to nandbus).
 365          */
 366         DELAY(1000);
 367
 368         /*
 369          * The ONFI spec mandates a minimum of three copies of the parameter
 370          * data, so loop up to 3 times trying to find good data.  Each copy is
 371          * validated by a signature of "ONFI" and a crc. There is a very strange
 372          * rule that the signature is valid if any 2 of the 4 bytes are correct.
 373          */
 374         for (found= 0, trycopy = 0; !found && trycopy < 3; trycopy++) {
 375                 NANDBUS_READ_BUFFER(nandbus, &params, sizeof(struct onfi_params));
 376                 sigcount  = params.signature[0] == 'O';
 377                 sigcount += params.signature[1] == 'N';
 378                 sigcount += params.signature[2] == 'F';
 379                 sigcount += params.signature[3] == 'I';
 380                 if (sigcount < 2)
 381                         continue;
 382                 if (onfi_crc(&params, 254) != params.crc)
 383                         continue;
 384                 found = 1;
 385         }
 386         if (!found)
 387                 return (ENXIO);
 388
 389         chip_params->luns = params.luns;
 390         chip_params->blocks_per_lun = le32dec(&params.blocks_per_lun);
 391         chip_params->pages_per_block = le32dec(&params.pages_per_block);
 392         chip_params->bytes_per_page = le32dec(&params.bytes_per_page);
 393         chip_params->spare_bytes_per_page = le16dec(&params.spare_bytes_per_page);
 394         chip_params->t_bers = le16dec(&params.t_bers);
 395         chip_params->t_prog = le16dec(&params.t_prog);
 396         chip_params->t_r = le16dec(&params.t_r);
 397         chip_params->t_ccs = le16dec(&params.t_ccs);
 398         chip_params->features = le16dec(&params.features);
 399         chip_params->address_cycles = params.address_cycles;
 400
 401         return (0);
 402 }
 403
 404 static int
 405 send_read_page(device_t nand, uint8_t start_command, uint8_t end_command,
 406     uint32_t row, uint32_t column)
 407 {
 408         device_t nandbus = device_get_parent(nand);
 409
 410         if (NANDBUS_SEND_COMMAND(nandbus, start_command))
 411                 return (ENXIO);
 412
 413         if (nand_send_address(nand, row, column, -1))
 414                 return (ENXIO);
 415
 416         if (NANDBUS_SEND_COMMAND(nandbus, end_command))
 417                 return (ENXIO);
 418
 419         if (NANDBUS_START_COMMAND(nandbus))
 420                 return (ENXIO);
 421
 422         return (0);
 423 }
 424
 425 static int
 426 generic_read_page(device_t nand, uint32_t page, void *buf, uint32_t len,
 427     uint32_t offset)
 428 {
 429         struct nand_chip *chip;
 430         struct page_stat *pg_stat;
 431         device_t nandbus;
 432         uint32_t row;
 433
 434         nand_debug(NDBG_GEN,"%p raw read page %x[%x] at %x", nand, page, len, offset);
 435         chip = device_get_softc(nand);
 436         nandbus = device_get_parent(nand);
 437
 438         if (nand_check_page_boundary(chip, page))
 439                 return (ENXIO);
 440
 441         page_to_row(&chip->chip_geom, page, &row);
 442
 443         if (send_read_page(nand, NAND_CMD_READ, NAND_CMD_READ_END, row,
 444             offset))
 445                 return (ENXIO);
 446
 447         DELAY(chip->t_r);
 448
 449         NANDBUS_READ_BUFFER(nandbus, buf, len);
 450
 451         if (check_fail(nandbus))
 452                 return (ENXIO);
 453
 454         pg_stat = &(chip->pg_stat[page]);
 455         pg_stat->page_raw_read++;
 456
 457         return (0);
 458 }
 459
 460 static int
 461 generic_read_oob(device_t nand, uint32_t page, void* buf, uint32_t len,
 462     uint32_t offset)
 463 {
 464         struct nand_chip *chip;
 465         device_t nandbus;
 466         uint32_t row;
 467
 468         nand_debug(NDBG_GEN,"%p raw read oob %x[%x] at %x", nand, page, len, offset);
 469         chip = device_get_softc(nand);
 470         nandbus = device_get_parent(nand);
 471
 472         if (nand_check_page_boundary(chip, page)) {
 473                 nand_debug(NDBG_GEN,"page boundary check failed: %08x\n", page);
 474                 return (ENXIO);
 475         }
 476
 477         page_to_row(&chip->chip_geom, page, &row);
 478
 479         offset += chip->chip_geom.page_size;
 480
 481         if (send_read_page(nand, NAND_CMD_READ, NAND_CMD_READ_END, row,
 482             offset))
 483                 return (ENXIO);
 484
 485         DELAY(chip->t_r);
 486
 487         NANDBUS_READ_BUFFER(nandbus, buf, len);
 488
 489         if (check_fail(nandbus))
 490                 return (ENXIO);
 491
 492         return (0);
 493 }
 494
 495 static int
 496 send_start_program_page(device_t nand, uint32_t row, uint32_t column)
 497 {
 498         device_t nandbus = device_get_parent(nand);
 499
 500         if (NANDBUS_SEND_COMMAND(nandbus, NAND_CMD_PROG))
 501                 return (ENXIO);
 502
 503         if (nand_send_address(nand, row, column, -1))
 504                 return (ENXIO);
 505
 506         return (0);
 507 }
 508
 509 static int
 510 send_end_program_page(device_t nandbus, uint8_t end_command)
 511 {
 512
 513         if (NANDBUS_SEND_COMMAND(nandbus, end_command))
 514                 return (ENXIO);
 515
 516         if (NANDBUS_START_COMMAND(nandbus))
 517                 return (ENXIO);
 518
 519         return (0);
 520 }
 521
 522 static int
 523 generic_program_page(device_t nand, uint32_t page, void *buf, uint32_t len,
 524     uint32_t offset)
 525 {
 526         struct nand_chip *chip;
 527         struct page_stat *pg_stat;
 528         device_t nandbus;
 529         uint32_t row;
 530
 531         nand_debug(NDBG_GEN,"%p raw prog page %x[%x] at %x", nand, page, len,
 532             offset);
 533         chip = device_get_softc(nand);
 534         nandbus = device_get_parent(nand);
 535
 536         if (nand_check_page_boundary(chip, page))
 537                 return (ENXIO);
 538
 539         page_to_row(&chip->chip_geom, page, &row);
 540
 541         if (!can_write(nandbus))
 542                 return (ENXIO);
 543
 544         if (send_start_program_page(nand, row, offset))
 545                 return (ENXIO);
 546
 547         NANDBUS_WRITE_BUFFER(nandbus, buf, len);
 548
 549         if (send_end_program_page(nandbus, NAND_CMD_PROG_END))
 550                 return (ENXIO);
 551
 552         DELAY(chip->t_prog);
 553
 554         if (check_fail(nandbus))
 555                 return (ENXIO);
 556
 557         pg_stat = &(chip->pg_stat[page]);
 558         pg_stat->page_raw_written++;
 559
 560         return (0);
 561 }
 562
 563 static int
 564 generic_program_page_intlv(device_t nand, uint32_t page, void *buf,
 565     uint32_t len, uint32_t offset)
 566 {
 567         struct nand_chip *chip;
 568         struct page_stat *pg_stat;
 569         device_t nandbus;
 570         uint32_t row;
 571
 572         nand_debug(NDBG_GEN,"%p raw prog page %x[%x] at %x", nand, page, len, offset);
 573         chip = device_get_softc(nand);
 574         nandbus = device_get_parent(nand);
 575
 576         if (nand_check_page_boundary(chip, page))
 577                 return (ENXIO);
 578
 579         page_to_row(&chip->chip_geom, page, &row);
 580
 581         if (!can_write(nandbus))
 582                 return (ENXIO);
 583
 584         if (send_start_program_page(nand, row, offset))
 585                 return (ENXIO);
 586
 587         NANDBUS_WRITE_BUFFER(nandbus, buf, len);
 588
 589         if (send_end_program_page(nandbus, NAND_CMD_PROG_INTLV))
 590                 return (ENXIO);
 591
 592         DELAY(chip->t_prog);
 593
 594         if (check_fail(nandbus))
 595                 return (ENXIO);
 596
 597         pg_stat = &(chip->pg_stat[page]);
 598         pg_stat->page_raw_written++;
 599
 600         return (0);
 601 }
 602
 603 static int
 604 generic_program_oob(device_t nand, uint32_t page, void* buf, uint32_t len,
 605     uint32_t offset)
 606 {
 607         struct nand_chip *chip;
 608         device_t nandbus;
 609         uint32_t row;
 610
 611         nand_debug(NDBG_GEN,"%p raw prog oob %x[%x] at %x", nand, page, len,
 612             offset);
 613         chip = device_get_softc(nand);
 614         nandbus = device_get_parent(nand);
 615
 616         if (nand_check_page_boundary(chip, page))
 617                 return (ENXIO);
 618
 619         page_to_row(&chip->chip_geom, page, &row);
 620         offset += chip->chip_geom.page_size;
 621
 622         if (!can_write(nandbus))
 623                 return (ENXIO);
 624
 625         if (send_start_program_page(nand, row, offset))
 626                 return (ENXIO);
 627
 628         NANDBUS_WRITE_BUFFER(nandbus, buf, len);
 629
 630         if (send_end_program_page(nandbus, NAND_CMD_PROG_END))
 631                 return (ENXIO);
 632
 633         DELAY(chip->t_prog);
 634
 635         if (check_fail(nandbus))
 636                 return (ENXIO);
 637
 638         return (0);
 639 }
 640
 641 static int
 642 send_erase_block(device_t nand, uint32_t row, uint8_t second_command)
 643 {
 644         device_t nandbus = device_get_parent(nand);
 645
 646         if (NANDBUS_SEND_COMMAND(nandbus, NAND_CMD_ERASE))
 647                 return (ENXIO);
 648
 649         if (nand_send_address(nand, row, -1, -1))
 650                 return (ENXIO);
 651
 652         if (NANDBUS_SEND_COMMAND(nandbus, second_command))
 653                 return (ENXIO);
 654
 655         if (NANDBUS_START_COMMAND(nandbus))
 656                 return (ENXIO);
 657
 658         return (0);
 659 }
 660
 661 static int
 662 generic_erase_block(device_t nand, uint32_t block)
 663 {
 664         struct block_stat *blk_stat;
 665         struct nand_chip *chip;
 666         device_t nandbus;
 667         int row;
 668
 669         nand_debug(NDBG_GEN,"%p erase block  %x", nand, block);
 670         nandbus = device_get_parent(nand);
 671         chip = device_get_softc(nand);
 672
 673         if (block >= (chip->chip_geom.blks_per_lun * chip->chip_geom.luns))
 674                 return (ENXIO);
 675
 676         row = (block << chip->chip_geom.blk_shift) &
 677             chip->chip_geom.blk_mask;
 678
 679         nand_debug(NDBG_GEN,"%p erase block  row %x", nand, row);
 680
 681         if (!can_write(nandbus))
 682                 return (ENXIO);
 683
 684         send_erase_block(nand, row, NAND_CMD_ERASE_END);
 685
 686         DELAY(chip->t_bers);
 687
 688         if (check_fail(nandbus))
 689                 return (ENXIO);
 690
 691         blk_stat = &(chip->blk_stat[block]);
 692         blk_stat->block_erased++;
 693
 694         return (0);
 695 }
 696
 697 static int
 698 generic_erase_block_intlv(device_t nand, uint32_t block)
 699 {
 700         struct block_stat *blk_stat;
 701         struct nand_chip *chip;
 702         device_t nandbus;
 703         int row;
 704
 705         nand_debug(NDBG_GEN,"%p erase block  %x", nand, block);
 706         nandbus = device_get_parent(nand);
 707         chip = device_get_softc(nand);
 708
 709         if (block >= (chip->chip_geom.blks_per_lun * chip->chip_geom.luns))
 710                 return (ENXIO);
 711
 712         row = (block << chip->chip_geom.blk_shift) &
 713             chip->chip_geom.blk_mask;
 714
 715         if (!can_write(nandbus))
 716                 return (ENXIO);
 717
 718         send_erase_block(nand, row, NAND_CMD_ERASE_INTLV);
 719
 720         DELAY(chip->t_bers);
 721
 722         if (check_fail(nandbus))
 723                 return (ENXIO);
 724
 725         blk_stat = &(chip->blk_stat[block]);
 726         blk_stat->block_erased++;
 727
 728         return (0);
 729
 730 }
 731
 732 static int
 733 onfi_is_blk_bad(device_t device, uint32_t block_number, uint8_t *bad)
 734 {
 735         struct nand_chip *chip;
 736         int page_number, i, j, err;
 737         uint8_t *oob;
 738
 739         chip = device_get_softc(device);
 740
 741         oob = malloc(chip->chip_geom.oob_size, M_NAND, M_WAITOK);
 742
 743         page_number = block_number * chip->chip_geom.pgs_per_blk;
 744         *bad = 0;
 745         /* Check OOB of first and last page */
 746         for (i = 0; i < 2; i++, page_number+= chip->chip_geom.pgs_per_blk - 1) {
 747                 err = generic_read_oob(device, page_number, oob,
 748                     chip->chip_geom.oob_size, 0);
 749                 if (err) {
 750                         device_printf(device, "%s: cannot allocate oob\n",
 751                             __func__);
 752                         free(oob, M_NAND);
 753                         return (ENOMEM);
 754                 }
 755
 756                 for (j = 0; j < chip->chip_geom.oob_size; j++) {
 757                         if (!oob[j]) {
 758                                 *bad = 1;
 759                                 free(oob, M_NAND);
 760                                 return (0);
 761                         }
 762                 }
 763         }
 764
 765         free(oob, M_NAND);
 766
 767         return (0);
 768 }
 769
 770 static int
 771 send_small_read_page(device_t nand, uint8_t start_command,
 772     uint32_t row, uint32_t column)
 773 {
 774         device_t nandbus = device_get_parent(nand);
 775
 776         if (NANDBUS_SEND_COMMAND(nandbus, start_command))
 777                 return (ENXIO);
 778
 779         if (nand_send_address(nand, row, column, -1))
 780                 return (ENXIO);
 781
 782         if (NANDBUS_START_COMMAND(nandbus))
 783                 return (ENXIO);
 784
 785         return (0);
 786 }
 787
 788
 789 static int
 790 small_read_page(device_t nand, uint32_t page, void *buf, uint32_t len,
 791     uint32_t offset)
 792 {
 793         struct nand_chip *chip;
 794         struct page_stat *pg_stat;
 795         device_t nandbus;
 796         uint32_t row;
 797
 798         nand_debug(NDBG_GEN,"%p small read page %x[%x] at %x", nand, page, len, offset);
 799         chip = device_get_softc(nand);
 800         nandbus = device_get_parent(nand);
 801
 802         if (nand_check_page_boundary(chip, page))
 803                 return (ENXIO);
 804
 805         page_to_row(&chip->chip_geom, page, &row);
 806
 807         if (offset < 256) {
 808                 if (send_small_read_page(nand, NAND_CMD_SMALLA, row, offset))
 809                         return (ENXIO);
 810         } else {
 811                 offset -= 256;
 812                 if (send_small_read_page(nandbus, NAND_CMD_SMALLB, row, offset))
 813                         return (ENXIO);
 814         }
 815
 816         DELAY(chip->t_r);
 817
 818         NANDBUS_READ_BUFFER(nandbus, buf, len);
 819
 820         if (check_fail(nandbus))
 821                 return (ENXIO);
 822
 823         pg_stat = &(chip->pg_stat[page]);
 824         pg_stat->page_raw_read++;
 825
 826         return (0);
 827 }
 828
 829 static int
 830 small_read_oob(device_t nand, uint32_t page, void *buf, uint32_t len,
 831     uint32_t offset)
 832 {
 833         struct nand_chip *chip;
 834         struct page_stat *pg_stat;
 835         device_t nandbus;
 836         uint32_t row;
 837
 838         nand_debug(NDBG_GEN,"%p small read oob %x[%x] at %x", nand, page, len, offset);
 839         chip = device_get_softc(nand);
 840         nandbus = device_get_parent(nand);
 841
 842         if (nand_check_page_boundary(chip, page))
 843                 return (ENXIO);
 844
 845         page_to_row(&chip->chip_geom, page, &row);
 846
 847         if (send_small_read_page(nand, NAND_CMD_SMALLOOB, row, 0))
 848                 return (ENXIO);
 849
 850         DELAY(chip->t_r);
 851
 852         NANDBUS_READ_BUFFER(nandbus, buf, len);
 853
 854         if (check_fail(nandbus))
 855                 return (ENXIO);
 856
 857         pg_stat = &(chip->pg_stat[page]);
 858         pg_stat->page_raw_read++;
 859
 860         return (0);
 861 }
 862
 863 static int
 864 small_program_page(device_t nand, uint32_t page, void* buf, uint32_t len,
 865     uint32_t offset)
 866 {
 867         struct nand_chip *chip;
 868         device_t nandbus;
 869         uint32_t row;
 870
 871         nand_debug(NDBG_GEN,"%p small prog page %x[%x] at %x", nand, page, len, offset);
 872         chip = device_get_softc(nand);
 873         nandbus = device_get_parent(nand);
 874
 875         if (nand_check_page_boundary(chip, page))
 876                 return (ENXIO);
 877
 878         page_to_row(&chip->chip_geom, page, &row);
 879
 880         if (!can_write(nandbus))
 881                 return (ENXIO);
 882
 883         if (offset < 256) {
 884                 if (NANDBUS_SEND_COMMAND(nandbus, NAND_CMD_SMALLA))
 885                         return (ENXIO);
 886         } else {
 887                 if (NANDBUS_SEND_COMMAND(nandbus, NAND_CMD_SMALLB))
 888                         return (ENXIO);
 889         }
 890
 891         if (send_start_program_page(nand, row, offset))
 892                 return (ENXIO);
 893
 894         NANDBUS_WRITE_BUFFER(nandbus, buf, len);
 895
 896         if (send_end_program_page(nandbus, NAND_CMD_PROG_END))
 897                 return (ENXIO);
 898
 899         DELAY(chip->t_prog);
 900
 901         if (check_fail(nandbus))
 902                 return (ENXIO);
 903
 904         return (0);
 905 }
 906
 907 static int
 908 small_program_oob(device_t nand, uint32_t page, void* buf, uint32_t len,
 909     uint32_t offset)
 910 {
 911         struct nand_chip *chip;
 912         device_t nandbus;
 913         uint32_t row;
 914
 915         nand_debug(NDBG_GEN,"%p small prog oob %x[%x] at %x", nand, page, len, offset);
 916         chip = device_get_softc(nand);
 917         nandbus = device_get_parent(nand);
 918
 919         if (nand_check_page_boundary(chip, page))
 920                 return (ENXIO);
 921
 922         page_to_row(&chip->chip_geom, page, &row);
 923
 924         if (!can_write(nandbus))
 925                 return (ENXIO);
 926
 927         if (NANDBUS_SEND_COMMAND(nandbus, NAND_CMD_SMALLOOB))
 928                 return (ENXIO);
 929
 930         if (send_start_program_page(nand, row, offset))
 931                 return (ENXIO);
 932
 933         NANDBUS_WRITE_BUFFER(nandbus, buf, len);
 934
 935         if (send_end_program_page(nandbus, NAND_CMD_PROG_END))
 936                 return (ENXIO);
 937
 938         DELAY(chip->t_prog);
 939
 940         if (check_fail(nandbus))
 941                 return (ENXIO);
 942
 943         return (0);
 944 }
 945
 946 int
 947 nand_send_address(device_t nand, int32_t row, int32_t col, int8_t id)
 948 {
 949         struct nandbus_ivar *ivar;
 950         device_t nandbus;
 951         uint8_t addr;
 952         int err = 0;
 953         int i;
 954
 955         nandbus = device_get_parent(nand);
 956         ivar = device_get_ivars(nand);
 957
 958         if (id != -1) {
 959                 nand_debug(NDBG_GEN,"send_address: send id %02x", id);
 960                 err = NANDBUS_SEND_ADDRESS(nandbus, id);
 961         }
 962
 963         if (!err && col != -1) {
 964                 for (i = 0; i < ivar->cols; i++, col >>= 8) {
 965                         addr = (uint8_t)(col & 0xff);
 966                         nand_debug(NDBG_GEN,"send_address: send address column "
 967                             "%02x", addr);
 968                         err = NANDBUS_SEND_ADDRESS(nandbus, addr);
 969                         if (err)
 970                                 break;
 971                 }
 972         }
 973
 974         if (!err && row != -1) {
 975                 for (i = 0; i < ivar->rows; i++, row >>= 8) {
 976                         addr = (uint8_t)(row & 0xff);
 977                         nand_debug(NDBG_GEN,"send_address: send address row "
 978                             "%02x", addr);
 979                         err = NANDBUS_SEND_ADDRESS(nandbus, addr);
 980                         if (err)
 981                                 break;
 982                 }
 983         }
 984
 985         return (err);
 986 }
 987
 988 static int
 989 generic_is_blk_bad(device_t dev, uint32_t block, uint8_t *bad)
 990 {
 991         struct nand_chip *chip;
 992         int page_number, err, i;
 993         uint8_t *oob;
 994
 995         chip = device_get_softc(dev);
 996
 997         oob = malloc(chip->chip_geom.oob_size, M_NAND, M_WAITOK);
 998
 999         page_number = block * chip->chip_geom.pgs_per_blk;
1000         *bad = 0;
1001
1002         /* Check OOB of first and second page */
1003         for (i = 0; i < 2; i++) {
1004                 err = NAND_READ_OOB(dev, page_number + i, oob,
1005                     chip->chip_geom.oob_size, 0);
1006                 if (err) {
1007                         device_printf(dev, "%s: cannot allocate OOB\n",
1008                             __func__);
1009                         free(oob, M_NAND);
1010                         return (ENOMEM);
1011                 }
1012
1013                 if (!oob[0]) {
1014                         *bad = 1;
1015                         free(oob, M_NAND);
1016                         return (0);
1017                 }
1018         }
1019
1020         free(oob, M_NAND);
1021
1022         return (0);
1023 }
1024
1025 static int
1026 generic_get_ecc(device_t dev, void *buf, void *ecc, int *needwrite)
1027 {
1028         struct nand_chip *chip = device_get_softc(dev);
1029         struct chip_geom *cg = &chip->chip_geom;
1030
1031         return (NANDBUS_GET_ECC(device_get_parent(dev), buf, cg->page_size,
1032             ecc, needwrite));
1033 }
1034
1035 static int
1036 generic_correct_ecc(device_t dev, void *buf, void *readecc, void *calcecc)
1037 {
1038         struct nand_chip *chip = device_get_softc(dev);
1039         struct chip_geom *cg = &chip->chip_geom;
1040
1041         return (NANDBUS_CORRECT_ECC(device_get_parent(dev), buf,
1042             cg->page_size, readecc, calcecc));
1043 }
1044
1045
1046 #if 0
1047 int
1048 nand_chng_read_col(device_t nand, uint32_t col, void *buf, size_t len)
1049 {
1050         struct nand_chip *chip;
1051         device_t nandbus;
1052
1053         chip = device_get_softc(nand);
1054         nandbus = device_get_parent(nand);
1055
1056         if (NANDBUS_SEND_COMMAND(nandbus, NAND_CMD_CHNG_READ_COL))
1057                 return (ENXIO);
1058
1059         if (NANDBUS_SEND_ADDRESS(nandbus, -1, col, -1))
1060                 return (ENXIO);
1061
1062         if (NANDBUS_SEND_COMMAND(nandbus, NAND_CMD_CHNG_READ_COL_END))
1063                 return (ENXIO);
1064
1065         if (NANDBUS_START_COMMAND(nandbus))
1066                 return (ENXIO);
1067
1068         if (buf != NULL && len > 0)
1069                 NANDBUS_READ_BUFFER(nandbus, buf, len);
1070
1071         return (0);
1072 }
1073
1074 int
1075 nand_chng_write_col(device_t dev, uint32_t col, void *buf,
1076     size_t len)
1077 {
1078         struct nand_chip *chip;
1079         device_t nandbus;
1080
1081         chip = device_get_softc(dev);
1082         nandbus = device_get_parent(dev);
1083
1084         if (NANDBUS_SEND_COMMAND(nandbus, NAND_CMD_CHNG_WRITE_COL))
1085                 return (ENXIO);
1086
1087         if (NANDBUS_SEND_ADDRESS(nandbus, -1, col, -1))
1088                 return (ENXIO);
1089
1090         if (buf != NULL && len > 0)
1091                 NANDBUS_WRITE_BUFFER(nandbus, buf, len);
1092
1093         if (NANDBUS_SEND_COMMAND(nandbus, NAND_CMD_CHNG_READ_COL_END))
1094                 return (ENXIO);
1095
1096         if (NANDBUS_START_COMMAND(nandbus))
1097                 return (ENXIO);
1098
1099         return (0);
1100 }
1101
1102 int
1103 nand_copyback_read(device_t dev, uint32_t page, uint32_t col,
1104     void *buf, size_t len)
1105 {
1106         struct nand_chip *chip;
1107         struct page_stat *pg_stat;
1108         device_t nandbus;
1109         uint32_t row;
1110
1111         nand_debug(NDBG_GEN," raw read page %x[%x] at %x", page, col, len);
1112         chip = device_get_softc(dev);
1113         nandbus = device_get_parent(dev);
1114
1115         if (nand_check_page_boundary(chip, page))
1116                 return (ENXIO);
1117
1118         page_to_row(&chip->chip_geom, page, &row);
1119
1120         if (send_read_page(nand, NAND_CMD_READ, NAND_CMD_READ_CPBK, row, 0))
1121                 return (ENXIO);
1122
1123         DELAY(chip->t_r);
1124         if (check_fail(nandbus))
1125                 return (ENXIO);
1126
1127         if (buf != NULL && len > 0)
1128                 NANDBUS_READ_BUFFER(nandbus, buf, len);
1129
1130         pg_stat = &(chip->pg_stat[page]);
1131         pg_stat->page_raw_read++;
1132
1133         return (0);
1134 }
1135
1136 int
1137 nand_copyback_prog(device_t dev, uint32_t page, uint32_t col,
1138     void *buf, size_t len)
1139 {
1140         struct nand_chip *chip;
1141         struct page_stat *pg_stat;
1142         device_t nandbus;
1143         uint32_t row;
1144
1145         nand_debug(NDBG_GEN,"copyback prog page %x[%x]",  page, len);
1146         chip = device_get_softc(dev);
1147         nandbus = device_get_parent(dev);
1148
1149         if (nand_check_page_boundary(chip, page))
1150                 return (ENXIO);
1151
1152         page_to_row(&chip->chip_geom, page, &row);
1153
1154         if (!can_write(nandbus))
1155                 return (ENXIO);
1156
1157         if (NANDBUS_SEND_COMMAND(nandbus, NAND_CMD_CHNG_WRITE_COL))
1158                 return (ENXIO);
1159
1160         if (NANDBUS_SEND_ADDRESS(nandbus, row, col, -1))
1161                 return (ENXIO);
1162
1163         if (buf != NULL && len > 0)
1164                 NANDBUS_WRITE_BUFFER(nandbus, buf, len);
1165
1166         if (send_end_program_page(nandbus, NAND_CMD_PROG_END))
1167                 return (ENXIO);
1168
1169         DELAY(chip->t_prog);
1170
1171         if (check_fail(nandbus))
1172                 return (ENXIO);
1173
1174         pg_stat = &(chip->pg_stat[page]);
1175         pg_stat->page_raw_written++;
1176
1177         return (0);
1178 }
1179
1180 int
1181 nand_copyback_prog_intlv(device_t dev, uint32_t page)
1182 {
1183         struct nand_chip *chip;
1184         struct page_stat *pg_stat;
1185         device_t nandbus;
1186         uint32_t row;
1187
1188         nand_debug(NDBG_GEN,"cache prog page %x", page);
1189         chip = device_get_softc(dev);
1190         nandbus = device_get_parent(dev);
1191
1192         if (nand_check_page_boundary(chip, page))
1193                 return (ENXIO);
1194
1195         page_to_row(&chip->chip_geom, page, &row);
1196
1197         if (!can_write(nandbus))
1198                 return (ENXIO);
1199
1200         if (send_start_program_page(nand, row, 0))
1201                 return (ENXIO);
1202
1203         if (send_end_program_page(nandbus, NAND_CMD_PROG_INTLV))
1204                 return (ENXIO);
1205
1206         DELAY(chip->t_prog);
1207
1208         if (check_fail(nandbus))
1209                 return (ENXIO);
1210
1211         pg_stat = &(chip->pg_stat[page]);
1212         pg_stat->page_raw_written++;
1213
1214         return (0);
1215 }
1216
1217 int
1218 nand_prog_cache(device_t dev, uint32_t page, uint32_t col,
1219     void *buf, size_t len, uint8_t end)
1220 {
1221         struct nand_chip *chip;
1222         struct page_stat *pg_stat;
1223         device_t nandbus;
1224         uint32_t row;
1225         uint8_t command;
1226
1227         nand_debug(NDBG_GEN,"cache prog page %x[%x]",  page, len);
1228         chip = device_get_softc(dev);
1229         nandbus = device_get_parent(dev);
1230
1231         if (nand_check_page_boundary(chip, page))
1232                 return (ENXIO);
1233
1234         page_to_row(&chip->chip_geom, page, &row);
1235
1236         if (!can_write(nandbus))
1237                 return (ENXIO);
1238
1239         if (send_start_program_page(dev, row, 0))
1240                 return (ENXIO);
1241
1242         NANDBUS_WRITE_BUFFER(nandbus, buf, len);
1243
1244         if (end)
1245                 command = NAND_CMD_PROG_END;
1246         else
1247                 command = NAND_CMD_PROG_CACHE;
1248
1249         if (send_end_program_page(nandbus, command))
1250                 return (ENXIO);
1251
1252         DELAY(chip->t_prog);
1253
1254         if (check_fail(nandbus))
1255                 return (ENXIO);
1256
1257         pg_stat = &(chip->pg_stat[page]);
1258         pg_stat->page_raw_written++;
1259
1260         return (0);
1261 }
1262
1263 int
1264 nand_read_cache(device_t dev, uint32_t page, uint32_t col,
1265     void *buf, size_t len, uint8_t end)
1266 {
1267         struct nand_chip *chip;
1268         struct page_stat *pg_stat;
1269         device_t nandbus;
1270         uint32_t row;
1271         uint8_t command;
1272
1273         nand_debug(NDBG_GEN,"cache read page %x[%x] ", page, len);
1274         chip = device_get_softc(dev);
1275         nandbus = device_get_parent(dev);
1276
1277         if (nand_check_page_boundary(chip, page))
1278                 return (ENXIO);
1279
1280         page_to_row(&chip->chip_geom, page, &row);
1281
1282         if (page != -1) {
1283                 if (NANDBUS_SEND_COMMAND(nandbus, NAND_CMD_READ))
1284                         return (ENXIO);
1285
1286                 if (NANDBUS_SEND_ADDRESS(nandbus, row, col, -1))
1287                         return (ENXIO);
1288         }
1289
1290         if (end)
1291                 command = NAND_CMD_READ_CACHE_END;
1292         else
1293                 command = NAND_CMD_READ_CACHE;
1294
1295         if (NANDBUS_SEND_COMMAND(nandbus, command))
1296                 return (ENXIO);
1297
1298         if (NANDBUS_START_COMMAND(nandbus))
1299                 return (ENXIO);
1300
1301         DELAY(chip->t_r);
1302         if (check_fail(nandbus))
1303                 return (ENXIO);
1304
1305         if (buf != NULL && len > 0)
1306                 NANDBUS_READ_BUFFER(nandbus, buf, len);
1307
1308         pg_stat = &(chip->pg_stat[page]);
1309         pg_stat->page_raw_read++;
1310
1311         return (0);
1312 }
1313
1314 int
1315 nand_get_feature(device_t dev, uint8_t feat, void *buf)
1316 {
1317         struct nand_chip *chip;
1318         device_t nandbus;
1319
1320         nand_debug(NDBG_GEN,"nand get feature");
1321
1322         chip = device_get_softc(dev);
1323         nandbus = device_get_parent(dev);
1324
1325         if (NANDBUS_SEND_COMMAND(nandbus, NAND_CMD_GET_FEATURE))
1326                 return (ENXIO);
1327
1328         if (NANDBUS_SEND_ADDRESS(nandbus, -1, -1, feat))
1329                 return (ENXIO);
1330
1331         if (NANDBUS_START_COMMAND(nandbus))
1332                 return (ENXIO);
1333
1334         DELAY(chip->t_r);
1335         NANDBUS_READ_BUFFER(nandbus, buf, 4);
1336
1337         return (0);
1338 }
1339
1340 int
1341 nand_set_feature(device_t dev, uint8_t feat, void *buf)
1342 {
1343         struct nand_chip *chip;
1344         device_t nandbus;
1345
1346         nand_debug(NDBG_GEN,"nand set feature");
1347
1348         chip = device_get_softc(dev);
1349         nandbus = device_get_parent(dev);
1350
1351         if (NANDBUS_SEND_COMMAND(nandbus, NAND_CMD_SET_FEATURE))
1352                 return (ENXIO);
1353
1354         if (NANDBUS_SEND_ADDRESS(nandbus, -1, -1, feat))
1355                 return (ENXIO);
1356
1357         NANDBUS_WRITE_BUFFER(nandbus, buf, 4);
1358
1359         if (NANDBUS_START_COMMAND(nandbus))
1360                 return (ENXIO);
1361
1362         return (0);
1363 }
1364 #endif