2 * Copyright (C) 2009-2012 Semihalf
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/types.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
35 #include <sys/malloc.h>
36 #include <sys/module.h>
37 #include <sys/mutex.h>
39 #include <sys/sched.h>
40 #include <sys/kthread.h>
41 #include <sys/unistd.h>
43 #include <dev/nand/nand.h>
44 #include <dev/nand/nandsim_chip.h>
45 #include <dev/nand/nandsim_log.h>
46 #include <dev/nand/nandsim_swap.h>
48 MALLOC_DEFINE(M_NANDSIM, "NANDsim", "NANDsim dynamic data");
50 #define NANDSIM_CHIP_LOCK(chip) mtx_lock(&(chip)->ns_lock)
51 #define NANDSIM_CHIP_UNLOCK(chip) mtx_unlock(&(chip)->ns_lock)
53 static nandsim_evh_t erase_evh;
54 static nandsim_evh_t idle_evh;
55 static nandsim_evh_t poweron_evh;
56 static nandsim_evh_t reset_evh;
57 static nandsim_evh_t read_evh;
58 static nandsim_evh_t readid_evh;
59 static nandsim_evh_t readparam_evh;
60 static nandsim_evh_t write_evh;
62 static void nandsim_loop(void *);
63 static void nandsim_undefined(struct nandsim_chip *, uint8_t);
64 static void nandsim_bad_address(struct nandsim_chip *, uint8_t *);
65 static void nandsim_ignore_address(struct nandsim_chip *, uint8_t);
66 static void nandsim_sm_error(struct nandsim_chip *);
67 static void nandsim_start_handler(struct nandsim_chip *, nandsim_evh_t);
69 static void nandsim_callout_eh(void *);
70 static int nandsim_delay(struct nandsim_chip *, int);
72 static int nandsim_bbm_init(struct nandsim_chip *, uint32_t, uint32_t *);
73 static int nandsim_blk_state_init(struct nandsim_chip *, uint32_t, uint32_t);
74 static void nandsim_blk_state_destroy(struct nandsim_chip *);
75 static int nandchip_is_block_valid(struct nandsim_chip *, int);
77 static void nandchip_set_status(struct nandsim_chip *, uint8_t);
78 static void nandchip_clear_status(struct nandsim_chip *, uint8_t);
80 struct proc *nandsim_proc;
83 nandsim_chip_init(struct nandsim_softc* sc, uint8_t chip_num,
84 struct sim_chip *sim_chip)
86 struct nandsim_chip *chip;
87 struct onfi_params *chip_param;
92 chip = malloc(sizeof(*chip), M_NANDSIM, M_WAITOK | M_ZERO);
94 mtx_init(&chip->ns_lock, "nandsim lock", NULL, MTX_DEF);
95 callout_init(&chip->ns_callout, 1);
96 STAILQ_INIT(&chip->nandsim_events);
98 chip->chip_num = chip_num;
99 chip->ctrl_num = sim_chip->ctrl_num;
102 if (!sim_chip->is_wp)
103 nandchip_set_status(chip, NAND_STATUS_WP);
105 chip_param = &chip->params;
107 chip->id.dev_id = sim_chip->device_id;
108 chip->id.man_id = sim_chip->manufact_id;
110 chip->error_ratio = sim_chip->error_ratio;
111 chip->wear_level = sim_chip->wear_level;
112 chip->prog_delay = sim_chip->prog_time;
113 chip->erase_delay = sim_chip->erase_time;
114 chip->read_delay = sim_chip->read_time;
116 chip_param->t_prog = sim_chip->prog_time;
117 chip_param->t_bers = sim_chip->erase_time;
118 chip_param->t_r = sim_chip->read_time;
119 bcopy("onfi", &chip_param->signature, 4);
121 chip_param->manufacturer_id = sim_chip->manufact_id;
122 strncpy(chip_param->manufacturer_name, sim_chip->manufacturer, 12);
123 chip_param->manufacturer_name[11] = 0;
124 strncpy(chip_param->device_model, sim_chip->device_model, 20);
125 chip_param->device_model[19] = 0;
127 chip_param->bytes_per_page = sim_chip->page_size;
128 chip_param->spare_bytes_per_page = sim_chip->oob_size;
129 chip_param->pages_per_block = sim_chip->pgs_per_blk;
130 chip_param->blocks_per_lun = sim_chip->blks_per_lun;
131 chip_param->luns = sim_chip->luns;
133 init_chip_geom(&chip->cg, chip_param->luns, chip_param->blocks_per_lun,
134 chip_param->pages_per_block, chip_param->bytes_per_page,
135 chip_param->spare_bytes_per_page);
137 chip_param->address_cycles = sim_chip->row_addr_cycles |
138 (sim_chip->col_addr_cycles << 4);
139 chip_param->features = sim_chip->features;
140 if (sim_chip->width == 16)
141 chip_param->features |= ONFI_FEAT_16BIT;
143 size = chip_param->blocks_per_lun * chip_param->luns;
145 error = nandsim_blk_state_init(chip, size, sim_chip->wear_level);
147 mtx_destroy(&chip->ns_lock);
148 free(chip, M_NANDSIM);
152 error = nandsim_bbm_init(chip, size, sim_chip->bad_block_map);
154 mtx_destroy(&chip->ns_lock);
155 nandsim_blk_state_destroy(chip);
156 free(chip, M_NANDSIM);
160 nandsim_start_handler(chip, poweron_evh);
162 nand_debug(NDBG_SIM,"Create thread for chip%d [%8p]", chip->chip_num,
164 /* Create chip thread */
165 error = kproc_kthread_add(nandsim_loop, chip, &nandsim_proc,
166 &chip->nandsim_td, RFSTOPPED | RFHIGHPID,
167 0, "nandsim", "chip");
169 mtx_destroy(&chip->ns_lock);
170 nandsim_blk_state_destroy(chip);
171 free(chip, M_NANDSIM);
175 thread_lock(chip->nandsim_td);
176 sched_class(chip->nandsim_td, PRI_REALTIME);
177 sched_add(chip->nandsim_td, SRQ_BORING);
178 thread_unlock(chip->nandsim_td);
180 size = (chip_param->bytes_per_page +
181 chip_param->spare_bytes_per_page) *
182 chip_param->pages_per_block;
184 sprintf(swapfile, "chip%d%d.swp", chip->ctrl_num, chip->chip_num);
185 chip->swap = nandsim_swap_init(swapfile, chip_param->blocks_per_lun *
186 chip_param->luns, size);
188 nandsim_chip_destroy(chip);
190 /* Wait for new thread to enter main loop */
191 tsleep(chip->nandsim_td, PWAIT, "ns_chip", 1 * hz);
197 nandsim_blk_state_init(struct nandsim_chip *chip, uint32_t size,
202 if (!chip || size == 0)
205 chip->blk_state = malloc(size * sizeof(struct nandsim_block_state),
206 M_NANDSIM, M_WAITOK | M_ZERO);
208 for (i = 0; i < size; i++) {
210 chip->blk_state[i].wear_lev = wear_lev;
212 chip->blk_state[i].wear_lev = -1;
219 nandsim_blk_state_destroy(struct nandsim_chip *chip)
222 if (chip && chip->blk_state)
223 free(chip->blk_state, M_NANDSIM);
227 nandsim_bbm_init(struct nandsim_chip *chip, uint32_t size,
233 if ((chip == NULL) || (size == 0))
236 if (chip->blk_state == NULL)
242 for (i = 0; i < MAX_BAD_BLOCKS; i++) {
245 if (index == 0xffffffff)
247 else if (index > size)
250 chip->blk_state[index].is_bad = 1;
257 nandsim_chip_destroy(struct nandsim_chip *chip)
259 struct nandsim_ev *ev;
261 ev = create_event(chip, NANDSIM_EV_EXIT, 0);
267 nandsim_chip_freeze(struct nandsim_chip *chip)
270 chip->flags |= NANDSIM_CHIP_FROZEN;
274 nandsim_loop(void *arg)
276 struct nandsim_chip *chip = (struct nandsim_chip *)arg;
277 struct nandsim_ev *ev;
279 nand_debug(NDBG_SIM,"Start main loop for chip%d [%8p]", chip->chip_num,
282 NANDSIM_CHIP_LOCK(chip);
283 if (!(chip->flags & NANDSIM_CHIP_ACTIVE)) {
284 chip->flags |= NANDSIM_CHIP_ACTIVE;
285 wakeup(chip->nandsim_td);
288 if (STAILQ_EMPTY(&chip->nandsim_events)) {
289 nand_debug(NDBG_SIM,"Chip%d [%8p] going sleep",
290 chip->chip_num, chip);
291 msleep(chip, &chip->ns_lock, PRIBIO, "nandev", 0);
294 ev = STAILQ_FIRST(&chip->nandsim_events);
295 STAILQ_REMOVE_HEAD(&chip->nandsim_events, links);
296 NANDSIM_CHIP_UNLOCK(chip);
297 if (ev->type == NANDSIM_EV_EXIT) {
298 NANDSIM_CHIP_LOCK(chip);
301 while (!STAILQ_EMPTY(&chip->nandsim_events)) {
302 ev = STAILQ_FIRST(&chip->nandsim_events);
303 STAILQ_REMOVE_HEAD(&chip->nandsim_events,
308 NANDSIM_CHIP_UNLOCK(chip);
309 nandsim_log(chip, NANDSIM_LOG_SM, "destroyed\n");
310 mtx_destroy(&chip->ns_lock);
311 nandsim_blk_state_destroy(chip);
312 nandsim_swap_destroy(chip->swap);
313 free(chip, M_NANDSIM);
319 if (!(chip->flags & NANDSIM_CHIP_FROZEN)) {
320 nand_debug(NDBG_SIM,"Chip [%x] get event [%x]",
321 chip->chip_num, ev->type);
322 chip->ev_handler(chip, ev->type, ev->data);
332 create_event(struct nandsim_chip *chip, uint8_t type, uint8_t data_size)
334 struct nandsim_ev *ev;
336 ev = malloc(sizeof(*ev), M_NANDSIM, M_NOWAIT | M_ZERO);
338 nand_debug(NDBG_SIM,"Cannot create event");
343 ev->data = malloc(sizeof(*ev), M_NANDSIM, M_NOWAIT | M_ZERO);
351 destroy_event(struct nandsim_ev *ev)
355 free(ev->data, M_NANDSIM);
360 send_event(struct nandsim_ev *ev)
362 struct nandsim_chip *chip = ev->chip;
364 if (!(chip->flags & NANDSIM_CHIP_FROZEN)) {
365 nand_debug(NDBG_SIM,"Chip%d [%p] send event %x",
366 chip->chip_num, chip, ev->type);
368 NANDSIM_CHIP_LOCK(chip);
369 STAILQ_INSERT_TAIL(&chip->nandsim_events, ev, links);
370 NANDSIM_CHIP_UNLOCK(chip);
373 if ((ev->type != NANDSIM_EV_TIMEOUT) && chip->nandsim_td &&
374 (curthread != chip->nandsim_td))
375 tsleep(ev, PWAIT, "ns_ev", 5 * hz);
382 nandsim_callout_eh(void *arg)
384 struct nandsim_ev *ev = (struct nandsim_ev *)arg;
390 nandsim_delay(struct nandsim_chip *chip, int timeout)
392 struct nandsim_ev *ev;
393 struct timeval delay;
396 nand_debug(NDBG_SIM,"Chip[%d] Set delay: %d", chip->chip_num, timeout);
398 ev = create_event(chip, NANDSIM_EV_TIMEOUT, 0);
402 chip->sm_state = NANDSIM_STATE_TIMEOUT;
403 tm = (timeout/10000) * (hz / 100);
404 if (callout_reset(&chip->ns_callout, tm, nandsim_callout_eh, ev))
407 delay.tv_sec = chip->read_delay / 1000000;
408 delay.tv_usec = chip->read_delay % 1000000;
409 timevaladd(&chip->delay_tv, &delay);
415 nandsim_start_handler(struct nandsim_chip *chip, nandsim_evh_t evh)
417 struct nandsim_ev *ev;
419 chip->ev_handler = evh;
421 nand_debug(NDBG_SIM,"Start handler %p for chip%d [%p]", evh,
422 chip->chip_num, chip);
423 ev = create_event(chip, NANDSIM_EV_START, 0);
425 nandsim_sm_error(chip);
431 nandchip_set_data(struct nandsim_chip *chip, uint8_t *data, uint32_t len,
435 nand_debug(NDBG_SIM,"Chip [%x] data %p [%x] at %x", chip->chip_num,
437 chip->data.data_ptr = data;
438 chip->data.size = len;
439 chip->data.index = idx;
443 nandchip_chip_space(struct nandsim_chip *chip, int32_t row, int32_t column,
444 size_t size, uint8_t writing)
446 struct block_space *blk_space;
447 uint32_t lun, block, page, offset, block_size;
450 block_size = chip->cg.block_size +
451 (chip->cg.oob_size * chip->cg.pgs_per_blk);
453 err = nand_row_to_blkpg(&chip->cg, row, &lun, &block, &page);
455 nand_debug(NDBG_SIM,"cannot get address\n");
459 if (!nandchip_is_block_valid(chip, block)) {
460 nandchip_set_data(chip, NULL, 0, 0);
464 blk_space = get_bs(chip->swap, block, writing);
466 nandchip_set_data(chip, NULL, 0, 0);
470 if (size > block_size)
473 if (size == block_size) {
477 offset = page * (chip->cg.page_size + chip->cg.oob_size);
479 nandchip_set_data(chip, &blk_space->blk_ptr[offset], size, column);
485 nandchip_get_addr_byte(struct nandsim_chip *chip, void *data, uint32_t *value)
491 buffer = (uint8_t *)value;
492 byte = *((uint8_t *)data);
494 KASSERT((chip->sm_state == NANDSIM_STATE_WAIT_ADDR_ROW ||
495 chip->sm_state == NANDSIM_STATE_WAIT_ADDR_COL),
496 ("unexpected state"));
498 if (chip->sm_state == NANDSIM_STATE_WAIT_ADDR_ROW) {
499 ncycles = chip->params.address_cycles & 0xf;
500 buffer[chip->sm_addr_cycle++] = byte;
501 } else if (chip->sm_state == NANDSIM_STATE_WAIT_ADDR_COL) {
502 ncycles = (chip->params.address_cycles >> 4) & 0xf;
503 buffer[chip->sm_addr_cycle++] = byte;
506 nand_debug(NDBG_SIM, "Chip [%x] read addr byte: %02x (%d of %d)\n",
507 chip->chip_num, byte, chip->sm_addr_cycle, ncycles);
509 if (chip->sm_addr_cycle == ncycles) {
510 chip->sm_addr_cycle = 0;
518 nandchip_is_block_valid(struct nandsim_chip *chip, int block_num)
521 if (!chip || !chip->blk_state)
524 if (chip->blk_state[block_num].wear_lev == 0 ||
525 chip->blk_state[block_num].is_bad)
532 nandchip_set_status(struct nandsim_chip *chip, uint8_t flags)
535 chip->chip_status |= flags;
539 nandchip_clear_status(struct nandsim_chip *chip, uint8_t flags)
542 chip->chip_status &= ~flags;
546 nandchip_get_status(struct nandsim_chip *chip)
548 return (chip->chip_status);
552 nandsim_chip_timeout(struct nandsim_chip *chip)
558 if (chip->sm_state == NANDSIM_STATE_TIMEOUT &&
559 timevalcmp(&tv, &chip->delay_tv, >=)) {
560 nandchip_set_status(chip, NAND_STATUS_RDY);
564 poweron_evh(struct nandsim_chip *chip, uint32_t type, void *data)
568 if (type == NANDSIM_EV_START)
569 chip->sm_state = NANDSIM_STATE_IDLE;
570 else if (type == NANDSIM_EV_CMD) {
571 cmd = *(uint8_t *)data;
574 nandsim_log(chip, NANDSIM_LOG_SM, "in RESET state\n");
575 nandsim_start_handler(chip, reset_evh);
578 nandsim_undefined(chip, type);
582 nandsim_undefined(chip, type);
586 idle_evh(struct nandsim_chip *chip, uint32_t type, void *data)
590 if (type == NANDSIM_EV_START) {
591 nandsim_log(chip, NANDSIM_LOG_SM, "in IDLE state\n");
592 chip->sm_state = NANDSIM_STATE_WAIT_CMD;
593 } else if (type == NANDSIM_EV_CMD) {
594 nandchip_clear_status(chip, NAND_STATUS_FAIL);
595 getmicrotime(&chip->delay_tv);
596 cmd = *(uint8_t *)data;
598 case NAND_CMD_READ_ID:
599 nandsim_start_handler(chip, readid_evh);
601 case NAND_CMD_READ_PARAMETER:
602 nandsim_start_handler(chip, readparam_evh);
605 nandsim_start_handler(chip, read_evh);
608 nandsim_start_handler(chip, write_evh);
611 nandsim_start_handler(chip, erase_evh);
614 nandsim_undefined(chip, type);
618 nandsim_undefined(chip, type);
622 readid_evh(struct nandsim_chip *chip, uint32_t type, void *data)
624 struct onfi_params *params;
627 params = &chip->params;
629 if (type == NANDSIM_EV_START) {
630 nandsim_log(chip, NANDSIM_LOG_SM, "in READID state\n");
631 chip->sm_state = NANDSIM_STATE_WAIT_ADDR_BYTE;
632 } else if (type == NANDSIM_EV_ADDR) {
634 addr = *((uint8_t *)data);
637 nandchip_set_data(chip, (uint8_t *)&chip->id, 2, 0);
638 else if (addr == ONFI_SIG_ADDR)
639 nandchip_set_data(chip, (uint8_t *)¶ms->signature,
642 nandsim_bad_address(chip, &addr);
644 nandsim_start_handler(chip, idle_evh);
646 nandsim_undefined(chip, type);
650 readparam_evh(struct nandsim_chip *chip, uint32_t type, void *data)
652 struct onfi_params *params;
655 params = &chip->params;
657 if (type == NANDSIM_EV_START) {
658 nandsim_log(chip, NANDSIM_LOG_SM, "in READPARAM state\n");
659 chip->sm_state = NANDSIM_STATE_WAIT_ADDR_BYTE;
660 } else if (type == NANDSIM_EV_ADDR) {
661 addr = *((uint8_t *)data);
664 nandchip_set_data(chip, (uint8_t *)params,
667 nandsim_bad_address(chip, &addr);
669 nandsim_start_handler(chip, idle_evh);
671 nandsim_undefined(chip, type);
675 read_evh(struct nandsim_chip *chip, uint32_t type, void *data)
677 static uint32_t column = 0, row = 0;
681 size = chip->cg.page_size + chip->cg.oob_size;
684 case NANDSIM_EV_START:
685 nandsim_log(chip, NANDSIM_LOG_SM, "in READ state\n");
686 chip->sm_state = NANDSIM_STATE_WAIT_ADDR_COL;
688 case NANDSIM_EV_ADDR:
689 if (chip->sm_state == NANDSIM_STATE_WAIT_ADDR_COL) {
690 if (nandchip_get_addr_byte(chip, data, &column))
693 chip->sm_state = NANDSIM_STATE_WAIT_ADDR_ROW;
694 } else if (chip->sm_state == NANDSIM_STATE_WAIT_ADDR_ROW) {
695 if (nandchip_get_addr_byte(chip, data, &row))
698 chip->sm_state = NANDSIM_STATE_WAIT_CMD;
700 nandsim_ignore_address(chip, *((uint8_t *)data));
703 cmd = *(uint8_t *)data;
704 if (chip->sm_state == NANDSIM_STATE_WAIT_CMD &&
705 cmd == NAND_CMD_READ_END) {
706 if (chip->read_delay != 0 &&
707 nandsim_delay(chip, chip->read_delay) == 0)
708 nandchip_clear_status(chip, NAND_STATUS_RDY);
710 nandchip_chip_space(chip, row, column, size, 0);
711 nandchip_set_status(chip, NAND_STATUS_RDY);
712 nandsim_start_handler(chip, idle_evh);
715 nandsim_undefined(chip, type);
717 case NANDSIM_EV_TIMEOUT:
718 if (chip->sm_state == NANDSIM_STATE_TIMEOUT) {
719 nandchip_chip_space(chip, row, column, size, 0);
720 nandchip_set_status(chip, NAND_STATUS_RDY);
721 nandsim_start_handler(chip, idle_evh);
723 nandsim_undefined(chip, type);
728 write_evh(struct nandsim_chip *chip, uint32_t type, void *data)
730 static uint32_t column, row;
735 size = chip->cg.page_size + chip->cg.oob_size;
738 case NANDSIM_EV_START:
739 nandsim_log(chip, NANDSIM_LOG_SM, "in WRITE state\n");
740 chip->sm_state = NANDSIM_STATE_WAIT_ADDR_COL;
742 case NANDSIM_EV_ADDR:
743 if (chip->sm_state == NANDSIM_STATE_WAIT_ADDR_COL) {
744 if (nandchip_get_addr_byte(chip, data, &column))
747 chip->sm_state = NANDSIM_STATE_WAIT_ADDR_ROW;
748 } else if (chip->sm_state == NANDSIM_STATE_WAIT_ADDR_ROW) {
749 if (nandchip_get_addr_byte(chip, data, &row))
752 err = nandchip_chip_space(chip, row, column, size, 1);
754 nandchip_set_status(chip, NAND_STATUS_FAIL);
756 chip->sm_state = NANDSIM_STATE_WAIT_CMD;
758 nandsim_ignore_address(chip, *((uint8_t *)data));
761 cmd = *(uint8_t *)data;
762 if (chip->sm_state == NANDSIM_STATE_WAIT_CMD &&
763 cmd == NAND_CMD_PROG_END) {
764 if (chip->prog_delay != 0 &&
765 nandsim_delay(chip, chip->prog_delay) == 0)
766 nandchip_clear_status(chip, NAND_STATUS_RDY);
768 nandchip_set_status(chip, NAND_STATUS_RDY);
769 nandsim_start_handler(chip, idle_evh);
772 nandsim_undefined(chip, type);
774 case NANDSIM_EV_TIMEOUT:
775 if (chip->sm_state == NANDSIM_STATE_TIMEOUT) {
776 nandsim_start_handler(chip, idle_evh);
777 nandchip_set_status(chip, NAND_STATUS_RDY);
779 nandsim_undefined(chip, type);
785 erase_evh(struct nandsim_chip *chip, uint32_t type, void *data)
787 static uint32_t row, block_size;
788 uint32_t lun, block, page;
792 block_size = chip->cg.block_size +
793 (chip->cg.oob_size * chip->cg.pgs_per_blk);
796 case NANDSIM_EV_START:
797 nandsim_log(chip, NANDSIM_LOG_SM, "in ERASE state\n");
798 chip->sm_state = NANDSIM_STATE_WAIT_ADDR_ROW;
801 cmd = *(uint8_t *)data;
802 if (chip->sm_state == NANDSIM_STATE_WAIT_CMD &&
803 cmd == NAND_CMD_ERASE_END) {
804 if (chip->data.data_ptr != NULL &&
805 chip->data.size == block_size)
806 memset(chip->data.data_ptr, 0xff, block_size);
808 nand_debug(NDBG_SIM,"Bad block erase data\n");
810 err = nand_row_to_blkpg(&chip->cg, row, &lun,
813 if (chip->blk_state[block].wear_lev > 0)
814 chip->blk_state[block].wear_lev--;
817 if (chip->erase_delay != 0 &&
818 nandsim_delay(chip, chip->erase_delay) == 0)
819 nandchip_clear_status(chip, NAND_STATUS_RDY);
821 nandchip_set_status(chip, NAND_STATUS_RDY);
822 nandsim_start_handler(chip, idle_evh);
825 nandsim_undefined(chip, type);
827 case NANDSIM_EV_ADDR:
828 if (chip->sm_state == NANDSIM_STATE_WAIT_ADDR_ROW) {
829 if (nandchip_get_addr_byte(chip, data, &row))
832 err = nandchip_chip_space(chip, row, 0, block_size, 1);
834 nandchip_set_status(chip, NAND_STATUS_FAIL);
836 chip->sm_state = NANDSIM_STATE_WAIT_CMD;
838 nandsim_ignore_address(chip, *((uint8_t *)data));
840 case NANDSIM_EV_TIMEOUT:
841 if (chip->sm_state == NANDSIM_STATE_TIMEOUT) {
842 nandchip_set_status(chip, NAND_STATUS_RDY);
843 nandsim_start_handler(chip, idle_evh);
845 nandsim_undefined(chip, type);
851 reset_evh(struct nandsim_chip *chip, uint32_t type, void *data)
854 if (type == NANDSIM_EV_START) {
855 nandsim_log(chip, NANDSIM_LOG_SM, "in RESET state\n");
856 chip->sm_state = NANDSIM_STATE_TIMEOUT;
857 nandchip_set_data(chip, NULL, 0, 0);
859 nandsim_start_handler(chip, idle_evh);
861 nandsim_undefined(chip, type);
865 nandsim_undefined(struct nandsim_chip *chip, uint8_t type)
868 nandsim_log(chip, NANDSIM_LOG_ERR,
869 "ERR: Chip received ev %x in state %x\n",
870 type, chip->sm_state);
871 nandsim_start_handler(chip, idle_evh);
875 nandsim_bad_address(struct nandsim_chip *chip, uint8_t *addr)
878 nandsim_log(chip, NANDSIM_LOG_ERR,
879 "ERR: Chip received out of range address"
880 "%02x%02x - %02x%02x%02x\n", addr[0], addr[1], addr[2],
885 nandsim_ignore_address(struct nandsim_chip *chip, uint8_t byte)
887 nandsim_log(chip, NANDSIM_LOG_SM, "ignored address byte: %d\n", byte);
891 nandsim_sm_error(struct nandsim_chip *chip)
894 nandsim_log(chip, NANDSIM_LOG_ERR, "ERR: State machine error."
895 "Restart required.\n");