2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (C) 2009-2012 Semihalf
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/types.h>
34 #include <sys/systm.h>
35 #include <sys/kernel.h>
37 #include <sys/malloc.h>
38 #include <sys/module.h>
39 #include <sys/mutex.h>
41 #include <sys/sched.h>
42 #include <sys/kthread.h>
43 #include <sys/unistd.h>
45 #include <dev/nand/nand.h>
46 #include <dev/nand/nandsim_chip.h>
47 #include <dev/nand/nandsim_log.h>
48 #include <dev/nand/nandsim_swap.h>
50 MALLOC_DEFINE(M_NANDSIM, "NANDsim", "NANDsim dynamic data");
52 #define NANDSIM_CHIP_LOCK(chip) mtx_lock(&(chip)->ns_lock)
53 #define NANDSIM_CHIP_UNLOCK(chip) mtx_unlock(&(chip)->ns_lock)
55 static nandsim_evh_t erase_evh;
56 static nandsim_evh_t idle_evh;
57 static nandsim_evh_t poweron_evh;
58 static nandsim_evh_t reset_evh;
59 static nandsim_evh_t read_evh;
60 static nandsim_evh_t readid_evh;
61 static nandsim_evh_t readparam_evh;
62 static nandsim_evh_t write_evh;
64 static void nandsim_loop(void *);
65 static void nandsim_undefined(struct nandsim_chip *, uint8_t);
66 static void nandsim_bad_address(struct nandsim_chip *, uint8_t *);
67 static void nandsim_ignore_address(struct nandsim_chip *, uint8_t);
68 static void nandsim_sm_error(struct nandsim_chip *);
69 static void nandsim_start_handler(struct nandsim_chip *, nandsim_evh_t);
71 static void nandsim_callout_eh(void *);
72 static int nandsim_delay(struct nandsim_chip *, int);
74 static int nandsim_bbm_init(struct nandsim_chip *, uint32_t, uint32_t *);
75 static int nandsim_blk_state_init(struct nandsim_chip *, uint32_t, uint32_t);
76 static void nandsim_blk_state_destroy(struct nandsim_chip *);
77 static int nandchip_is_block_valid(struct nandsim_chip *, int);
79 static void nandchip_set_status(struct nandsim_chip *, uint8_t);
80 static void nandchip_clear_status(struct nandsim_chip *, uint8_t);
82 struct proc *nandsim_proc;
85 nandsim_chip_init(struct nandsim_softc* sc, uint8_t chip_num,
86 struct sim_chip *sim_chip)
88 struct nandsim_chip *chip;
89 struct onfi_params *chip_param;
94 chip = malloc(sizeof(*chip), M_NANDSIM, M_WAITOK | M_ZERO);
96 mtx_init(&chip->ns_lock, "nandsim lock", NULL, MTX_DEF);
97 callout_init(&chip->ns_callout, 1);
98 STAILQ_INIT(&chip->nandsim_events);
100 chip->chip_num = chip_num;
101 chip->ctrl_num = sim_chip->ctrl_num;
104 if (!sim_chip->is_wp)
105 nandchip_set_status(chip, NAND_STATUS_WP);
107 chip_param = &chip->params;
109 chip->id.dev_id = sim_chip->device_id;
110 chip->id.man_id = sim_chip->manufact_id;
112 chip->error_ratio = sim_chip->error_ratio;
113 chip->wear_level = sim_chip->wear_level;
114 chip->prog_delay = sim_chip->prog_time;
115 chip->erase_delay = sim_chip->erase_time;
116 chip->read_delay = sim_chip->read_time;
118 chip_param->t_prog = sim_chip->prog_time;
119 chip_param->t_bers = sim_chip->erase_time;
120 chip_param->t_r = sim_chip->read_time;
121 bcopy("onfi", &chip_param->signature, 4);
123 chip_param->manufacturer_id = sim_chip->manufact_id;
124 strncpy(chip_param->manufacturer_name, sim_chip->manufacturer, 12);
125 chip_param->manufacturer_name[11] = 0;
126 strncpy(chip_param->device_model, sim_chip->device_model, 20);
127 chip_param->device_model[19] = 0;
129 chip_param->bytes_per_page = sim_chip->page_size;
130 chip_param->spare_bytes_per_page = sim_chip->oob_size;
131 chip_param->pages_per_block = sim_chip->pgs_per_blk;
132 chip_param->blocks_per_lun = sim_chip->blks_per_lun;
133 chip_param->luns = sim_chip->luns;
135 init_chip_geom(&chip->cg, chip_param->luns, chip_param->blocks_per_lun,
136 chip_param->pages_per_block, chip_param->bytes_per_page,
137 chip_param->spare_bytes_per_page);
139 chip_param->address_cycles = sim_chip->row_addr_cycles |
140 (sim_chip->col_addr_cycles << 4);
141 chip_param->features = sim_chip->features;
142 if (sim_chip->width == 16)
143 chip_param->features |= ONFI_FEAT_16BIT;
145 size = chip_param->blocks_per_lun * chip_param->luns;
147 error = nandsim_blk_state_init(chip, size, sim_chip->wear_level);
149 mtx_destroy(&chip->ns_lock);
150 free(chip, M_NANDSIM);
154 error = nandsim_bbm_init(chip, size, sim_chip->bad_block_map);
156 mtx_destroy(&chip->ns_lock);
157 nandsim_blk_state_destroy(chip);
158 free(chip, M_NANDSIM);
162 nandsim_start_handler(chip, poweron_evh);
164 nand_debug(NDBG_SIM,"Create thread for chip%d [%8p]", chip->chip_num,
166 /* Create chip thread */
167 error = kproc_kthread_add(nandsim_loop, chip, &nandsim_proc,
168 &chip->nandsim_td, RFSTOPPED | RFHIGHPID,
169 0, "nandsim", "chip");
171 mtx_destroy(&chip->ns_lock);
172 nandsim_blk_state_destroy(chip);
173 free(chip, M_NANDSIM);
177 thread_lock(chip->nandsim_td);
178 sched_class(chip->nandsim_td, PRI_REALTIME);
179 sched_add(chip->nandsim_td, SRQ_BORING);
180 thread_unlock(chip->nandsim_td);
182 size = (chip_param->bytes_per_page +
183 chip_param->spare_bytes_per_page) *
184 chip_param->pages_per_block;
186 sprintf(swapfile, "chip%d%d.swp", chip->ctrl_num, chip->chip_num);
187 chip->swap = nandsim_swap_init(swapfile, chip_param->blocks_per_lun *
188 chip_param->luns, size);
190 nandsim_chip_destroy(chip);
192 /* Wait for new thread to enter main loop */
193 tsleep(chip->nandsim_td, PWAIT, "ns_chip", 1 * hz);
199 nandsim_blk_state_init(struct nandsim_chip *chip, uint32_t size,
204 if (!chip || size == 0)
207 chip->blk_state = malloc(size * sizeof(struct nandsim_block_state),
208 M_NANDSIM, M_WAITOK | M_ZERO);
210 for (i = 0; i < size; i++) {
212 chip->blk_state[i].wear_lev = wear_lev;
214 chip->blk_state[i].wear_lev = -1;
221 nandsim_blk_state_destroy(struct nandsim_chip *chip)
224 if (chip && chip->blk_state)
225 free(chip->blk_state, M_NANDSIM);
229 nandsim_bbm_init(struct nandsim_chip *chip, uint32_t size,
235 if ((chip == NULL) || (size == 0))
238 if (chip->blk_state == NULL)
244 for (i = 0; i < MAX_BAD_BLOCKS; i++) {
247 if (index == 0xffffffff)
249 else if (index > size)
252 chip->blk_state[index].is_bad = 1;
259 nandsim_chip_destroy(struct nandsim_chip *chip)
261 struct nandsim_ev *ev;
263 ev = create_event(chip, NANDSIM_EV_EXIT, 0);
269 nandsim_chip_freeze(struct nandsim_chip *chip)
272 chip->flags |= NANDSIM_CHIP_FROZEN;
276 nandsim_loop(void *arg)
278 struct nandsim_chip *chip = (struct nandsim_chip *)arg;
279 struct nandsim_ev *ev;
281 nand_debug(NDBG_SIM,"Start main loop for chip%d [%8p]", chip->chip_num,
284 NANDSIM_CHIP_LOCK(chip);
285 if (!(chip->flags & NANDSIM_CHIP_ACTIVE)) {
286 chip->flags |= NANDSIM_CHIP_ACTIVE;
287 wakeup(chip->nandsim_td);
290 if (STAILQ_EMPTY(&chip->nandsim_events)) {
291 nand_debug(NDBG_SIM,"Chip%d [%8p] going sleep",
292 chip->chip_num, chip);
293 msleep(chip, &chip->ns_lock, PRIBIO, "nandev", 0);
296 ev = STAILQ_FIRST(&chip->nandsim_events);
297 STAILQ_REMOVE_HEAD(&chip->nandsim_events, links);
298 NANDSIM_CHIP_UNLOCK(chip);
299 if (ev->type == NANDSIM_EV_EXIT) {
300 NANDSIM_CHIP_LOCK(chip);
303 while (!STAILQ_EMPTY(&chip->nandsim_events)) {
304 ev = STAILQ_FIRST(&chip->nandsim_events);
305 STAILQ_REMOVE_HEAD(&chip->nandsim_events,
310 NANDSIM_CHIP_UNLOCK(chip);
311 nandsim_log(chip, NANDSIM_LOG_SM, "destroyed\n");
312 mtx_destroy(&chip->ns_lock);
313 nandsim_blk_state_destroy(chip);
314 nandsim_swap_destroy(chip->swap);
315 free(chip, M_NANDSIM);
321 if (!(chip->flags & NANDSIM_CHIP_FROZEN)) {
322 nand_debug(NDBG_SIM,"Chip [%x] get event [%x]",
323 chip->chip_num, ev->type);
324 chip->ev_handler(chip, ev->type, ev->data);
334 create_event(struct nandsim_chip *chip, uint8_t type, uint8_t data_size)
336 struct nandsim_ev *ev;
338 ev = malloc(sizeof(*ev), M_NANDSIM, M_NOWAIT | M_ZERO);
340 nand_debug(NDBG_SIM,"Cannot create event");
345 ev->data = malloc(sizeof(*ev), M_NANDSIM, M_NOWAIT | M_ZERO);
353 destroy_event(struct nandsim_ev *ev)
357 free(ev->data, M_NANDSIM);
362 send_event(struct nandsim_ev *ev)
364 struct nandsim_chip *chip = ev->chip;
366 if (!(chip->flags & NANDSIM_CHIP_FROZEN)) {
367 nand_debug(NDBG_SIM,"Chip%d [%p] send event %x",
368 chip->chip_num, chip, ev->type);
370 NANDSIM_CHIP_LOCK(chip);
371 STAILQ_INSERT_TAIL(&chip->nandsim_events, ev, links);
372 NANDSIM_CHIP_UNLOCK(chip);
375 if ((ev->type != NANDSIM_EV_TIMEOUT) && chip->nandsim_td &&
376 (curthread != chip->nandsim_td))
377 tsleep(ev, PWAIT, "ns_ev", 5 * hz);
384 nandsim_callout_eh(void *arg)
386 struct nandsim_ev *ev = (struct nandsim_ev *)arg;
392 nandsim_delay(struct nandsim_chip *chip, int timeout)
394 struct nandsim_ev *ev;
395 struct timeval delay;
398 nand_debug(NDBG_SIM,"Chip[%d] Set delay: %d", chip->chip_num, timeout);
400 ev = create_event(chip, NANDSIM_EV_TIMEOUT, 0);
404 chip->sm_state = NANDSIM_STATE_TIMEOUT;
405 tm = (timeout/10000) * (hz / 100);
406 if (callout_reset(&chip->ns_callout, tm, nandsim_callout_eh, ev))
409 delay.tv_sec = chip->read_delay / 1000000;
410 delay.tv_usec = chip->read_delay % 1000000;
411 timevaladd(&chip->delay_tv, &delay);
417 nandsim_start_handler(struct nandsim_chip *chip, nandsim_evh_t evh)
419 struct nandsim_ev *ev;
421 chip->ev_handler = evh;
423 nand_debug(NDBG_SIM,"Start handler %p for chip%d [%p]", evh,
424 chip->chip_num, chip);
425 ev = create_event(chip, NANDSIM_EV_START, 0);
427 nandsim_sm_error(chip);
433 nandchip_set_data(struct nandsim_chip *chip, uint8_t *data, uint32_t len,
437 nand_debug(NDBG_SIM,"Chip [%x] data %p [%x] at %x", chip->chip_num,
439 chip->data.data_ptr = data;
440 chip->data.size = len;
441 chip->data.index = idx;
445 nandchip_chip_space(struct nandsim_chip *chip, int32_t row, int32_t column,
446 size_t size, uint8_t writing)
448 struct block_space *blk_space;
449 uint32_t lun, block, page, offset, block_size;
452 block_size = chip->cg.block_size +
453 (chip->cg.oob_size * chip->cg.pgs_per_blk);
455 err = nand_row_to_blkpg(&chip->cg, row, &lun, &block, &page);
457 nand_debug(NDBG_SIM,"cannot get address\n");
461 if (!nandchip_is_block_valid(chip, block)) {
462 nandchip_set_data(chip, NULL, 0, 0);
466 blk_space = get_bs(chip->swap, block, writing);
468 nandchip_set_data(chip, NULL, 0, 0);
472 if (size > block_size)
475 if (size == block_size) {
479 offset = page * (chip->cg.page_size + chip->cg.oob_size);
481 nandchip_set_data(chip, &blk_space->blk_ptr[offset], size, column);
487 nandchip_get_addr_byte(struct nandsim_chip *chip, void *data, uint32_t *value)
493 buffer = (uint8_t *)value;
494 byte = *((uint8_t *)data);
496 KASSERT((chip->sm_state == NANDSIM_STATE_WAIT_ADDR_ROW ||
497 chip->sm_state == NANDSIM_STATE_WAIT_ADDR_COL),
498 ("unexpected state"));
500 if (chip->sm_state == NANDSIM_STATE_WAIT_ADDR_ROW) {
501 ncycles = chip->params.address_cycles & 0xf;
502 buffer[chip->sm_addr_cycle++] = byte;
503 } else if (chip->sm_state == NANDSIM_STATE_WAIT_ADDR_COL) {
504 ncycles = (chip->params.address_cycles >> 4) & 0xf;
505 buffer[chip->sm_addr_cycle++] = byte;
508 nand_debug(NDBG_SIM, "Chip [%x] read addr byte: %02x (%d of %d)\n",
509 chip->chip_num, byte, chip->sm_addr_cycle, ncycles);
511 if (chip->sm_addr_cycle == ncycles) {
512 chip->sm_addr_cycle = 0;
520 nandchip_is_block_valid(struct nandsim_chip *chip, int block_num)
523 if (!chip || !chip->blk_state)
526 if (chip->blk_state[block_num].wear_lev == 0 ||
527 chip->blk_state[block_num].is_bad)
534 nandchip_set_status(struct nandsim_chip *chip, uint8_t flags)
537 chip->chip_status |= flags;
541 nandchip_clear_status(struct nandsim_chip *chip, uint8_t flags)
544 chip->chip_status &= ~flags;
548 nandchip_get_status(struct nandsim_chip *chip)
550 return (chip->chip_status);
554 nandsim_chip_timeout(struct nandsim_chip *chip)
560 if (chip->sm_state == NANDSIM_STATE_TIMEOUT &&
561 timevalcmp(&tv, &chip->delay_tv, >=)) {
562 nandchip_set_status(chip, NAND_STATUS_RDY);
566 poweron_evh(struct nandsim_chip *chip, uint32_t type, void *data)
570 if (type == NANDSIM_EV_START)
571 chip->sm_state = NANDSIM_STATE_IDLE;
572 else if (type == NANDSIM_EV_CMD) {
573 cmd = *(uint8_t *)data;
576 nandsim_log(chip, NANDSIM_LOG_SM, "in RESET state\n");
577 nandsim_start_handler(chip, reset_evh);
580 nandsim_undefined(chip, type);
584 nandsim_undefined(chip, type);
588 idle_evh(struct nandsim_chip *chip, uint32_t type, void *data)
592 if (type == NANDSIM_EV_START) {
593 nandsim_log(chip, NANDSIM_LOG_SM, "in IDLE state\n");
594 chip->sm_state = NANDSIM_STATE_WAIT_CMD;
595 } else if (type == NANDSIM_EV_CMD) {
596 nandchip_clear_status(chip, NAND_STATUS_FAIL);
597 getmicrotime(&chip->delay_tv);
598 cmd = *(uint8_t *)data;
600 case NAND_CMD_READ_ID:
601 nandsim_start_handler(chip, readid_evh);
603 case NAND_CMD_READ_PARAMETER:
604 nandsim_start_handler(chip, readparam_evh);
607 nandsim_start_handler(chip, read_evh);
610 nandsim_start_handler(chip, write_evh);
613 nandsim_start_handler(chip, erase_evh);
616 nandsim_undefined(chip, type);
620 nandsim_undefined(chip, type);
624 readid_evh(struct nandsim_chip *chip, uint32_t type, void *data)
626 struct onfi_params *params;
629 params = &chip->params;
631 if (type == NANDSIM_EV_START) {
632 nandsim_log(chip, NANDSIM_LOG_SM, "in READID state\n");
633 chip->sm_state = NANDSIM_STATE_WAIT_ADDR_BYTE;
634 } else if (type == NANDSIM_EV_ADDR) {
636 addr = *((uint8_t *)data);
639 nandchip_set_data(chip, (uint8_t *)&chip->id, 2, 0);
640 else if (addr == ONFI_SIG_ADDR)
641 nandchip_set_data(chip, (uint8_t *)¶ms->signature,
644 nandsim_bad_address(chip, &addr);
646 nandsim_start_handler(chip, idle_evh);
648 nandsim_undefined(chip, type);
652 readparam_evh(struct nandsim_chip *chip, uint32_t type, void *data)
654 struct onfi_params *params;
657 params = &chip->params;
659 if (type == NANDSIM_EV_START) {
660 nandsim_log(chip, NANDSIM_LOG_SM, "in READPARAM state\n");
661 chip->sm_state = NANDSIM_STATE_WAIT_ADDR_BYTE;
662 } else if (type == NANDSIM_EV_ADDR) {
663 addr = *((uint8_t *)data);
666 nandchip_set_data(chip, (uint8_t *)params,
669 nandsim_bad_address(chip, &addr);
671 nandsim_start_handler(chip, idle_evh);
673 nandsim_undefined(chip, type);
677 read_evh(struct nandsim_chip *chip, uint32_t type, void *data)
679 static uint32_t column = 0, row = 0;
683 size = chip->cg.page_size + chip->cg.oob_size;
686 case NANDSIM_EV_START:
687 nandsim_log(chip, NANDSIM_LOG_SM, "in READ state\n");
688 chip->sm_state = NANDSIM_STATE_WAIT_ADDR_COL;
690 case NANDSIM_EV_ADDR:
691 if (chip->sm_state == NANDSIM_STATE_WAIT_ADDR_COL) {
692 if (nandchip_get_addr_byte(chip, data, &column))
695 chip->sm_state = NANDSIM_STATE_WAIT_ADDR_ROW;
696 } else if (chip->sm_state == NANDSIM_STATE_WAIT_ADDR_ROW) {
697 if (nandchip_get_addr_byte(chip, data, &row))
700 chip->sm_state = NANDSIM_STATE_WAIT_CMD;
702 nandsim_ignore_address(chip, *((uint8_t *)data));
705 cmd = *(uint8_t *)data;
706 if (chip->sm_state == NANDSIM_STATE_WAIT_CMD &&
707 cmd == NAND_CMD_READ_END) {
708 if (chip->read_delay != 0 &&
709 nandsim_delay(chip, chip->read_delay) == 0)
710 nandchip_clear_status(chip, NAND_STATUS_RDY);
712 nandchip_chip_space(chip, row, column, size, 0);
713 nandchip_set_status(chip, NAND_STATUS_RDY);
714 nandsim_start_handler(chip, idle_evh);
717 nandsim_undefined(chip, type);
719 case NANDSIM_EV_TIMEOUT:
720 if (chip->sm_state == NANDSIM_STATE_TIMEOUT) {
721 nandchip_chip_space(chip, row, column, size, 0);
722 nandchip_set_status(chip, NAND_STATUS_RDY);
723 nandsim_start_handler(chip, idle_evh);
725 nandsim_undefined(chip, type);
730 write_evh(struct nandsim_chip *chip, uint32_t type, void *data)
732 static uint32_t column, row;
737 size = chip->cg.page_size + chip->cg.oob_size;
740 case NANDSIM_EV_START:
741 nandsim_log(chip, NANDSIM_LOG_SM, "in WRITE state\n");
742 chip->sm_state = NANDSIM_STATE_WAIT_ADDR_COL;
744 case NANDSIM_EV_ADDR:
745 if (chip->sm_state == NANDSIM_STATE_WAIT_ADDR_COL) {
746 if (nandchip_get_addr_byte(chip, data, &column))
749 chip->sm_state = NANDSIM_STATE_WAIT_ADDR_ROW;
750 } else if (chip->sm_state == NANDSIM_STATE_WAIT_ADDR_ROW) {
751 if (nandchip_get_addr_byte(chip, data, &row))
754 err = nandchip_chip_space(chip, row, column, size, 1);
756 nandchip_set_status(chip, NAND_STATUS_FAIL);
758 chip->sm_state = NANDSIM_STATE_WAIT_CMD;
760 nandsim_ignore_address(chip, *((uint8_t *)data));
763 cmd = *(uint8_t *)data;
764 if (chip->sm_state == NANDSIM_STATE_WAIT_CMD &&
765 cmd == NAND_CMD_PROG_END) {
766 if (chip->prog_delay != 0 &&
767 nandsim_delay(chip, chip->prog_delay) == 0)
768 nandchip_clear_status(chip, NAND_STATUS_RDY);
770 nandchip_set_status(chip, NAND_STATUS_RDY);
771 nandsim_start_handler(chip, idle_evh);
774 nandsim_undefined(chip, type);
776 case NANDSIM_EV_TIMEOUT:
777 if (chip->sm_state == NANDSIM_STATE_TIMEOUT) {
778 nandsim_start_handler(chip, idle_evh);
779 nandchip_set_status(chip, NAND_STATUS_RDY);
781 nandsim_undefined(chip, type);
787 erase_evh(struct nandsim_chip *chip, uint32_t type, void *data)
789 static uint32_t row, block_size;
790 uint32_t lun, block, page;
794 block_size = chip->cg.block_size +
795 (chip->cg.oob_size * chip->cg.pgs_per_blk);
798 case NANDSIM_EV_START:
799 nandsim_log(chip, NANDSIM_LOG_SM, "in ERASE state\n");
800 chip->sm_state = NANDSIM_STATE_WAIT_ADDR_ROW;
803 cmd = *(uint8_t *)data;
804 if (chip->sm_state == NANDSIM_STATE_WAIT_CMD &&
805 cmd == NAND_CMD_ERASE_END) {
806 if (chip->data.data_ptr != NULL &&
807 chip->data.size == block_size)
808 memset(chip->data.data_ptr, 0xff, block_size);
810 nand_debug(NDBG_SIM,"Bad block erase data\n");
812 err = nand_row_to_blkpg(&chip->cg, row, &lun,
815 if (chip->blk_state[block].wear_lev > 0)
816 chip->blk_state[block].wear_lev--;
819 if (chip->erase_delay != 0 &&
820 nandsim_delay(chip, chip->erase_delay) == 0)
821 nandchip_clear_status(chip, NAND_STATUS_RDY);
823 nandchip_set_status(chip, NAND_STATUS_RDY);
824 nandsim_start_handler(chip, idle_evh);
827 nandsim_undefined(chip, type);
829 case NANDSIM_EV_ADDR:
830 if (chip->sm_state == NANDSIM_STATE_WAIT_ADDR_ROW) {
831 if (nandchip_get_addr_byte(chip, data, &row))
834 err = nandchip_chip_space(chip, row, 0, block_size, 1);
836 nandchip_set_status(chip, NAND_STATUS_FAIL);
838 chip->sm_state = NANDSIM_STATE_WAIT_CMD;
840 nandsim_ignore_address(chip, *((uint8_t *)data));
842 case NANDSIM_EV_TIMEOUT:
843 if (chip->sm_state == NANDSIM_STATE_TIMEOUT) {
844 nandchip_set_status(chip, NAND_STATUS_RDY);
845 nandsim_start_handler(chip, idle_evh);
847 nandsim_undefined(chip, type);
853 reset_evh(struct nandsim_chip *chip, uint32_t type, void *data)
856 if (type == NANDSIM_EV_START) {
857 nandsim_log(chip, NANDSIM_LOG_SM, "in RESET state\n");
858 chip->sm_state = NANDSIM_STATE_TIMEOUT;
859 nandchip_set_data(chip, NULL, 0, 0);
861 nandsim_start_handler(chip, idle_evh);
863 nandsim_undefined(chip, type);
867 nandsim_undefined(struct nandsim_chip *chip, uint8_t type)
870 nandsim_log(chip, NANDSIM_LOG_ERR,
871 "ERR: Chip received ev %x in state %x\n",
872 type, chip->sm_state);
873 nandsim_start_handler(chip, idle_evh);
877 nandsim_bad_address(struct nandsim_chip *chip, uint8_t *addr)
880 nandsim_log(chip, NANDSIM_LOG_ERR,
881 "ERR: Chip received out of range address"
882 "%02x%02x - %02x%02x%02x\n", addr[0], addr[1], addr[2],
887 nandsim_ignore_address(struct nandsim_chip *chip, uint8_t byte)
889 nandsim_log(chip, NANDSIM_LOG_SM, "ignored address byte: %d\n", byte);
893 nandsim_sm_error(struct nandsim_chip *chip)
896 nandsim_log(chip, NANDSIM_LOG_ERR, "ERR: State machine error."
897 "Restart required.\n");