2 * Copyright (C) 2012 Juniper Networks, Inc.
3 * Copyright (C) 2009-2012 Semihalf
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * -- test support for small pages
31 * -- support for reading ONFI parameters
32 * -- support for cached and interleaving commands
33 * -- proper setting of AL bits in FMR
36 #include <sys/cdefs.h>
37 __FBSDID("$FreeBSD$");
39 #include <sys/param.h>
40 #include <sys/systm.h>
44 #include <sys/kernel.h>
45 #include <sys/module.h>
46 #include <sys/malloc.h>
48 #include <sys/sysctl.h>
52 #include <machine/bus.h>
53 #include <machine/fdt.h>
55 #include <dev/ofw/ofw_bus.h>
56 #include <dev/ofw/ofw_bus_subr.h>
58 #include <powerpc/mpc85xx/lbc.h>
60 #include <dev/nand/nand.h>
61 #include <dev/nand/nandbus.h>
67 #define LBC_READ(regname) lbc_read_reg(dev, (LBC85XX_ ## regname))
68 #define LBC_WRITE(regname, val) lbc_write_reg(dev, (LBC85XX_ ## regname), val)
78 /* Read-only after initialization */
81 /* To be preserved across "start_command" */
86 /* Command state -- cleared by "start_command" */
87 uint32_t fcm_startzero;
97 enum addr_type addr_type;
102 uint32_t fcm_endzero;
105 struct fsl_nand_softc {
106 struct nand_softc nand_dev;
108 struct resource *res;
109 int rid; /* Resourceid */
110 struct lbc_devinfo *dinfo;
111 struct fsl_nfc_fcm fcm;
114 uint16_t pgsz; /* Page size */
117 static int fsl_nand_attach(device_t dev);
118 static int fsl_nand_probe(device_t dev);
119 static int fsl_nand_detach(device_t dev);
121 static int fsl_nfc_select_cs(device_t dev, uint8_t cs);
122 static int fsl_nfc_read_rnb(device_t dev);
123 static int fsl_nfc_send_command(device_t dev, uint8_t command);
124 static int fsl_nfc_send_address(device_t dev, uint8_t address);
125 static uint8_t fsl_nfc_read_byte(device_t dev);
126 static int fsl_nfc_start_command(device_t dev);
127 static void fsl_nfc_read_buf(device_t dev, void *buf, uint32_t len);
128 static void fsl_nfc_write_buf(device_t dev, void *buf, uint32_t len);
130 static device_method_t fsl_nand_methods[] = {
131 DEVMETHOD(device_probe, fsl_nand_probe),
132 DEVMETHOD(device_attach, fsl_nand_attach),
133 DEVMETHOD(device_detach, fsl_nand_detach),
135 DEVMETHOD(nfc_select_cs, fsl_nfc_select_cs),
136 DEVMETHOD(nfc_read_rnb, fsl_nfc_read_rnb),
137 DEVMETHOD(nfc_start_command, fsl_nfc_start_command),
138 DEVMETHOD(nfc_send_command, fsl_nfc_send_command),
139 DEVMETHOD(nfc_send_address, fsl_nfc_send_address),
140 DEVMETHOD(nfc_read_byte, fsl_nfc_read_byte),
141 DEVMETHOD(nfc_read_buf, fsl_nfc_read_buf),
142 DEVMETHOD(nfc_write_buf, fsl_nfc_write_buf),
146 static driver_t fsl_nand_driver = {
149 sizeof(struct fsl_nand_softc),
152 static devclass_t fsl_nand_devclass;
154 DRIVER_MODULE(fsl_nand, lbc, fsl_nand_driver, fsl_nand_devclass,
157 static int fsl_nand_build_address(device_t dev, uint32_t page, uint32_t column);
158 static int fsl_nand_chip_preprobe(device_t dev, struct nand_id *id);
160 #ifdef NAND_DEBUG_TIMING
161 static device_t fcm_devs[8];
164 #define CMD_SHIFT(cmd_num) (24 - ((cmd_num) * 8))
165 #define OP_SHIFT(op_num) (28 - ((op_num) * 4))
167 #define FSL_LARGE_PAGE_SIZE (2112)
168 #define FSL_SMALL_PAGE_SIZE (528)
171 fsl_nand_init_regs(struct fsl_nand_softc *sc)
178 sc->fcm.reg_fmr = (15 << FMR_CWTO_SHIFT);
181 * Setup 4 row cycles and hope that chip ignores superfluous address
184 sc->fcm.reg_fmr |= (2 << FMR_AL_SHIFT);
186 /* Reprogram BR(x) */
187 br_v = lbc_read_reg(dev, LBC85XX_BR(sc->dinfo->di_bank));
189 br_v |= 1 << 11; /* 8-bit port size */
190 br_v |= 0 << 9; /* No ECC checking and generation */
191 br_v |= 1 << 5; /* FCM machine */
192 br_v |= 1; /* Valid */
193 lbc_write_reg(dev, LBC85XX_BR(sc->dinfo->di_bank), br_v);
195 /* Reprogram OR(x) */
196 or_v = lbc_read_reg(dev, LBC85XX_OR(sc->dinfo->di_bank));
198 or_v |= 0x03AE; /* Default POR timing */
199 lbc_write_reg(dev, LBC85XX_OR(sc->dinfo->di_bank), or_v);
201 if (or_v & OR_FCM_PAGESIZE) {
202 sc->pgsz = FSL_LARGE_PAGE_SIZE;
204 nand_debug(NDBG_DRV, "%s: large page NAND device at #%d",
205 device_get_nameunit(dev), sc->dinfo->di_bank);
207 sc->pgsz = FSL_SMALL_PAGE_SIZE;
209 nand_debug(NDBG_DRV, "%s: small page NAND device at #%d",
210 device_get_nameunit(dev), sc->dinfo->di_bank);
215 fsl_nand_probe(device_t dev)
218 if (!ofw_bus_is_compatible(dev, "fsl,elbc-fcm-nand"))
221 device_set_desc(dev, "Freescale localbus FCM Controller");
222 return (BUS_PROBE_DEFAULT);
226 fsl_nand_attach(device_t dev)
228 struct fsl_nand_softc *sc;
230 struct nand_params *param;
233 sc = device_get_softc(dev);
235 sc->dinfo = device_get_ivars(dev);
237 sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->rid,
239 if (sc->res == NULL) {
240 device_printf(dev, "could not allocate resources!\n");
244 bzero(&sc->fcm, sizeof(sc->fcm));
246 /* Init register and check if HW ECC turned on */
247 fsl_nand_init_regs(sc);
249 /* Chip is probed, so determine number of row address cycles */
250 fsl_nand_chip_preprobe(dev, &id);
251 param = nand_get_params(&id);
253 num_pages = (param->chip_size << 20) / param->page_size;
259 sc->fcm.reg_fmr &= ~(FMR_AL);
260 sc->fcm.reg_fmr |= (sc->row_cycles - 2) << FMR_AL_SHIFT;
263 nand_init(&sc->nand_dev, dev, NAND_ECC_SOFT, 0, 0, NULL, NULL);
265 #ifdef NAND_DEBUG_TIMING
266 fcm_devs[sc->dinfo->di_bank] = dev;
269 return (nandbus_create(dev));
273 fsl_nand_detach(device_t dev)
275 struct fsl_nand_softc *sc;
277 sc = device_get_softc(dev);
280 bus_release_resource(dev, SYS_RES_MEMORY, sc->rid, sc->res);
286 fsl_nfc_select_cs(device_t dev, uint8_t cs)
289 // device_printf(dev, "%s(cs=%u)\n", __func__, cs);
290 return ((cs > 0) ? EINVAL : 0);
294 fsl_nfc_read_rnb(device_t dev)
297 // device_printf(dev, "%s()\n", __func__);
302 fsl_nfc_send_command(device_t dev, uint8_t command)
304 struct fsl_nand_softc *sc;
305 struct fsl_nfc_fcm *fcm;
308 // device_printf(dev, "%s(command=%u)\n", __func__, command);
310 sc = device_get_softc(dev);
313 if (command == NAND_CMD_PROG_END) {
314 fcm->reg_fir |= (FIR_OP_WB << OP_SHIFT(fcm->opnr));
317 fcm->reg_fcr |= command << CMD_SHIFT(fcm->cmdnr);
318 fir_op = (fcm->cmdnr == 0) ? FIR_OP_CW0 : FIR_OP_CM(fcm->cmdnr);
321 fcm->reg_fir |= (fir_op << OP_SHIFT(fcm->opnr));
325 case NAND_CMD_READ_ID:
326 fcm->data_fir = FIR_OP_RBW;
327 fcm->addr_type = ADDR_ID;
329 case NAND_CMD_SMALLOOB:
332 case NAND_CMD_SMALLB:
335 case NAND_CMD_READ: /* NAND_CMD_SMALLA */
336 fcm->data_fir = FIR_OP_RBW;
337 fcm->addr_type = ADDR_ROWCOL;
339 case NAND_CMD_STATUS:
340 fcm->data_fir = FIR_OP_RS;
344 fcm->addr_type = ADDR_ROW;
347 fcm->addr_type = ADDR_ROWCOL;
354 fsl_nfc_send_address(device_t dev, uint8_t addr)
356 struct fsl_nand_softc *sc;
357 struct fsl_nfc_fcm *fcm;
360 // device_printf(dev, "%s(address=%u)\n", __func__, addr);
362 sc = device_get_softc(dev);
365 KASSERT(fcm->addr_type != ADDR_NONE,
366 ("controller doesn't expect address cycle"));
370 if (fcm->addr_type == ADDR_ID) {
371 fcm->reg_fir |= (FIR_OP_UA << OP_SHIFT(fcm->opnr));
377 fcm->reg_mdr = addr_bits;
383 if (fcm->addr_type == ADDR_ROW) {
384 addr_bits <<= fcm->addr_bytes * 8;
385 fcm->row_addr |= addr_bits;
387 if (fcm->addr_bytes < sc->row_cycles)
390 if (fcm->addr_bytes < sc->col_cycles) {
391 addr_bits <<= fcm->addr_bytes * 8;
392 fcm->column_addr |= addr_bits;
394 addr_bits <<= (fcm->addr_bytes - sc->col_cycles) * 8;
395 fcm->row_addr |= addr_bits;
398 if (fcm->addr_bytes < (sc->row_cycles + sc->col_cycles))
402 return (fsl_nand_build_address(dev, fcm->row_addr, fcm->column_addr));
406 fsl_nand_build_address(device_t dev, uint32_t row, uint32_t column)
408 struct fsl_nand_softc *sc;
409 struct fsl_nfc_fcm *fcm;
410 uint32_t byte_count = 0;
411 uint32_t block_address = 0;
412 uint32_t page_address = 0;
414 sc = device_get_softc(dev);
420 if (fcm->addr_type == ADDR_ROWCOL) {
421 fcm->reg_fir |= (FIR_OP_CA << OP_SHIFT(fcm->opnr));
424 column += fcm->pg_ofs;
427 page_address |= column;
430 byte_count = sc->pgsz - column;
431 fcm->read_ptr = column;
435 fcm->reg_fir |= (FIR_OP_PA << OP_SHIFT(fcm->opnr));
438 if (sc->pgsz == FSL_LARGE_PAGE_SIZE) {
439 block_address = row >> 6;
440 page_address |= ((row << FPAR_LP_PI_SHIFT) & FPAR_LP_PI);
441 fcm->buf_ofs = (row & 1) * 4096;
443 block_address = row >> 5;
444 page_address |= ((row << FPAR_SP_PI_SHIFT) & FPAR_SP_PI);
445 fcm->buf_ofs = (row & 7) * 1024;
448 fcm->reg_fbcr = byte_count;
449 fcm->reg_fbar = block_address;
450 fcm->reg_fpar = page_address;
455 fsl_nfc_start_command(device_t dev)
457 struct fsl_nand_softc *sc;
458 struct fsl_nfc_fcm *fcm;
459 uint32_t fmr, ltesr_v;
462 // device_printf(dev, "%s()\n", __func__);
464 sc = device_get_softc(dev);
467 fmr = fcm->reg_fmr | FMR_OP;
470 fcm->reg_fir |= (fcm->data_fir << OP_SHIFT(fcm->opnr));
472 LBC_WRITE(FIR, fcm->reg_fir);
473 LBC_WRITE(FCR, fcm->reg_fcr);
477 LBC_WRITE(FBCR, fcm->reg_fbcr);
478 LBC_WRITE(FBAR, fcm->reg_fbar);
479 LBC_WRITE(FPAR, fcm->reg_fpar);
481 if (fcm->addr_type == ADDR_ID)
482 LBC_WRITE(MDR, fcm->reg_mdr);
484 nand_debug(NDBG_DRV, "BEFORE:\nFMR=%#x, FIR=%#x, FCR=%#x", fmr,
485 fcm->reg_fir, fcm->reg_fcr);
486 nand_debug(NDBG_DRV, "MDR=%#x, FBAR=%#x, FPAR=%#x, FBCR=%#x",
487 LBC_READ(MDR), fcm->reg_fbar, fcm->reg_fpar, fcm->reg_fbcr);
489 LBC_WRITE(LSOR, sc->dinfo->di_bank);
491 timeout = (cold) ? FSL_FCM_WAIT_TIMEOUT : ~0;
493 ltesr_v = LBC_READ(LTESR);
494 while (!error && (ltesr_v & LTESR_CC) == 0) {
501 error = tsleep(device_get_parent(sc->dev), PRIBIO,
503 ltesr_v = LBC_READ(LTESR);
506 nand_debug(NDBG_DRV, "Command complete wait timeout\n");
508 nand_debug(NDBG_DRV, "AFTER:\nLTESR=%#x, LTEDR=%#x, LTEIR=%#x,"
509 " LTEATR=%#x, LTEAR=%#x, LTECCR=%#x", ltesr_v,
510 LBC_READ(LTEDR), LBC_READ(LTEIR), LBC_READ(LTEATR),
511 LBC_READ(LTEAR), LBC_READ(LTECCR));
513 bzero(&fcm->fcm_startzero,
514 __rangeof(struct fsl_nfc_fcm, fcm_startzero, fcm_endzero));
517 sc->fcm.reg_mdr = LBC_READ(MDR);
519 /* Even if timeout occured, we should perform steps below */
520 LBC_WRITE(LTESR, ltesr_v);
521 LBC_WRITE(LTEATR, 0);
527 fsl_nfc_read_byte(device_t dev)
529 struct fsl_nand_softc *sc = device_get_softc(dev);
532 // device_printf(dev, "%s()\n", __func__);
535 * LBC controller allows us to read status into a MDR instead of FCM
536 * buffer. If last operation requested before read_byte() was STATUS,
537 * then return MDR instead of reading a single byte from a buffer.
539 if (sc->fcm.status) {
541 return (sc->fcm.reg_mdr);
544 KASSERT(sc->fcm.read_ptr < sc->pgsz,
545 ("Attempt to read beyond buffer %x %x", sc->fcm.read_ptr,
548 offset = sc->fcm.buf_ofs + sc->fcm.read_ptr;
550 return (bus_read_1(sc->res, offset));
554 fsl_nfc_read_buf(device_t dev, void *buf, uint32_t len)
556 struct fsl_nand_softc *sc = device_get_softc(dev);
560 // device_printf(dev, "%s(buf=%p, len=%u)\n", __func__, buf, len);
562 nand_debug(NDBG_DRV, "REQUEST OF 0x%0x B (BIB=0x%0x, NTR=0x%0x)",
563 len, sc->pgsz, sc->fcm.read_ptr);
565 bytesleft = MIN((unsigned int)len, sc->pgsz - sc->fcm.read_ptr);
567 offset = sc->fcm.buf_ofs + sc->fcm.read_ptr;
568 bus_read_region_1(sc->res, offset, buf, bytesleft);
569 sc->fcm.read_ptr += bytesleft;
573 fsl_nfc_write_buf(device_t dev, void *buf, uint32_t len)
575 struct fsl_nand_softc *sc = device_get_softc(dev);
579 // device_printf(dev, "%s(buf=%p, len=%u)\n", __func__, buf, len);
581 KASSERT(len <= sc->pgsz - sc->fcm.read_ptr,
582 ("Attempt to write beyond buffer"));
584 bytesleft = MIN((unsigned int)len, sc->pgsz - sc->fcm.read_ptr);
586 nand_debug(NDBG_DRV, "REQUEST TO WRITE 0x%0x (BIB=0x%0x, NTR=0x%0x)",
587 bytesleft, sc->pgsz, sc->fcm.read_ptr);
589 offset = sc->fcm.buf_ofs + sc->fcm.read_ptr;
590 bus_write_region_1(sc->res, offset, buf, bytesleft);
591 sc->fcm.read_ptr += bytesleft;
595 fsl_nand_chip_preprobe(device_t dev, struct nand_id *id)
598 if (fsl_nfc_send_command(dev, NAND_CMD_RESET) != 0)
601 if (fsl_nfc_start_command(dev) != 0)
606 if (fsl_nfc_send_command(dev, NAND_CMD_READ_ID))
609 if (fsl_nfc_send_address(dev, 0))
612 if (fsl_nfc_start_command(dev) != 0)
617 id->man_id = fsl_nfc_read_byte(dev);
618 id->dev_id = fsl_nfc_read_byte(dev);
620 nand_debug(NDBG_DRV, "manufacturer id: %x chip id: %x",
621 id->man_id, id->dev_id);
626 #ifdef NAND_DEBUG_TIMING
628 static SYSCTL_NODE(_debug, OID_AUTO, fcm, CTLFLAG_RD, 0, "FCM timing");
630 static u_int csct = 1; /* 22: Chip select to command time (trlx). */
631 SYSCTL_UINT(_debug_fcm, OID_AUTO, csct, CTLFLAG_RW, &csct, 1,
632 "Chip select to command time: determines how far in advance -LCSn is "
633 "asserted prior to any bus activity during a NAND Flash access handled "
634 "by the FCM. This helps meet chip-select setup times for slow memories.");
636 static u_int cst = 1; /* 23: Command setup time (trlx). */
637 SYSCTL_UINT(_debug_fcm, OID_AUTO, cst, CTLFLAG_RW, &cst, 1,
638 "Command setup time: determines the delay of -LFWE assertion relative to "
639 "the command, address, or data change when the external memory access "
640 "is handled by the FCM.");
642 static u_int cht = 1; /* 24: Command hold time (trlx). */
643 SYSCTL_UINT(_debug_fcm, OID_AUTO, cht, CTLFLAG_RW, &cht, 1,
644 "Command hold time: determines the -LFWE negation prior to the command, "
645 "address, or data change when the external memory access is handled by "
648 static u_int scy = 2; /* 25-27: Cycle length in bus clocks */
649 SYSCTL_UINT(_debug_fcm, OID_AUTO, scy, CTLFLAG_RW, &scy, 2,
650 "Cycle length in bus clocks: see RM");
652 static u_int rst = 1; /* 28: Read setup time (trlx). */
653 SYSCTL_UINT(_debug_fcm, OID_AUTO, rst, CTLFLAG_RW, &rst, 1,
654 "Read setup time: determines the delay of -LFRE assertion relative to "
655 "sampling of read data when the external memory access is handled by "
658 static u_int trlx = 1; /* 29: Timing relaxed. */
659 SYSCTL_UINT(_debug_fcm, OID_AUTO, trlx, CTLFLAG_RW, &trlx, 1,
660 "Timing relaxed: modifies the settings of timing parameters for slow "
663 static u_int ehtr = 1; /* 30: Extended hold time on read accesses. */
664 SYSCTL_UINT(_debug_fcm, OID_AUTO, ehtr, CTLFLAG_RW, &ehtr, 1,
665 "Extended hold time on read accesses: indicates with TRLX how many "
666 "cycles are inserted between a read access from the current bank and "
670 fsl_nand_get_timing(void)
674 timing = ((csct & 1) << 9) | ((cst & 1) << 8) | ((cht & 1) << 7) |
675 ((scy & 7) << 4) | ((rst & 1) << 3) | ((trlx & 1) << 2) |
678 printf("nfc_fsl: timing = %u\n", timing);
683 fsl_sysctl_program(SYSCTL_HANDLER_ARGS)
685 struct fsl_nand_softc *sc;
690 error = sysctl_wire_old_buffer(req, sizeof(int));
693 error = sysctl_handle_int(oidp, &i, 0, req);
695 if (error != 0 || req->newptr == NULL)
698 for (i = 0; i < 8; i++) {
702 sc = device_get_softc(dev);
704 /* Reprogram OR(x) */
705 or_v = lbc_read_reg(dev, LBC85XX_OR(sc->dinfo->di_bank));
707 or_v |= fsl_nand_get_timing();
708 lbc_write_reg(dev, LBC85XX_OR(sc->dinfo->di_bank), or_v);
713 SYSCTL_PROC(_debug_fcm, OID_AUTO, program, CTLTYPE_INT | CTLFLAG_RW, NULL, 0,
714 fsl_sysctl_program, "I", "write to program FCM with current values");
716 #endif /* NAND_DEBUG_TIMING */