2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (C) 2012 Juniper Networks, Inc.
5 * Copyright (C) 2009-2012 Semihalf
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * -- test support for small pages
33 * -- support for reading ONFI parameters
34 * -- support for cached and interleaving commands
35 * -- proper setting of AL bits in FMR
38 #include <sys/cdefs.h>
39 __FBSDID("$FreeBSD$");
41 #include <sys/param.h>
42 #include <sys/systm.h>
46 #include <sys/kernel.h>
47 #include <sys/module.h>
48 #include <sys/malloc.h>
50 #include <sys/sysctl.h>
54 #include <machine/bus.h>
56 #include <dev/ofw/ofw_bus.h>
57 #include <dev/ofw/ofw_bus_subr.h>
59 #include <powerpc/mpc85xx/lbc.h>
61 #include <dev/nand/nand.h>
62 #include <dev/nand/nandbus.h>
68 #define LBC_READ(regname) lbc_read_reg(dev, (LBC85XX_ ## regname))
69 #define LBC_WRITE(regname, val) lbc_write_reg(dev, (LBC85XX_ ## regname), val)
79 /* Read-only after initialization */
82 /* To be preserved across "start_command" */
87 /* Command state -- cleared by "start_command" */
88 uint32_t fcm_startzero;
98 enum addr_type addr_type;
103 uint32_t fcm_endzero;
106 struct fsl_nand_softc {
107 struct nand_softc nand_dev;
109 struct resource *res;
110 int rid; /* Resourceid */
111 struct lbc_devinfo *dinfo;
112 struct fsl_nfc_fcm fcm;
115 uint16_t pgsz; /* Page size */
118 static int fsl_nand_attach(device_t dev);
119 static int fsl_nand_probe(device_t dev);
120 static int fsl_nand_detach(device_t dev);
122 static int fsl_nfc_select_cs(device_t dev, uint8_t cs);
123 static int fsl_nfc_read_rnb(device_t dev);
124 static int fsl_nfc_send_command(device_t dev, uint8_t command);
125 static int fsl_nfc_send_address(device_t dev, uint8_t address);
126 static uint8_t fsl_nfc_read_byte(device_t dev);
127 static int fsl_nfc_start_command(device_t dev);
128 static void fsl_nfc_read_buf(device_t dev, void *buf, uint32_t len);
129 static void fsl_nfc_write_buf(device_t dev, void *buf, uint32_t len);
131 static device_method_t fsl_nand_methods[] = {
132 DEVMETHOD(device_probe, fsl_nand_probe),
133 DEVMETHOD(device_attach, fsl_nand_attach),
134 DEVMETHOD(device_detach, fsl_nand_detach),
136 DEVMETHOD(nfc_select_cs, fsl_nfc_select_cs),
137 DEVMETHOD(nfc_read_rnb, fsl_nfc_read_rnb),
138 DEVMETHOD(nfc_start_command, fsl_nfc_start_command),
139 DEVMETHOD(nfc_send_command, fsl_nfc_send_command),
140 DEVMETHOD(nfc_send_address, fsl_nfc_send_address),
141 DEVMETHOD(nfc_read_byte, fsl_nfc_read_byte),
142 DEVMETHOD(nfc_read_buf, fsl_nfc_read_buf),
143 DEVMETHOD(nfc_write_buf, fsl_nfc_write_buf),
147 static driver_t fsl_nand_driver = {
150 sizeof(struct fsl_nand_softc),
153 static devclass_t fsl_nand_devclass;
155 DRIVER_MODULE(fsl_nand, lbc, fsl_nand_driver, fsl_nand_devclass,
158 static int fsl_nand_build_address(device_t dev, uint32_t page, uint32_t column);
159 static int fsl_nand_chip_preprobe(device_t dev, struct nand_id *id);
161 #ifdef NAND_DEBUG_TIMING
162 static device_t fcm_devs[8];
165 #define CMD_SHIFT(cmd_num) (24 - ((cmd_num) * 8))
166 #define OP_SHIFT(op_num) (28 - ((op_num) * 4))
168 #define FSL_LARGE_PAGE_SIZE (2112)
169 #define FSL_SMALL_PAGE_SIZE (528)
172 fsl_nand_init_regs(struct fsl_nand_softc *sc)
179 sc->fcm.reg_fmr = (15 << FMR_CWTO_SHIFT);
182 * Setup 4 row cycles and hope that chip ignores superfluous address
185 sc->fcm.reg_fmr |= (2 << FMR_AL_SHIFT);
187 /* Reprogram BR(x) */
188 br_v = lbc_read_reg(dev, LBC85XX_BR(sc->dinfo->di_bank));
190 br_v |= 1 << 11; /* 8-bit port size */
191 br_v |= 0 << 9; /* No ECC checking and generation */
192 br_v |= 1 << 5; /* FCM machine */
193 br_v |= 1; /* Valid */
194 lbc_write_reg(dev, LBC85XX_BR(sc->dinfo->di_bank), br_v);
196 /* Reprogram OR(x) */
197 or_v = lbc_read_reg(dev, LBC85XX_OR(sc->dinfo->di_bank));
199 or_v |= 0x03AE; /* Default POR timing */
200 lbc_write_reg(dev, LBC85XX_OR(sc->dinfo->di_bank), or_v);
202 if (or_v & OR_FCM_PAGESIZE) {
203 sc->pgsz = FSL_LARGE_PAGE_SIZE;
205 nand_debug(NDBG_DRV, "%s: large page NAND device at #%d",
206 device_get_nameunit(dev), sc->dinfo->di_bank);
208 sc->pgsz = FSL_SMALL_PAGE_SIZE;
210 nand_debug(NDBG_DRV, "%s: small page NAND device at #%d",
211 device_get_nameunit(dev), sc->dinfo->di_bank);
216 fsl_nand_probe(device_t dev)
219 if (!ofw_bus_is_compatible(dev, "fsl,elbc-fcm-nand"))
222 device_set_desc(dev, "Freescale localbus FCM Controller");
223 return (BUS_PROBE_DEFAULT);
227 fsl_nand_attach(device_t dev)
229 struct fsl_nand_softc *sc;
231 struct nand_params *param;
234 sc = device_get_softc(dev);
236 sc->dinfo = device_get_ivars(dev);
238 sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->rid,
240 if (sc->res == NULL) {
241 device_printf(dev, "could not allocate resources!\n");
245 bzero(&sc->fcm, sizeof(sc->fcm));
247 /* Init register and check if HW ECC turned on */
248 fsl_nand_init_regs(sc);
250 /* Chip is probed, so determine number of row address cycles */
251 fsl_nand_chip_preprobe(dev, &id);
252 param = nand_get_params(&id);
254 num_pages = (param->chip_size << 20) / param->page_size;
260 sc->fcm.reg_fmr &= ~(FMR_AL);
261 sc->fcm.reg_fmr |= (sc->row_cycles - 2) << FMR_AL_SHIFT;
264 nand_init(&sc->nand_dev, dev, NAND_ECC_SOFT, 0, 0, NULL, NULL);
266 #ifdef NAND_DEBUG_TIMING
267 fcm_devs[sc->dinfo->di_bank] = dev;
270 return (nandbus_create(dev));
274 fsl_nand_detach(device_t dev)
276 struct fsl_nand_softc *sc;
278 sc = device_get_softc(dev);
281 bus_release_resource(dev, SYS_RES_MEMORY, sc->rid, sc->res);
287 fsl_nfc_select_cs(device_t dev, uint8_t cs)
290 // device_printf(dev, "%s(cs=%u)\n", __func__, cs);
291 return ((cs > 0) ? EINVAL : 0);
295 fsl_nfc_read_rnb(device_t dev)
298 // device_printf(dev, "%s()\n", __func__);
303 fsl_nfc_send_command(device_t dev, uint8_t command)
305 struct fsl_nand_softc *sc;
306 struct fsl_nfc_fcm *fcm;
309 // device_printf(dev, "%s(command=%u)\n", __func__, command);
311 sc = device_get_softc(dev);
314 if (command == NAND_CMD_PROG_END) {
315 fcm->reg_fir |= (FIR_OP_WB << OP_SHIFT(fcm->opnr));
318 fcm->reg_fcr |= command << CMD_SHIFT(fcm->cmdnr);
319 fir_op = (fcm->cmdnr == 0) ? FIR_OP_CW0 : FIR_OP_CM(fcm->cmdnr);
322 fcm->reg_fir |= (fir_op << OP_SHIFT(fcm->opnr));
326 case NAND_CMD_READ_ID:
327 fcm->data_fir = FIR_OP_RBW;
328 fcm->addr_type = ADDR_ID;
330 case NAND_CMD_SMALLOOB:
333 case NAND_CMD_SMALLB:
336 case NAND_CMD_READ: /* NAND_CMD_SMALLA */
337 fcm->data_fir = FIR_OP_RBW;
338 fcm->addr_type = ADDR_ROWCOL;
340 case NAND_CMD_STATUS:
341 fcm->data_fir = FIR_OP_RS;
345 fcm->addr_type = ADDR_ROW;
348 fcm->addr_type = ADDR_ROWCOL;
355 fsl_nfc_send_address(device_t dev, uint8_t addr)
357 struct fsl_nand_softc *sc;
358 struct fsl_nfc_fcm *fcm;
361 // device_printf(dev, "%s(address=%u)\n", __func__, addr);
363 sc = device_get_softc(dev);
366 KASSERT(fcm->addr_type != ADDR_NONE,
367 ("controller doesn't expect address cycle"));
371 if (fcm->addr_type == ADDR_ID) {
372 fcm->reg_fir |= (FIR_OP_UA << OP_SHIFT(fcm->opnr));
378 fcm->reg_mdr = addr_bits;
384 if (fcm->addr_type == ADDR_ROW) {
385 addr_bits <<= fcm->addr_bytes * 8;
386 fcm->row_addr |= addr_bits;
388 if (fcm->addr_bytes < sc->row_cycles)
391 if (fcm->addr_bytes < sc->col_cycles) {
392 addr_bits <<= fcm->addr_bytes * 8;
393 fcm->column_addr |= addr_bits;
395 addr_bits <<= (fcm->addr_bytes - sc->col_cycles) * 8;
396 fcm->row_addr |= addr_bits;
399 if (fcm->addr_bytes < (sc->row_cycles + sc->col_cycles))
403 return (fsl_nand_build_address(dev, fcm->row_addr, fcm->column_addr));
407 fsl_nand_build_address(device_t dev, uint32_t row, uint32_t column)
409 struct fsl_nand_softc *sc;
410 struct fsl_nfc_fcm *fcm;
411 uint32_t byte_count = 0;
412 uint32_t block_address = 0;
413 uint32_t page_address = 0;
415 sc = device_get_softc(dev);
421 if (fcm->addr_type == ADDR_ROWCOL) {
422 fcm->reg_fir |= (FIR_OP_CA << OP_SHIFT(fcm->opnr));
425 column += fcm->pg_ofs;
428 page_address |= column;
431 byte_count = sc->pgsz - column;
432 fcm->read_ptr = column;
436 fcm->reg_fir |= (FIR_OP_PA << OP_SHIFT(fcm->opnr));
439 if (sc->pgsz == FSL_LARGE_PAGE_SIZE) {
440 block_address = row >> 6;
441 page_address |= ((row << FPAR_LP_PI_SHIFT) & FPAR_LP_PI);
442 fcm->buf_ofs = (row & 1) * 4096;
444 block_address = row >> 5;
445 page_address |= ((row << FPAR_SP_PI_SHIFT) & FPAR_SP_PI);
446 fcm->buf_ofs = (row & 7) * 1024;
449 fcm->reg_fbcr = byte_count;
450 fcm->reg_fbar = block_address;
451 fcm->reg_fpar = page_address;
456 fsl_nfc_start_command(device_t dev)
458 struct fsl_nand_softc *sc;
459 struct fsl_nfc_fcm *fcm;
460 uint32_t fmr, ltesr_v;
463 // device_printf(dev, "%s()\n", __func__);
465 sc = device_get_softc(dev);
468 fmr = fcm->reg_fmr | FMR_OP;
471 fcm->reg_fir |= (fcm->data_fir << OP_SHIFT(fcm->opnr));
473 LBC_WRITE(FIR, fcm->reg_fir);
474 LBC_WRITE(FCR, fcm->reg_fcr);
478 LBC_WRITE(FBCR, fcm->reg_fbcr);
479 LBC_WRITE(FBAR, fcm->reg_fbar);
480 LBC_WRITE(FPAR, fcm->reg_fpar);
482 if (fcm->addr_type == ADDR_ID)
483 LBC_WRITE(MDR, fcm->reg_mdr);
485 nand_debug(NDBG_DRV, "BEFORE:\nFMR=%#x, FIR=%#x, FCR=%#x", fmr,
486 fcm->reg_fir, fcm->reg_fcr);
487 nand_debug(NDBG_DRV, "MDR=%#x, FBAR=%#x, FPAR=%#x, FBCR=%#x",
488 LBC_READ(MDR), fcm->reg_fbar, fcm->reg_fpar, fcm->reg_fbcr);
490 LBC_WRITE(LSOR, sc->dinfo->di_bank);
492 timeout = (cold) ? FSL_FCM_WAIT_TIMEOUT : ~0;
494 ltesr_v = LBC_READ(LTESR);
495 while (!error && (ltesr_v & LTESR_CC) == 0) {
502 error = tsleep(device_get_parent(sc->dev), PRIBIO,
504 ltesr_v = LBC_READ(LTESR);
507 nand_debug(NDBG_DRV, "Command complete wait timeout\n");
509 nand_debug(NDBG_DRV, "AFTER:\nLTESR=%#x, LTEDR=%#x, LTEIR=%#x,"
510 " LTEATR=%#x, LTEAR=%#x, LTECCR=%#x", ltesr_v,
511 LBC_READ(LTEDR), LBC_READ(LTEIR), LBC_READ(LTEATR),
512 LBC_READ(LTEAR), LBC_READ(LTECCR));
514 bzero(&fcm->fcm_startzero,
515 __rangeof(struct fsl_nfc_fcm, fcm_startzero, fcm_endzero));
518 sc->fcm.reg_mdr = LBC_READ(MDR);
520 /* Even if timeout occurred, we should perform steps below */
521 LBC_WRITE(LTESR, ltesr_v);
522 LBC_WRITE(LTEATR, 0);
528 fsl_nfc_read_byte(device_t dev)
530 struct fsl_nand_softc *sc = device_get_softc(dev);
533 // device_printf(dev, "%s()\n", __func__);
536 * LBC controller allows us to read status into a MDR instead of FCM
537 * buffer. If last operation requested before read_byte() was STATUS,
538 * then return MDR instead of reading a single byte from a buffer.
540 if (sc->fcm.status) {
542 return (sc->fcm.reg_mdr);
545 KASSERT(sc->fcm.read_ptr < sc->pgsz,
546 ("Attempt to read beyond buffer %x %x", sc->fcm.read_ptr,
549 offset = sc->fcm.buf_ofs + sc->fcm.read_ptr;
551 return (bus_read_1(sc->res, offset));
555 fsl_nfc_read_buf(device_t dev, void *buf, uint32_t len)
557 struct fsl_nand_softc *sc = device_get_softc(dev);
561 // device_printf(dev, "%s(buf=%p, len=%u)\n", __func__, buf, len);
563 nand_debug(NDBG_DRV, "REQUEST OF 0x%0x B (BIB=0x%0x, NTR=0x%0x)",
564 len, sc->pgsz, sc->fcm.read_ptr);
566 bytesleft = MIN((unsigned int)len, sc->pgsz - sc->fcm.read_ptr);
568 offset = sc->fcm.buf_ofs + sc->fcm.read_ptr;
569 bus_read_region_1(sc->res, offset, buf, bytesleft);
570 sc->fcm.read_ptr += bytesleft;
574 fsl_nfc_write_buf(device_t dev, void *buf, uint32_t len)
576 struct fsl_nand_softc *sc = device_get_softc(dev);
580 // device_printf(dev, "%s(buf=%p, len=%u)\n", __func__, buf, len);
582 KASSERT(len <= sc->pgsz - sc->fcm.read_ptr,
583 ("Attempt to write beyond buffer"));
585 bytesleft = MIN((unsigned int)len, sc->pgsz - sc->fcm.read_ptr);
587 nand_debug(NDBG_DRV, "REQUEST TO WRITE 0x%0x (BIB=0x%0x, NTR=0x%0x)",
588 bytesleft, sc->pgsz, sc->fcm.read_ptr);
590 offset = sc->fcm.buf_ofs + sc->fcm.read_ptr;
591 bus_write_region_1(sc->res, offset, buf, bytesleft);
592 sc->fcm.read_ptr += bytesleft;
596 fsl_nand_chip_preprobe(device_t dev, struct nand_id *id)
599 if (fsl_nfc_send_command(dev, NAND_CMD_RESET) != 0)
602 if (fsl_nfc_start_command(dev) != 0)
607 if (fsl_nfc_send_command(dev, NAND_CMD_READ_ID))
610 if (fsl_nfc_send_address(dev, 0))
613 if (fsl_nfc_start_command(dev) != 0)
618 id->man_id = fsl_nfc_read_byte(dev);
619 id->dev_id = fsl_nfc_read_byte(dev);
621 nand_debug(NDBG_DRV, "manufacturer id: %x chip id: %x",
622 id->man_id, id->dev_id);
627 #ifdef NAND_DEBUG_TIMING
629 static SYSCTL_NODE(_debug, OID_AUTO, fcm, CTLFLAG_RD, 0, "FCM timing");
631 static u_int csct = 1; /* 22: Chip select to command time (trlx). */
632 SYSCTL_UINT(_debug_fcm, OID_AUTO, csct, CTLFLAG_RW, &csct, 1,
633 "Chip select to command time: determines how far in advance -LCSn is "
634 "asserted prior to any bus activity during a NAND Flash access handled "
635 "by the FCM. This helps meet chip-select setup times for slow memories.");
637 static u_int cst = 1; /* 23: Command setup time (trlx). */
638 SYSCTL_UINT(_debug_fcm, OID_AUTO, cst, CTLFLAG_RW, &cst, 1,
639 "Command setup time: determines the delay of -LFWE assertion relative to "
640 "the command, address, or data change when the external memory access "
641 "is handled by the FCM.");
643 static u_int cht = 1; /* 24: Command hold time (trlx). */
644 SYSCTL_UINT(_debug_fcm, OID_AUTO, cht, CTLFLAG_RW, &cht, 1,
645 "Command hold time: determines the -LFWE negation prior to the command, "
646 "address, or data change when the external memory access is handled by "
649 static u_int scy = 2; /* 25-27: Cycle length in bus clocks */
650 SYSCTL_UINT(_debug_fcm, OID_AUTO, scy, CTLFLAG_RW, &scy, 2,
651 "Cycle length in bus clocks: see RM");
653 static u_int rst = 1; /* 28: Read setup time (trlx). */
654 SYSCTL_UINT(_debug_fcm, OID_AUTO, rst, CTLFLAG_RW, &rst, 1,
655 "Read setup time: determines the delay of -LFRE assertion relative to "
656 "sampling of read data when the external memory access is handled by "
659 static u_int trlx = 1; /* 29: Timing relaxed. */
660 SYSCTL_UINT(_debug_fcm, OID_AUTO, trlx, CTLFLAG_RW, &trlx, 1,
661 "Timing relaxed: modifies the settings of timing parameters for slow "
664 static u_int ehtr = 1; /* 30: Extended hold time on read accesses. */
665 SYSCTL_UINT(_debug_fcm, OID_AUTO, ehtr, CTLFLAG_RW, &ehtr, 1,
666 "Extended hold time on read accesses: indicates with TRLX how many "
667 "cycles are inserted between a read access from the current bank and "
671 fsl_nand_get_timing(void)
675 timing = ((csct & 1) << 9) | ((cst & 1) << 8) | ((cht & 1) << 7) |
676 ((scy & 7) << 4) | ((rst & 1) << 3) | ((trlx & 1) << 2) |
679 printf("nfc_fsl: timing = %u\n", timing);
684 fsl_sysctl_program(SYSCTL_HANDLER_ARGS)
686 struct fsl_nand_softc *sc;
691 error = sysctl_wire_old_buffer(req, sizeof(int));
694 error = sysctl_handle_int(oidp, &i, 0, req);
696 if (error != 0 || req->newptr == NULL)
699 for (i = 0; i < 8; i++) {
703 sc = device_get_softc(dev);
705 /* Reprogram OR(x) */
706 or_v = lbc_read_reg(dev, LBC85XX_OR(sc->dinfo->di_bank));
708 or_v |= fsl_nand_get_timing();
709 lbc_write_reg(dev, LBC85XX_OR(sc->dinfo->di_bank), or_v);
714 SYSCTL_PROC(_debug_fcm, OID_AUTO, program, CTLTYPE_INT | CTLFLAG_RW, NULL, 0,
715 fsl_sysctl_program, "I", "write to program FCM with current values");
717 #endif /* NAND_DEBUG_TIMING */