2 * Copyright (c) 2016 Daniel Wyatt <Daniel.Wyatt@gmail.com>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * Nuvoton GPIO driver.
35 #include <sys/cdefs.h>
37 #include <sys/param.h>
38 #include <sys/kernel.h>
39 #include <sys/systm.h>
41 #include <sys/eventhandler.h>
44 #include <sys/module.h>
48 #include <isa/isavar.h>
50 #include <machine/bus.h>
51 #include <machine/resource.h>
53 #include <dev/gpio/gpiobusvar.h>
58 * Global configuration registers (CR).
60 #define NCT_CR_LDN 0x07 /* Logical Device Number */
61 #define NCT_CR_CHIP_ID 0x20 /* Chip ID */
62 #define NCT_CR_CHIP_ID_H 0x20 /* Chip ID (high byte) */
63 #define NCT_CR_CHIP_ID_L 0x21 /* Chip ID (low byte) */
64 #define NCT_CR_OPT_1 0x26 /* Global Options (1) */
66 /* Logical Device Numbers. */
67 #define NCT_LDN_GPIO 0x07
68 #define NCT_LDN_GPIO_CFG 0x08
69 #define NCT_LDN_GPIO_MODE 0x0f
71 /* Logical Device 7 */
72 #define NCT_LD7_GPIO_ENABLE 0x30
73 #define NCT_LD7_GPIO0_IOR 0xe0
74 #define NCT_LD7_GPIO0_DAT 0xe1
75 #define NCT_LD7_GPIO0_INV 0xe2
76 #define NCT_LD7_GPIO0_DST 0xe3
77 #define NCT_LD7_GPIO1_IOR 0xe4
78 #define NCT_LD7_GPIO1_DAT 0xe5
79 #define NCT_LD7_GPIO1_INV 0xe6
80 #define NCT_LD7_GPIO1_DST 0xe7
82 /* Logical Device F */
83 #define NCT_LDF_GPIO0_OUTCFG 0xe0
84 #define NCT_LDF_GPIO1_OUTCFG 0xe1
86 #define NCT_EXTFUNC_ENTER 0x87
87 #define NCT_EXTFUNC_EXIT 0xaa
89 #define NCT_MAX_PIN 15
90 #define NCT_IS_VALID_PIN(_p) ((_p) >= 0 && (_p) <= NCT_MAX_PIN)
92 #define NCT_PIN_BIT(_p) (1 << ((_p) % 8))
94 #define NCT_GPIO_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \
95 GPIO_PIN_OPENDRAIN | GPIO_PIN_PUSHPULL | \
96 GPIO_PIN_INVIN | GPIO_PIN_INVOUT)
102 struct resource *portres;
104 struct gpio_pin pins[NCT_MAX_PIN + 1];
107 #define GPIO_LOCK_INIT(_sc) mtx_init(&(_sc)->mtx, \
108 device_get_nameunit(dev), NULL, MTX_DEF)
109 #define GPIO_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->mtx)
110 #define GPIO_LOCK(_sc) mtx_lock(&(_sc)->mtx)
111 #define GPIO_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx)
112 #define GPIO_ASSERT_LOCKED(_sc) mtx_assert(&(_sc)->mtx, MA_OWNED)
113 #define GPIO_ASSERT_UNLOCKED(_sc) mtx_assert(&(_sc)->mtx, MA_NOTOWNED)
115 #define NCT_BARRIER_WRITE(_sc) \
116 bus_barrier((_sc)->portres, 0, 2, BUS_SPACE_BARRIER_WRITE)
118 #define NCT_BARRIER_READ_WRITE(_sc) \
119 bus_barrier((_sc)->portres, 0, 2, \
120 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE)
122 static void ext_cfg_enter(struct nct_softc *);
123 static void ext_cfg_exit(struct nct_softc *);
126 * Potential Extended Function Enable Register addresses.
127 * Same address as EFIR.
129 uint8_t probe_addrs[] = {0x2e, 0x4e};
131 struct nuvoton_vendor_device_id {
137 .descr = "Nuvoton NCT5104D",
141 .descr = "Nuvoton NCT5104D (PC-Engines APU)",
145 .descr = "Nuvoton NCT5104D (PC-Engines APU3)",
150 write_cfg_reg_1(struct nct_softc *sc, uint8_t reg, uint8_t value)
152 GPIO_ASSERT_LOCKED(sc);
153 bus_write_1(sc->portres, 0, reg);
154 NCT_BARRIER_WRITE(sc);
155 bus_write_1(sc->portres, 1, value);
156 NCT_BARRIER_WRITE(sc);
160 read_cfg_reg_1(struct nct_softc *sc, uint8_t reg)
164 GPIO_ASSERT_LOCKED(sc);
165 bus_write_1(sc->portres, 0, reg);
166 NCT_BARRIER_READ_WRITE(sc);
167 value = bus_read_1(sc->portres, 1);
168 NCT_BARRIER_READ_WRITE(sc);
174 read_cfg_reg_2(struct nct_softc *sc, uint8_t reg)
178 value = read_cfg_reg_1(sc, reg) << 8;
179 value |= read_cfg_reg_1(sc, reg + 1);
185 * Enable extended function mode.
189 ext_cfg_enter(struct nct_softc *sc)
191 GPIO_ASSERT_LOCKED(sc);
192 bus_write_1(sc->portres, 0, NCT_EXTFUNC_ENTER);
193 NCT_BARRIER_WRITE(sc);
194 bus_write_1(sc->portres, 0, NCT_EXTFUNC_ENTER);
195 NCT_BARRIER_WRITE(sc);
199 * Disable extended function mode.
203 ext_cfg_exit(struct nct_softc *sc)
205 GPIO_ASSERT_LOCKED(sc);
206 bus_write_1(sc->portres, 0, NCT_EXTFUNC_EXIT);
207 NCT_BARRIER_WRITE(sc);
211 * Select a Logical Device.
214 select_ldn(struct nct_softc *sc, uint8_t ldn)
216 write_cfg_reg_1(sc, NCT_CR_LDN, ldn);
220 * Get the GPIO Input/Output register address
224 nct_ior_addr(uint32_t pin_num)
228 addr = NCT_LD7_GPIO0_IOR;
230 addr = NCT_LD7_GPIO1_IOR;
236 * Get the GPIO Data register address for a pin.
239 nct_dat_addr(uint32_t pin_num)
243 addr = NCT_LD7_GPIO0_DAT;
245 addr = NCT_LD7_GPIO1_DAT;
251 * Get the GPIO Inversion register address
255 nct_inv_addr(uint32_t pin_num)
259 addr = NCT_LD7_GPIO0_INV;
261 addr = NCT_LD7_GPIO1_INV;
267 * Get the GPIO Output Configuration/Mode
268 * register address for a pin.
271 nct_outcfg_addr(uint32_t pin_num)
275 addr = NCT_LDF_GPIO0_OUTCFG;
277 addr = NCT_LDF_GPIO1_OUTCFG;
283 * Set a pin to output mode.
286 nct_set_pin_is_output(struct nct_softc *sc, uint32_t pin_num)
291 reg = nct_ior_addr(pin_num);
292 select_ldn(sc, NCT_LDN_GPIO);
293 ior = read_cfg_reg_1(sc, reg);
294 ior &= ~(NCT_PIN_BIT(pin_num));
295 write_cfg_reg_1(sc, reg, ior);
299 * Set a pin to input mode.
302 nct_set_pin_is_input(struct nct_softc *sc, uint32_t pin_num)
307 reg = nct_ior_addr(pin_num);
308 select_ldn(sc, NCT_LDN_GPIO);
309 ior = read_cfg_reg_1(sc, reg);
310 ior |= NCT_PIN_BIT(pin_num);
311 write_cfg_reg_1(sc, reg, ior);
315 * Check whether a pin is configured as an input.
318 nct_pin_is_input(struct nct_softc *sc, uint32_t pin_num)
323 reg = nct_ior_addr(pin_num);
324 select_ldn(sc, NCT_LDN_GPIO);
325 ior = read_cfg_reg_1(sc, reg);
327 return (ior & NCT_PIN_BIT(pin_num));
331 * Write a value to an output pin.
334 nct_write_pin(struct nct_softc *sc, uint32_t pin_num, uint8_t data)
339 reg = nct_dat_addr(pin_num);
340 select_ldn(sc, NCT_LDN_GPIO);
341 value = read_cfg_reg_1(sc, reg);
343 value |= NCT_PIN_BIT(pin_num);
345 value &= ~(NCT_PIN_BIT(pin_num));
347 write_cfg_reg_1(sc, reg, value);
351 nct_read_pin(struct nct_softc *sc, uint32_t pin_num)
355 reg = nct_dat_addr(pin_num);
356 select_ldn(sc, NCT_LDN_GPIO);
358 return (read_cfg_reg_1(sc, reg) & NCT_PIN_BIT(pin_num));
362 nct_set_pin_is_inverted(struct nct_softc *sc, uint32_t pin_num)
367 reg = nct_inv_addr(pin_num);
368 select_ldn(sc, NCT_LDN_GPIO);
369 inv = read_cfg_reg_1(sc, reg);
370 inv |= (NCT_PIN_BIT(pin_num));
371 write_cfg_reg_1(sc, reg, inv);
375 nct_set_pin_not_inverted(struct nct_softc *sc, uint32_t pin_num)
380 reg = nct_inv_addr(pin_num);
381 select_ldn(sc, NCT_LDN_GPIO);
382 inv = read_cfg_reg_1(sc, reg);
383 inv &= ~(NCT_PIN_BIT(pin_num));
384 write_cfg_reg_1(sc, reg, inv);
388 nct_pin_is_inverted(struct nct_softc *sc, uint32_t pin_num)
393 reg = nct_inv_addr(pin_num);
394 select_ldn(sc, NCT_LDN_GPIO);
395 inv = read_cfg_reg_1(sc, reg);
397 return (inv & NCT_PIN_BIT(pin_num));
401 nct_set_pin_opendrain(struct nct_softc *sc, uint32_t pin_num)
406 reg = nct_outcfg_addr(pin_num);
407 select_ldn(sc, NCT_LDN_GPIO_MODE);
408 outcfg = read_cfg_reg_1(sc, reg);
409 outcfg |= (NCT_PIN_BIT(pin_num));
410 write_cfg_reg_1(sc, reg, outcfg);
414 nct_set_pin_pushpull(struct nct_softc *sc, uint32_t pin_num)
419 reg = nct_outcfg_addr(pin_num);
420 select_ldn(sc, NCT_LDN_GPIO_MODE);
421 outcfg = read_cfg_reg_1(sc, reg);
422 outcfg &= ~(NCT_PIN_BIT(pin_num));
423 write_cfg_reg_1(sc, reg, outcfg);
427 nct_pin_is_opendrain(struct nct_softc *sc, uint32_t pin_num)
432 reg = nct_outcfg_addr(pin_num);
433 select_ldn(sc, NCT_LDN_GPIO_MODE);
434 outcfg = read_cfg_reg_1(sc, reg);
436 return (outcfg & NCT_PIN_BIT(pin_num));
440 nct_identify(driver_t *driver, device_t parent)
442 if (device_find_child(parent, driver->name, 0) != NULL)
445 BUS_ADD_CHILD(parent, 0, driver->name, 0);
449 nct_probe(device_t dev)
453 struct nct_softc *sc;
456 /* Make sure we do not claim some ISA PNP device. */
457 if (isa_get_logicalid(dev) != 0)
460 sc = device_get_softc(dev);
462 for (i = 0; i < nitems(probe_addrs); i++) {
464 sc->portres = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->rid,
465 probe_addrs[i], probe_addrs[i] + 1, 2, RF_ACTIVE);
466 if (sc->portres == NULL)
471 GPIO_ASSERT_UNLOCKED(sc);
474 chipid = read_cfg_reg_2(sc, NCT_CR_CHIP_ID);
478 GPIO_LOCK_DESTROY(sc);
480 bus_release_resource(dev, SYS_RES_IOPORT, sc->rid, sc->portres);
481 bus_delete_resource(dev, SYS_RES_IOPORT, sc->rid);
483 for (j = 0; j < nitems(nct_devs); j++) {
484 if (chipid == nct_devs[j].chip_id) {
485 rc = bus_set_resource(dev, SYS_RES_IOPORT, 0, probe_addrs[i], 2);
487 device_printf(dev, "bus_set_resource failed for address 0x%02X\n", probe_addrs[i]);
490 device_set_desc(dev, nct_devs[j].descr);
491 return (BUS_PROBE_DEFAULT);
499 nct_attach(device_t dev)
501 struct nct_softc *sc;
504 sc = device_get_softc(dev);
507 sc->portres = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->rid,
508 0ul, ~0ul, 2, RF_ACTIVE);
509 if (sc->portres == NULL) {
510 device_printf(dev, "cannot allocate ioport\n");
516 GPIO_ASSERT_UNLOCKED(sc);
519 select_ldn(sc, NCT_LDN_GPIO);
520 /* Enable gpio0 and gpio1. */
521 write_cfg_reg_1(sc, NCT_LD7_GPIO_ENABLE,
522 read_cfg_reg_1(sc, NCT_LD7_GPIO_ENABLE) | 0x03);
524 for (i = 0; i <= NCT_MAX_PIN; i++) {
525 struct gpio_pin *pin;
529 pin->gp_caps = NCT_GPIO_CAPS;
532 snprintf(pin->gp_name, GPIOMAXNAME, "GPIO%02o", i);
533 pin->gp_name[GPIOMAXNAME - 1] = '\0';
535 if (nct_pin_is_input(sc, i))
536 pin->gp_flags |= GPIO_PIN_INPUT;
538 pin->gp_flags |= GPIO_PIN_OUTPUT;
540 if (nct_pin_is_opendrain(sc, i))
541 pin->gp_flags |= GPIO_PIN_OPENDRAIN;
543 pin->gp_flags |= GPIO_PIN_PUSHPULL;
545 if (nct_pin_is_inverted(sc, i))
546 pin->gp_flags |= (GPIO_PIN_INVIN | GPIO_PIN_INVOUT);
550 sc->busdev = gpiobus_attach_bus(dev);
551 if (sc->busdev == NULL) {
552 GPIO_ASSERT_UNLOCKED(sc);
556 bus_release_resource(dev, SYS_RES_IOPORT, sc->rid, sc->portres);
557 GPIO_LOCK_DESTROY(sc);
566 nct_detach(device_t dev)
568 struct nct_softc *sc;
570 sc = device_get_softc(dev);
571 gpiobus_detach_bus(dev);
573 GPIO_ASSERT_UNLOCKED(sc);
578 /* Cleanup resources. */
579 bus_release_resource(dev, SYS_RES_IOPORT, sc->rid, sc->portres);
581 GPIO_LOCK_DESTROY(sc);
587 nct_gpio_get_bus(device_t dev)
589 struct nct_softc *sc;
591 sc = device_get_softc(dev);
597 nct_gpio_pin_max(device_t dev, int *npins)
599 *npins = NCT_MAX_PIN;
605 nct_gpio_pin_set(device_t dev, uint32_t pin_num, uint32_t pin_value)
607 struct nct_softc *sc;
609 if (!NCT_IS_VALID_PIN(pin_num))
612 sc = device_get_softc(dev);
613 GPIO_ASSERT_UNLOCKED(sc);
615 nct_write_pin(sc, pin_num, pin_value);
622 nct_gpio_pin_get(device_t dev, uint32_t pin_num, uint32_t *pin_value)
624 struct nct_softc *sc;
626 if (!NCT_IS_VALID_PIN(pin_num))
629 sc = device_get_softc(dev);
630 GPIO_ASSERT_UNLOCKED(sc);
632 *pin_value = nct_read_pin(sc, pin_num);
639 nct_gpio_pin_toggle(device_t dev, uint32_t pin_num)
641 struct nct_softc *sc;
643 if (!NCT_IS_VALID_PIN(pin_num))
646 sc = device_get_softc(dev);
647 GPIO_ASSERT_UNLOCKED(sc);
649 if (nct_read_pin(sc, pin_num))
650 nct_write_pin(sc, pin_num, 0);
652 nct_write_pin(sc, pin_num, 1);
660 nct_gpio_pin_getcaps(device_t dev, uint32_t pin_num, uint32_t *caps)
662 struct nct_softc *sc;
664 if (!NCT_IS_VALID_PIN(pin_num))
667 sc = device_get_softc(dev);
668 GPIO_ASSERT_UNLOCKED(sc);
670 *caps = sc->pins[pin_num].gp_caps;
677 nct_gpio_pin_getflags(device_t dev, uint32_t pin_num, uint32_t *flags)
679 struct nct_softc *sc;
681 if (!NCT_IS_VALID_PIN(pin_num))
684 sc = device_get_softc(dev);
685 GPIO_ASSERT_UNLOCKED(sc);
687 *flags = sc->pins[pin_num].gp_flags;
694 nct_gpio_pin_getname(device_t dev, uint32_t pin_num, char *name)
696 struct nct_softc *sc;
698 if (!NCT_IS_VALID_PIN(pin_num))
701 sc = device_get_softc(dev);
702 GPIO_ASSERT_UNLOCKED(sc);
704 memcpy(name, sc->pins[pin_num].gp_name, GPIOMAXNAME);
711 nct_gpio_pin_setflags(device_t dev, uint32_t pin_num, uint32_t flags)
713 struct nct_softc *sc;
714 struct gpio_pin *pin;
716 if (!NCT_IS_VALID_PIN(pin_num))
719 sc = device_get_softc(dev);
720 pin = &sc->pins[pin_num];
721 if ((flags & pin->gp_caps) != flags)
724 GPIO_ASSERT_UNLOCKED(sc);
726 if (flags & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) {
727 if ((flags & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) ==
728 (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) {
733 if (flags & GPIO_PIN_INPUT)
734 nct_set_pin_is_input(sc, pin_num);
736 nct_set_pin_is_output(sc, pin_num);
739 if (flags & (GPIO_PIN_OPENDRAIN | GPIO_PIN_PUSHPULL)) {
740 if (flags & GPIO_PIN_INPUT) {
745 if ((flags & (GPIO_PIN_OPENDRAIN | GPIO_PIN_PUSHPULL)) ==
746 (GPIO_PIN_OPENDRAIN | GPIO_PIN_PUSHPULL)) {
751 if (flags & GPIO_PIN_OPENDRAIN)
752 nct_set_pin_opendrain(sc, pin_num);
754 nct_set_pin_pushpull(sc, pin_num);
757 if (flags & (GPIO_PIN_INVIN | GPIO_PIN_INVOUT)) {
758 if ((flags & (GPIO_PIN_INVIN | GPIO_PIN_INVOUT)) !=
759 (GPIO_PIN_INVIN | GPIO_PIN_INVOUT)) {
764 if (flags & GPIO_PIN_INVIN)
765 nct_set_pin_is_inverted(sc, pin_num);
767 nct_set_pin_not_inverted(sc, pin_num);
770 pin->gp_flags = flags;
776 static device_method_t nct_methods[] = {
777 /* Device interface */
778 DEVMETHOD(device_identify, nct_identify),
779 DEVMETHOD(device_probe, nct_probe),
780 DEVMETHOD(device_attach, nct_attach),
781 DEVMETHOD(device_detach, nct_detach),
784 DEVMETHOD(gpio_get_bus, nct_gpio_get_bus),
785 DEVMETHOD(gpio_pin_max, nct_gpio_pin_max),
786 DEVMETHOD(gpio_pin_get, nct_gpio_pin_get),
787 DEVMETHOD(gpio_pin_set, nct_gpio_pin_set),
788 DEVMETHOD(gpio_pin_toggle, nct_gpio_pin_toggle),
789 DEVMETHOD(gpio_pin_getname, nct_gpio_pin_getname),
790 DEVMETHOD(gpio_pin_getcaps, nct_gpio_pin_getcaps),
791 DEVMETHOD(gpio_pin_getflags, nct_gpio_pin_getflags),
792 DEVMETHOD(gpio_pin_setflags, nct_gpio_pin_setflags),
797 static driver_t nct_isa_driver = {
800 sizeof(struct nct_softc)
803 static devclass_t nct_devclass;
805 DRIVER_MODULE(nctgpio, isa, nct_isa_driver, nct_devclass, NULL, NULL);
806 MODULE_DEPEND(nctgpio, gpiobus, 1, 1, 1);