2 * Copyright (c) 2016 Daniel Wyatt <Daniel.Wyatt@gmail.com>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * Nuvoton GPIO driver.
35 #include <sys/cdefs.h>
37 #include <sys/param.h>
38 #include <sys/kernel.h>
39 #include <sys/systm.h>
41 #include <sys/eventhandler.h>
44 #include <sys/module.h>
47 #include <machine/bus.h>
49 #include <dev/gpio/gpiobusvar.h>
50 #include <dev/superio/superio.h>
54 /* Logical Device Numbers. */
55 #define NCT_LDN_GPIO 0x07
56 #define NCT_LDN_GPIO_MODE 0x0f
58 /* Logical Device 7 */
59 #define NCT_LD7_GPIO0_IOR 0xe0
60 #define NCT_LD7_GPIO0_DAT 0xe1
61 #define NCT_LD7_GPIO0_INV 0xe2
62 #define NCT_LD7_GPIO0_DST 0xe3
63 #define NCT_LD7_GPIO1_IOR 0xe4
64 #define NCT_LD7_GPIO1_DAT 0xe5
65 #define NCT_LD7_GPIO1_INV 0xe6
66 #define NCT_LD7_GPIO1_DST 0xe7
68 /* Logical Device F */
69 #define NCT_LDF_GPIO0_OUTCFG 0xe0
70 #define NCT_LDF_GPIO1_OUTCFG 0xe1
72 /* Direct I/O port access. */
78 #define NCT_MAX_PIN 15
79 #define NCT_IS_VALID_PIN(_p) ((_p) >= 0 && (_p) <= NCT_MAX_PIN)
81 #define NCT_PIN_BIT(_p) (1 << ((_p) & 7))
83 #define NCT_GPIO_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \
84 GPIO_PIN_OPENDRAIN | GPIO_PIN_PUSHPULL | \
85 GPIO_PIN_INVIN | GPIO_PIN_INVOUT)
88 * Note that the values are important.
89 * They match actual register offsets.
102 struct resource *iores;
106 /* direction, 1: pin is input */
110 /* whether out is valid */
111 uint8_t out_known[2];
112 /* inversion, 1: pin is inverted */
115 struct gpio_pin pins[NCT_MAX_PIN + 1];
118 #define GPIO_LOCK_INIT(_sc) mtx_init(&(_sc)->mtx, \
119 device_get_nameunit(dev), NULL, MTX_DEF)
120 #define GPIO_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->mtx)
121 #define GPIO_LOCK(_sc) mtx_lock(&(_sc)->mtx)
122 #define GPIO_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx)
123 #define GPIO_ASSERT_LOCKED(_sc) mtx_assert(&(_sc)->mtx, MA_OWNED)
124 #define GPIO_ASSERT_UNLOCKED(_sc) mtx_assert(&(_sc)->mtx, MA_NOTOWNED)
126 struct nuvoton_vendor_device_id {
132 .descr = "Nuvoton NCT5104D",
136 .descr = "Nuvoton NCT5104D (PC-Engines APU)",
140 .descr = "Nuvoton NCT5104D (PC-Engines APU3)",
145 nct_io_set_group(struct nct_softc *sc, int group)
148 GPIO_ASSERT_LOCKED(sc);
149 if (group != sc->curgrp) {
150 bus_write_1(sc->iores, NCT_IO_GSR, group);
156 nct_io_read(struct nct_softc *sc, int group, uint8_t reg)
158 nct_io_set_group(sc, group);
159 return (bus_read_1(sc->iores, reg));
163 nct_io_write(struct nct_softc *sc, int group, uint8_t reg, uint8_t val)
165 nct_io_set_group(sc, group);
166 return (bus_write_1(sc->iores, reg, val));
170 nct_get_ioreg(struct nct_softc *sc, reg_t reg, int group)
174 if (sc->iores != NULL)
175 ioreg = NCT_IO_IOR + reg;
177 ioreg = NCT_LD7_GPIO0_IOR + reg;
179 ioreg = NCT_LD7_GPIO1_IOR + reg;
184 nct_read_reg(struct nct_softc *sc, reg_t reg, int group)
189 ioreg = nct_get_ioreg(sc, reg, group);
190 if (sc->iores != NULL)
191 val = nct_io_read(sc, group, ioreg);
193 val = superio_read(sc->dev, ioreg);
198 #define GET_BIT(v, b) (((v) >> (b)) & 1)
200 nct_get_pin_reg(struct nct_softc *sc, reg_t reg, uint32_t pin_num)
206 KASSERT(NCT_IS_VALID_PIN(pin_num), ("%s: invalid pin number %d",
209 group = pin_num >> 3;
211 val = nct_read_reg(sc, reg, group);
212 return (GET_BIT(val, bit));
216 nct_get_pin_cache(struct nct_softc *sc, uint32_t pin_num, uint8_t *cache)
222 KASSERT(NCT_IS_VALID_PIN(pin_num), ("%s: invalid pin number %d",
225 group = pin_num >> 3;
228 return (GET_BIT(val, bit));
232 nct_write_reg(struct nct_softc *sc, reg_t reg, int group, uint8_t val)
236 ioreg = nct_get_ioreg(sc, reg, group);
237 if (sc->iores != NULL)
238 nct_io_write(sc, group, ioreg, val);
240 superio_write(sc->dev, ioreg, val);
244 nct_set_pin_reg(struct nct_softc *sc, reg_t reg, uint32_t pin_num, bool val)
252 KASSERT(NCT_IS_VALID_PIN(pin_num),
253 ("%s: invalid pin number %d", __func__, pin_num));
254 KASSERT(reg == REG_IOR || reg == REG_INV,
255 ("%s: unsupported register %d", __func__, reg));
257 group = pin_num >> 3;
259 mask = (uint8_t)1 << bit;
260 bitval = (uint8_t)val << bit;
263 cache = &sc->cache.ior[group];
265 cache = &sc->cache.inv[group];
266 if ((*cache & mask) == bitval)
270 nct_write_reg(sc, reg, group, *cache);
274 * Set a pin to input (val is true) or output (val is false) mode.
277 nct_set_pin_input(struct nct_softc *sc, uint32_t pin_num, bool val)
279 nct_set_pin_reg(sc, REG_IOR, pin_num, val);
283 * Check whether a pin is configured as an input.
286 nct_pin_is_input(struct nct_softc *sc, uint32_t pin_num)
288 return (nct_get_pin_cache(sc, pin_num, sc->cache.ior));
292 * Set a pin to inverted (val is true) or normal (val is false) mode.
295 nct_set_pin_inverted(struct nct_softc *sc, uint32_t pin_num, bool val)
297 nct_set_pin_reg(sc, REG_INV, pin_num, val);
301 nct_pin_is_inverted(struct nct_softc *sc, uint32_t pin_num)
303 return (nct_get_pin_cache(sc, pin_num, sc->cache.inv));
307 * Write a value to an output pin.
308 * NB: the hardware remembers last output value across switching from
309 * output mode to input mode and back.
310 * Writes to a pin in input mode are not allowed here as they cannot
311 * have any effect and would corrupt the output value cache.
314 nct_write_pin(struct nct_softc *sc, uint32_t pin_num, bool val)
319 KASSERT(!nct_pin_is_input(sc, pin_num), ("attempt to write input pin"));
320 group = pin_num >> 3;
322 if (GET_BIT(sc->cache.out_known[group], bit) &&
323 GET_BIT(sc->cache.out[group], bit) == val) {
324 /* The pin is already in requested state. */
327 sc->cache.out_known[group] |= 1 << bit;
329 sc->cache.out[group] |= 1 << bit;
331 sc->cache.out[group] &= ~(1 << bit);
332 nct_write_reg(sc, REG_DAT, group, sc->cache.out[group]);
336 * NB: state of an input pin cannot be cached, of course.
337 * For an output we can either take the value from the cache if it's valid
338 * or read the state from the hadrware and cache it.
341 nct_read_pin(struct nct_softc *sc, uint32_t pin_num)
347 if (nct_pin_is_input(sc, pin_num))
348 return (nct_get_pin_reg(sc, REG_DAT, pin_num));
350 group = pin_num >> 3;
352 if (GET_BIT(sc->cache.out_known[group], bit))
353 return (GET_BIT(sc->cache.out[group], bit));
355 val = nct_get_pin_reg(sc, REG_DAT, pin_num);
356 sc->cache.out_known[group] |= 1 << bit;
358 sc->cache.out[group] |= 1 << bit;
360 sc->cache.out[group] &= ~(1 << bit);
365 nct_outcfg_addr(uint32_t pin_num)
367 KASSERT(NCT_IS_VALID_PIN(pin_num), ("%s: invalid pin number %d",
369 if ((pin_num >> 3) == 0)
370 return (NCT_LDF_GPIO0_OUTCFG);
372 return (NCT_LDF_GPIO1_OUTCFG);
376 * NB: PP/OD can be configured only via configuration registers.
377 * Also, the registers are in a different logical device.
378 * So, this is a special case. No caching too.
381 nct_set_pin_opendrain(struct nct_softc *sc, uint32_t pin_num)
386 reg = nct_outcfg_addr(pin_num);
387 outcfg = superio_read(sc->dev_f, reg);
388 outcfg |= NCT_PIN_BIT(pin_num);
389 superio_write(sc->dev_f, reg, outcfg);
393 nct_set_pin_pushpull(struct nct_softc *sc, uint32_t pin_num)
398 reg = nct_outcfg_addr(pin_num);
399 outcfg = superio_read(sc->dev_f, reg);
400 outcfg &= ~NCT_PIN_BIT(pin_num);
401 superio_write(sc->dev_f, reg, outcfg);
405 nct_pin_is_opendrain(struct nct_softc *sc, uint32_t pin_num)
410 reg = nct_outcfg_addr(pin_num);
411 outcfg = superio_read(sc->dev_f, reg);
412 return (outcfg & NCT_PIN_BIT(pin_num));
416 nct_probe(device_t dev)
421 if (superio_vendor(dev) != SUPERIO_VENDOR_NUVOTON)
423 if (superio_get_type(dev) != SUPERIO_DEV_GPIO)
427 * There are several GPIO devices, we attach only to one of them
428 * and use the rest without attaching.
430 if (superio_get_ldn(dev) != NCT_LDN_GPIO)
433 chipid = superio_devid(dev);
434 for (j = 0; j < nitems(nct_devs); j++) {
435 if (chipid == nct_devs[j].chip_id) {
436 device_set_desc(dev, "Nuvoton GPIO controller");
437 return (BUS_PROBE_DEFAULT);
444 nct_attach(device_t dev)
446 struct nct_softc *sc;
452 sc = device_get_softc(dev);
454 sc->dev_f = superio_find_dev(device_get_parent(dev), SUPERIO_DEV_GPIO,
456 if (sc->dev_f == NULL) {
457 device_printf(dev, "failed to find LDN F\n");
462 * As strange as it may seem, I/O port base is configured in the
463 * Logical Device 8 which is primarily used for WDT, but also plays
464 * a role in GPIO configuration.
467 dev_8 = superio_find_dev(device_get_parent(dev), SUPERIO_DEV_WDT, 8);
469 iobase = superio_get_iobase(dev_8);
470 if (iobase != 0 && iobase != 0xffff) {
473 err = bus_set_resource(dev, SYS_RES_IOPORT, sc->iorid,
476 sc->iores = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
477 &sc->iorid, RF_ACTIVE);
478 if (sc->iores == NULL) {
479 device_printf(dev, "can't map i/o space, "
480 "iobase=0x%04x\n", iobase);
484 "failed to set io port resource at 0x%x\n", iobase);
488 /* Enable gpio0 and gpio1. */
489 superio_dev_enable(dev, 0x03);
494 sc->cache.inv[0] = nct_read_reg(sc, REG_INV, 0);
495 sc->cache.inv[1] = nct_read_reg(sc, REG_INV, 1);
496 sc->cache.ior[0] = nct_read_reg(sc, REG_IOR, 0);
497 sc->cache.ior[1] = nct_read_reg(sc, REG_IOR, 1);
500 * Caching input values is meaningless as an input can be changed at any
501 * time by an external agent. But outputs are controlled by this
502 * driver, so it can cache their state. Also, the hardware remembers
503 * the output state of a pin when the pin is switched to input mode and
504 * then back to output mode. So, the cache stays valid.
505 * The only problem is with pins that are in input mode at the attach
506 * time. For them the output state is not known until it is set by the
507 * driver for the first time.
508 * 'out' and 'out_known' bits form a tri-state output cache:
509 * |-----+-----------+---------|
510 * | out | out_known | cache |
511 * |-----+-----------+---------|
512 * | X | 0 | invalid |
515 * |-----+-----------+---------|
517 sc->cache.out[0] = nct_read_reg(sc, REG_DAT, 0);
518 sc->cache.out[1] = nct_read_reg(sc, REG_DAT, 1);
519 sc->cache.out_known[0] = ~sc->cache.ior[0];
520 sc->cache.out_known[1] = ~sc->cache.ior[1];
522 for (i = 0; i <= NCT_MAX_PIN; i++) {
523 struct gpio_pin *pin;
527 pin->gp_caps = NCT_GPIO_CAPS;
530 snprintf(pin->gp_name, GPIOMAXNAME, "GPIO%02o", i);
531 pin->gp_name[GPIOMAXNAME - 1] = '\0';
533 if (nct_pin_is_input(sc, i))
534 pin->gp_flags |= GPIO_PIN_INPUT;
536 pin->gp_flags |= GPIO_PIN_OUTPUT;
538 if (nct_pin_is_opendrain(sc, i))
539 pin->gp_flags |= GPIO_PIN_OPENDRAIN;
541 pin->gp_flags |= GPIO_PIN_PUSHPULL;
543 if (nct_pin_is_inverted(sc, i))
544 pin->gp_flags |= (GPIO_PIN_INVIN | GPIO_PIN_INVOUT);
548 sc->busdev = gpiobus_attach_bus(dev);
549 if (sc->busdev == NULL) {
550 GPIO_LOCK_DESTROY(sc);
558 nct_detach(device_t dev)
560 struct nct_softc *sc;
562 sc = device_get_softc(dev);
563 gpiobus_detach_bus(dev);
565 if (sc->iores != NULL)
566 bus_release_resource(dev, SYS_RES_IOPORT, sc->iorid, sc->iores);
567 GPIO_ASSERT_UNLOCKED(sc);
568 GPIO_LOCK_DESTROY(sc);
574 nct_gpio_get_bus(device_t dev)
576 struct nct_softc *sc;
578 sc = device_get_softc(dev);
584 nct_gpio_pin_max(device_t dev, int *npins)
586 *npins = NCT_MAX_PIN;
592 nct_gpio_pin_set(device_t dev, uint32_t pin_num, uint32_t pin_value)
594 struct nct_softc *sc;
596 if (!NCT_IS_VALID_PIN(pin_num))
599 sc = device_get_softc(dev);
601 if ((sc->pins[pin_num].gp_flags & GPIO_PIN_OUTPUT) == 0) {
605 nct_write_pin(sc, pin_num, pin_value);
612 nct_gpio_pin_get(device_t dev, uint32_t pin_num, uint32_t *pin_value)
614 struct nct_softc *sc;
616 if (!NCT_IS_VALID_PIN(pin_num))
619 sc = device_get_softc(dev);
620 GPIO_ASSERT_UNLOCKED(sc);
622 *pin_value = nct_read_pin(sc, pin_num);
629 nct_gpio_pin_toggle(device_t dev, uint32_t pin_num)
631 struct nct_softc *sc;
633 if (!NCT_IS_VALID_PIN(pin_num))
636 sc = device_get_softc(dev);
637 GPIO_ASSERT_UNLOCKED(sc);
639 if ((sc->pins[pin_num].gp_flags & GPIO_PIN_OUTPUT) == 0) {
643 if (nct_read_pin(sc, pin_num))
644 nct_write_pin(sc, pin_num, 0);
646 nct_write_pin(sc, pin_num, 1);
654 nct_gpio_pin_getcaps(device_t dev, uint32_t pin_num, uint32_t *caps)
656 struct nct_softc *sc;
658 if (!NCT_IS_VALID_PIN(pin_num))
661 sc = device_get_softc(dev);
662 GPIO_ASSERT_UNLOCKED(sc);
664 *caps = sc->pins[pin_num].gp_caps;
671 nct_gpio_pin_getflags(device_t dev, uint32_t pin_num, uint32_t *flags)
673 struct nct_softc *sc;
675 if (!NCT_IS_VALID_PIN(pin_num))
678 sc = device_get_softc(dev);
679 GPIO_ASSERT_UNLOCKED(sc);
681 *flags = sc->pins[pin_num].gp_flags;
688 nct_gpio_pin_getname(device_t dev, uint32_t pin_num, char *name)
690 struct nct_softc *sc;
692 if (!NCT_IS_VALID_PIN(pin_num))
695 sc = device_get_softc(dev);
696 GPIO_ASSERT_UNLOCKED(sc);
698 memcpy(name, sc->pins[pin_num].gp_name, GPIOMAXNAME);
705 nct_gpio_pin_setflags(device_t dev, uint32_t pin_num, uint32_t flags)
707 struct nct_softc *sc;
708 struct gpio_pin *pin;
710 if (!NCT_IS_VALID_PIN(pin_num))
713 sc = device_get_softc(dev);
714 pin = &sc->pins[pin_num];
715 if ((flags & pin->gp_caps) != flags)
718 if ((flags & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) ==
719 (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) {
722 if ((flags & (GPIO_PIN_OPENDRAIN | GPIO_PIN_PUSHPULL)) ==
723 (GPIO_PIN_OPENDRAIN | GPIO_PIN_PUSHPULL)) {
726 if ((flags & (GPIO_PIN_INVIN | GPIO_PIN_INVOUT)) ==
727 (GPIO_PIN_INVIN | GPIO_PIN_INVOUT)) {
731 GPIO_ASSERT_UNLOCKED(sc);
733 if ((flags & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) != 0) {
734 nct_set_pin_input(sc, pin_num, (flags & GPIO_PIN_INPUT) != 0);
735 pin->gp_flags &= ~(GPIO_PIN_INPUT | GPIO_PIN_OUTPUT);
736 pin->gp_flags |= flags & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT);
738 if ((flags & (GPIO_PIN_INVIN | GPIO_PIN_INVOUT)) != 0) {
739 nct_set_pin_inverted(sc, pin_num,
740 (flags & GPIO_PIN_INVIN) != 0);
741 pin->gp_flags &= ~(GPIO_PIN_INVIN | GPIO_PIN_INVOUT);
742 pin->gp_flags |= flags & (GPIO_PIN_INVIN | GPIO_PIN_INVOUT);
744 if ((flags & (GPIO_PIN_OPENDRAIN | GPIO_PIN_PUSHPULL)) != 0) {
745 if (flags & GPIO_PIN_OPENDRAIN)
746 nct_set_pin_opendrain(sc, pin_num);
748 nct_set_pin_pushpull(sc, pin_num);
749 pin->gp_flags &= ~(GPIO_PIN_OPENDRAIN | GPIO_PIN_PUSHPULL);
751 flags & (GPIO_PIN_OPENDRAIN | GPIO_PIN_PUSHPULL);
758 static device_method_t nct_methods[] = {
759 /* Device interface */
760 DEVMETHOD(device_probe, nct_probe),
761 DEVMETHOD(device_attach, nct_attach),
762 DEVMETHOD(device_detach, nct_detach),
765 DEVMETHOD(gpio_get_bus, nct_gpio_get_bus),
766 DEVMETHOD(gpio_pin_max, nct_gpio_pin_max),
767 DEVMETHOD(gpio_pin_get, nct_gpio_pin_get),
768 DEVMETHOD(gpio_pin_set, nct_gpio_pin_set),
769 DEVMETHOD(gpio_pin_toggle, nct_gpio_pin_toggle),
770 DEVMETHOD(gpio_pin_getname, nct_gpio_pin_getname),
771 DEVMETHOD(gpio_pin_getcaps, nct_gpio_pin_getcaps),
772 DEVMETHOD(gpio_pin_getflags, nct_gpio_pin_getflags),
773 DEVMETHOD(gpio_pin_setflags, nct_gpio_pin_setflags),
778 static driver_t nct_driver = {
781 sizeof(struct nct_softc)
784 static devclass_t nct_devclass;
786 DRIVER_MODULE(nctgpio, superio, nct_driver, nct_devclass, NULL, NULL);
787 MODULE_DEPEND(nctgpio, gpiobus, 1, 1, 1);
788 MODULE_DEPEND(nctgpio, superio, 1, 1, 1);
789 MODULE_VERSION(nctgpio, 1);