2 * Copyright (c) 2017 Stormshield.
3 * Copyright (c) 2017 Semihalf.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
28 #include "opt_platform.h"
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/endian.h>
37 #include <sys/mutex.h>
38 #include <sys/kernel.h>
39 #include <sys/module.h>
40 #include <sys/socket.h>
41 #include <sys/sysctl.h>
43 #include <sys/taskqueue.h>
48 #include <net/ethernet.h>
51 #include <net/if_arp.h>
52 #include <net/if_dl.h>
53 #include <net/if_media.h>
54 #include <net/if_types.h>
55 #include <net/if_vlan_var.h>
57 #include <netinet/in_systm.h>
58 #include <netinet/in.h>
59 #include <netinet/ip.h>
60 #include <netinet/tcp_lro.h>
62 #include <sys/sockio.h>
64 #include <machine/bus.h>
66 #include <machine/resource.h>
68 #include <dev/mii/mii.h>
69 #include <dev/mii/miivar.h>
71 #include <dev/ofw/openfirm.h>
72 #include <dev/ofw/ofw_bus.h>
73 #include <dev/ofw/ofw_bus_subr.h>
75 #include <dev/mdio/mdio.h>
77 #include <arm/mv/mvvar.h>
79 #if !defined(__aarch64__)
80 #include <arm/mv/mvreg.h>
81 #include <arm/mv/mvwin.h>
84 #include "if_mvnetareg.h"
85 #include "if_mvnetavar.h"
87 #include "miibus_if.h"
91 #define STATIC /* nothing */
96 #define DASSERT(x) KASSERT((x), (#x))
98 #define A3700_TCLK_250MHZ 250000000
100 /* Device Register Initialization */
101 STATIC int mvneta_initreg(struct ifnet *);
103 /* Descriptor Ring Control for each of queues */
104 STATIC int mvneta_ring_alloc_rx_queue(struct mvneta_softc *, int);
105 STATIC int mvneta_ring_alloc_tx_queue(struct mvneta_softc *, int);
106 STATIC void mvneta_ring_dealloc_rx_queue(struct mvneta_softc *, int);
107 STATIC void mvneta_ring_dealloc_tx_queue(struct mvneta_softc *, int);
108 STATIC int mvneta_ring_init_rx_queue(struct mvneta_softc *, int);
109 STATIC int mvneta_ring_init_tx_queue(struct mvneta_softc *, int);
110 STATIC void mvneta_ring_flush_rx_queue(struct mvneta_softc *, int);
111 STATIC void mvneta_ring_flush_tx_queue(struct mvneta_softc *, int);
112 STATIC void mvneta_dmamap_cb(void *, bus_dma_segment_t *, int, int);
113 STATIC int mvneta_dma_create(struct mvneta_softc *);
115 /* Rx/Tx Queue Control */
116 STATIC int mvneta_rx_queue_init(struct ifnet *, int);
117 STATIC int mvneta_tx_queue_init(struct ifnet *, int);
118 STATIC int mvneta_rx_queue_enable(struct ifnet *, int);
119 STATIC int mvneta_tx_queue_enable(struct ifnet *, int);
120 STATIC void mvneta_rx_lockq(struct mvneta_softc *, int);
121 STATIC void mvneta_rx_unlockq(struct mvneta_softc *, int);
122 STATIC void mvneta_tx_lockq(struct mvneta_softc *, int);
123 STATIC void mvneta_tx_unlockq(struct mvneta_softc *, int);
125 /* Interrupt Handlers */
126 STATIC void mvneta_disable_intr(struct mvneta_softc *);
127 STATIC void mvneta_enable_intr(struct mvneta_softc *);
128 STATIC void mvneta_rxtxth_intr(void *);
129 STATIC int mvneta_misc_intr(struct mvneta_softc *);
130 STATIC void mvneta_tick(void *);
131 /* struct ifnet and mii callbacks*/
132 STATIC int mvneta_xmitfast_locked(struct mvneta_softc *, int, struct mbuf **);
133 STATIC int mvneta_xmit_locked(struct mvneta_softc *, int);
134 #ifdef MVNETA_MULTIQUEUE
135 STATIC int mvneta_transmit(struct ifnet *, struct mbuf *);
136 #else /* !MVNETA_MULTIQUEUE */
137 STATIC void mvneta_start(struct ifnet *);
139 STATIC void mvneta_qflush(struct ifnet *);
140 STATIC void mvneta_tx_task(void *, int);
141 STATIC int mvneta_ioctl(struct ifnet *, u_long, caddr_t);
142 STATIC void mvneta_init(void *);
143 STATIC void mvneta_init_locked(void *);
144 STATIC void mvneta_stop(struct mvneta_softc *);
145 STATIC void mvneta_stop_locked(struct mvneta_softc *);
146 STATIC int mvneta_mediachange(struct ifnet *);
147 STATIC void mvneta_mediastatus(struct ifnet *, struct ifmediareq *);
148 STATIC void mvneta_portup(struct mvneta_softc *);
149 STATIC void mvneta_portdown(struct mvneta_softc *);
151 /* Link State Notify */
152 STATIC void mvneta_update_autoneg(struct mvneta_softc *, int);
153 STATIC int mvneta_update_media(struct mvneta_softc *, int);
154 STATIC void mvneta_adjust_link(struct mvneta_softc *);
155 STATIC void mvneta_update_eee(struct mvneta_softc *);
156 STATIC void mvneta_update_fc(struct mvneta_softc *);
157 STATIC void mvneta_link_isr(struct mvneta_softc *);
158 STATIC void mvneta_linkupdate(struct mvneta_softc *, boolean_t);
159 STATIC void mvneta_linkup(struct mvneta_softc *);
160 STATIC void mvneta_linkdown(struct mvneta_softc *);
161 STATIC void mvneta_linkreset(struct mvneta_softc *);
164 STATIC int mvneta_tx_queue(struct mvneta_softc *, struct mbuf **, int);
165 STATIC void mvneta_tx_set_csumflag(struct ifnet *,
166 struct mvneta_tx_desc *, struct mbuf *);
167 STATIC void mvneta_tx_queue_complete(struct mvneta_softc *, int);
168 STATIC void mvneta_tx_drain(struct mvneta_softc *);
171 STATIC int mvneta_rx(struct mvneta_softc *, int, int);
172 STATIC void mvneta_rx_queue(struct mvneta_softc *, int, int);
173 STATIC void mvneta_rx_queue_refill(struct mvneta_softc *, int);
174 STATIC void mvneta_rx_set_csumflag(struct ifnet *,
175 struct mvneta_rx_desc *, struct mbuf *);
176 STATIC void mvneta_rx_buf_free(struct mvneta_softc *, struct mvneta_buf *);
178 /* MAC address filter */
179 STATIC void mvneta_filter_setup(struct mvneta_softc *);
182 STATIC int sysctl_read_mib(SYSCTL_HANDLER_ARGS);
183 STATIC int sysctl_clear_mib(SYSCTL_HANDLER_ARGS);
184 STATIC int sysctl_set_queue_rxthtime(SYSCTL_HANDLER_ARGS);
185 STATIC void sysctl_mvneta_init(struct mvneta_softc *);
188 STATIC void mvneta_clear_mib(struct mvneta_softc *);
189 STATIC void mvneta_update_mib(struct mvneta_softc *);
192 STATIC boolean_t mvneta_has_switch(device_t);
194 #define mvneta_sc_lock(sc) mtx_lock(&sc->mtx)
195 #define mvneta_sc_unlock(sc) mtx_unlock(&sc->mtx)
197 STATIC struct mtx mii_mutex;
198 STATIC int mii_init = 0;
201 STATIC int mvneta_detach(device_t);
203 STATIC int mvneta_miibus_readreg(device_t, int, int);
204 STATIC int mvneta_miibus_writereg(device_t, int, int, int);
207 STATIC uint32_t mvneta_get_clk(void);
209 static device_method_t mvneta_methods[] = {
210 /* Device interface */
211 DEVMETHOD(device_detach, mvneta_detach),
213 DEVMETHOD(miibus_readreg, mvneta_miibus_readreg),
214 DEVMETHOD(miibus_writereg, mvneta_miibus_writereg),
216 DEVMETHOD(mdio_readreg, mvneta_miibus_readreg),
217 DEVMETHOD(mdio_writereg, mvneta_miibus_writereg),
223 DEFINE_CLASS_0(mvneta, mvneta_driver, mvneta_methods, sizeof(struct mvneta_softc));
225 DRIVER_MODULE(miibus, mvneta, miibus_driver, miibus_devclass, 0, 0);
226 DRIVER_MODULE(mdio, mvneta, mdio_driver, mdio_devclass, 0, 0);
227 MODULE_DEPEND(mvneta, mdio, 1, 1, 1);
228 MODULE_DEPEND(mvneta, ether, 1, 1, 1);
229 MODULE_DEPEND(mvneta, miibus, 1, 1, 1);
230 MODULE_DEPEND(mvneta, mvxpbm, 1, 1, 1);
233 * List of MIB register and names
237 MVNETA_MIB_RX_GOOD_OCT_IDX,
238 MVNETA_MIB_RX_BAD_OCT_IDX,
239 MVNETA_MIB_TX_MAC_TRNS_ERR_IDX,
240 MVNETA_MIB_RX_GOOD_FRAME_IDX,
241 MVNETA_MIB_RX_BAD_FRAME_IDX,
242 MVNETA_MIB_RX_BCAST_FRAME_IDX,
243 MVNETA_MIB_RX_MCAST_FRAME_IDX,
244 MVNETA_MIB_RX_FRAME64_OCT_IDX,
245 MVNETA_MIB_RX_FRAME127_OCT_IDX,
246 MVNETA_MIB_RX_FRAME255_OCT_IDX,
247 MVNETA_MIB_RX_FRAME511_OCT_IDX,
248 MVNETA_MIB_RX_FRAME1023_OCT_IDX,
249 MVNETA_MIB_RX_FRAMEMAX_OCT_IDX,
250 MVNETA_MIB_TX_GOOD_OCT_IDX,
251 MVNETA_MIB_TX_GOOD_FRAME_IDX,
252 MVNETA_MIB_TX_EXCES_COL_IDX,
253 MVNETA_MIB_TX_MCAST_FRAME_IDX,
254 MVNETA_MIB_TX_BCAST_FRAME_IDX,
255 MVNETA_MIB_TX_MAC_CTL_ERR_IDX,
256 MVNETA_MIB_FC_SENT_IDX,
257 MVNETA_MIB_FC_GOOD_IDX,
258 MVNETA_MIB_FC_BAD_IDX,
259 MVNETA_MIB_PKT_UNDERSIZE_IDX,
260 MVNETA_MIB_PKT_FRAGMENT_IDX,
261 MVNETA_MIB_PKT_OVERSIZE_IDX,
262 MVNETA_MIB_PKT_JABBER_IDX,
263 MVNETA_MIB_MAC_RX_ERR_IDX,
264 MVNETA_MIB_MAC_CRC_ERR_IDX,
265 MVNETA_MIB_MAC_COL_IDX,
266 MVNETA_MIB_MAC_LATE_COL_IDX,
269 STATIC struct mvneta_mib_def {
272 const char *sysctl_name;
274 } mvneta_mib_list[] = {
275 [MVNETA_MIB_RX_GOOD_OCT_IDX] = {MVNETA_MIB_RX_GOOD_OCT, 1,
276 "rx_good_oct", "Good Octets Rx"},
277 [MVNETA_MIB_RX_BAD_OCT_IDX] = {MVNETA_MIB_RX_BAD_OCT, 0,
278 "rx_bad_oct", "Bad Octets Rx"},
279 [MVNETA_MIB_TX_MAC_TRNS_ERR_IDX] = {MVNETA_MIB_TX_MAC_TRNS_ERR, 0,
280 "tx_mac_err", "MAC Transmit Error"},
281 [MVNETA_MIB_RX_GOOD_FRAME_IDX] = {MVNETA_MIB_RX_GOOD_FRAME, 0,
282 "rx_good_frame", "Good Frames Rx"},
283 [MVNETA_MIB_RX_BAD_FRAME_IDX] = {MVNETA_MIB_RX_BAD_FRAME, 0,
284 "rx_bad_frame", "Bad Frames Rx"},
285 [MVNETA_MIB_RX_BCAST_FRAME_IDX] = {MVNETA_MIB_RX_BCAST_FRAME, 0,
286 "rx_bcast_frame", "Broadcast Frames Rx"},
287 [MVNETA_MIB_RX_MCAST_FRAME_IDX] = {MVNETA_MIB_RX_MCAST_FRAME, 0,
288 "rx_mcast_frame", "Multicast Frames Rx"},
289 [MVNETA_MIB_RX_FRAME64_OCT_IDX] = {MVNETA_MIB_RX_FRAME64_OCT, 0,
290 "rx_frame_1_64", "Frame Size 1 - 64"},
291 [MVNETA_MIB_RX_FRAME127_OCT_IDX] = {MVNETA_MIB_RX_FRAME127_OCT, 0,
292 "rx_frame_65_127", "Frame Size 65 - 127"},
293 [MVNETA_MIB_RX_FRAME255_OCT_IDX] = {MVNETA_MIB_RX_FRAME255_OCT, 0,
294 "rx_frame_128_255", "Frame Size 128 - 255"},
295 [MVNETA_MIB_RX_FRAME511_OCT_IDX] = {MVNETA_MIB_RX_FRAME511_OCT, 0,
296 "rx_frame_256_511", "Frame Size 256 - 511"},
297 [MVNETA_MIB_RX_FRAME1023_OCT_IDX] = {MVNETA_MIB_RX_FRAME1023_OCT, 0,
298 "rx_frame_512_1023", "Frame Size 512 - 1023"},
299 [MVNETA_MIB_RX_FRAMEMAX_OCT_IDX] = {MVNETA_MIB_RX_FRAMEMAX_OCT, 0,
300 "rx_fame_1024_max", "Frame Size 1024 - Max"},
301 [MVNETA_MIB_TX_GOOD_OCT_IDX] = {MVNETA_MIB_TX_GOOD_OCT, 1,
302 "tx_good_oct", "Good Octets Tx"},
303 [MVNETA_MIB_TX_GOOD_FRAME_IDX] = {MVNETA_MIB_TX_GOOD_FRAME, 0,
304 "tx_good_frame", "Good Frames Tx"},
305 [MVNETA_MIB_TX_EXCES_COL_IDX] = {MVNETA_MIB_TX_EXCES_COL, 0,
306 "tx_exces_collision", "Excessive Collision"},
307 [MVNETA_MIB_TX_MCAST_FRAME_IDX] = {MVNETA_MIB_TX_MCAST_FRAME, 0,
308 "tx_mcast_frame", "Multicast Frames Tx"},
309 [MVNETA_MIB_TX_BCAST_FRAME_IDX] = {MVNETA_MIB_TX_BCAST_FRAME, 0,
310 "tx_bcast_frame", "Broadcast Frames Tx"},
311 [MVNETA_MIB_TX_MAC_CTL_ERR_IDX] = {MVNETA_MIB_TX_MAC_CTL_ERR, 0,
312 "tx_mac_ctl_err", "Unknown MAC Control"},
313 [MVNETA_MIB_FC_SENT_IDX] = {MVNETA_MIB_FC_SENT, 0,
314 "fc_tx", "Flow Control Tx"},
315 [MVNETA_MIB_FC_GOOD_IDX] = {MVNETA_MIB_FC_GOOD, 0,
316 "fc_rx_good", "Good Flow Control Rx"},
317 [MVNETA_MIB_FC_BAD_IDX] = {MVNETA_MIB_FC_BAD, 0,
318 "fc_rx_bad", "Bad Flow Control Rx"},
319 [MVNETA_MIB_PKT_UNDERSIZE_IDX] = {MVNETA_MIB_PKT_UNDERSIZE, 0,
320 "pkt_undersize", "Undersized Packets Rx"},
321 [MVNETA_MIB_PKT_FRAGMENT_IDX] = {MVNETA_MIB_PKT_FRAGMENT, 0,
322 "pkt_fragment", "Fragmented Packets Rx"},
323 [MVNETA_MIB_PKT_OVERSIZE_IDX] = {MVNETA_MIB_PKT_OVERSIZE, 0,
324 "pkt_oversize", "Oversized Packets Rx"},
325 [MVNETA_MIB_PKT_JABBER_IDX] = {MVNETA_MIB_PKT_JABBER, 0,
326 "pkt_jabber", "Jabber Packets Rx"},
327 [MVNETA_MIB_MAC_RX_ERR_IDX] = {MVNETA_MIB_MAC_RX_ERR, 0,
328 "mac_rx_err", "MAC Rx Errors"},
329 [MVNETA_MIB_MAC_CRC_ERR_IDX] = {MVNETA_MIB_MAC_CRC_ERR, 0,
330 "mac_crc_err", "MAC CRC Errors"},
331 [MVNETA_MIB_MAC_COL_IDX] = {MVNETA_MIB_MAC_COL, 0,
332 "mac_collision", "MAC Collision"},
333 [MVNETA_MIB_MAC_LATE_COL_IDX] = {MVNETA_MIB_MAC_LATE_COL, 0,
334 "mac_late_collision", "MAC Late Collision"},
337 static struct resource_spec res_spec[] = {
338 { SYS_RES_MEMORY, 0, RF_ACTIVE },
339 { SYS_RES_IRQ, 0, RF_ACTIVE },
344 driver_intr_t *handler;
347 { mvneta_rxtxth_intr, "MVNETA aggregated interrupt" },
353 #if defined(__aarch64__)
354 return (A3700_TCLK_250MHZ);
361 mvneta_set_mac_address(struct mvneta_softc *sc, uint8_t *addr)
366 mac_l = (addr[4] << 8) | (addr[5]);
367 mac_h = (addr[0] << 24) | (addr[1] << 16) |
368 (addr[2] << 8) | (addr[3] << 0);
370 MVNETA_WRITE(sc, MVNETA_MACAL, mac_l);
371 MVNETA_WRITE(sc, MVNETA_MACAH, mac_h);
376 mvneta_get_mac_address(struct mvneta_softc *sc, uint8_t *addr)
378 uint32_t mac_l, mac_h;
381 if (mvneta_fdt_mac_address(sc, addr) == 0)
385 * Fall back -- use the currently programmed address.
387 mac_l = MVNETA_READ(sc, MVNETA_MACAL);
388 mac_h = MVNETA_READ(sc, MVNETA_MACAH);
389 if (mac_l == 0 && mac_h == 0) {
391 * Generate pseudo-random MAC.
392 * Set lower part to random number | unit number.
394 mac_l = arc4random() & ~0xff;
395 mac_l |= device_get_unit(sc->dev) & 0xff;
396 mac_h = arc4random();
397 mac_h &= ~(3 << 24); /* Clear multicast and LAA bits */
399 device_printf(sc->dev,
400 "Could not acquire MAC address. "
401 "Using randomized one.\n");
405 addr[0] = (mac_h & 0xff000000) >> 24;
406 addr[1] = (mac_h & 0x00ff0000) >> 16;
407 addr[2] = (mac_h & 0x0000ff00) >> 8;
408 addr[3] = (mac_h & 0x000000ff);
409 addr[4] = (mac_l & 0x0000ff00) >> 8;
410 addr[5] = (mac_l & 0x000000ff);
415 mvneta_has_switch(device_t self)
417 phandle_t node, switch_node, switch_eth, switch_eth_handle;
419 node = ofw_bus_get_node(self);
421 ofw_bus_find_compatible(OF_finddevice("/"), "marvell,dsa");
424 OF_getencprop(switch_node, "dsa,ethernet",
425 (void*)&switch_eth_handle, sizeof(switch_eth_handle));
427 if (switch_eth_handle > 0)
428 switch_eth = OF_node_from_xref(switch_eth_handle);
430 /* Return true if dsa,ethernet cell points to us */
431 return (node == switch_eth);
435 mvneta_dma_create(struct mvneta_softc *sc)
437 size_t maxsize, maxsegsz;
444 maxsize = maxsegsz = sizeof(struct mvneta_tx_desc) * MVNETA_TX_RING_CNT;
446 error = bus_dma_tag_create(
447 bus_get_dma_tag(sc->dev), /* parent */
448 16, 0, /* alignment, boundary */
449 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
450 BUS_SPACE_MAXADDR, /* highaddr */
451 NULL, NULL, /* filtfunc, filtfuncarg */
452 maxsize, /* maxsize */
454 maxsegsz, /* maxsegsz */
456 NULL, NULL, /* lockfunc, lockfuncarg */
457 &sc->tx_dtag); /* dmat */
459 device_printf(sc->dev,
460 "Failed to create DMA tag for Tx descriptors.\n");
463 error = bus_dma_tag_create(
464 bus_get_dma_tag(sc->dev), /* parent */
465 1, 0, /* alignment, boundary */
466 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
467 BUS_SPACE_MAXADDR, /* highaddr */
468 NULL, NULL, /* filtfunc, filtfuncarg */
469 MVNETA_PACKET_SIZE, /* maxsize */
470 MVNETA_TX_SEGLIMIT, /* nsegments */
471 MVNETA_PACKET_SIZE, /* maxsegsz */
472 BUS_DMA_ALLOCNOW, /* flags */
473 NULL, NULL, /* lockfunc, lockfuncarg */
476 device_printf(sc->dev,
477 "Failed to create DMA tag for Tx mbufs.\n");
481 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) {
482 error = mvneta_ring_alloc_tx_queue(sc, q);
484 device_printf(sc->dev,
485 "Failed to allocate DMA safe memory for TxQ: %zu\n", q);
493 /* Create tag for Rx descripors */
494 error = bus_dma_tag_create(
495 bus_get_dma_tag(sc->dev), /* parent */
496 32, 0, /* alignment, boundary */
497 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
498 BUS_SPACE_MAXADDR, /* highaddr */
499 NULL, NULL, /* filtfunc, filtfuncarg */
500 sizeof(struct mvneta_rx_desc) * MVNETA_RX_RING_CNT, /* maxsize */
502 sizeof(struct mvneta_rx_desc) * MVNETA_RX_RING_CNT, /* maxsegsz */
504 NULL, NULL, /* lockfunc, lockfuncarg */
505 &sc->rx_dtag); /* dmat */
507 device_printf(sc->dev,
508 "Failed to create DMA tag for Rx descriptors.\n");
512 /* Create tag for Rx buffers */
513 error = bus_dma_tag_create(
514 bus_get_dma_tag(sc->dev), /* parent */
515 32, 0, /* alignment, boundary */
516 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
517 BUS_SPACE_MAXADDR, /* highaddr */
518 NULL, NULL, /* filtfunc, filtfuncarg */
519 MVNETA_PACKET_SIZE, 1, /* maxsize, nsegments */
520 MVNETA_PACKET_SIZE, /* maxsegsz */
522 NULL, NULL, /* lockfunc, lockfuncarg */
523 &sc->rxbuf_dtag); /* dmat */
525 device_printf(sc->dev,
526 "Failed to create DMA tag for Rx buffers.\n");
530 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) {
531 if (mvneta_ring_alloc_rx_queue(sc, q) != 0) {
532 device_printf(sc->dev,
533 "Failed to allocate DMA safe memory for RxQ: %zu\n", q);
540 mvneta_detach(sc->dev);
547 mvneta_attach(device_t self)
549 struct mvneta_softc *sc;
554 #if !defined(__aarch64__)
558 sc = device_get_softc(self);
561 mtx_init(&sc->mtx, "mvneta_sc", NULL, MTX_DEF);
563 error = bus_alloc_resources(self, res_spec, sc->res);
565 device_printf(self, "could not allocate resources\n");
569 sc->version = MVNETA_READ(sc, MVNETA_PV);
570 device_printf(self, "version is %x\n", sc->version);
571 callout_init(&sc->tick_ch, 0);
574 * make sure DMA engines are in reset state
576 MVNETA_WRITE(sc, MVNETA_PRXINIT, 0x00000001);
577 MVNETA_WRITE(sc, MVNETA_PTXINIT, 0x00000001);
579 #if !defined(__aarch64__)
581 * Disable port snoop for buffers and descriptors
582 * to avoid L2 caching of both without DRAM copy.
583 * Obtain coherency settings from the first MBUS
586 if ((MVNETA_READ(sc, MV_WIN_NETA_BASE(0)) & IO_WIN_COH_ATTR_MASK) == 0) {
587 reg = MVNETA_READ(sc, MVNETA_PSNPCFG);
588 reg &= ~MVNETA_PSNPCFG_DESCSNP_MASK;
589 reg &= ~MVNETA_PSNPCFG_BUFSNP_MASK;
590 MVNETA_WRITE(sc, MVNETA_PSNPCFG, reg);
597 if (mvneta_get_mac_address(sc, sc->enaddr)) {
598 device_printf(self, "no mac address.\n");
601 mvneta_set_mac_address(sc, sc->enaddr);
603 mvneta_disable_intr(sc);
605 /* Allocate network interface */
606 ifp = sc->ifp = if_alloc(IFT_ETHER);
608 device_printf(self, "if_alloc() failed\n");
612 if_initname(ifp, device_get_name(self), device_get_unit(self));
615 * We can support 802.1Q VLAN-sized frames and jumbo
618 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_JUMBO_MTU;
621 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
622 #ifdef MVNETA_MULTIQUEUE
623 ifp->if_transmit = mvneta_transmit;
624 ifp->if_qflush = mvneta_qflush;
625 #else /* !MVNETA_MULTIQUEUE */
626 ifp->if_start = mvneta_start;
627 ifp->if_snd.ifq_drv_maxlen = MVNETA_TX_RING_CNT - 1;
628 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
629 IFQ_SET_READY(&ifp->if_snd);
631 ifp->if_init = mvneta_init;
632 ifp->if_ioctl = mvneta_ioctl;
635 * We can do IPv4/TCPv4/UDPv4/TCPv6/UDPv6 checksums in hardware.
637 ifp->if_capabilities |= IFCAP_HWCSUM;
640 * As VLAN hardware tagging is not supported
641 * but is necessary to perform VLAN hardware checksums,
642 * it is done in the driver
644 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWCSUM;
647 * Currently IPv6 HW checksum is broken, so make sure it is disabled.
649 ifp->if_capabilities &= ~IFCAP_HWCSUM_IPV6;
650 ifp->if_capenable = ifp->if_capabilities;
653 * Disabled option(s):
654 * - Support for Large Receive Offload
656 ifp->if_capabilities |= IFCAP_LRO;
658 ifp->if_hwassist = CSUM_IP | CSUM_TCP | CSUM_UDP;
661 * Device DMA Buffer allocation.
662 * Handles resource deallocation in case of failure.
664 error = mvneta_dma_create(sc);
670 /* Initialize queues */
671 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) {
672 error = mvneta_ring_init_tx_queue(sc, q);
679 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) {
680 error = mvneta_ring_init_rx_queue(sc, q);
687 ether_ifattach(ifp, sc->enaddr);
690 * Enable DMA engines and Initialize Device Registers.
692 MVNETA_WRITE(sc, MVNETA_PRXINIT, 0x00000000);
693 MVNETA_WRITE(sc, MVNETA_PTXINIT, 0x00000000);
694 MVNETA_WRITE(sc, MVNETA_PACC, MVNETA_PACC_ACCELERATIONMODE_EDM);
696 mvneta_filter_setup(sc);
697 mvneta_sc_unlock(sc);
701 * Now MAC is working, setup MII.
705 * MII bus is shared by all MACs and all PHYs in SoC.
706 * serializing the bus access should be safe.
708 mtx_init(&mii_mutex, "mvneta_mii", NULL, MTX_DEF);
713 if ((sc->phy_addr != MII_PHY_ANY) && (!sc->use_inband_status)) {
714 error = mii_attach(self, &sc->miibus, ifp, mvneta_mediachange,
715 mvneta_mediastatus, BMSR_DEFCAPMASK, sc->phy_addr,
720 "MII attach failed, error: %d\n", error);
722 ether_ifdetach(sc->ifp);
726 sc->mii = device_get_softc(sc->miibus);
727 sc->phy_attached = 1;
729 /* Disable auto-negotiation in MAC - rely on PHY layer */
730 mvneta_update_autoneg(sc, FALSE);
731 } else if (sc->use_inband_status == TRUE) {
732 /* In-band link status */
733 ifmedia_init(&sc->mvneta_ifmedia, 0, mvneta_mediachange,
736 /* Configure media */
737 ifmedia_add(&sc->mvneta_ifmedia, IFM_ETHER | IFM_1000_T | IFM_FDX,
739 ifmedia_add(&sc->mvneta_ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL);
740 ifmedia_add(&sc->mvneta_ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX,
742 ifmedia_add(&sc->mvneta_ifmedia, IFM_ETHER | IFM_10_T, 0, NULL);
743 ifmedia_add(&sc->mvneta_ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX,
745 ifmedia_add(&sc->mvneta_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
746 ifmedia_set(&sc->mvneta_ifmedia, IFM_ETHER | IFM_AUTO);
748 /* Enable auto-negotiation */
749 mvneta_update_autoneg(sc, TRUE);
752 if (MVNETA_IS_LINKUP(sc))
756 mvneta_sc_unlock(sc);
759 /* Fixed-link, use predefined values */
760 mvneta_update_autoneg(sc, FALSE);
761 ifmedia_init(&sc->mvneta_ifmedia, 0, mvneta_mediachange,
764 ifm_target = IFM_ETHER;
765 switch (sc->phy_speed) {
767 if (sc->phy_mode != MVNETA_PHY_SGMII &&
768 sc->phy_mode != MVNETA_PHY_QSGMII) {
770 "2.5G speed can work only in (Q)SGMII mode\n");
771 ether_ifdetach(sc->ifp);
775 ifm_target |= IFM_2500_T;
778 ifm_target |= IFM_1000_T;
781 ifm_target |= IFM_100_TX;
784 ifm_target |= IFM_10_T;
787 ether_ifdetach(sc->ifp);
793 ifm_target |= IFM_FDX;
795 ifm_target |= IFM_HDX;
797 ifmedia_add(&sc->mvneta_ifmedia, ifm_target, 0, NULL);
798 ifmedia_set(&sc->mvneta_ifmedia, ifm_target);
799 if_link_state_change(sc->ifp, LINK_STATE_UP);
801 if (mvneta_has_switch(self)) {
802 child = device_add_child(sc->dev, "mdio", -1);
804 ether_ifdetach(sc->ifp);
808 bus_generic_attach(sc->dev);
809 bus_generic_attach(child);
812 /* Configure MAC media */
813 mvneta_update_media(sc, ifm_target);
816 sysctl_mvneta_init(sc);
818 callout_reset(&sc->tick_ch, 0, mvneta_tick, sc);
820 error = bus_setup_intr(self, sc->res[1],
821 INTR_TYPE_NET | INTR_MPSAFE, NULL, mvneta_intrs[0].handler, sc,
824 device_printf(self, "could not setup %s\n",
825 mvneta_intrs[0].description);
826 ether_ifdetach(sc->ifp);
835 mvneta_detach(device_t dev)
837 struct mvneta_softc *sc;
840 sc = device_get_softc(dev);
843 /* Detach network interface */
847 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++)
848 mvneta_ring_dealloc_rx_queue(sc, q);
849 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++)
850 mvneta_ring_dealloc_tx_queue(sc, q);
852 if (sc->tx_dtag != NULL)
853 bus_dma_tag_destroy(sc->tx_dtag);
854 if (sc->rx_dtag != NULL)
855 bus_dma_tag_destroy(sc->rx_dtag);
856 if (sc->txmbuf_dtag != NULL)
857 bus_dma_tag_destroy(sc->txmbuf_dtag);
859 bus_release_resources(dev, res_spec, sc->res);
867 mvneta_miibus_readreg(device_t dev, int phy, int reg)
869 struct mvneta_softc *sc;
874 sc = device_get_softc(dev);
877 mtx_lock(&mii_mutex);
879 for (i = 0; i < MVNETA_PHY_TIMEOUT; i++) {
880 if ((MVNETA_READ(sc, MVNETA_SMI) & MVNETA_SMI_BUSY) == 0)
884 if (i == MVNETA_PHY_TIMEOUT) {
885 if_printf(ifp, "SMI busy timeout\n");
886 mtx_unlock(&mii_mutex);
890 smi = MVNETA_SMI_PHYAD(phy) |
891 MVNETA_SMI_REGAD(reg) | MVNETA_SMI_OPCODE_READ;
892 MVNETA_WRITE(sc, MVNETA_SMI, smi);
894 for (i = 0; i < MVNETA_PHY_TIMEOUT; i++) {
895 if ((MVNETA_READ(sc, MVNETA_SMI) & MVNETA_SMI_BUSY) == 0)
900 if (i == MVNETA_PHY_TIMEOUT) {
901 if_printf(ifp, "SMI busy timeout\n");
902 mtx_unlock(&mii_mutex);
905 for (i = 0; i < MVNETA_PHY_TIMEOUT; i++) {
906 smi = MVNETA_READ(sc, MVNETA_SMI);
907 if (smi & MVNETA_SMI_READVALID)
912 if (i == MVNETA_PHY_TIMEOUT) {
913 if_printf(ifp, "SMI busy timeout\n");
914 mtx_unlock(&mii_mutex);
918 mtx_unlock(&mii_mutex);
921 CTR3(KTR_SPARE2, "%s i=%d, timeout=%d\n", ifp->if_xname, i,
925 val = smi & MVNETA_SMI_DATA_MASK;
928 CTR4(KTR_SPARE2, "%s phy=%d, reg=%#x, val=%#x\n", ifp->if_xname, phy,
935 mvneta_miibus_writereg(device_t dev, int phy, int reg, int val)
937 struct mvneta_softc *sc;
942 sc = device_get_softc(dev);
945 CTR4(KTR_SPARE2, "%s phy=%d, reg=%#x, val=%#x\n", ifp->if_xname,
949 mtx_lock(&mii_mutex);
951 for (i = 0; i < MVNETA_PHY_TIMEOUT; i++) {
952 if ((MVNETA_READ(sc, MVNETA_SMI) & MVNETA_SMI_BUSY) == 0)
956 if (i == MVNETA_PHY_TIMEOUT) {
957 if_printf(ifp, "SMI busy timeout\n");
958 mtx_unlock(&mii_mutex);
962 smi = MVNETA_SMI_PHYAD(phy) | MVNETA_SMI_REGAD(reg) |
963 MVNETA_SMI_OPCODE_WRITE | (val & MVNETA_SMI_DATA_MASK);
964 MVNETA_WRITE(sc, MVNETA_SMI, smi);
966 for (i = 0; i < MVNETA_PHY_TIMEOUT; i++) {
967 if ((MVNETA_READ(sc, MVNETA_SMI) & MVNETA_SMI_BUSY) == 0)
972 mtx_unlock(&mii_mutex);
974 if (i == MVNETA_PHY_TIMEOUT)
975 if_printf(ifp, "phy write timed out\n");
981 mvneta_portup(struct mvneta_softc *sc)
985 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) {
986 mvneta_rx_lockq(sc, q);
987 mvneta_rx_queue_enable(sc->ifp, q);
988 mvneta_rx_unlockq(sc, q);
991 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) {
992 mvneta_tx_lockq(sc, q);
993 mvneta_tx_queue_enable(sc->ifp, q);
994 mvneta_tx_unlockq(sc, q);
1000 mvneta_portdown(struct mvneta_softc *sc)
1002 struct mvneta_rx_ring *rx;
1003 struct mvneta_tx_ring *tx;
1007 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) {
1008 rx = MVNETA_RX_RING(sc, q);
1009 mvneta_rx_lockq(sc, q);
1010 rx->queue_status = MVNETA_QUEUE_DISABLED;
1011 mvneta_rx_unlockq(sc, q);
1014 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) {
1015 tx = MVNETA_TX_RING(sc, q);
1016 mvneta_tx_lockq(sc, q);
1017 tx->queue_status = MVNETA_QUEUE_DISABLED;
1018 mvneta_tx_unlockq(sc, q);
1021 /* Wait for all Rx activity to terminate. */
1022 reg = MVNETA_READ(sc, MVNETA_RQC) & MVNETA_RQC_EN_MASK;
1023 reg = MVNETA_RQC_DIS(reg);
1024 MVNETA_WRITE(sc, MVNETA_RQC, reg);
1027 if (cnt >= RX_DISABLE_TIMEOUT) {
1029 "timeout for RX stopped. rqc 0x%x\n", reg);
1033 reg = MVNETA_READ(sc, MVNETA_RQC);
1034 } while ((reg & MVNETA_RQC_EN_MASK) != 0);
1036 /* Wait for all Tx activity to terminate. */
1037 reg = MVNETA_READ(sc, MVNETA_PIE);
1038 reg &= ~MVNETA_PIE_TXPKTINTRPTENB_MASK;
1039 MVNETA_WRITE(sc, MVNETA_PIE, reg);
1041 reg = MVNETA_READ(sc, MVNETA_PRXTXTIM);
1042 reg &= ~MVNETA_PRXTXTI_TBTCQ_MASK;
1043 MVNETA_WRITE(sc, MVNETA_PRXTXTIM, reg);
1045 reg = MVNETA_READ(sc, MVNETA_TQC) & MVNETA_TQC_EN_MASK;
1046 reg = MVNETA_TQC_DIS(reg);
1047 MVNETA_WRITE(sc, MVNETA_TQC, reg);
1050 if (cnt >= TX_DISABLE_TIMEOUT) {
1052 "timeout for TX stopped. tqc 0x%x\n", reg);
1056 reg = MVNETA_READ(sc, MVNETA_TQC);
1057 } while ((reg & MVNETA_TQC_EN_MASK) != 0);
1059 /* Wait for all Tx FIFO is empty */
1062 if (cnt >= TX_FIFO_EMPTY_TIMEOUT) {
1064 "timeout for TX FIFO drained. ps0 0x%x\n", reg);
1068 reg = MVNETA_READ(sc, MVNETA_PS0);
1069 } while (((reg & MVNETA_PS0_TXFIFOEMP) == 0) &&
1070 ((reg & MVNETA_PS0_TXINPROG) != 0));
1074 * Device Register Initialization
1075 * reset device registers to device driver default value.
1076 * the device is not enabled here.
1079 mvneta_initreg(struct ifnet *ifp)
1081 struct mvneta_softc *sc;
1087 CTR1(KTR_SPARE2, "%s initializing device register", ifp->if_xname);
1090 /* Disable Legacy WRR, Disable EJP, Release from reset. */
1091 MVNETA_WRITE(sc, MVNETA_TQC_1, 0);
1092 /* Enable mbus retry. */
1093 MVNETA_WRITE(sc, MVNETA_MBUS_CONF, MVNETA_MBUS_RETRY_EN);
1095 /* Init TX/RX Queue Registers */
1096 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) {
1097 mvneta_rx_lockq(sc, q);
1098 if (mvneta_rx_queue_init(ifp, q) != 0) {
1099 device_printf(sc->dev,
1100 "initialization failed: cannot initialize queue\n");
1101 mvneta_rx_unlockq(sc, q);
1104 mvneta_rx_unlockq(sc, q);
1106 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) {
1107 mvneta_tx_lockq(sc, q);
1108 if (mvneta_tx_queue_init(ifp, q) != 0) {
1109 device_printf(sc->dev,
1110 "initialization failed: cannot initialize queue\n");
1111 mvneta_tx_unlockq(sc, q);
1114 mvneta_tx_unlockq(sc, q);
1118 * Ethernet Unit Control - disable automatic PHY management by HW.
1119 * In case the port uses SMI-controlled PHY, poll its status with
1120 * mii_tick() and update MAC settings accordingly.
1122 reg = MVNETA_READ(sc, MVNETA_EUC);
1123 reg &= ~MVNETA_EUC_POLLING;
1124 MVNETA_WRITE(sc, MVNETA_EUC, reg);
1126 /* EEE: Low Power Idle */
1127 reg = MVNETA_LPIC0_LILIMIT(MVNETA_LPI_LI);
1128 reg |= MVNETA_LPIC0_TSLIMIT(MVNETA_LPI_TS);
1129 MVNETA_WRITE(sc, MVNETA_LPIC0, reg);
1131 reg = MVNETA_LPIC1_TWLIMIT(MVNETA_LPI_TW);
1132 MVNETA_WRITE(sc, MVNETA_LPIC1, reg);
1134 reg = MVNETA_LPIC2_MUSTSET;
1135 MVNETA_WRITE(sc, MVNETA_LPIC2, reg);
1137 /* Port MAC Control set 0 */
1138 reg = MVNETA_PMACC0_MUSTSET; /* must write 0x1 */
1139 reg &= ~MVNETA_PMACC0_PORTEN; /* port is still disabled */
1140 reg |= MVNETA_PMACC0_FRAMESIZELIMIT(MVNETA_MAX_FRAME);
1141 MVNETA_WRITE(sc, MVNETA_PMACC0, reg);
1143 /* Port MAC Control set 2 */
1144 reg = MVNETA_READ(sc, MVNETA_PMACC2);
1145 switch (sc->phy_mode) {
1146 case MVNETA_PHY_QSGMII:
1147 reg |= (MVNETA_PMACC2_PCSEN | MVNETA_PMACC2_RGMIIEN);
1148 MVNETA_WRITE(sc, MVNETA_PSERDESCFG, MVNETA_PSERDESCFG_QSGMII);
1150 case MVNETA_PHY_SGMII:
1151 reg |= (MVNETA_PMACC2_PCSEN | MVNETA_PMACC2_RGMIIEN);
1152 MVNETA_WRITE(sc, MVNETA_PSERDESCFG, MVNETA_PSERDESCFG_SGMII);
1154 case MVNETA_PHY_RGMII:
1155 case MVNETA_PHY_RGMII_ID:
1156 reg |= MVNETA_PMACC2_RGMIIEN;
1159 reg |= MVNETA_PMACC2_MUSTSET;
1160 reg &= ~MVNETA_PMACC2_PORTMACRESET;
1161 MVNETA_WRITE(sc, MVNETA_PMACC2, reg);
1163 /* Port Configuration Extended: enable Tx CRC generation */
1164 reg = MVNETA_READ(sc, MVNETA_PXCX);
1165 reg &= ~MVNETA_PXCX_TXCRCDIS;
1166 MVNETA_WRITE(sc, MVNETA_PXCX, reg);
1168 /* clear MIB counter registers(clear by read) */
1169 for (i = 0; i < nitems(mvneta_mib_list); i++) {
1170 if (mvneta_mib_list[i].reg64)
1171 MVNETA_READ_MIB_8(sc, mvneta_mib_list[i].regnum);
1173 MVNETA_READ_MIB_4(sc, mvneta_mib_list[i].regnum);
1175 MVNETA_READ(sc, MVNETA_PDFC);
1176 MVNETA_READ(sc, MVNETA_POFC);
1178 /* Set SDC register except IPGINT bits */
1179 reg = MVNETA_SDC_RXBSZ_16_64BITWORDS;
1180 reg |= MVNETA_SDC_TXBSZ_16_64BITWORDS;
1181 reg |= MVNETA_SDC_BLMR;
1182 reg |= MVNETA_SDC_BLMT;
1183 MVNETA_WRITE(sc, MVNETA_SDC, reg);
1189 mvneta_dmamap_cb(void *arg, bus_dma_segment_t * segs, int nseg, int error)
1194 *(bus_addr_t *)arg = segs->ds_addr;
1198 mvneta_ring_alloc_rx_queue(struct mvneta_softc *sc, int q)
1200 struct mvneta_rx_ring *rx;
1201 struct mvneta_buf *rxbuf;
1205 if (q >= MVNETA_RX_QNUM_MAX)
1208 rx = MVNETA_RX_RING(sc, q);
1209 mtx_init(&rx->ring_mtx, "mvneta_rx", NULL, MTX_DEF);
1210 /* Allocate DMA memory for Rx descriptors */
1211 error = bus_dmamem_alloc(sc->rx_dtag,
1212 (void**)&(rx->desc),
1213 BUS_DMA_NOWAIT | BUS_DMA_ZERO,
1215 if (error != 0 || rx->desc == NULL)
1217 error = bus_dmamap_load(sc->rx_dtag, rx->desc_map,
1219 sizeof(struct mvneta_rx_desc) * MVNETA_RX_RING_CNT,
1220 mvneta_dmamap_cb, &rx->desc_pa, BUS_DMA_NOWAIT);
1224 for (i = 0; i < MVNETA_RX_RING_CNT; i++) {
1225 error = bus_dmamap_create(sc->rxbuf_dtag, 0, &dmap);
1227 device_printf(sc->dev,
1228 "Failed to create DMA map for Rx buffer num: %d\n", i);
1231 rxbuf = &rx->rxbuf[i];
1238 mvneta_ring_dealloc_rx_queue(sc, q);
1239 device_printf(sc->dev, "DMA Ring buffer allocation failure.\n");
1244 mvneta_ring_alloc_tx_queue(struct mvneta_softc *sc, int q)
1246 struct mvneta_tx_ring *tx;
1249 if (q >= MVNETA_TX_QNUM_MAX)
1251 tx = MVNETA_TX_RING(sc, q);
1252 mtx_init(&tx->ring_mtx, "mvneta_tx", NULL, MTX_DEF);
1253 error = bus_dmamem_alloc(sc->tx_dtag,
1254 (void**)&(tx->desc),
1255 BUS_DMA_NOWAIT | BUS_DMA_ZERO,
1257 if (error != 0 || tx->desc == NULL)
1259 error = bus_dmamap_load(sc->tx_dtag, tx->desc_map,
1261 sizeof(struct mvneta_tx_desc) * MVNETA_TX_RING_CNT,
1262 mvneta_dmamap_cb, &tx->desc_pa, BUS_DMA_NOWAIT);
1266 #ifdef MVNETA_MULTIQUEUE
1267 tx->br = buf_ring_alloc(MVNETA_BUFRING_SIZE, M_DEVBUF, M_NOWAIT,
1269 if (tx->br == NULL) {
1270 device_printf(sc->dev,
1271 "Could not setup buffer ring for TxQ(%d)\n", q);
1279 mvneta_ring_dealloc_tx_queue(sc, q);
1280 device_printf(sc->dev, "DMA Ring buffer allocation failure.\n");
1285 mvneta_ring_dealloc_tx_queue(struct mvneta_softc *sc, int q)
1287 struct mvneta_tx_ring *tx;
1288 struct mvneta_buf *txbuf;
1293 if (q >= MVNETA_TX_QNUM_MAX)
1295 tx = MVNETA_TX_RING(sc, q);
1297 if (tx->taskq != NULL) {
1299 while (taskqueue_cancel(tx->taskq, &tx->task, NULL) != 0)
1300 taskqueue_drain(tx->taskq, &tx->task);
1302 #ifdef MVNETA_MULTIQUEUE
1304 drbr_free(tx->br, M_DEVBUF);
1307 if (sc->txmbuf_dtag != NULL) {
1308 if (mtx_name(&tx->ring_mtx) != NULL) {
1310 * It is assumed that maps are being loaded after mutex
1311 * is initialized. Therefore we can skip unloading maps
1312 * when mutex is empty.
1314 mvneta_tx_lockq(sc, q);
1315 mvneta_ring_flush_tx_queue(sc, q);
1316 mvneta_tx_unlockq(sc, q);
1318 for (i = 0; i < MVNETA_TX_RING_CNT; i++) {
1319 txbuf = &tx->txbuf[i];
1320 if (txbuf->dmap != NULL) {
1321 error = bus_dmamap_destroy(sc->txmbuf_dtag,
1324 panic("%s: map busy for Tx descriptor (Q%d, %d)",
1331 if (tx->desc_pa != 0)
1332 bus_dmamap_unload(sc->tx_dtag, tx->desc_map);
1334 kva = (void *)tx->desc;
1336 bus_dmamem_free(sc->tx_dtag, tx->desc, tx->desc_map);
1338 if (mtx_name(&tx->ring_mtx) != NULL)
1339 mtx_destroy(&tx->ring_mtx);
1341 memset(tx, 0, sizeof(*tx));
1345 mvneta_ring_dealloc_rx_queue(struct mvneta_softc *sc, int q)
1347 struct mvneta_rx_ring *rx;
1348 struct lro_ctrl *lro;
1351 if (q >= MVNETA_RX_QNUM_MAX)
1354 rx = MVNETA_RX_RING(sc, q);
1356 mvneta_ring_flush_rx_queue(sc, q);
1358 if (rx->desc_pa != 0)
1359 bus_dmamap_unload(sc->rx_dtag, rx->desc_map);
1361 kva = (void *)rx->desc;
1363 bus_dmamem_free(sc->rx_dtag, rx->desc, rx->desc_map);
1368 if (mtx_name(&rx->ring_mtx) != NULL)
1369 mtx_destroy(&rx->ring_mtx);
1371 memset(rx, 0, sizeof(*rx));
1375 mvneta_ring_init_rx_queue(struct mvneta_softc *sc, int q)
1377 struct mvneta_rx_ring *rx;
1378 struct lro_ctrl *lro;
1381 if (q >= MVNETA_RX_QNUM_MAX)
1384 rx = MVNETA_RX_RING(sc, q);
1385 rx->dma = rx->cpu = 0;
1386 rx->queue_th_received = MVNETA_RXTH_COUNT;
1387 rx->queue_th_time = (mvneta_get_clk() / 1000) / 10; /* 0.1 [ms] */
1389 /* Initialize LRO */
1390 rx->lro_enabled = FALSE;
1391 if ((sc->ifp->if_capenable & IFCAP_LRO) != 0) {
1393 error = tcp_lro_init(lro);
1395 device_printf(sc->dev, "LRO Initialization failed!\n");
1397 rx->lro_enabled = TRUE;
1406 mvneta_ring_init_tx_queue(struct mvneta_softc *sc, int q)
1408 struct mvneta_tx_ring *tx;
1409 struct mvneta_buf *txbuf;
1412 if (q >= MVNETA_TX_QNUM_MAX)
1415 tx = MVNETA_TX_RING(sc, q);
1418 for (i = 0; i < MVNETA_TX_RING_CNT; i++) {
1419 txbuf = &tx->txbuf[i];
1421 /* Tx handle needs DMA map for busdma_load_mbuf() */
1422 error = bus_dmamap_create(sc->txmbuf_dtag, 0,
1425 device_printf(sc->dev,
1426 "can't create dma map (tx ring %d)\n", i);
1430 tx->dma = tx->cpu = 0;
1433 tx->queue_status = MVNETA_QUEUE_DISABLED;
1434 tx->queue_hung = FALSE;
1438 TASK_INIT(&tx->task, 0, mvneta_tx_task, tx);
1439 tx->taskq = taskqueue_create_fast("mvneta_tx_taskq", M_WAITOK,
1440 taskqueue_thread_enqueue, &tx->taskq);
1441 taskqueue_start_threads(&tx->taskq, 1, PI_NET, "%s: tx_taskq(%d)",
1442 device_get_nameunit(sc->dev), q);
1448 mvneta_ring_flush_tx_queue(struct mvneta_softc *sc, int q)
1450 struct mvneta_tx_ring *tx;
1451 struct mvneta_buf *txbuf;
1454 tx = MVNETA_TX_RING(sc, q);
1455 KASSERT_TX_MTX(sc, q);
1458 for (i = 0; i < MVNETA_TX_RING_CNT; i++) {
1459 txbuf = &tx->txbuf[i];
1460 bus_dmamap_unload(sc->txmbuf_dtag, txbuf->dmap);
1461 if (txbuf->m != NULL) {
1466 tx->dma = tx->cpu = 0;
1471 mvneta_ring_flush_rx_queue(struct mvneta_softc *sc, int q)
1473 struct mvneta_rx_ring *rx;
1474 struct mvneta_buf *rxbuf;
1477 rx = MVNETA_RX_RING(sc, q);
1478 KASSERT_RX_MTX(sc, q);
1481 for (i = 0; i < MVNETA_RX_RING_CNT; i++) {
1482 rxbuf = &rx->rxbuf[i];
1483 mvneta_rx_buf_free(sc, rxbuf);
1485 rx->dma = rx->cpu = 0;
1489 * Rx/Tx Queue Control
1492 mvneta_rx_queue_init(struct ifnet *ifp, int q)
1494 struct mvneta_softc *sc;
1495 struct mvneta_rx_ring *rx;
1499 KASSERT_RX_MTX(sc, q);
1500 rx = MVNETA_RX_RING(sc, q);
1501 DASSERT(rx->desc_pa != 0);
1503 /* descriptor address */
1504 MVNETA_WRITE(sc, MVNETA_PRXDQA(q), rx->desc_pa);
1506 /* Rx buffer size and descriptor ring size */
1507 reg = MVNETA_PRXDQS_BUFFERSIZE(MVNETA_PACKET_SIZE >> 3);
1508 reg |= MVNETA_PRXDQS_DESCRIPTORSQUEUESIZE(MVNETA_RX_RING_CNT);
1509 MVNETA_WRITE(sc, MVNETA_PRXDQS(q), reg);
1511 CTR3(KTR_SPARE2, "%s PRXDQS(%d): %#x", ifp->if_xname, q,
1512 MVNETA_READ(sc, MVNETA_PRXDQS(q)));
1514 /* Rx packet offset address */
1515 reg = MVNETA_PRXC_PACKETOFFSET(MVNETA_PACKET_OFFSET >> 3);
1516 MVNETA_WRITE(sc, MVNETA_PRXC(q), reg);
1518 CTR3(KTR_SPARE2, "%s PRXC(%d): %#x", ifp->if_xname, q,
1519 MVNETA_READ(sc, MVNETA_PRXC(q)));
1522 /* if DMA is not working, register is not updated */
1523 DASSERT(MVNETA_READ(sc, MVNETA_PRXDQA(q)) == rx->desc_pa);
1528 mvneta_tx_queue_init(struct ifnet *ifp, int q)
1530 struct mvneta_softc *sc;
1531 struct mvneta_tx_ring *tx;
1535 KASSERT_TX_MTX(sc, q);
1536 tx = MVNETA_TX_RING(sc, q);
1537 DASSERT(tx->desc_pa != 0);
1539 /* descriptor address */
1540 MVNETA_WRITE(sc, MVNETA_PTXDQA(q), tx->desc_pa);
1542 /* descriptor ring size */
1543 reg = MVNETA_PTXDQS_DQS(MVNETA_TX_RING_CNT);
1544 MVNETA_WRITE(sc, MVNETA_PTXDQS(q), reg);
1546 /* if DMA is not working, register is not updated */
1547 DASSERT(MVNETA_READ(sc, MVNETA_PTXDQA(q)) == tx->desc_pa);
1552 mvneta_rx_queue_enable(struct ifnet *ifp, int q)
1554 struct mvneta_softc *sc;
1555 struct mvneta_rx_ring *rx;
1559 rx = MVNETA_RX_RING(sc, q);
1560 KASSERT_RX_MTX(sc, q);
1562 /* Set Rx interrupt threshold */
1563 reg = MVNETA_PRXDQTH_ODT(rx->queue_th_received);
1564 MVNETA_WRITE(sc, MVNETA_PRXDQTH(q), reg);
1566 reg = MVNETA_PRXITTH_RITT(rx->queue_th_time);
1567 MVNETA_WRITE(sc, MVNETA_PRXITTH(q), reg);
1569 /* Unmask RXTX_TH Intr. */
1570 reg = MVNETA_READ(sc, MVNETA_PRXTXTIM);
1571 reg |= MVNETA_PRXTXTI_RBICTAPQ(q); /* Rx Buffer Interrupt Coalese */
1572 MVNETA_WRITE(sc, MVNETA_PRXTXTIM, reg);
1574 /* Enable Rx queue */
1575 reg = MVNETA_READ(sc, MVNETA_RQC) & MVNETA_RQC_EN_MASK;
1576 reg |= MVNETA_RQC_ENQ(q);
1577 MVNETA_WRITE(sc, MVNETA_RQC, reg);
1579 rx->queue_status = MVNETA_QUEUE_WORKING;
1584 mvneta_tx_queue_enable(struct ifnet *ifp, int q)
1586 struct mvneta_softc *sc;
1587 struct mvneta_tx_ring *tx;
1590 tx = MVNETA_TX_RING(sc, q);
1591 KASSERT_TX_MTX(sc, q);
1593 /* Enable Tx queue */
1594 MVNETA_WRITE(sc, MVNETA_TQC, MVNETA_TQC_ENQ(q));
1596 tx->queue_status = MVNETA_QUEUE_IDLE;
1597 tx->queue_hung = FALSE;
1601 STATIC __inline void
1602 mvneta_rx_lockq(struct mvneta_softc *sc, int q)
1606 DASSERT(q < MVNETA_RX_QNUM_MAX);
1607 mtx_lock(&sc->rx_ring[q].ring_mtx);
1610 STATIC __inline void
1611 mvneta_rx_unlockq(struct mvneta_softc *sc, int q)
1615 DASSERT(q < MVNETA_RX_QNUM_MAX);
1616 mtx_unlock(&sc->rx_ring[q].ring_mtx);
1619 STATIC __inline int __unused
1620 mvneta_tx_trylockq(struct mvneta_softc *sc, int q)
1624 DASSERT(q < MVNETA_TX_QNUM_MAX);
1625 return (mtx_trylock(&sc->tx_ring[q].ring_mtx));
1628 STATIC __inline void
1629 mvneta_tx_lockq(struct mvneta_softc *sc, int q)
1633 DASSERT(q < MVNETA_TX_QNUM_MAX);
1634 mtx_lock(&sc->tx_ring[q].ring_mtx);
1637 STATIC __inline void
1638 mvneta_tx_unlockq(struct mvneta_softc *sc, int q)
1642 DASSERT(q < MVNETA_TX_QNUM_MAX);
1643 mtx_unlock(&sc->tx_ring[q].ring_mtx);
1647 * Interrupt Handlers
1650 mvneta_disable_intr(struct mvneta_softc *sc)
1653 MVNETA_WRITE(sc, MVNETA_EUIM, 0);
1654 MVNETA_WRITE(sc, MVNETA_EUIC, 0);
1655 MVNETA_WRITE(sc, MVNETA_PRXTXTIM, 0);
1656 MVNETA_WRITE(sc, MVNETA_PRXTXTIC, 0);
1657 MVNETA_WRITE(sc, MVNETA_PRXTXIM, 0);
1658 MVNETA_WRITE(sc, MVNETA_PRXTXIC, 0);
1659 MVNETA_WRITE(sc, MVNETA_PMIM, 0);
1660 MVNETA_WRITE(sc, MVNETA_PMIC, 0);
1661 MVNETA_WRITE(sc, MVNETA_PIE, 0);
1665 mvneta_enable_intr(struct mvneta_softc *sc)
1669 /* Enable Summary Bit to check all interrupt cause. */
1670 reg = MVNETA_READ(sc, MVNETA_PRXTXTIM);
1671 reg |= MVNETA_PRXTXTI_PMISCICSUMMARY;
1672 MVNETA_WRITE(sc, MVNETA_PRXTXTIM, reg);
1674 if (sc->use_inband_status) {
1675 /* Enable Port MISC Intr. (via RXTX_TH_Summary bit) */
1676 MVNETA_WRITE(sc, MVNETA_PMIM, MVNETA_PMI_PHYSTATUSCHNG |
1677 MVNETA_PMI_LINKCHANGE | MVNETA_PMI_PSCSYNCCHANGE);
1680 /* Enable All Queue Interrupt */
1681 reg = MVNETA_READ(sc, MVNETA_PIE);
1682 reg |= MVNETA_PIE_RXPKTINTRPTENB_MASK;
1683 reg |= MVNETA_PIE_TXPKTINTRPTENB_MASK;
1684 MVNETA_WRITE(sc, MVNETA_PIE, reg);
1688 mvneta_rxtxth_intr(void *arg)
1690 struct mvneta_softc *sc;
1692 uint32_t ic, queues;
1697 CTR1(KTR_SPARE2, "%s got RXTX_TH_Intr", ifp->if_xname);
1699 ic = MVNETA_READ(sc, MVNETA_PRXTXTIC);
1702 MVNETA_WRITE(sc, MVNETA_PRXTXTIC, ~ic);
1704 /* Ack maintance interrupt first */
1705 if (__predict_false((ic & MVNETA_PRXTXTI_PMISCICSUMMARY) &&
1706 sc->use_inband_status)) {
1708 mvneta_misc_intr(sc);
1709 mvneta_sc_unlock(sc);
1711 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING)))
1713 /* RxTxTH interrupt */
1714 queues = MVNETA_PRXTXTI_GET_RBICTAPQ(ic);
1715 if (__predict_true(queues)) {
1717 CTR1(KTR_SPARE2, "%s got PRXTXTIC: +RXEOF", ifp->if_xname);
1719 /* At the moment the driver support only one RX queue. */
1720 DASSERT(MVNETA_IS_QUEUE_SET(queues, 0));
1721 mvneta_rx(sc, 0, 0);
1726 mvneta_misc_intr(struct mvneta_softc *sc)
1732 CTR1(KTR_SPARE2, "%s got MISC_INTR", sc->ifp->if_xname);
1737 ic = MVNETA_READ(sc, MVNETA_PMIC);
1738 ic &= MVNETA_READ(sc, MVNETA_PMIM);
1741 MVNETA_WRITE(sc, MVNETA_PMIC, ~ic);
1744 if (ic & (MVNETA_PMI_PHYSTATUSCHNG |
1745 MVNETA_PMI_LINKCHANGE | MVNETA_PMI_PSCSYNCCHANGE))
1746 mvneta_link_isr(sc);
1752 mvneta_tick(void *arg)
1754 struct mvneta_softc *sc;
1755 struct mvneta_tx_ring *tx;
1756 struct mvneta_rx_ring *rx;
1758 uint32_t fc_prev, fc_curr;
1763 * This is done before mib update to get the right stats
1766 mvneta_tx_drain(sc);
1768 /* Extract previous flow-control frame received counter. */
1769 fc_prev = sc->sysctl_mib[MVNETA_MIB_FC_GOOD_IDX].counter;
1770 /* Read mib registers (clear by read). */
1771 mvneta_update_mib(sc);
1772 /* Extract current flow-control frame received counter. */
1773 fc_curr = sc->sysctl_mib[MVNETA_MIB_FC_GOOD_IDX].counter;
1776 if (sc->phy_attached && sc->ifp->if_flags & IFF_UP) {
1780 /* Adjust MAC settings */
1781 mvneta_adjust_link(sc);
1782 mvneta_sc_unlock(sc);
1786 * We were unable to refill the rx queue and left the rx func, leaving
1787 * the ring without mbuf and no way to call the refill func.
1789 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) {
1790 rx = MVNETA_RX_RING(sc, q);
1791 if (rx->needs_refill == TRUE) {
1792 mvneta_rx_lockq(sc, q);
1793 mvneta_rx_queue_refill(sc, q);
1794 mvneta_rx_unlockq(sc, q);
1800 * - check if queue is mark as hung.
1801 * - ignore hung status if we received some pause frame
1802 * as hardware may have paused packet transmit.
1804 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) {
1806 * We should take queue lock, but as we only read
1807 * queue status we can do it without lock, we may
1808 * only missdetect queue status for one tick.
1810 tx = MVNETA_TX_RING(sc, q);
1812 if (tx->queue_hung && (fc_curr - fc_prev) == 0)
1816 callout_schedule(&sc->tick_ch, hz);
1820 if_printf(sc->ifp, "watchdog timeout\n");
1823 sc->counter_watchdog++;
1824 sc->counter_watchdog_mib++;
1825 /* Trigger reinitialize sequence. */
1826 mvneta_stop_locked(sc);
1827 mvneta_init_locked(sc);
1828 mvneta_sc_unlock(sc);
1832 mvneta_qflush(struct ifnet *ifp)
1834 #ifdef MVNETA_MULTIQUEUE
1835 struct mvneta_softc *sc;
1836 struct mvneta_tx_ring *tx;
1842 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) {
1843 tx = MVNETA_TX_RING(sc, q);
1844 mvneta_tx_lockq(sc, q);
1845 while ((m = buf_ring_dequeue_sc(tx->br)) != NULL)
1847 mvneta_tx_unlockq(sc, q);
1854 mvneta_tx_task(void *arg, int pending)
1856 struct mvneta_softc *sc;
1857 struct mvneta_tx_ring *tx;
1865 mvneta_tx_lockq(sc, tx->qidx);
1866 error = mvneta_xmit_locked(sc, tx->qidx);
1867 mvneta_tx_unlockq(sc, tx->qidx);
1870 if (__predict_false(error != 0 && error != ENETDOWN)) {
1871 pause("mvneta_tx_task_sleep", 1);
1872 taskqueue_enqueue(tx->taskq, &tx->task);
1877 mvneta_xmitfast_locked(struct mvneta_softc *sc, int q, struct mbuf **m)
1879 struct mvneta_tx_ring *tx;
1883 KASSERT_TX_MTX(sc, q);
1884 tx = MVNETA_TX_RING(sc, q);
1889 /* Dont enqueue packet if the queue is disabled. */
1890 if (__predict_false(tx->queue_status == MVNETA_QUEUE_DISABLED)) {
1896 /* Reclaim mbuf if above threshold. */
1897 if (__predict_true(tx->used > MVNETA_TX_RECLAIM_COUNT))
1898 mvneta_tx_queue_complete(sc, q);
1900 /* Do not call transmit path if queue is already too full. */
1901 if (__predict_false(tx->used >
1902 MVNETA_TX_RING_CNT - MVNETA_TX_SEGLIMIT))
1905 error = mvneta_tx_queue(sc, m, q);
1906 if (__predict_false(error != 0))
1909 /* Send a copy of the frame to the BPF listener */
1910 ETHER_BPF_MTAP(ifp, *m);
1912 /* Set watchdog on */
1913 tx->watchdog_time = ticks;
1914 tx->queue_status = MVNETA_QUEUE_WORKING;
1919 #ifdef MVNETA_MULTIQUEUE
1921 mvneta_transmit(struct ifnet *ifp, struct mbuf *m)
1923 struct mvneta_softc *sc;
1924 struct mvneta_tx_ring *tx;
1930 /* Use default queue if there is no flow id as thread can migrate. */
1931 if (__predict_true(M_HASHTYPE_GET(m) != M_HASHTYPE_NONE))
1932 q = m->m_pkthdr.flowid % MVNETA_TX_QNUM_MAX;
1936 tx = MVNETA_TX_RING(sc, q);
1938 /* If buf_ring is full start transmit immediatly. */
1939 if (buf_ring_full(tx->br)) {
1940 mvneta_tx_lockq(sc, q);
1941 mvneta_xmit_locked(sc, q);
1942 mvneta_tx_unlockq(sc, q);
1946 * If the buf_ring is empty we will not reorder packets.
1947 * If the lock is available transmit without using buf_ring.
1949 if (buf_ring_empty(tx->br) && mvneta_tx_trylockq(sc, q) != 0) {
1950 error = mvneta_xmitfast_locked(sc, q, &m);
1951 mvneta_tx_unlockq(sc, q);
1952 if (__predict_true(error == 0))
1955 /* Transmit can fail in fastpath. */
1956 if (__predict_false(m == NULL))
1960 /* Enqueue then schedule taskqueue. */
1961 error = drbr_enqueue(ifp, tx->br, m);
1962 if (__predict_false(error != 0))
1965 taskqueue_enqueue(tx->taskq, &tx->task);
1970 mvneta_xmit_locked(struct mvneta_softc *sc, int q)
1973 struct mvneta_tx_ring *tx;
1977 KASSERT_TX_MTX(sc, q);
1979 tx = MVNETA_TX_RING(sc, q);
1982 while ((m = drbr_peek(ifp, tx->br)) != NULL) {
1983 error = mvneta_xmitfast_locked(sc, q, &m);
1984 if (__predict_false(error != 0)) {
1986 drbr_putback(ifp, tx->br, m);
1988 drbr_advance(ifp, tx->br);
1991 drbr_advance(ifp, tx->br);
1996 #else /* !MVNETA_MULTIQUEUE */
1998 mvneta_start(struct ifnet *ifp)
2000 struct mvneta_softc *sc;
2001 struct mvneta_tx_ring *tx;
2005 tx = MVNETA_TX_RING(sc, 0);
2007 mvneta_tx_lockq(sc, 0);
2008 error = mvneta_xmit_locked(sc, 0);
2009 mvneta_tx_unlockq(sc, 0);
2010 /* Handle retransmit in the background taskq. */
2011 if (__predict_false(error != 0 && error != ENETDOWN))
2012 taskqueue_enqueue(tx->taskq, &tx->task);
2016 mvneta_xmit_locked(struct mvneta_softc *sc, int q)
2019 struct mvneta_tx_ring *tx;
2023 KASSERT_TX_MTX(sc, q);
2025 tx = MVNETA_TX_RING(sc, 0);
2028 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
2029 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
2033 error = mvneta_xmitfast_locked(sc, q, &m);
2034 if (__predict_false(error != 0)) {
2036 IFQ_DRV_PREPEND(&ifp->if_snd, m);
2046 mvneta_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
2048 struct mvneta_softc *sc;
2049 struct mvneta_rx_ring *rx;
2057 ifr = (struct ifreq *)data;
2061 if (ifp->if_flags & IFF_UP) {
2062 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2063 flags = ifp->if_flags ^ sc->mvneta_if_flags;
2066 sc->mvneta_if_flags = ifp->if_flags;
2068 if ((flags & IFF_PROMISC) != 0)
2069 mvneta_filter_setup(sc);
2071 mvneta_init_locked(sc);
2072 sc->mvneta_if_flags = ifp->if_flags;
2073 if (sc->phy_attached)
2074 mii_mediachg(sc->mii);
2075 mvneta_sc_unlock(sc);
2078 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2079 mvneta_stop_locked(sc);
2081 sc->mvneta_if_flags = ifp->if_flags;
2082 mvneta_sc_unlock(sc);
2085 if (ifp->if_mtu > MVNETA_MAX_CSUM_MTU &&
2086 ifr->ifr_reqcap & IFCAP_TXCSUM)
2087 ifr->ifr_reqcap &= ~IFCAP_TXCSUM;
2088 mask = ifp->if_capenable ^ ifr->ifr_reqcap;
2089 if (mask & IFCAP_HWCSUM) {
2090 ifp->if_capenable &= ~IFCAP_HWCSUM;
2091 ifp->if_capenable |= IFCAP_HWCSUM & ifr->ifr_reqcap;
2092 if (ifp->if_capenable & IFCAP_TXCSUM)
2093 ifp->if_hwassist = CSUM_IP | CSUM_TCP |
2096 ifp->if_hwassist = 0;
2098 if (mask & IFCAP_LRO) {
2100 ifp->if_capenable ^= IFCAP_LRO;
2101 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2102 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) {
2103 rx = MVNETA_RX_RING(sc, q);
2104 rx->lro_enabled = !rx->lro_enabled;
2107 mvneta_sc_unlock(sc);
2109 VLAN_CAPABILITIES(ifp);
2112 if ((IFM_SUBTYPE(ifr->ifr_media) == IFM_1000_T ||
2113 IFM_SUBTYPE(ifr->ifr_media) == IFM_2500_T) &&
2114 (ifr->ifr_media & IFM_FDX) == 0) {
2115 device_printf(sc->dev,
2116 "%s half-duplex unsupported\n",
2117 IFM_SUBTYPE(ifr->ifr_media) == IFM_1000_T ?
2123 case SIOCGIFMEDIA: /* FALLTHROUGH */
2125 if (!sc->phy_attached)
2126 error = ifmedia_ioctl(ifp, ifr, &sc->mvneta_ifmedia,
2129 error = ifmedia_ioctl(ifp, ifr, &sc->mii->mii_media,
2133 if (ifr->ifr_mtu < 68 || ifr->ifr_mtu > MVNETA_MAX_FRAME -
2134 MVNETA_ETHER_SIZE) {
2137 ifp->if_mtu = ifr->ifr_mtu;
2139 if (ifp->if_mtu > MVNETA_MAX_CSUM_MTU) {
2140 ifp->if_capenable &= ~IFCAP_TXCSUM;
2141 ifp->if_hwassist = 0;
2143 ifp->if_capenable |= IFCAP_TXCSUM;
2144 ifp->if_hwassist = CSUM_IP | CSUM_TCP |
2148 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2149 /* Trigger reinitialize sequence */
2150 mvneta_stop_locked(sc);
2151 mvneta_init_locked(sc);
2153 mvneta_sc_unlock(sc);
2158 error = ether_ioctl(ifp, cmd, data);
2166 mvneta_init_locked(void *arg)
2168 struct mvneta_softc *sc;
2176 if (!device_is_attached(sc->dev) ||
2177 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2180 mvneta_disable_intr(sc);
2181 callout_stop(&sc->tick_ch);
2183 /* Get the latest mac address */
2184 bcopy(IF_LLADDR(ifp), sc->enaddr, ETHER_ADDR_LEN);
2185 mvneta_set_mac_address(sc, sc->enaddr);
2186 mvneta_filter_setup(sc);
2188 /* Start DMA Engine */
2189 MVNETA_WRITE(sc, MVNETA_PRXINIT, 0x00000000);
2190 MVNETA_WRITE(sc, MVNETA_PTXINIT, 0x00000000);
2191 MVNETA_WRITE(sc, MVNETA_PACC, MVNETA_PACC_ACCELERATIONMODE_EDM);
2194 reg = MVNETA_READ(sc, MVNETA_PMACC0);
2195 reg |= MVNETA_PMACC0_PORTEN;
2196 MVNETA_WRITE(sc, MVNETA_PMACC0, reg);
2198 /* Allow access to each TXQ/RXQ from both CPU's */
2199 for (cpu = 0; cpu < mp_ncpus; ++cpu)
2200 MVNETA_WRITE(sc, MVNETA_PCP2Q(cpu),
2201 MVNETA_PCP2Q_TXQEN_MASK | MVNETA_PCP2Q_RXQEN_MASK);
2203 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) {
2204 mvneta_rx_lockq(sc, q);
2205 mvneta_rx_queue_refill(sc, q);
2206 mvneta_rx_unlockq(sc, q);
2209 if (!sc->phy_attached)
2212 /* Enable interrupt */
2213 mvneta_enable_intr(sc);
2216 callout_schedule(&sc->tick_ch, hz);
2218 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2222 mvneta_init(void *arg)
2224 struct mvneta_softc *sc;
2228 mvneta_init_locked(sc);
2229 if (sc->phy_attached)
2230 mii_mediachg(sc->mii);
2231 mvneta_sc_unlock(sc);
2236 mvneta_stop_locked(struct mvneta_softc *sc)
2239 struct mvneta_rx_ring *rx;
2240 struct mvneta_tx_ring *tx;
2245 if (ifp == NULL || (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
2248 mvneta_disable_intr(sc);
2250 callout_stop(&sc->tick_ch);
2252 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2255 if (sc->linkup == TRUE)
2256 mvneta_linkdown(sc);
2258 /* Reset the MAC Port Enable bit */
2259 reg = MVNETA_READ(sc, MVNETA_PMACC0);
2260 reg &= ~MVNETA_PMACC0_PORTEN;
2261 MVNETA_WRITE(sc, MVNETA_PMACC0, reg);
2263 /* Disable each of queue */
2264 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) {
2265 rx = MVNETA_RX_RING(sc, q);
2267 mvneta_rx_lockq(sc, q);
2268 mvneta_ring_flush_rx_queue(sc, q);
2269 mvneta_rx_unlockq(sc, q);
2273 * Hold Reset state of DMA Engine
2274 * (must write 0x0 to restart it)
2276 MVNETA_WRITE(sc, MVNETA_PRXINIT, 0x00000001);
2277 MVNETA_WRITE(sc, MVNETA_PTXINIT, 0x00000001);
2279 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) {
2280 tx = MVNETA_TX_RING(sc, q);
2282 mvneta_tx_lockq(sc, q);
2283 mvneta_ring_flush_tx_queue(sc, q);
2284 mvneta_tx_unlockq(sc, q);
2289 mvneta_stop(struct mvneta_softc *sc)
2293 mvneta_stop_locked(sc);
2294 mvneta_sc_unlock(sc);
2298 mvneta_mediachange(struct ifnet *ifp)
2300 struct mvneta_softc *sc;
2304 if (!sc->phy_attached && !sc->use_inband_status) {
2305 /* We shouldn't be here */
2306 if_printf(ifp, "Cannot change media in fixed-link mode!\n");
2310 if (sc->use_inband_status) {
2311 mvneta_update_media(sc, sc->mvneta_ifmedia.ifm_media);
2318 mii_mediachg(sc->mii);
2320 mvneta_sc_unlock(sc);
2326 mvneta_get_media(struct mvneta_softc *sc, struct ifmediareq *ifmr)
2330 psr = MVNETA_READ(sc, MVNETA_PSR);
2333 if (psr & MVNETA_PSR_GMIISPEED)
2334 ifmr->ifm_active = IFM_ETHER_SUBTYPE_SET(IFM_1000_T);
2335 else if (psr & MVNETA_PSR_MIISPEED)
2336 ifmr->ifm_active = IFM_ETHER_SUBTYPE_SET(IFM_100_TX);
2337 else if (psr & MVNETA_PSR_LINKUP)
2338 ifmr->ifm_active = IFM_ETHER_SUBTYPE_SET(IFM_10_T);
2341 if (psr & MVNETA_PSR_FULLDX)
2342 ifmr->ifm_active |= IFM_FDX;
2345 ifmr->ifm_status = IFM_AVALID;
2346 if (psr & MVNETA_PSR_LINKUP)
2347 ifmr->ifm_status |= IFM_ACTIVE;
2351 mvneta_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
2353 struct mvneta_softc *sc;
2354 struct mii_data *mii;
2358 if (!sc->phy_attached && !sc->use_inband_status) {
2359 ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE;
2365 if (sc->use_inband_status) {
2366 mvneta_get_media(sc, ifmr);
2367 mvneta_sc_unlock(sc);
2374 ifmr->ifm_active = mii->mii_media_active;
2375 ifmr->ifm_status = mii->mii_media_status;
2377 mvneta_sc_unlock(sc);
2384 mvneta_update_autoneg(struct mvneta_softc *sc, int enable)
2389 reg = MVNETA_READ(sc, MVNETA_PANC);
2390 reg &= ~(MVNETA_PANC_FORCELINKFAIL | MVNETA_PANC_FORCELINKPASS |
2391 MVNETA_PANC_ANFCEN);
2392 reg |= MVNETA_PANC_ANDUPLEXEN | MVNETA_PANC_ANSPEEDEN |
2393 MVNETA_PANC_INBANDANEN;
2394 MVNETA_WRITE(sc, MVNETA_PANC, reg);
2396 reg = MVNETA_READ(sc, MVNETA_PMACC2);
2397 reg |= MVNETA_PMACC2_INBANDANMODE;
2398 MVNETA_WRITE(sc, MVNETA_PMACC2, reg);
2400 reg = MVNETA_READ(sc, MVNETA_PSOMSCD);
2401 reg |= MVNETA_PSOMSCD_ENABLE;
2402 MVNETA_WRITE(sc, MVNETA_PSOMSCD, reg);
2404 reg = MVNETA_READ(sc, MVNETA_PANC);
2405 reg &= ~(MVNETA_PANC_FORCELINKFAIL | MVNETA_PANC_FORCELINKPASS |
2406 MVNETA_PANC_ANDUPLEXEN | MVNETA_PANC_ANSPEEDEN |
2407 MVNETA_PANC_INBANDANEN);
2408 MVNETA_WRITE(sc, MVNETA_PANC, reg);
2410 reg = MVNETA_READ(sc, MVNETA_PMACC2);
2411 reg &= ~MVNETA_PMACC2_INBANDANMODE;
2412 MVNETA_WRITE(sc, MVNETA_PMACC2, reg);
2414 reg = MVNETA_READ(sc, MVNETA_PSOMSCD);
2415 reg &= ~MVNETA_PSOMSCD_ENABLE;
2416 MVNETA_WRITE(sc, MVNETA_PSOMSCD, reg);
2421 mvneta_update_media(struct mvneta_softc *sc, int media)
2430 mvneta_linkreset(sc);
2432 running = (sc->ifp->if_drv_flags & IFF_DRV_RUNNING) != 0;
2434 mvneta_stop_locked(sc);
2436 sc->autoneg = (IFM_SUBTYPE(media) == IFM_AUTO);
2438 if (sc->use_inband_status)
2439 mvneta_update_autoneg(sc, IFM_SUBTYPE(media) == IFM_AUTO);
2441 mvneta_update_eee(sc);
2442 mvneta_update_fc(sc);
2444 if (IFM_SUBTYPE(media) != IFM_AUTO) {
2445 reg = MVNETA_READ(sc, MVNETA_PANC);
2446 reg &= ~(MVNETA_PANC_SETGMIISPEED |
2447 MVNETA_PANC_SETMIISPEED |
2448 MVNETA_PANC_SETFULLDX);
2449 if (IFM_SUBTYPE(media) == IFM_1000_T ||
2450 IFM_SUBTYPE(media) == IFM_2500_T) {
2451 if ((media & IFM_FDX) == 0) {
2452 device_printf(sc->dev,
2453 "%s half-duplex unsupported\n",
2454 IFM_SUBTYPE(media) == IFM_1000_T ?
2460 reg |= MVNETA_PANC_SETGMIISPEED;
2461 } else if (IFM_SUBTYPE(media) == IFM_100_TX)
2462 reg |= MVNETA_PANC_SETMIISPEED;
2464 if (media & IFM_FDX)
2465 reg |= MVNETA_PANC_SETFULLDX;
2467 MVNETA_WRITE(sc, MVNETA_PANC, reg);
2471 mvneta_init_locked(sc);
2472 mvneta_sc_unlock(sc);
2477 mvneta_adjust_link(struct mvneta_softc *sc)
2479 boolean_t phy_linkup;
2483 mvneta_update_eee(sc);
2484 mvneta_update_fc(sc);
2486 /* Check for link change */
2487 phy_linkup = (sc->mii->mii_media_status &
2488 (IFM_AVALID | IFM_ACTIVE)) == (IFM_AVALID | IFM_ACTIVE);
2490 if (sc->linkup != phy_linkup)
2491 mvneta_linkupdate(sc, phy_linkup);
2493 /* Don't update media on disabled link */
2497 /* Check for media type change */
2498 if (sc->mvneta_media != sc->mii->mii_media_active) {
2499 sc->mvneta_media = sc->mii->mii_media_active;
2501 reg = MVNETA_READ(sc, MVNETA_PANC);
2502 reg &= ~(MVNETA_PANC_SETGMIISPEED |
2503 MVNETA_PANC_SETMIISPEED |
2504 MVNETA_PANC_SETFULLDX);
2505 if (IFM_SUBTYPE(sc->mvneta_media) == IFM_1000_T ||
2506 IFM_SUBTYPE(sc->mvneta_media) == IFM_2500_T) {
2507 reg |= MVNETA_PANC_SETGMIISPEED;
2508 } else if (IFM_SUBTYPE(sc->mvneta_media) == IFM_100_TX)
2509 reg |= MVNETA_PANC_SETMIISPEED;
2511 if (sc->mvneta_media & IFM_FDX)
2512 reg |= MVNETA_PANC_SETFULLDX;
2514 MVNETA_WRITE(sc, MVNETA_PANC, reg);
2519 mvneta_link_isr(struct mvneta_softc *sc)
2525 linkup = MVNETA_IS_LINKUP(sc) ? TRUE : FALSE;
2526 if (sc->linkup == linkup)
2532 mvneta_linkdown(sc);
2536 "%s: link %s\n", device_xname(sc->dev), linkup ? "up" : "down");
2541 mvneta_linkupdate(struct mvneta_softc *sc, boolean_t linkup)
2549 mvneta_linkdown(sc);
2553 "%s: link %s\n", device_xname(sc->dev), linkup ? "up" : "down");
2558 mvneta_update_eee(struct mvneta_softc *sc)
2564 /* set EEE parameters */
2565 reg = MVNETA_READ(sc, MVNETA_LPIC1);
2567 reg |= MVNETA_LPIC1_LPIRE;
2569 reg &= ~MVNETA_LPIC1_LPIRE;
2570 MVNETA_WRITE(sc, MVNETA_LPIC1, reg);
2574 mvneta_update_fc(struct mvneta_softc *sc)
2580 reg = MVNETA_READ(sc, MVNETA_PANC);
2582 /* Flow control negotiation */
2583 reg |= MVNETA_PANC_PAUSEADV;
2584 reg |= MVNETA_PANC_ANFCEN;
2586 /* Disable flow control negotiation */
2587 reg &= ~MVNETA_PANC_PAUSEADV;
2588 reg &= ~MVNETA_PANC_ANFCEN;
2591 MVNETA_WRITE(sc, MVNETA_PANC, reg);
2595 mvneta_linkup(struct mvneta_softc *sc)
2601 if (!sc->use_inband_status) {
2602 reg = MVNETA_READ(sc, MVNETA_PANC);
2603 reg |= MVNETA_PANC_FORCELINKPASS;
2604 reg &= ~MVNETA_PANC_FORCELINKFAIL;
2605 MVNETA_WRITE(sc, MVNETA_PANC, reg);
2608 mvneta_qflush(sc->ifp);
2611 if_link_state_change(sc->ifp, LINK_STATE_UP);
2615 mvneta_linkdown(struct mvneta_softc *sc)
2621 if (!sc->use_inband_status) {
2622 reg = MVNETA_READ(sc, MVNETA_PANC);
2623 reg &= ~MVNETA_PANC_FORCELINKPASS;
2624 reg |= MVNETA_PANC_FORCELINKFAIL;
2625 MVNETA_WRITE(sc, MVNETA_PANC, reg);
2628 mvneta_portdown(sc);
2629 mvneta_qflush(sc->ifp);
2631 if_link_state_change(sc->ifp, LINK_STATE_DOWN);
2635 mvneta_linkreset(struct mvneta_softc *sc)
2637 struct mii_softc *mii;
2639 if (sc->phy_attached) {
2640 /* Force reset PHY */
2641 mii = LIST_FIRST(&sc->mii->mii_phys);
2651 mvneta_tx_queue(struct mvneta_softc *sc, struct mbuf **mbufp, int q)
2654 bus_dma_segment_t txsegs[MVNETA_TX_SEGLIMIT];
2655 struct mbuf *mtmp, *mbuf;
2656 struct mvneta_tx_ring *tx;
2657 struct mvneta_buf *txbuf;
2658 struct mvneta_tx_desc *t;
2660 int start, used, error, i, txnsegs;
2663 tx = MVNETA_TX_RING(sc, q);
2664 DASSERT(tx->used >= 0);
2665 DASSERT(tx->used <= MVNETA_TX_RING_CNT);
2669 if (__predict_false(mbuf->m_flags & M_VLANTAG)) {
2670 mbuf = ether_vlanencap(mbuf, mbuf->m_pkthdr.ether_vtag);
2676 mbuf->m_flags &= ~M_VLANTAG;
2680 if (__predict_false(mbuf->m_next != NULL &&
2681 (mbuf->m_pkthdr.csum_flags &
2682 (CSUM_IP | CSUM_TCP | CSUM_UDP)) != 0)) {
2683 if (M_WRITABLE(mbuf) == 0) {
2684 mtmp = m_dup(mbuf, M_NOWAIT);
2691 *mbufp = mbuf = mtmp;
2695 /* load mbuf using dmamap of 1st descriptor */
2696 txbuf = &tx->txbuf[tx->cpu];
2697 error = bus_dmamap_load_mbuf_sg(sc->txmbuf_dtag,
2698 txbuf->dmap, mbuf, txsegs, &txnsegs,
2700 if (__predict_false(error != 0)) {
2702 CTR3(KTR_SPARE2, "%s:%u bus_dmamap_load_mbuf_sg error=%d", ifp->if_xname, q, error);
2704 /* This is the only recoverable error (except EFBIG). */
2705 if (error != ENOMEM) {
2714 if (__predict_false(txnsegs <= 0
2715 || (txnsegs + tx->used) > MVNETA_TX_RING_CNT)) {
2716 /* we have no enough descriptors or mbuf is broken */
2718 CTR3(KTR_SPARE2, "%s:%u not enough descriptors txnsegs=%d",
2719 ifp->if_xname, q, txnsegs);
2721 bus_dmamap_unload(sc->txmbuf_dtag, txbuf->dmap);
2724 DASSERT(txbuf->m == NULL);
2726 /* remember mbuf using 1st descriptor */
2728 bus_dmamap_sync(sc->txmbuf_dtag, txbuf->dmap,
2729 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
2731 /* load to tx descriptors */
2734 for (i = 0; i < txnsegs; i++) {
2735 t = &tx->desc[tx->cpu];
2739 if (__predict_true(i == 0)) {
2740 /* 1st descriptor */
2741 t->command |= MVNETA_TX_CMD_W_PACKET_OFFSET(0);
2742 t->command |= MVNETA_TX_CMD_F;
2743 mvneta_tx_set_csumflag(ifp, t, mbuf);
2745 t->bufptr_pa = txsegs[i].ds_addr;
2746 t->bytecnt = txsegs[i].ds_len;
2747 tx->cpu = tx_counter_adv(tx->cpu, 1);
2752 /* t is last descriptor here */
2754 t->command |= MVNETA_TX_CMD_L|MVNETA_TX_CMD_PADDING;
2756 bus_dmamap_sync(sc->tx_dtag, tx->desc_map,
2757 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
2759 while (__predict_false(used > 255)) {
2760 ptxsu = MVNETA_PTXSU_NOWD(255);
2761 MVNETA_WRITE(sc, MVNETA_PTXSU(q), ptxsu);
2764 if (__predict_true(used > 0)) {
2765 ptxsu = MVNETA_PTXSU_NOWD(used);
2766 MVNETA_WRITE(sc, MVNETA_PTXSU(q), ptxsu);
2772 mvneta_tx_set_csumflag(struct ifnet *ifp,
2773 struct mvneta_tx_desc *t, struct mbuf *m)
2775 struct ether_header *eh;
2777 uint32_t iphl, ipoff;
2781 csum_flags = ifp->if_hwassist & m->m_pkthdr.csum_flags;
2782 eh = mtod(m, struct ether_header *);
2783 switch (ntohs(eh->ether_type)) {
2785 ipoff = ETHER_HDR_LEN;
2787 case ETHERTYPE_IPV6:
2789 case ETHERTYPE_VLAN:
2790 ipoff = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
2794 if (__predict_true(csum_flags & (CSUM_IP|CSUM_IP_TCP|CSUM_IP_UDP))) {
2795 ip = (struct ip *)(m->m_data + ipoff);
2796 iphl = ip->ip_hl<<2;
2797 t->command |= MVNETA_TX_CMD_L3_IP4;
2799 t->command |= MVNETA_TX_CMD_L4_CHECKSUM_NONE;
2805 if (csum_flags & CSUM_IP) {
2806 t->command |= MVNETA_TX_CMD_IP4_CHECKSUM;
2810 if (csum_flags & CSUM_IP_TCP) {
2811 t->command |= MVNETA_TX_CMD_L4_CHECKSUM_NOFRAG;
2812 t->command |= MVNETA_TX_CMD_L4_TCP;
2813 } else if (csum_flags & CSUM_IP_UDP) {
2814 t->command |= MVNETA_TX_CMD_L4_CHECKSUM_NOFRAG;
2815 t->command |= MVNETA_TX_CMD_L4_UDP;
2817 t->command |= MVNETA_TX_CMD_L4_CHECKSUM_NONE;
2820 t->command |= MVNETA_TX_CMD_IP_HEADER_LEN(iphl >> 2);
2821 t->command |= MVNETA_TX_CMD_L3_OFFSET(ipoff);
2825 mvneta_tx_queue_complete(struct mvneta_softc *sc, int q)
2827 struct mvneta_tx_ring *tx;
2828 struct mvneta_buf *txbuf;
2829 struct mvneta_tx_desc *t;
2830 uint32_t ptxs, ptxsu, ndesc;
2833 KASSERT_TX_MTX(sc, q);
2835 tx = MVNETA_TX_RING(sc, q);
2836 if (__predict_false(tx->queue_status == MVNETA_QUEUE_DISABLED))
2839 ptxs = MVNETA_READ(sc, MVNETA_PTXS(q));
2840 ndesc = MVNETA_PTXS_GET_TBC(ptxs);
2842 if (__predict_false(ndesc == 0)) {
2844 tx->queue_status = MVNETA_QUEUE_IDLE;
2845 else if (tx->queue_status == MVNETA_QUEUE_WORKING &&
2846 ((ticks - tx->watchdog_time) > MVNETA_WATCHDOG))
2847 tx->queue_hung = TRUE;
2852 CTR3(KTR_SPARE2, "%s:%u tx_complete begin ndesc=%u",
2853 sc->ifp->if_xname, q, ndesc);
2856 bus_dmamap_sync(sc->tx_dtag, tx->desc_map,
2857 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
2859 for (i = 0; i < ndesc; i++) {
2860 t = &tx->desc[tx->dma];
2862 if (t->flags & MVNETA_TX_F_ES)
2863 CTR3(KTR_SPARE2, "%s tx error queue %d desc %d",
2864 sc->ifp->if_xname, q, tx->dma);
2866 txbuf = &tx->txbuf[tx->dma];
2867 if (__predict_true(txbuf->m != NULL)) {
2868 DASSERT((t->command & MVNETA_TX_CMD_F) != 0);
2869 bus_dmamap_unload(sc->txmbuf_dtag, txbuf->dmap);
2874 DASSERT((t->flags & MVNETA_TX_CMD_F) == 0);
2875 tx->dma = tx_counter_adv(tx->dma, 1);
2878 DASSERT(tx->used >= 0);
2879 DASSERT(tx->used <= MVNETA_TX_RING_CNT);
2880 while (__predict_false(ndesc > 255)) {
2881 ptxsu = MVNETA_PTXSU_NORB(255);
2882 MVNETA_WRITE(sc, MVNETA_PTXSU(q), ptxsu);
2885 if (__predict_true(ndesc > 0)) {
2886 ptxsu = MVNETA_PTXSU_NORB(ndesc);
2887 MVNETA_WRITE(sc, MVNETA_PTXSU(q), ptxsu);
2890 CTR5(KTR_SPARE2, "%s:%u tx_complete tx_cpu=%d tx_dma=%d tx_used=%d",
2891 sc->ifp->if_xname, q, tx->cpu, tx->dma, tx->used);
2894 tx->watchdog_time = ticks;
2897 tx->queue_status = MVNETA_QUEUE_IDLE;
2901 * Do a final TX complete when TX is idle.
2904 mvneta_tx_drain(struct mvneta_softc *sc)
2906 struct mvneta_tx_ring *tx;
2910 * Handle trailing mbuf on TX queue.
2911 * Check is done lockess to avoid TX path contention.
2913 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) {
2914 tx = MVNETA_TX_RING(sc, q);
2915 if ((ticks - tx->watchdog_time) > MVNETA_WATCHDOG_TXCOMP &&
2917 mvneta_tx_lockq(sc, q);
2918 mvneta_tx_queue_complete(sc, q);
2919 mvneta_tx_unlockq(sc, q);
2928 mvneta_rx(struct mvneta_softc *sc, int q, int count)
2930 uint32_t prxs, npkt;
2934 mvneta_rx_lockq(sc, q);
2935 prxs = MVNETA_READ(sc, MVNETA_PRXS(q));
2936 npkt = MVNETA_PRXS_GET_ODC(prxs);
2937 if (__predict_false(npkt == 0))
2940 if (count > 0 && npkt > count) {
2944 mvneta_rx_queue(sc, q, npkt);
2946 mvneta_rx_unlockq(sc, q);
2951 * Helper routine for updating PRXSU register of a given queue.
2952 * Handles number of processed descriptors bigger than maximum acceptable value.
2954 STATIC __inline void
2955 mvneta_prxsu_update(struct mvneta_softc *sc, int q, int processed)
2959 while (__predict_false(processed > 255)) {
2960 prxsu = MVNETA_PRXSU_NOOFPROCESSEDDESCRIPTORS(255);
2961 MVNETA_WRITE(sc, MVNETA_PRXSU(q), prxsu);
2964 prxsu = MVNETA_PRXSU_NOOFPROCESSEDDESCRIPTORS(processed);
2965 MVNETA_WRITE(sc, MVNETA_PRXSU(q), prxsu);
2968 static __inline void
2969 mvneta_prefetch(void *p)
2972 __builtin_prefetch(p);
2976 mvneta_rx_queue(struct mvneta_softc *sc, int q, int npkt)
2979 struct mvneta_rx_ring *rx;
2980 struct mvneta_rx_desc *r;
2981 struct mvneta_buf *rxbuf;
2983 struct lro_ctrl *lro;
2984 struct lro_entry *queued;
2986 int i, pktlen, processed, ndma;
2988 KASSERT_RX_MTX(sc, q);
2991 rx = MVNETA_RX_RING(sc, q);
2994 if (__predict_false(rx->queue_status == MVNETA_QUEUE_DISABLED))
2997 bus_dmamap_sync(sc->rx_dtag, rx->desc_map,
2998 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
3000 for (i = 0; i < npkt; i++) {
3001 /* Prefetch next desc, rxbuf. */
3002 ndma = rx_counter_adv(rx->dma, 1);
3003 mvneta_prefetch(&rx->desc[ndma]);
3004 mvneta_prefetch(&rx->rxbuf[ndma]);
3006 /* get descriptor and packet */
3007 r = &rx->desc[rx->dma];
3008 rxbuf = &rx->rxbuf[rx->dma];
3012 bus_dmamap_sync(sc->rxbuf_dtag, rxbuf->dmap,
3013 BUS_DMASYNC_POSTREAD);
3014 bus_dmamap_unload(sc->rxbuf_dtag, rxbuf->dmap);
3015 /* Prefetch mbuf header. */
3019 /* Drop desc with error status or not in a single buffer. */
3020 DASSERT((r->status & (MVNETA_RX_F|MVNETA_RX_L)) ==
3021 (MVNETA_RX_F|MVNETA_RX_L));
3022 if (__predict_false((r->status & MVNETA_RX_ES) ||
3023 (r->status & (MVNETA_RX_F|MVNETA_RX_L)) !=
3024 (MVNETA_RX_F|MVNETA_RX_L)))
3028 * [ OFF | MH | PKT | CRC ]
3029 * bytecnt cover MH, PKT, CRC
3031 pktlen = r->bytecnt - ETHER_CRC_LEN - MVNETA_HWHEADER_SIZE;
3032 pktbuf = (uint8_t *)rx->rxbuf_virt_addr[rx->dma] + MVNETA_PACKET_OFFSET +
3033 MVNETA_HWHEADER_SIZE;
3035 /* Prefetch mbuf data. */
3036 mvneta_prefetch(pktbuf);
3038 /* Write value to mbuf (avoid read). */
3040 m->m_len = m->m_pkthdr.len = pktlen;
3041 m->m_pkthdr.rcvif = ifp;
3042 mvneta_rx_set_csumflag(ifp, r, m);
3044 /* Increase rx_dma before releasing the lock. */
3047 if (__predict_false(rx->lro_enabled &&
3048 ((r->status & MVNETA_RX_L3_IP) != 0) &&
3049 ((r->status & MVNETA_RX_L4_MASK) == MVNETA_RX_L4_TCP) &&
3050 (m->m_pkthdr.csum_flags &
3051 (CSUM_DATA_VALID | CSUM_PSEUDO_HDR)) ==
3052 (CSUM_DATA_VALID | CSUM_PSEUDO_HDR))) {
3053 if (rx->lro.lro_cnt != 0) {
3054 if (tcp_lro_rx(&rx->lro, m, 0) == 0)
3059 mvneta_rx_unlockq(sc, q);
3060 (*ifp->if_input)(ifp, m);
3061 mvneta_rx_lockq(sc, q);
3063 * Check whether this queue has been disabled in the
3064 * meantime. If yes, then clear LRO and exit.
3066 if(__predict_false(rx->queue_status == MVNETA_QUEUE_DISABLED))
3069 /* Refresh receive ring to avoid stall and minimize jitter. */
3070 if (processed >= MVNETA_RX_REFILL_COUNT) {
3071 mvneta_prxsu_update(sc, q, processed);
3072 mvneta_rx_queue_refill(sc, q);
3079 /* Refresh receive ring to avoid stall and minimize jitter. */
3080 if (processed >= MVNETA_RX_REFILL_COUNT) {
3081 mvneta_prxsu_update(sc, q, processed);
3082 mvneta_rx_queue_refill(sc, q);
3087 CTR3(KTR_SPARE2, "%s:%u %u packets received", ifp->if_xname, q, npkt);
3089 /* DMA status update */
3090 mvneta_prxsu_update(sc, q, processed);
3091 /* Refill the rest of buffers if there are any to refill */
3092 mvneta_rx_queue_refill(sc, q);
3096 * Flush any outstanding LRO work
3099 while (__predict_false((queued = LIST_FIRST(&lro->lro_active)) != NULL)) {
3100 LIST_REMOVE(LIST_FIRST((&lro->lro_active)), next);
3101 tcp_lro_flush(lro, queued);
3106 mvneta_rx_buf_free(struct mvneta_softc *sc, struct mvneta_buf *rxbuf)
3109 bus_dmamap_unload(sc->rxbuf_dtag, rxbuf->dmap);
3110 /* This will remove all data at once */
3115 mvneta_rx_queue_refill(struct mvneta_softc *sc, int q)
3117 struct mvneta_rx_ring *rx;
3118 struct mvneta_rx_desc *r;
3119 struct mvneta_buf *rxbuf;
3120 bus_dma_segment_t segs;
3122 uint32_t prxs, prxsu, ndesc;
3123 int npkt, refill, nsegs, error;
3125 KASSERT_RX_MTX(sc, q);
3127 rx = MVNETA_RX_RING(sc, q);
3128 prxs = MVNETA_READ(sc, MVNETA_PRXS(q));
3129 ndesc = MVNETA_PRXS_GET_NODC(prxs) + MVNETA_PRXS_GET_ODC(prxs);
3130 refill = MVNETA_RX_RING_CNT - ndesc;
3132 CTR3(KTR_SPARE2, "%s:%u refill %u packets", sc->ifp->if_xname, q,
3135 if (__predict_false(refill <= 0))
3138 for (npkt = 0; npkt < refill; npkt++) {
3139 rxbuf = &rx->rxbuf[rx->cpu];
3140 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
3141 if (__predict_false(m == NULL)) {
3145 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size;
3147 error = bus_dmamap_load_mbuf_sg(sc->rxbuf_dtag, rxbuf->dmap,
3148 m, &segs, &nsegs, BUS_DMA_NOWAIT);
3149 if (__predict_false(error != 0 || nsegs != 1)) {
3150 KASSERT(1, ("Failed to load Rx mbuf DMA map"));
3155 /* Add the packet to the ring */
3157 r = &rx->desc[rx->cpu];
3158 r->bufptr_pa = segs.ds_addr;
3159 rx->rxbuf_virt_addr[rx->cpu] = m->m_data;
3161 rx->cpu = rx_counter_adv(rx->cpu, 1);
3164 if (refill == MVNETA_RX_RING_CNT)
3165 rx->needs_refill = TRUE;
3169 rx->needs_refill = FALSE;
3170 bus_dmamap_sync(sc->rx_dtag, rx->desc_map, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
3172 while (__predict_false(npkt > 255)) {
3173 prxsu = MVNETA_PRXSU_NOOFNEWDESCRIPTORS(255);
3174 MVNETA_WRITE(sc, MVNETA_PRXSU(q), prxsu);
3177 if (__predict_true(npkt > 0)) {
3178 prxsu = MVNETA_PRXSU_NOOFNEWDESCRIPTORS(npkt);
3179 MVNETA_WRITE(sc, MVNETA_PRXSU(q), prxsu);
3183 STATIC __inline void
3184 mvneta_rx_set_csumflag(struct ifnet *ifp,
3185 struct mvneta_rx_desc *r, struct mbuf *m)
3187 uint32_t csum_flags;
3190 if (__predict_false((r->status &
3191 (MVNETA_RX_IP_HEADER_OK|MVNETA_RX_L3_IP)) == 0))
3192 return; /* not a IP packet */
3195 if (__predict_true((r->status & MVNETA_RX_IP_HEADER_OK) ==
3196 MVNETA_RX_IP_HEADER_OK))
3197 csum_flags |= CSUM_L3_CALC|CSUM_L3_VALID;
3199 if (__predict_true((r->status & (MVNETA_RX_IP_HEADER_OK|MVNETA_RX_L3_IP)) ==
3200 (MVNETA_RX_IP_HEADER_OK|MVNETA_RX_L3_IP))) {
3202 switch (r->status & MVNETA_RX_L4_MASK) {
3203 case MVNETA_RX_L4_TCP:
3204 case MVNETA_RX_L4_UDP:
3205 csum_flags |= CSUM_L4_CALC;
3206 if (__predict_true((r->status &
3207 MVNETA_RX_L4_CHECKSUM_OK) == MVNETA_RX_L4_CHECKSUM_OK)) {
3208 csum_flags |= CSUM_L4_VALID;
3209 m->m_pkthdr.csum_data = htons(0xffff);
3212 case MVNETA_RX_L4_OTH:
3217 m->m_pkthdr.csum_flags = csum_flags;
3221 * MAC address filter
3224 mvneta_filter_setup(struct mvneta_softc *sc)
3227 uint32_t dfut[MVNETA_NDFUT], dfsmt[MVNETA_NDFSMT], dfomt[MVNETA_NDFOMT];
3233 memset(dfut, 0, sizeof(dfut));
3234 memset(dfsmt, 0, sizeof(dfsmt));
3235 memset(dfomt, 0, sizeof(dfomt));
3238 ifp->if_flags |= IFF_ALLMULTI;
3239 if (ifp->if_flags & (IFF_ALLMULTI|IFF_PROMISC)) {
3240 for (i = 0; i < MVNETA_NDFSMT; i++) {
3241 dfsmt[i] = dfomt[i] =
3242 MVNETA_DF(0, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) |
3243 MVNETA_DF(1, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) |
3244 MVNETA_DF(2, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) |
3245 MVNETA_DF(3, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS);
3249 pxc = MVNETA_READ(sc, MVNETA_PXC);
3250 pxc &= ~(MVNETA_PXC_UPM | MVNETA_PXC_RXQ_MASK | MVNETA_PXC_RXQARP_MASK |
3251 MVNETA_PXC_TCPQ_MASK | MVNETA_PXC_UDPQ_MASK | MVNETA_PXC_BPDUQ_MASK);
3252 pxc |= MVNETA_PXC_RXQ(MVNETA_RX_QNUM_MAX-1);
3253 pxc |= MVNETA_PXC_RXQARP(MVNETA_RX_QNUM_MAX-1);
3254 pxc |= MVNETA_PXC_TCPQ(MVNETA_RX_QNUM_MAX-1);
3255 pxc |= MVNETA_PXC_UDPQ(MVNETA_RX_QNUM_MAX-1);
3256 pxc |= MVNETA_PXC_BPDUQ(MVNETA_RX_QNUM_MAX-1);
3257 pxc |= MVNETA_PXC_RB | MVNETA_PXC_RBIP | MVNETA_PXC_RBARP;
3258 if (ifp->if_flags & IFF_BROADCAST) {
3259 pxc &= ~(MVNETA_PXC_RB | MVNETA_PXC_RBIP | MVNETA_PXC_RBARP);
3261 if (ifp->if_flags & IFF_PROMISC) {
3262 pxc |= MVNETA_PXC_UPM;
3264 MVNETA_WRITE(sc, MVNETA_PXC, pxc);
3266 /* Set Destination Address Filter Unicast Table */
3267 if (ifp->if_flags & IFF_PROMISC) {
3268 /* pass all unicast addresses */
3269 for (i = 0; i < MVNETA_NDFUT; i++) {
3271 MVNETA_DF(0, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) |
3272 MVNETA_DF(1, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) |
3273 MVNETA_DF(2, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) |
3274 MVNETA_DF(3, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS);
3277 i = sc->enaddr[5] & 0xf; /* last nibble */
3278 dfut[i>>2] = MVNETA_DF(i&3, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS);
3280 MVNETA_WRITE_REGION(sc, MVNETA_DFUT(0), dfut, MVNETA_NDFUT);
3282 /* Set Destination Address Filter Multicast Tables */
3283 MVNETA_WRITE_REGION(sc, MVNETA_DFSMT(0), dfsmt, MVNETA_NDFSMT);
3284 MVNETA_WRITE_REGION(sc, MVNETA_DFOMT(0), dfomt, MVNETA_NDFOMT);
3291 sysctl_read_mib(SYSCTL_HANDLER_ARGS)
3293 struct mvneta_sysctl_mib *arg;
3294 struct mvneta_softc *sc;
3297 arg = (struct mvneta_sysctl_mib *)arg1;
3304 if (arg->index < 0 || arg->index > MVNETA_PORTMIB_NOCOUNTER)
3309 mvneta_sc_unlock(sc);
3310 return sysctl_handle_64(oidp, &val, 0, req);
3315 sysctl_clear_mib(SYSCTL_HANDLER_ARGS)
3317 struct mvneta_softc *sc;
3321 sc = (struct mvneta_softc *)arg1;
3325 err = sysctl_handle_int(oidp, &val, 0, req);
3329 if (val < 0 || val > 1)
3334 mvneta_clear_mib(sc);
3335 mvneta_sc_unlock(sc);
3342 sysctl_set_queue_rxthtime(SYSCTL_HANDLER_ARGS)
3344 struct mvneta_sysctl_queue *arg;
3345 struct mvneta_rx_ring *rx;
3346 struct mvneta_softc *sc;
3347 uint32_t reg, time_mvtclk;
3351 arg = (struct mvneta_sysctl_queue *)arg1;
3354 if (arg->queue < 0 || arg->queue > MVNETA_RX_RING_CNT)
3356 if (arg->rxtx != MVNETA_SYSCTL_RX)
3363 /* read queue length */
3365 mvneta_rx_lockq(sc, arg->queue);
3366 rx = MVNETA_RX_RING(sc, arg->queue);
3367 time_mvtclk = rx->queue_th_time;
3368 time_us = ((uint64_t)time_mvtclk * 1000ULL * 1000ULL) / mvneta_get_clk();
3369 mvneta_rx_unlockq(sc, arg->queue);
3370 mvneta_sc_unlock(sc);
3372 err = sysctl_handle_int(oidp, &time_us, 0, req);
3377 mvneta_rx_lockq(sc, arg->queue);
3379 /* update queue length (0[sec] - 1[sec]) */
3380 if (time_us < 0 || time_us > (1000 * 1000)) {
3381 mvneta_rx_unlockq(sc, arg->queue);
3382 mvneta_sc_unlock(sc);
3386 (uint64_t)mvneta_get_clk() * (uint64_t)time_us / (1000ULL * 1000ULL);
3387 rx->queue_th_time = time_mvtclk;
3388 reg = MVNETA_PRXITTH_RITT(rx->queue_th_time);
3389 MVNETA_WRITE(sc, MVNETA_PRXITTH(arg->queue), reg);
3390 mvneta_rx_unlockq(sc, arg->queue);
3391 mvneta_sc_unlock(sc);
3397 sysctl_mvneta_init(struct mvneta_softc *sc)
3399 struct sysctl_ctx_list *ctx;
3400 struct sysctl_oid_list *children;
3401 struct sysctl_oid_list *rxchildren;
3402 struct sysctl_oid_list *qchildren, *mchildren;
3403 struct sysctl_oid *tree;
3405 struct mvneta_sysctl_queue *rxarg;
3406 #define MVNETA_SYSCTL_NAME(num) "queue" # num
3407 static const char *sysctl_queue_names[] = {
3408 MVNETA_SYSCTL_NAME(0), MVNETA_SYSCTL_NAME(1),
3409 MVNETA_SYSCTL_NAME(2), MVNETA_SYSCTL_NAME(3),
3410 MVNETA_SYSCTL_NAME(4), MVNETA_SYSCTL_NAME(5),
3411 MVNETA_SYSCTL_NAME(6), MVNETA_SYSCTL_NAME(7),
3413 #undef MVNETA_SYSCTL_NAME
3415 #ifndef NO_SYSCTL_DESCR
3416 #define MVNETA_SYSCTL_DESCR(num) "configuration parameters for queue " # num
3417 static const char *sysctl_queue_descrs[] = {
3418 MVNETA_SYSCTL_DESCR(0), MVNETA_SYSCTL_DESCR(1),
3419 MVNETA_SYSCTL_DESCR(2), MVNETA_SYSCTL_DESCR(3),
3420 MVNETA_SYSCTL_DESCR(4), MVNETA_SYSCTL_DESCR(5),
3421 MVNETA_SYSCTL_DESCR(6), MVNETA_SYSCTL_DESCR(7),
3423 #undef MVNETA_SYSCTL_DESCR
3427 ctx = device_get_sysctl_ctx(sc->dev);
3428 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev));
3430 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "rx",
3431 CTLFLAG_RD, 0, "NETA RX");
3432 rxchildren = SYSCTL_CHILDREN(tree);
3433 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "mib",
3434 CTLFLAG_RD, 0, "NETA MIB");
3435 mchildren = SYSCTL_CHILDREN(tree);
3438 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "flow_control",
3439 CTLFLAG_RW, &sc->cf_fc, 0, "flow control");
3440 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lpi",
3441 CTLFLAG_RW, &sc->cf_lpi, 0, "Low Power Idle");
3446 /* dev.mvneta.[unit].mib.<mibs> */
3447 for (i = 0; i < MVNETA_PORTMIB_NOCOUNTER; i++) {
3448 struct mvneta_sysctl_mib *mib_arg = &sc->sysctl_mib[i];
3452 SYSCTL_ADD_PROC(ctx, mchildren, OID_AUTO,
3453 mvneta_mib_list[i].sysctl_name,
3454 CTLTYPE_U64|CTLFLAG_RD, (void *)mib_arg, 0,
3455 sysctl_read_mib, "I", mvneta_mib_list[i].desc);
3457 SYSCTL_ADD_UQUAD(ctx, mchildren, OID_AUTO, "rx_discard",
3458 CTLFLAG_RD, &sc->counter_pdfc, "Port Rx Discard Frame Counter");
3459 SYSCTL_ADD_UQUAD(ctx, mchildren, OID_AUTO, "overrun",
3460 CTLFLAG_RD, &sc->counter_pofc, "Port Overrun Frame Counter");
3461 SYSCTL_ADD_UINT(ctx, mchildren, OID_AUTO, "watchdog",
3462 CTLFLAG_RD, &sc->counter_watchdog, 0, "TX Watchdog Counter");
3464 SYSCTL_ADD_PROC(ctx, mchildren, OID_AUTO, "reset",
3465 CTLTYPE_INT|CTLFLAG_RW, (void *)sc, 0,
3466 sysctl_clear_mib, "I", "Reset MIB counters");
3468 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) {
3469 rxarg = &sc->sysctl_rx_queue[q];
3473 rxarg->rxtx = MVNETA_SYSCTL_RX;
3475 /* hw.mvneta.mvneta[unit].rx.[queue] */
3476 tree = SYSCTL_ADD_NODE(ctx, rxchildren, OID_AUTO,
3477 sysctl_queue_names[q], CTLFLAG_RD, 0,
3478 sysctl_queue_descrs[q]);
3479 qchildren = SYSCTL_CHILDREN(tree);
3481 /* hw.mvneta.mvneta[unit].rx.[queue].threshold_timer_us */
3482 SYSCTL_ADD_PROC(ctx, qchildren, OID_AUTO, "threshold_timer_us",
3483 CTLTYPE_UINT | CTLFLAG_RW, rxarg, 0,
3484 sysctl_set_queue_rxthtime, "I",
3485 "interrupt coalescing threshold timer [us]");
3493 mvneta_clear_mib(struct mvneta_softc *sc)
3499 for (i = 0; i < nitems(mvneta_mib_list); i++) {
3500 if (mvneta_mib_list[i].reg64)
3501 MVNETA_READ_MIB_8(sc, mvneta_mib_list[i].regnum);
3503 MVNETA_READ_MIB_4(sc, mvneta_mib_list[i].regnum);
3504 sc->sysctl_mib[i].counter = 0;
3506 MVNETA_READ(sc, MVNETA_PDFC);
3507 sc->counter_pdfc = 0;
3508 MVNETA_READ(sc, MVNETA_POFC);
3509 sc->counter_pofc = 0;
3510 sc->counter_watchdog = 0;
3514 mvneta_update_mib(struct mvneta_softc *sc)
3516 struct mvneta_tx_ring *tx;
3521 for (i = 0; i < nitems(mvneta_mib_list); i++) {
3523 if (mvneta_mib_list[i].reg64)
3524 val = MVNETA_READ_MIB_8(sc, mvneta_mib_list[i].regnum);
3526 val = MVNETA_READ_MIB_4(sc, mvneta_mib_list[i].regnum);
3531 sc->sysctl_mib[i].counter += val;
3532 switch (mvneta_mib_list[i].regnum) {
3533 case MVNETA_MIB_RX_GOOD_OCT:
3534 if_inc_counter(sc->ifp, IFCOUNTER_IBYTES, val);
3536 case MVNETA_MIB_RX_BAD_FRAME:
3537 if_inc_counter(sc->ifp, IFCOUNTER_IERRORS, val);
3539 case MVNETA_MIB_RX_GOOD_FRAME:
3540 if_inc_counter(sc->ifp, IFCOUNTER_IPACKETS, val);
3542 case MVNETA_MIB_RX_MCAST_FRAME:
3543 if_inc_counter(sc->ifp, IFCOUNTER_IMCASTS, val);
3545 case MVNETA_MIB_TX_GOOD_OCT:
3546 if_inc_counter(sc->ifp, IFCOUNTER_OBYTES, val);
3548 case MVNETA_MIB_TX_GOOD_FRAME:
3549 if_inc_counter(sc->ifp, IFCOUNTER_OPACKETS, val);
3551 case MVNETA_MIB_TX_MCAST_FRAME:
3552 if_inc_counter(sc->ifp, IFCOUNTER_OMCASTS, val);
3554 case MVNETA_MIB_MAC_COL:
3555 if_inc_counter(sc->ifp, IFCOUNTER_COLLISIONS, val);
3557 case MVNETA_MIB_TX_MAC_TRNS_ERR:
3558 case MVNETA_MIB_TX_EXCES_COL:
3559 case MVNETA_MIB_MAC_LATE_COL:
3560 if_inc_counter(sc->ifp, IFCOUNTER_OERRORS, val);
3565 reg = MVNETA_READ(sc, MVNETA_PDFC);
3566 sc->counter_pdfc += reg;
3567 if_inc_counter(sc->ifp, IFCOUNTER_IQDROPS, reg);
3568 reg = MVNETA_READ(sc, MVNETA_POFC);
3569 sc->counter_pofc += reg;
3570 if_inc_counter(sc->ifp, IFCOUNTER_IQDROPS, reg);
3573 if (sc->counter_watchdog_mib > 0) {
3574 if_inc_counter(sc->ifp, IFCOUNTER_OERRORS, sc->counter_watchdog_mib);
3575 sc->counter_watchdog_mib = 0;
3579 * We do not take queue locks to not disrupt TX path.
3580 * We may only miss one drv error which will be fixed at
3581 * next mib update. We may also clear counter when TX path
3582 * is incrementing it but we only do it if counter was not zero
3583 * thus we may only loose one error.
3585 for (i = 0; i < MVNETA_TX_QNUM_MAX; i++) {
3586 tx = MVNETA_TX_RING(sc, i);
3588 if (tx->drv_error > 0) {
3589 if_inc_counter(sc->ifp, IFCOUNTER_OERRORS, tx->drv_error);