1 /* $OpenBSD: if_nfereg.h,v 1.16 2006/02/22 19:23:44 damien Exp $ */
4 * Copyright (c) 2005 Jonathan Gray <jsg@openbsd.org>
6 * Permission to use, copy, modify, and distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 #define NFE_PCI_BA 0x10
23 #define NFE_RX_RING_COUNT 128
24 #define NFE_TX_RING_COUNT 256
26 #define NFE_JBYTES (ETHER_MAX_LEN_JUMBO + ETHER_ALIGN)
27 #define NFE_JPOOL_COUNT (NFE_RX_RING_COUNT + 64)
28 #define NFE_JPOOL_SIZE (NFE_JPOOL_COUNT * NFE_JBYTES)
30 #define NFE_MAX_SCATTER (NFE_TX_RING_COUNT - 2)
32 #define NFE_IRQ_STATUS 0x000
33 #define NFE_IRQ_MASK 0x004
34 #define NFE_SETUP_R6 0x008
35 #define NFE_IMTIMER 0x00c
36 #define NFE_MISC1 0x080
37 #define NFE_TX_CTL 0x084
38 #define NFE_TX_STATUS 0x088
39 #define NFE_RXFILTER 0x08c
40 #define NFE_RXBUFSZ 0x090
41 #define NFE_RX_CTL 0x094
42 #define NFE_RX_STATUS 0x098
43 #define NFE_RNDSEED 0x09c
44 #define NFE_SETUP_R1 0x0a0
45 #define NFE_SETUP_R2 0x0a4
46 #define NFE_MACADDR_HI 0x0a8
47 #define NFE_MACADDR_LO 0x0ac
48 #define NFE_MULTIADDR_HI 0x0b0
49 #define NFE_MULTIADDR_LO 0x0b4
50 #define NFE_MULTIMASK_HI 0x0b8
51 #define NFE_MULTIMASK_LO 0x0bc
52 #define NFE_PHY_IFACE 0x0c0
53 #define NFE_TX_RING_ADDR_LO 0x100
54 #define NFE_RX_RING_ADDR_LO 0x104
55 #define NFE_RING_SIZE 0x108
56 #define NFE_TX_UNK 0x10c
57 #define NFE_LINKSPEED 0x110
58 #define NFE_SETUP_R5 0x130
59 #define NFE_SETUP_R3 0x13C
60 #define NFE_SETUP_R7 0x140
61 #define NFE_RXTX_CTL 0x144
62 #define NFE_TX_RING_ADDR_HI 0x148
63 #define NFE_RX_RING_ADDR_HI 0x14c
64 #define NFE_PHY_STATUS 0x180
65 #define NFE_SETUP_R4 0x184
66 #define NFE_STATUS 0x188
67 #define NFE_PHY_SPEED 0x18c
68 #define NFE_PHY_CTL 0x190
69 #define NFE_PHY_DATA 0x194
70 #define NFE_WOL_CTL 0x200
71 #define NFE_PATTERN_CRC 0x204
72 #define NFE_PATTERN_MASK 0x208
73 #define NFE_PWR_CAP 0x268
74 #define NFE_PWR_STATE 0x26c
75 #define NFE_VTAG_CTL 0x300
77 #define NFE_PHY_ERROR 0x00001
78 #define NFE_PHY_WRITE 0x00400
79 #define NFE_PHY_BUSY 0x08000
80 #define NFE_PHYADD_SHIFT 5
82 #define NFE_STATUS_MAGIC 0x140000
84 #define NFE_R1_MAGIC 0x16070f
85 #define NFE_R2_MAGIC 0x16
86 #define NFE_R4_MAGIC 0x08
87 #define NFE_R6_MAGIC 0x03
88 #define NFE_WOL_MAGIC 0x7770
89 #define NFE_RX_START 0x01
90 #define NFE_TX_START 0x01
92 #define NFE_IRQ_RXERR 0x0001
93 #define NFE_IRQ_RX 0x0002
94 #define NFE_IRQ_RX_NOBUF 0x0004
95 #define NFE_IRQ_TXERR 0x0008
96 #define NFE_IRQ_TX_DONE 0x0010
97 #define NFE_IRQ_TIMER 0x0020
98 #define NFE_IRQ_LINK 0x0040
99 #define NFE_IRQ_TXERR2 0x0080
100 #define NFE_IRQ_TX1 0x0100
102 #define NFE_IRQ_WANTED \
103 (NFE_IRQ_RXERR | NFE_IRQ_RX_NOBUF | NFE_IRQ_RX | \
104 NFE_IRQ_TXERR | NFE_IRQ_TXERR2 | NFE_IRQ_TX_DONE | \
107 #define NFE_RXTX_KICKTX 0x0001
108 #define NFE_RXTX_BIT1 0x0002
109 #define NFE_RXTX_BIT2 0x0004
110 #define NFE_RXTX_RESET 0x0010
111 #define NFE_RXTX_VTAG_STRIP 0x0040
112 #define NFE_RXTX_VTAG_INSERT 0x0080
113 #define NFE_RXTX_RXCSUM 0x0400
114 #define NFE_RXTX_V2MAGIC 0x2100
115 #define NFE_RXTX_V3MAGIC 0x2200
116 #define NFE_RXFILTER_MAGIC 0x007f0008
117 #define NFE_U2M (1 << 5)
118 #define NFE_PROMISC (1 << 7)
120 /* default interrupt moderation timer of 128us */
121 #define NFE_IM_DEFAULT ((128 * 100) / 1024)
123 #define NFE_VTAG_ENABLE (1 << 13)
125 #define NFE_PWR_VALID (1 << 8)
126 #define NFE_PWR_WAKEUP (1 << 15)
128 #define NFE_MEDIA_SET 0x10000
129 #define NFE_MEDIA_1000T 0x00032
130 #define NFE_MEDIA_100TX 0x00064
131 #define NFE_MEDIA_10T 0x003e8
133 #define NFE_PHY_100TX (1 << 0)
134 #define NFE_PHY_1000T (1 << 1)
135 #define NFE_PHY_HDX (1 << 8)
137 #define NFE_MISC1_MAGIC 0x003b0f3c
138 #define NFE_MISC1_HDX (1 << 1)
140 #define NFE_SEED_MASK 0x0003ff00
141 #define NFE_SEED_10T 0x00007f00
142 #define NFE_SEED_100TX 0x00002d00
143 #define NFE_SEED_1000T 0x00007400
145 /* Rx/Tx descriptor */
150 #define NFE_RX_FIXME_V1 0x6004
151 #define NFE_RX_VALID_V1 (1 << 0)
152 #define NFE_TX_ERROR_V1 0x7808
153 #define NFE_TX_LASTFRAG_V1 (1 << 0)
154 #define NFE_RX_ERROR1_V1 (1<<7)
155 #define NFE_RX_ERROR2_V1 (1<<8)
156 #define NFE_RX_ERROR3_V1 (1<<9)
157 #define NFE_RX_ERROR4_V1 (1<<10)
160 #define NFE_V1_TXERR "\020" \
161 "\14TXERROR\13UNDERFLOW\12LATECOLLISION\11LOSTCARRIER\10DEFERRED" \
162 "\08FORCEDINT\03RETRY\00LASTPACKET"
164 /* V2 Rx/Tx descriptor */
166 uint32_t physaddr[2];
168 #define NFE_RX_VTAG (1 << 16)
169 #define NFE_TX_VTAG (1 << 18)
172 #define NFE_RX_FIXME_V2 0x4300
173 #define NFE_RX_VALID_V2 (1 << 13)
174 #define NFE_TX_ERROR_V2 0x5c04
175 #define NFE_TX_LASTFRAG_V2 (1 << 13)
176 #define NFE_RX_IP_CSUMOK_V2 0x1000
177 #define NFE_RX_UDP_CSUMOK_V2 0x1400
178 #define NFE_RX_TCP_CSUMOK_V2 0x1800
179 #define NFE_RX_ERROR1_V2 (1<<2)
180 #define NFE_RX_ERROR2_V2 (1<<3)
181 #define NFE_RX_ERROR3_V2 (1<<4)
182 #define NFE_RX_ERROR4_V2 (1<<5)
185 #define NFE_V2_TXERR "\020" \
186 "\14FORCEDINT\13LASTPACKET\12UNDERFLOW\10LOSTCARRIER\09DEFERRED\02RETRY"
188 /* flags common to V1/V2 descriptors */
189 #define NFE_RX_CSUMOK 0x1c00
190 #define NFE_RX_ERROR (1 << 14)
191 #define NFE_RX_READY (1 << 15)
192 #define NFE_TX_TCP_CSUM (1 << 10)
193 #define NFE_TX_IP_CSUM (1 << 11)
194 #define NFE_TX_VALID (1 << 15)
196 #define NFE_READ(sc, reg) \
197 bus_space_read_4((sc)->nfe_memt, (sc)->nfe_memh, (reg))
199 #define NFE_WRITE(sc, reg, val) \
200 bus_space_write_4((sc)->nfe_memt, (sc)->nfe_memh, (reg), (val))
202 #ifndef PCI_VENDOR_NVIDIA
203 #define PCI_VENDOR_NVIDIA 0x10DE
206 #define PCI_PRODUCT_NVIDIA_NFORCE_LAN 0x01C3
207 #define PCI_PRODUCT_NVIDIA_NFORCE2_LAN 0x0066
208 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN1 0x00D6
209 #define PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1 0x0086
210 #define PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2 0x008C
211 #define PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN 0x00E6
212 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN4 0x00DF
213 #define PCI_PRODUCT_NVIDIA_NFORCE4_LAN1 0x0056
214 #define PCI_PRODUCT_NVIDIA_NFORCE4_LAN2 0x0057
215 #define PCI_PRODUCT_NVIDIA_MCP04_LAN1 0x0037
216 #define PCI_PRODUCT_NVIDIA_MCP04_LAN2 0x0038
217 #define PCI_PRODUCT_NVIDIA_NFORCE430_LAN1 0x0268
218 #define PCI_PRODUCT_NVIDIA_NFORCE430_LAN2 0x0269
219 #define PCI_PRODUCT_NVIDIA_MCP55_LAN1 0x0372
220 #define PCI_PRODUCT_NVIDIA_MCP55_LAN2 0x0373
221 #define PCI_PRODUCT_NVIDIA_MCP61_LAN1 0x03e5
222 #define PCI_PRODUCT_NVIDIA_MCP61_LAN2 0x03e6
223 #define PCI_PRODUCT_NVIDIA_MCP61_LAN3 0x03ee
224 #define PCI_PRODUCT_NVIDIA_MCP61_LAN4 0x03ef
225 #define PCI_PRODUCT_NVIDIA_MCP65_LAN1 0x0450
226 #define PCI_PRODUCT_NVIDIA_MCP65_LAN2 0x0451
227 #define PCI_PRODUCT_NVIDIA_MCP65_LAN3 0x0452
228 #define PCI_PRODUCT_NVIDIA_MCP65_LAN4 0x0453
230 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1
231 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2
232 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN
233 #define PCI_PRODUCT_NVIDIA_CK804_LAN1 PCI_PRODUCT_NVIDIA_NFORCE4_LAN1
234 #define PCI_PRODUCT_NVIDIA_CK804_LAN2 PCI_PRODUCT_NVIDIA_NFORCE4_LAN2
235 #define PCI_PRODUCT_NVIDIA_MCP51_LAN1 PCI_PRODUCT_NVIDIA_NFORCE430_LAN1
236 #define PCI_PRODUCT_NVIDIA_MCP51_LAN2 PCI_PRODUCT_NVIDIA_NFORCE430_LAN2
238 #define NFE_DEBUG 0x0000
239 #define NFE_DEBUG_INIT 0x0001
240 #define NFE_DEBUG_RUNNING 0x0002
241 #define NFE_DEBUG_DEINIT 0x0004
242 #define NFE_DEBUG_IOCTL 0x0008
243 #define NFE_DEBUG_INTERRUPT 0x0010
244 #define NFE_DEBUG_API 0x0020
245 #define NFE_DEBUG_LOCK 0x0040
246 #define NFE_DEBUG_BROKEN 0x0080
247 #define NFE_DEBUG_MII 0x0100
248 #define NFE_DEBUG_ALL 0xFFFF