2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 2001 Wind River Systems
5 * Copyright (c) 1997, 1998, 1999, 2000, 2001
6 * Bill Paul <wpaul@bsdi.com>. All rights reserved.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Bill Paul.
19 * 4. Neither the name of the author nor the names of any co-contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
33 * THE POSSIBILITY OF SUCH DAMAGE.
36 #include <sys/cdefs.h>
37 __FBSDID("$FreeBSD$");
40 * National Semiconductor DP83820/DP83821 gigabit ethernet driver
41 * for FreeBSD. Datasheets are available from:
43 * http://www.national.com/ds/DP/DP83820.pdf
44 * http://www.national.com/ds/DP/DP83821.pdf
46 * These chips are used on several low cost gigabit ethernet NICs
47 * sold by D-Link, Addtron, SMC and Asante. Both parts are
48 * virtually the same, except the 83820 is a 64-bit/32-bit part,
49 * while the 83821 is 32-bit only.
51 * Many cards also use National gigE transceivers, such as the
52 * DP83891, DP83861 and DP83862 gigPHYTER parts. The DP83861 datasheet
53 * contains a full register description that applies to all of these
56 * http://www.national.com/ds/DP/DP83861.pdf
58 * Written by Bill Paul <wpaul@bsdi.com>
59 * BSDi Open Source Solutions
63 * The NatSemi DP83820 and 83821 controllers are enhanced versions
64 * of the NatSemi MacPHYTER 10/100 devices. They support 10, 100
65 * and 1000Mbps speeds with 1000baseX (ten bit interface), MII and GMII
66 * ports. Other features include 8K TX FIFO and 32K RX FIFO, TCP/IP
67 * hardware checksum offload (IPv4 only), VLAN tagging and filtering,
68 * priority TX and RX queues, a 2048 bit multicast hash filter, 4 RX pattern
69 * matching buffers, one perfect address filter buffer and interrupt
70 * moderation. The 83820 supports both 64-bit and 32-bit addressing
71 * and data transfers: the 64-bit support can be toggled on or off
72 * via software. This affects the size of certain fields in the DMA
75 * There are two bugs/misfeatures in the 83820/83821 that I have
78 * - Receive buffers must be aligned on 64-bit boundaries, which means
79 * you must resort to copying data in order to fix up the payload
82 * - In order to transmit jumbo frames larger than 8170 bytes, you have
83 * to turn off transmit checksum offloading, because the chip can't
84 * compute the checksum on an outgoing frame unless it fits entirely
85 * within the TX FIFO, which is only 8192 bytes in size. If you have
86 * TX checksum offload enabled and you transmit attempt to transmit a
87 * frame larger than 8170 bytes, the transmitter will wedge.
89 * To work around the latter problem, TX checksum offload is disabled
90 * if the user selects an MTU larger than 8152 (8170 - 18).
93 #ifdef HAVE_KERNEL_OPTION_HEADERS
94 #include "opt_device_polling.h"
97 #include <sys/param.h>
98 #include <sys/systm.h>
100 #include <sys/endian.h>
101 #include <sys/kernel.h>
102 #include <sys/lock.h>
103 #include <sys/malloc.h>
104 #include <sys/mbuf.h>
105 #include <sys/module.h>
106 #include <sys/mutex.h>
107 #include <sys/rman.h>
108 #include <sys/socket.h>
109 #include <sys/sockio.h>
110 #include <sys/sysctl.h>
114 #include <net/if_var.h>
115 #include <net/if_arp.h>
116 #include <net/ethernet.h>
117 #include <net/if_dl.h>
118 #include <net/if_media.h>
119 #include <net/if_types.h>
120 #include <net/if_vlan_var.h>
122 #include <dev/mii/mii.h>
123 #include <dev/mii/mii_bitbang.h>
124 #include <dev/mii/miivar.h>
126 #include <dev/pci/pcireg.h>
127 #include <dev/pci/pcivar.h>
129 #include <machine/bus.h>
131 #include <dev/nge/if_ngereg.h>
133 /* "device miibus" required. See GENERIC if you get errors here. */
134 #include "miibus_if.h"
136 MODULE_DEPEND(nge, pci, 1, 1, 1);
137 MODULE_DEPEND(nge, ether, 1, 1, 1);
138 MODULE_DEPEND(nge, miibus, 1, 1, 1);
140 #define NGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
143 * Various supported device vendors/types and their names.
145 static const struct nge_type nge_devs[] = {
146 { NGE_VENDORID, NGE_DEVICEID,
147 "National Semiconductor Gigabit Ethernet" },
151 static int nge_probe(device_t);
152 static int nge_attach(device_t);
153 static int nge_detach(device_t);
154 static int nge_shutdown(device_t);
155 static int nge_suspend(device_t);
156 static int nge_resume(device_t);
158 static __inline void nge_discard_rxbuf(struct nge_softc *, int);
159 static int nge_newbuf(struct nge_softc *, int);
160 static int nge_encap(struct nge_softc *, struct mbuf **);
161 #ifndef __NO_STRICT_ALIGNMENT
162 static __inline void nge_fixup_rx(struct mbuf *);
164 static int nge_rxeof(struct nge_softc *);
165 static void nge_txeof(struct nge_softc *);
166 static void nge_intr(void *);
167 static void nge_tick(void *);
168 static void nge_stats_update(struct nge_softc *);
169 static void nge_start(struct ifnet *);
170 static void nge_start_locked(struct ifnet *);
171 static int nge_ioctl(struct ifnet *, u_long, caddr_t);
172 static void nge_init(void *);
173 static void nge_init_locked(struct nge_softc *);
174 static int nge_stop_mac(struct nge_softc *);
175 static void nge_stop(struct nge_softc *);
176 static void nge_wol(struct nge_softc *);
177 static void nge_watchdog(struct nge_softc *);
178 static int nge_mediachange(struct ifnet *);
179 static void nge_mediastatus(struct ifnet *, struct ifmediareq *);
181 static void nge_delay(struct nge_softc *);
182 static void nge_eeprom_idle(struct nge_softc *);
183 static void nge_eeprom_putbyte(struct nge_softc *, int);
184 static void nge_eeprom_getword(struct nge_softc *, int, uint16_t *);
185 static void nge_read_eeprom(struct nge_softc *, caddr_t, int, int);
187 static int nge_miibus_readreg(device_t, int, int);
188 static int nge_miibus_writereg(device_t, int, int, int);
189 static void nge_miibus_statchg(device_t);
191 static void nge_rxfilter(struct nge_softc *);
192 static void nge_reset(struct nge_softc *);
193 static void nge_dmamap_cb(void *, bus_dma_segment_t *, int, int);
194 static int nge_dma_alloc(struct nge_softc *);
195 static void nge_dma_free(struct nge_softc *);
196 static int nge_list_rx_init(struct nge_softc *);
197 static int nge_list_tx_init(struct nge_softc *);
198 static void nge_sysctl_node(struct nge_softc *);
199 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
200 static int sysctl_hw_nge_int_holdoff(SYSCTL_HANDLER_ARGS);
205 static uint32_t nge_mii_bitbang_read(device_t);
206 static void nge_mii_bitbang_write(device_t, uint32_t);
208 static const struct mii_bitbang_ops nge_mii_bitbang_ops = {
209 nge_mii_bitbang_read,
210 nge_mii_bitbang_write,
212 NGE_MEAR_MII_DATA, /* MII_BIT_MDO */
213 NGE_MEAR_MII_DATA, /* MII_BIT_MDI */
214 NGE_MEAR_MII_CLK, /* MII_BIT_MDC */
215 NGE_MEAR_MII_DIR, /* MII_BIT_DIR_HOST_PHY */
216 0, /* MII_BIT_DIR_PHY_HOST */
220 static device_method_t nge_methods[] = {
221 /* Device interface */
222 DEVMETHOD(device_probe, nge_probe),
223 DEVMETHOD(device_attach, nge_attach),
224 DEVMETHOD(device_detach, nge_detach),
225 DEVMETHOD(device_shutdown, nge_shutdown),
226 DEVMETHOD(device_suspend, nge_suspend),
227 DEVMETHOD(device_resume, nge_resume),
230 DEVMETHOD(miibus_readreg, nge_miibus_readreg),
231 DEVMETHOD(miibus_writereg, nge_miibus_writereg),
232 DEVMETHOD(miibus_statchg, nge_miibus_statchg),
237 static driver_t nge_driver = {
240 sizeof(struct nge_softc)
243 static devclass_t nge_devclass;
245 DRIVER_MODULE(nge, pci, nge_driver, nge_devclass, 0, 0);
246 DRIVER_MODULE(miibus, nge, miibus_driver, miibus_devclass, 0, 0);
248 #define NGE_SETBIT(sc, reg, x) \
249 CSR_WRITE_4(sc, reg, \
250 CSR_READ_4(sc, reg) | (x))
252 #define NGE_CLRBIT(sc, reg, x) \
253 CSR_WRITE_4(sc, reg, \
254 CSR_READ_4(sc, reg) & ~(x))
257 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | (x))
260 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~(x))
263 nge_delay(struct nge_softc *sc)
267 for (idx = (300 / 33) + 1; idx > 0; idx--)
268 CSR_READ_4(sc, NGE_CSR);
272 nge_eeprom_idle(struct nge_softc *sc)
276 SIO_SET(NGE_MEAR_EE_CSEL);
278 SIO_SET(NGE_MEAR_EE_CLK);
281 for (i = 0; i < 25; i++) {
282 SIO_CLR(NGE_MEAR_EE_CLK);
284 SIO_SET(NGE_MEAR_EE_CLK);
288 SIO_CLR(NGE_MEAR_EE_CLK);
290 SIO_CLR(NGE_MEAR_EE_CSEL);
292 CSR_WRITE_4(sc, NGE_MEAR, 0x00000000);
296 * Send a read command and address to the EEPROM, check for ACK.
299 nge_eeprom_putbyte(struct nge_softc *sc, int addr)
303 d = addr | NGE_EECMD_READ;
306 * Feed in each bit and stobe the clock.
308 for (i = 0x400; i; i >>= 1) {
310 SIO_SET(NGE_MEAR_EE_DIN);
312 SIO_CLR(NGE_MEAR_EE_DIN);
315 SIO_SET(NGE_MEAR_EE_CLK);
317 SIO_CLR(NGE_MEAR_EE_CLK);
323 * Read a word of data stored in the EEPROM at address 'addr.'
326 nge_eeprom_getword(struct nge_softc *sc, int addr, uint16_t *dest)
331 /* Force EEPROM to idle state. */
334 /* Enter EEPROM access mode. */
336 SIO_CLR(NGE_MEAR_EE_CLK);
338 SIO_SET(NGE_MEAR_EE_CSEL);
342 * Send address of word we want to read.
344 nge_eeprom_putbyte(sc, addr);
347 * Start reading bits from EEPROM.
349 for (i = 0x8000; i; i >>= 1) {
350 SIO_SET(NGE_MEAR_EE_CLK);
352 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_EE_DOUT)
355 SIO_CLR(NGE_MEAR_EE_CLK);
359 /* Turn off EEPROM access mode. */
366 * Read a sequence of words from the EEPROM.
369 nge_read_eeprom(struct nge_softc *sc, caddr_t dest, int off, int cnt)
372 uint16_t word = 0, *ptr;
374 for (i = 0; i < cnt; i++) {
375 nge_eeprom_getword(sc, off + i, &word);
376 ptr = (uint16_t *)(dest + (i * 2));
382 * Read the MII serial port for the MII bit-bang module.
385 nge_mii_bitbang_read(device_t dev)
387 struct nge_softc *sc;
390 sc = device_get_softc(dev);
392 val = CSR_READ_4(sc, NGE_MEAR);
393 CSR_BARRIER_4(sc, NGE_MEAR,
394 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
400 * Write the MII serial port for the MII bit-bang module.
403 nge_mii_bitbang_write(device_t dev, uint32_t val)
405 struct nge_softc *sc;
407 sc = device_get_softc(dev);
409 CSR_WRITE_4(sc, NGE_MEAR, val);
410 CSR_BARRIER_4(sc, NGE_MEAR,
411 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
415 nge_miibus_readreg(device_t dev, int phy, int reg)
417 struct nge_softc *sc;
420 sc = device_get_softc(dev);
421 if ((sc->nge_flags & NGE_FLAG_TBI) != 0) {
422 /* Pretend PHY is at address 0. */
430 /* 83820/83821 has different bit layout for BMSR. */
431 rv = BMSR_ANEG | BMSR_EXTCAP | BMSR_EXTSTAT;
432 reg = CSR_READ_4(sc, NGE_TBI_BMSR);
433 if ((reg & NGE_TBIBMSR_ANEG_DONE) != 0)
435 if ((reg & NGE_TBIBMSR_LINKSTAT) != 0)
442 reg = NGE_TBI_ANLPAR;
454 device_printf(sc->nge_dev,
455 "bad phy register read : %d\n", reg);
458 return (CSR_READ_4(sc, reg));
461 return (mii_bitbang_readreg(dev, &nge_mii_bitbang_ops, phy, reg));
465 nge_miibus_writereg(device_t dev, int phy, int reg, int data)
467 struct nge_softc *sc;
469 sc = device_get_softc(dev);
470 if ((sc->nge_flags & NGE_FLAG_TBI) != 0) {
471 /* Pretend PHY is at address 0. */
484 reg = NGE_TBI_ANLPAR;
496 device_printf(sc->nge_dev,
497 "bad phy register write : %d\n", reg);
500 CSR_WRITE_4(sc, reg, data);
504 mii_bitbang_writereg(dev, &nge_mii_bitbang_ops, phy, reg, data);
510 * media status/link state change handler.
513 nge_miibus_statchg(device_t dev)
515 struct nge_softc *sc;
516 struct mii_data *mii;
518 struct nge_txdesc *txd;
519 uint32_t done, reg, status;
522 sc = device_get_softc(dev);
525 mii = device_get_softc(sc->nge_miibus);
527 if (mii == NULL || ifp == NULL ||
528 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
531 sc->nge_flags &= ~NGE_FLAG_LINK;
532 if ((mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) ==
533 (IFM_AVALID | IFM_ACTIVE)) {
534 switch (IFM_SUBTYPE(mii->mii_media_active)) {
541 sc->nge_flags |= NGE_FLAG_LINK;
548 /* Stop Tx/Rx MACs. */
549 if (nge_stop_mac(sc) == ETIMEDOUT)
550 device_printf(sc->nge_dev,
551 "%s: unable to stop Tx/Rx MAC\n", __func__);
554 if (sc->nge_head != NULL) {
555 m_freem(sc->nge_head);
556 sc->nge_head = sc->nge_tail = NULL;
559 /* Release queued frames. */
560 for (i = 0; i < NGE_TX_RING_CNT; i++) {
561 txd = &sc->nge_cdata.nge_txdesc[i];
562 if (txd->tx_m != NULL) {
563 bus_dmamap_sync(sc->nge_cdata.nge_tx_tag,
564 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
565 bus_dmamap_unload(sc->nge_cdata.nge_tx_tag,
572 /* Program MAC with resolved speed/duplex. */
573 if ((sc->nge_flags & NGE_FLAG_LINK) != 0) {
574 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
575 NGE_SETBIT(sc, NGE_TX_CFG,
576 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
577 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
579 /* Enable flow-control. */
580 if ((IFM_OPTIONS(mii->mii_media_active) &
581 (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) != 0)
582 NGE_SETBIT(sc, NGE_PAUSECSR,
583 NGE_PAUSECSR_PAUSE_ENB);
586 NGE_CLRBIT(sc, NGE_TX_CFG,
587 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
588 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
589 NGE_CLRBIT(sc, NGE_PAUSECSR, NGE_PAUSECSR_PAUSE_ENB);
591 /* If we have a 1000Mbps link, set the mode_1000 bit. */
592 reg = CSR_READ_4(sc, NGE_CFG);
593 switch (IFM_SUBTYPE(mii->mii_media_active)) {
598 reg |= NGE_CFG_MODE_1000;
601 reg &= ~NGE_CFG_MODE_1000;
604 CSR_WRITE_4(sc, NGE_CFG, reg);
606 /* Reset Tx/Rx MAC. */
607 reg = CSR_READ_4(sc, NGE_CSR);
608 reg |= NGE_CSR_TX_RESET | NGE_CSR_RX_RESET;
609 CSR_WRITE_4(sc, NGE_CSR, reg);
610 /* Check the completion of reset. */
612 for (i = 0; i < NGE_TIMEOUT; i++) {
614 status = CSR_READ_4(sc, NGE_ISR);
615 if ((status & NGE_ISR_RX_RESET_DONE) != 0)
616 done |= NGE_ISR_RX_RESET_DONE;
617 if ((status & NGE_ISR_TX_RESET_DONE) != 0)
618 done |= NGE_ISR_TX_RESET_DONE;
620 (NGE_ISR_TX_RESET_DONE | NGE_ISR_RX_RESET_DONE))
623 if (i == NGE_TIMEOUT)
624 device_printf(sc->nge_dev,
625 "%s: unable to reset Tx/Rx MAC\n", __func__);
626 /* Reuse Rx buffer and reset consumer pointer. */
627 sc->nge_cdata.nge_rx_cons = 0;
629 * It seems that resetting Rx/Tx MAC results in
630 * resetting Tx/Rx descriptor pointer registers such
631 * that reloading Tx/Rx lists address are needed.
633 CSR_WRITE_4(sc, NGE_RX_LISTPTR_HI,
634 NGE_ADDR_HI(sc->nge_rdata.nge_rx_ring_paddr));
635 CSR_WRITE_4(sc, NGE_RX_LISTPTR_LO,
636 NGE_ADDR_LO(sc->nge_rdata.nge_rx_ring_paddr));
637 CSR_WRITE_4(sc, NGE_TX_LISTPTR_HI,
638 NGE_ADDR_HI(sc->nge_rdata.nge_tx_ring_paddr));
639 CSR_WRITE_4(sc, NGE_TX_LISTPTR_LO,
640 NGE_ADDR_LO(sc->nge_rdata.nge_tx_ring_paddr));
641 /* Reinitialize Tx buffers. */
642 nge_list_tx_init(sc);
644 /* Restart Rx MAC. */
645 reg = CSR_READ_4(sc, NGE_CSR);
646 reg |= NGE_CSR_RX_ENABLE;
647 CSR_WRITE_4(sc, NGE_CSR, reg);
648 for (i = 0; i < NGE_TIMEOUT; i++) {
649 if ((CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RX_ENABLE) != 0)
653 if (i == NGE_TIMEOUT)
654 device_printf(sc->nge_dev,
655 "%s: unable to restart Rx MAC\n", __func__);
658 /* Data LED off for TBI mode */
659 if ((sc->nge_flags & NGE_FLAG_TBI) != 0)
660 CSR_WRITE_4(sc, NGE_GPIO,
661 CSR_READ_4(sc, NGE_GPIO) & ~NGE_GPIO_GP3_OUT);
665 nge_rxfilter(struct nge_softc *sc)
668 struct ifmultiaddr *ifma;
669 uint32_t h, i, rxfilt;
675 /* Make sure to stop Rx filtering. */
676 rxfilt = CSR_READ_4(sc, NGE_RXFILT_CTL);
677 rxfilt &= ~NGE_RXFILTCTL_ENABLE;
678 CSR_WRITE_4(sc, NGE_RXFILT_CTL, rxfilt);
679 CSR_BARRIER_4(sc, NGE_RXFILT_CTL, BUS_SPACE_BARRIER_WRITE);
681 rxfilt &= ~(NGE_RXFILTCTL_ALLMULTI | NGE_RXFILTCTL_ALLPHYS);
682 rxfilt &= ~NGE_RXFILTCTL_BROAD;
684 * We don't want to use the hash table for matching unicast
687 rxfilt &= ~(NGE_RXFILTCTL_MCHASH | NGE_RXFILTCTL_UCHASH);
690 * For the NatSemi chip, we have to explicitly enable the
691 * reception of ARP frames, as well as turn on the 'perfect
692 * match' filter where we store the station address, otherwise
693 * we won't receive unicasts meant for this host.
695 rxfilt |= NGE_RXFILTCTL_ARP | NGE_RXFILTCTL_PERFECT;
698 * Set the capture broadcast bit to capture broadcast frames.
700 if ((ifp->if_flags & IFF_BROADCAST) != 0)
701 rxfilt |= NGE_RXFILTCTL_BROAD;
703 if ((ifp->if_flags & IFF_PROMISC) != 0 ||
704 (ifp->if_flags & IFF_ALLMULTI) != 0) {
705 rxfilt |= NGE_RXFILTCTL_ALLMULTI;
706 if ((ifp->if_flags & IFF_PROMISC) != 0)
707 rxfilt |= NGE_RXFILTCTL_ALLPHYS;
712 * We have to explicitly enable the multicast hash table
713 * on the NatSemi chip if we want to use it, which we do.
715 rxfilt |= NGE_RXFILTCTL_MCHASH;
717 /* first, zot all the existing hash bits */
718 for (i = 0; i < NGE_MCAST_FILTER_LEN; i += 2) {
719 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_MCAST_LO + i);
720 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 0);
724 * From the 11 bits returned by the crc routine, the top 7
725 * bits represent the 16-bit word in the mcast hash table
726 * that needs to be updated, and the lower 4 bits represent
727 * which bit within that byte needs to be set.
730 CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
731 if (ifma->ifma_addr->sa_family != AF_LINK)
733 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
734 ifma->ifma_addr), ETHER_ADDR_LEN) >> 21;
735 index = (h >> 4) & 0x7F;
737 CSR_WRITE_4(sc, NGE_RXFILT_CTL,
738 NGE_FILTADDR_MCAST_LO + (index * 2));
739 NGE_SETBIT(sc, NGE_RXFILT_DATA, (1 << bit));
741 if_maddr_runlock(ifp);
744 CSR_WRITE_4(sc, NGE_RXFILT_CTL, rxfilt);
745 /* Turn the receive filter on. */
746 rxfilt |= NGE_RXFILTCTL_ENABLE;
747 CSR_WRITE_4(sc, NGE_RXFILT_CTL, rxfilt);
748 CSR_BARRIER_4(sc, NGE_RXFILT_CTL, BUS_SPACE_BARRIER_WRITE);
752 nge_reset(struct nge_softc *sc)
757 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RESET);
759 for (i = 0; i < NGE_TIMEOUT; i++) {
760 if (!(CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RESET))
765 if (i == NGE_TIMEOUT)
766 device_printf(sc->nge_dev, "reset never completed\n");
768 /* Wait a little while for the chip to get its brains in order. */
772 * If this is a NetSemi chip, make sure to clear
775 CSR_WRITE_4(sc, NGE_CLKRUN, NGE_CLKRUN_PMESTS);
776 CSR_WRITE_4(sc, NGE_CLKRUN, 0);
778 /* Clear WOL events which may interfere normal Rx filter opertaion. */
779 CSR_WRITE_4(sc, NGE_WOLCSR, 0);
782 * Only DP83820 supports 64bits addressing/data transfers and
783 * 64bit addressing requires different descriptor structures.
784 * To make it simple, disable 64bit addressing/data transfers.
786 v = CSR_READ_4(sc, NGE_CFG);
787 v &= ~(NGE_CFG_64BIT_ADDR_ENB | NGE_CFG_64BIT_DATA_ENB);
788 CSR_WRITE_4(sc, NGE_CFG, v);
792 * Probe for a NatSemi chip. Check the PCI vendor and device
793 * IDs against our list and return a device name if we find a match.
796 nge_probe(device_t dev)
798 const struct nge_type *t;
802 while (t->nge_name != NULL) {
803 if ((pci_get_vendor(dev) == t->nge_vid) &&
804 (pci_get_device(dev) == t->nge_did)) {
805 device_set_desc(dev, t->nge_name);
806 return (BUS_PROBE_DEFAULT);
815 * Attach the interface. Allocate softc structures, do ifmedia
816 * setup and ethernet/BPF attach.
819 nge_attach(device_t dev)
821 uint8_t eaddr[ETHER_ADDR_LEN];
822 uint16_t ea[ETHER_ADDR_LEN/2], ea_temp, reg;
823 struct nge_softc *sc;
828 sc = device_get_softc(dev);
831 NGE_LOCK_INIT(sc, device_get_nameunit(dev));
832 callout_init_mtx(&sc->nge_stat_ch, &sc->nge_mtx, 0);
835 * Map control/status registers.
837 pci_enable_busmaster(dev);
839 #ifdef NGE_USEIOSPACE
840 sc->nge_res_type = SYS_RES_IOPORT;
841 sc->nge_res_id = PCIR_BAR(0);
843 sc->nge_res_type = SYS_RES_MEMORY;
844 sc->nge_res_id = PCIR_BAR(1);
846 sc->nge_res = bus_alloc_resource_any(dev, sc->nge_res_type,
847 &sc->nge_res_id, RF_ACTIVE);
849 if (sc->nge_res == NULL) {
850 if (sc->nge_res_type == SYS_RES_MEMORY) {
851 sc->nge_res_type = SYS_RES_IOPORT;
852 sc->nge_res_id = PCIR_BAR(0);
854 sc->nge_res_type = SYS_RES_MEMORY;
855 sc->nge_res_id = PCIR_BAR(1);
857 sc->nge_res = bus_alloc_resource_any(dev, sc->nge_res_type,
858 &sc->nge_res_id, RF_ACTIVE);
859 if (sc->nge_res == NULL) {
860 device_printf(dev, "couldn't allocate %s resources\n",
861 sc->nge_res_type == SYS_RES_MEMORY ? "memory" :
863 NGE_LOCK_DESTROY(sc);
868 /* Allocate interrupt */
870 sc->nge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
871 RF_SHAREABLE | RF_ACTIVE);
873 if (sc->nge_irq == NULL) {
874 device_printf(dev, "couldn't map interrupt\n");
880 reg = pci_read_config(dev, PCIR_COMMAND, 2);
881 reg |= PCIM_CMD_MWRICEN;
882 pci_write_config(dev, PCIR_COMMAND, reg, 2);
884 /* Reset the adapter. */
888 * Get station address from the EEPROM.
890 nge_read_eeprom(sc, (caddr_t)ea, NGE_EE_NODEADDR, 3);
891 for (i = 0; i < ETHER_ADDR_LEN / 2; i++)
892 ea[i] = le16toh(ea[i]);
896 bcopy(ea, eaddr, sizeof(eaddr));
898 if (nge_dma_alloc(sc) != 0) {
905 ifp = sc->nge_ifp = if_alloc(IFT_ETHER);
907 device_printf(dev, "can not allocate ifnet structure\n");
912 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
913 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
914 ifp->if_ioctl = nge_ioctl;
915 ifp->if_start = nge_start;
916 ifp->if_init = nge_init;
917 ifp->if_snd.ifq_drv_maxlen = NGE_TX_RING_CNT - 1;
918 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
919 IFQ_SET_READY(&ifp->if_snd);
920 ifp->if_hwassist = NGE_CSUM_FEATURES;
921 ifp->if_capabilities = IFCAP_HWCSUM;
923 * It seems that some hardwares doesn't provide 3.3V auxiliary
924 * supply(3VAUX) to drive PME such that checking PCI power
925 * management capability is necessary.
927 if (pci_find_cap(sc->nge_dev, PCIY_PMG, &i) == 0)
928 ifp->if_capabilities |= IFCAP_WOL;
929 ifp->if_capenable = ifp->if_capabilities;
931 if ((CSR_READ_4(sc, NGE_CFG) & NGE_CFG_TBI_EN) != 0) {
932 sc->nge_flags |= NGE_FLAG_TBI;
933 device_printf(dev, "Using TBI\n");
934 /* Configure GPIO. */
935 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
937 | NGE_GPIO_GP1_OUTENB | NGE_GPIO_GP2_OUTENB
938 | NGE_GPIO_GP3_OUTENB
939 | NGE_GPIO_GP3_IN | NGE_GPIO_GP4_IN);
945 error = mii_attach(dev, &sc->nge_miibus, ifp, nge_mediachange,
946 nge_mediastatus, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
948 device_printf(dev, "attaching PHYs failed\n");
953 * Call MI attach routine.
955 ether_ifattach(ifp, eaddr);
957 /* VLAN capability setup. */
958 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
959 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
960 ifp->if_capenable = ifp->if_capabilities;
961 #ifdef DEVICE_POLLING
962 ifp->if_capabilities |= IFCAP_POLLING;
965 * Tell the upper layer(s) we support long frames.
966 * Must appear after the call to ether_ifattach() because
967 * ether_ifattach() sets ifi_hdrlen to the default value.
969 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
974 error = bus_setup_intr(dev, sc->nge_irq, INTR_TYPE_NET | INTR_MPSAFE,
975 NULL, nge_intr, sc, &sc->nge_intrhand);
977 device_printf(dev, "couldn't set up irq\n");
988 nge_detach(device_t dev)
990 struct nge_softc *sc;
993 sc = device_get_softc(dev);
996 #ifdef DEVICE_POLLING
997 if (ifp != NULL && ifp->if_capenable & IFCAP_POLLING)
998 ether_poll_deregister(ifp);
1001 if (device_is_attached(dev)) {
1003 sc->nge_flags |= NGE_FLAG_DETACH;
1006 callout_drain(&sc->nge_stat_ch);
1008 ether_ifdetach(ifp);
1011 if (sc->nge_miibus != NULL) {
1012 device_delete_child(dev, sc->nge_miibus);
1013 sc->nge_miibus = NULL;
1015 bus_generic_detach(dev);
1016 if (sc->nge_intrhand != NULL)
1017 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand);
1018 if (sc->nge_irq != NULL)
1019 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
1020 if (sc->nge_res != NULL)
1021 bus_release_resource(dev, sc->nge_res_type, sc->nge_res_id,
1028 NGE_LOCK_DESTROY(sc);
1033 struct nge_dmamap_arg {
1034 bus_addr_t nge_busaddr;
1038 nge_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1040 struct nge_dmamap_arg *ctx;
1045 ctx->nge_busaddr = segs[0].ds_addr;
1049 nge_dma_alloc(struct nge_softc *sc)
1051 struct nge_dmamap_arg ctx;
1052 struct nge_txdesc *txd;
1053 struct nge_rxdesc *rxd;
1056 /* Create parent DMA tag. */
1057 error = bus_dma_tag_create(
1058 bus_get_dma_tag(sc->nge_dev), /* parent */
1059 1, 0, /* alignment, boundary */
1060 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1061 BUS_SPACE_MAXADDR, /* highaddr */
1062 NULL, NULL, /* filter, filterarg */
1063 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1065 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1067 NULL, NULL, /* lockfunc, lockarg */
1068 &sc->nge_cdata.nge_parent_tag);
1070 device_printf(sc->nge_dev, "failed to create parent DMA tag\n");
1073 /* Create tag for Tx ring. */
1074 error = bus_dma_tag_create(sc->nge_cdata.nge_parent_tag,/* parent */
1075 NGE_RING_ALIGN, 0, /* alignment, boundary */
1076 BUS_SPACE_MAXADDR, /* lowaddr */
1077 BUS_SPACE_MAXADDR, /* highaddr */
1078 NULL, NULL, /* filter, filterarg */
1079 NGE_TX_RING_SIZE, /* maxsize */
1081 NGE_TX_RING_SIZE, /* maxsegsize */
1083 NULL, NULL, /* lockfunc, lockarg */
1084 &sc->nge_cdata.nge_tx_ring_tag);
1086 device_printf(sc->nge_dev, "failed to create Tx ring DMA tag\n");
1090 /* Create tag for Rx ring. */
1091 error = bus_dma_tag_create(sc->nge_cdata.nge_parent_tag,/* parent */
1092 NGE_RING_ALIGN, 0, /* alignment, boundary */
1093 BUS_SPACE_MAXADDR, /* lowaddr */
1094 BUS_SPACE_MAXADDR, /* highaddr */
1095 NULL, NULL, /* filter, filterarg */
1096 NGE_RX_RING_SIZE, /* maxsize */
1098 NGE_RX_RING_SIZE, /* maxsegsize */
1100 NULL, NULL, /* lockfunc, lockarg */
1101 &sc->nge_cdata.nge_rx_ring_tag);
1103 device_printf(sc->nge_dev,
1104 "failed to create Rx ring DMA tag\n");
1108 /* Create tag for Tx buffers. */
1109 error = bus_dma_tag_create(sc->nge_cdata.nge_parent_tag,/* parent */
1110 1, 0, /* alignment, boundary */
1111 BUS_SPACE_MAXADDR, /* lowaddr */
1112 BUS_SPACE_MAXADDR, /* highaddr */
1113 NULL, NULL, /* filter, filterarg */
1114 MCLBYTES * NGE_MAXTXSEGS, /* maxsize */
1115 NGE_MAXTXSEGS, /* nsegments */
1116 MCLBYTES, /* maxsegsize */
1118 NULL, NULL, /* lockfunc, lockarg */
1119 &sc->nge_cdata.nge_tx_tag);
1121 device_printf(sc->nge_dev, "failed to create Tx DMA tag\n");
1125 /* Create tag for Rx buffers. */
1126 error = bus_dma_tag_create(sc->nge_cdata.nge_parent_tag,/* parent */
1127 NGE_RX_ALIGN, 0, /* alignment, boundary */
1128 BUS_SPACE_MAXADDR, /* lowaddr */
1129 BUS_SPACE_MAXADDR, /* highaddr */
1130 NULL, NULL, /* filter, filterarg */
1131 MCLBYTES, /* maxsize */
1133 MCLBYTES, /* maxsegsize */
1135 NULL, NULL, /* lockfunc, lockarg */
1136 &sc->nge_cdata.nge_rx_tag);
1138 device_printf(sc->nge_dev, "failed to create Rx DMA tag\n");
1142 /* Allocate DMA'able memory and load the DMA map for Tx ring. */
1143 error = bus_dmamem_alloc(sc->nge_cdata.nge_tx_ring_tag,
1144 (void **)&sc->nge_rdata.nge_tx_ring, BUS_DMA_WAITOK |
1145 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->nge_cdata.nge_tx_ring_map);
1147 device_printf(sc->nge_dev,
1148 "failed to allocate DMA'able memory for Tx ring\n");
1152 ctx.nge_busaddr = 0;
1153 error = bus_dmamap_load(sc->nge_cdata.nge_tx_ring_tag,
1154 sc->nge_cdata.nge_tx_ring_map, sc->nge_rdata.nge_tx_ring,
1155 NGE_TX_RING_SIZE, nge_dmamap_cb, &ctx, 0);
1156 if (error != 0 || ctx.nge_busaddr == 0) {
1157 device_printf(sc->nge_dev,
1158 "failed to load DMA'able memory for Tx ring\n");
1161 sc->nge_rdata.nge_tx_ring_paddr = ctx.nge_busaddr;
1163 /* Allocate DMA'able memory and load the DMA map for Rx ring. */
1164 error = bus_dmamem_alloc(sc->nge_cdata.nge_rx_ring_tag,
1165 (void **)&sc->nge_rdata.nge_rx_ring, BUS_DMA_WAITOK |
1166 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->nge_cdata.nge_rx_ring_map);
1168 device_printf(sc->nge_dev,
1169 "failed to allocate DMA'able memory for Rx ring\n");
1173 ctx.nge_busaddr = 0;
1174 error = bus_dmamap_load(sc->nge_cdata.nge_rx_ring_tag,
1175 sc->nge_cdata.nge_rx_ring_map, sc->nge_rdata.nge_rx_ring,
1176 NGE_RX_RING_SIZE, nge_dmamap_cb, &ctx, 0);
1177 if (error != 0 || ctx.nge_busaddr == 0) {
1178 device_printf(sc->nge_dev,
1179 "failed to load DMA'able memory for Rx ring\n");
1182 sc->nge_rdata.nge_rx_ring_paddr = ctx.nge_busaddr;
1184 /* Create DMA maps for Tx buffers. */
1185 for (i = 0; i < NGE_TX_RING_CNT; i++) {
1186 txd = &sc->nge_cdata.nge_txdesc[i];
1188 txd->tx_dmamap = NULL;
1189 error = bus_dmamap_create(sc->nge_cdata.nge_tx_tag, 0,
1192 device_printf(sc->nge_dev,
1193 "failed to create Tx dmamap\n");
1197 /* Create DMA maps for Rx buffers. */
1198 if ((error = bus_dmamap_create(sc->nge_cdata.nge_rx_tag, 0,
1199 &sc->nge_cdata.nge_rx_sparemap)) != 0) {
1200 device_printf(sc->nge_dev,
1201 "failed to create spare Rx dmamap\n");
1204 for (i = 0; i < NGE_RX_RING_CNT; i++) {
1205 rxd = &sc->nge_cdata.nge_rxdesc[i];
1207 rxd->rx_dmamap = NULL;
1208 error = bus_dmamap_create(sc->nge_cdata.nge_rx_tag, 0,
1211 device_printf(sc->nge_dev,
1212 "failed to create Rx dmamap\n");
1222 nge_dma_free(struct nge_softc *sc)
1224 struct nge_txdesc *txd;
1225 struct nge_rxdesc *rxd;
1229 if (sc->nge_cdata.nge_tx_ring_tag) {
1230 if (sc->nge_rdata.nge_tx_ring_paddr)
1231 bus_dmamap_unload(sc->nge_cdata.nge_tx_ring_tag,
1232 sc->nge_cdata.nge_tx_ring_map);
1233 if (sc->nge_rdata.nge_tx_ring)
1234 bus_dmamem_free(sc->nge_cdata.nge_tx_ring_tag,
1235 sc->nge_rdata.nge_tx_ring,
1236 sc->nge_cdata.nge_tx_ring_map);
1237 sc->nge_rdata.nge_tx_ring = NULL;
1238 sc->nge_rdata.nge_tx_ring_paddr = 0;
1239 bus_dma_tag_destroy(sc->nge_cdata.nge_tx_ring_tag);
1240 sc->nge_cdata.nge_tx_ring_tag = NULL;
1243 if (sc->nge_cdata.nge_rx_ring_tag) {
1244 if (sc->nge_rdata.nge_rx_ring_paddr)
1245 bus_dmamap_unload(sc->nge_cdata.nge_rx_ring_tag,
1246 sc->nge_cdata.nge_rx_ring_map);
1247 if (sc->nge_rdata.nge_rx_ring)
1248 bus_dmamem_free(sc->nge_cdata.nge_rx_ring_tag,
1249 sc->nge_rdata.nge_rx_ring,
1250 sc->nge_cdata.nge_rx_ring_map);
1251 sc->nge_rdata.nge_rx_ring = NULL;
1252 sc->nge_rdata.nge_rx_ring_paddr = 0;
1253 bus_dma_tag_destroy(sc->nge_cdata.nge_rx_ring_tag);
1254 sc->nge_cdata.nge_rx_ring_tag = NULL;
1257 if (sc->nge_cdata.nge_tx_tag) {
1258 for (i = 0; i < NGE_TX_RING_CNT; i++) {
1259 txd = &sc->nge_cdata.nge_txdesc[i];
1260 if (txd->tx_dmamap) {
1261 bus_dmamap_destroy(sc->nge_cdata.nge_tx_tag,
1263 txd->tx_dmamap = NULL;
1266 bus_dma_tag_destroy(sc->nge_cdata.nge_tx_tag);
1267 sc->nge_cdata.nge_tx_tag = NULL;
1270 if (sc->nge_cdata.nge_rx_tag) {
1271 for (i = 0; i < NGE_RX_RING_CNT; i++) {
1272 rxd = &sc->nge_cdata.nge_rxdesc[i];
1273 if (rxd->rx_dmamap) {
1274 bus_dmamap_destroy(sc->nge_cdata.nge_rx_tag,
1276 rxd->rx_dmamap = NULL;
1279 if (sc->nge_cdata.nge_rx_sparemap) {
1280 bus_dmamap_destroy(sc->nge_cdata.nge_rx_tag,
1281 sc->nge_cdata.nge_rx_sparemap);
1282 sc->nge_cdata.nge_rx_sparemap = 0;
1284 bus_dma_tag_destroy(sc->nge_cdata.nge_rx_tag);
1285 sc->nge_cdata.nge_rx_tag = NULL;
1288 if (sc->nge_cdata.nge_parent_tag) {
1289 bus_dma_tag_destroy(sc->nge_cdata.nge_parent_tag);
1290 sc->nge_cdata.nge_parent_tag = NULL;
1295 * Initialize the transmit descriptors.
1298 nge_list_tx_init(struct nge_softc *sc)
1300 struct nge_ring_data *rd;
1301 struct nge_txdesc *txd;
1305 sc->nge_cdata.nge_tx_prod = 0;
1306 sc->nge_cdata.nge_tx_cons = 0;
1307 sc->nge_cdata.nge_tx_cnt = 0;
1309 rd = &sc->nge_rdata;
1310 bzero(rd->nge_tx_ring, sizeof(struct nge_desc) * NGE_TX_RING_CNT);
1311 for (i = 0; i < NGE_TX_RING_CNT; i++) {
1312 if (i == NGE_TX_RING_CNT - 1)
1313 addr = NGE_TX_RING_ADDR(sc, 0);
1315 addr = NGE_TX_RING_ADDR(sc, i + 1);
1316 rd->nge_tx_ring[i].nge_next = htole32(NGE_ADDR_LO(addr));
1317 txd = &sc->nge_cdata.nge_txdesc[i];
1321 bus_dmamap_sync(sc->nge_cdata.nge_tx_ring_tag,
1322 sc->nge_cdata.nge_tx_ring_map,
1323 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1329 * Initialize the RX descriptors and allocate mbufs for them. Note that
1330 * we arrange the descriptors in a closed ring, so that the last descriptor
1331 * points back to the first.
1334 nge_list_rx_init(struct nge_softc *sc)
1336 struct nge_ring_data *rd;
1340 sc->nge_cdata.nge_rx_cons = 0;
1341 sc->nge_head = sc->nge_tail = NULL;
1343 rd = &sc->nge_rdata;
1344 bzero(rd->nge_rx_ring, sizeof(struct nge_desc) * NGE_RX_RING_CNT);
1345 for (i = 0; i < NGE_RX_RING_CNT; i++) {
1346 if (nge_newbuf(sc, i) != 0)
1348 if (i == NGE_RX_RING_CNT - 1)
1349 addr = NGE_RX_RING_ADDR(sc, 0);
1351 addr = NGE_RX_RING_ADDR(sc, i + 1);
1352 rd->nge_rx_ring[i].nge_next = htole32(NGE_ADDR_LO(addr));
1355 bus_dmamap_sync(sc->nge_cdata.nge_rx_ring_tag,
1356 sc->nge_cdata.nge_rx_ring_map,
1357 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1362 static __inline void
1363 nge_discard_rxbuf(struct nge_softc *sc, int idx)
1365 struct nge_desc *desc;
1367 desc = &sc->nge_rdata.nge_rx_ring[idx];
1368 desc->nge_cmdsts = htole32(MCLBYTES - sizeof(uint64_t));
1369 desc->nge_extsts = 0;
1373 * Initialize an RX descriptor and attach an MBUF cluster.
1376 nge_newbuf(struct nge_softc *sc, int idx)
1378 struct nge_desc *desc;
1379 struct nge_rxdesc *rxd;
1381 bus_dma_segment_t segs[1];
1385 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1388 m->m_len = m->m_pkthdr.len = MCLBYTES;
1389 m_adj(m, sizeof(uint64_t));
1391 if (bus_dmamap_load_mbuf_sg(sc->nge_cdata.nge_rx_tag,
1392 sc->nge_cdata.nge_rx_sparemap, m, segs, &nsegs, 0) != 0) {
1396 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1398 rxd = &sc->nge_cdata.nge_rxdesc[idx];
1399 if (rxd->rx_m != NULL) {
1400 bus_dmamap_sync(sc->nge_cdata.nge_rx_tag, rxd->rx_dmamap,
1401 BUS_DMASYNC_POSTREAD);
1402 bus_dmamap_unload(sc->nge_cdata.nge_rx_tag, rxd->rx_dmamap);
1404 map = rxd->rx_dmamap;
1405 rxd->rx_dmamap = sc->nge_cdata.nge_rx_sparemap;
1406 sc->nge_cdata.nge_rx_sparemap = map;
1407 bus_dmamap_sync(sc->nge_cdata.nge_rx_tag, rxd->rx_dmamap,
1408 BUS_DMASYNC_PREREAD);
1410 desc = &sc->nge_rdata.nge_rx_ring[idx];
1411 desc->nge_ptr = htole32(NGE_ADDR_LO(segs[0].ds_addr));
1412 desc->nge_cmdsts = htole32(segs[0].ds_len);
1413 desc->nge_extsts = 0;
1418 #ifndef __NO_STRICT_ALIGNMENT
1419 static __inline void
1420 nge_fixup_rx(struct mbuf *m)
1423 uint16_t *src, *dst;
1425 src = mtod(m, uint16_t *);
1428 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
1431 m->m_data -= ETHER_ALIGN;
1436 * A frame has been uploaded: pass the resulting mbuf chain up to
1437 * the higher level protocols.
1440 nge_rxeof(struct nge_softc *sc)
1444 struct nge_desc *cur_rx;
1445 struct nge_rxdesc *rxd;
1446 int cons, prog, rx_npkts, total_len;
1447 uint32_t cmdsts, extsts;
1449 NGE_LOCK_ASSERT(sc);
1452 cons = sc->nge_cdata.nge_rx_cons;
1455 bus_dmamap_sync(sc->nge_cdata.nge_rx_ring_tag,
1456 sc->nge_cdata.nge_rx_ring_map,
1457 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1459 for (prog = 0; prog < NGE_RX_RING_CNT &&
1460 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0;
1461 NGE_INC(cons, NGE_RX_RING_CNT)) {
1462 #ifdef DEVICE_POLLING
1463 if (ifp->if_capenable & IFCAP_POLLING) {
1464 if (sc->rxcycles <= 0)
1469 cur_rx = &sc->nge_rdata.nge_rx_ring[cons];
1470 cmdsts = le32toh(cur_rx->nge_cmdsts);
1471 extsts = le32toh(cur_rx->nge_extsts);
1472 if ((cmdsts & NGE_CMDSTS_OWN) == 0)
1475 rxd = &sc->nge_cdata.nge_rxdesc[cons];
1477 total_len = cmdsts & NGE_CMDSTS_BUFLEN;
1479 if ((cmdsts & NGE_CMDSTS_MORE) != 0) {
1480 if (nge_newbuf(sc, cons) != 0) {
1481 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
1482 if (sc->nge_head != NULL) {
1483 m_freem(sc->nge_head);
1484 sc->nge_head = sc->nge_tail = NULL;
1486 nge_discard_rxbuf(sc, cons);
1489 m->m_len = total_len;
1490 if (sc->nge_head == NULL) {
1491 m->m_pkthdr.len = total_len;
1492 sc->nge_head = sc->nge_tail = m;
1494 m->m_flags &= ~M_PKTHDR;
1495 sc->nge_head->m_pkthdr.len += total_len;
1496 sc->nge_tail->m_next = m;
1503 * If an error occurs, update stats, clear the
1504 * status word and leave the mbuf cluster in place:
1505 * it should simply get re-used next time this descriptor
1506 * comes up in the ring.
1508 if ((cmdsts & NGE_CMDSTS_PKT_OK) == 0) {
1509 if ((cmdsts & NGE_RXSTAT_RUNT) &&
1510 total_len >= (ETHER_MIN_LEN - ETHER_CRC_LEN - 4)) {
1512 * Work-around hardware bug, accept runt frames
1513 * if its length is larger than or equal to 56.
1517 * Input error counters are updated by hardware.
1519 if (sc->nge_head != NULL) {
1520 m_freem(sc->nge_head);
1521 sc->nge_head = sc->nge_tail = NULL;
1523 nge_discard_rxbuf(sc, cons);
1528 /* Try conjure up a replacement mbuf. */
1530 if (nge_newbuf(sc, cons) != 0) {
1531 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
1532 if (sc->nge_head != NULL) {
1533 m_freem(sc->nge_head);
1534 sc->nge_head = sc->nge_tail = NULL;
1536 nge_discard_rxbuf(sc, cons);
1540 /* Chain received mbufs. */
1541 if (sc->nge_head != NULL) {
1542 m->m_len = total_len;
1543 m->m_flags &= ~M_PKTHDR;
1544 sc->nge_tail->m_next = m;
1546 m->m_pkthdr.len += total_len;
1547 sc->nge_head = sc->nge_tail = NULL;
1549 m->m_pkthdr.len = m->m_len = total_len;
1552 * Ok. NatSemi really screwed up here. This is the
1553 * only gigE chip I know of with alignment constraints
1554 * on receive buffers. RX buffers must be 64-bit aligned.
1557 * By popular demand, ignore the alignment problems
1558 * on the non-strict alignment platform. The performance hit
1559 * incurred due to unaligned accesses is much smaller
1560 * than the hit produced by forcing buffer copies all
1561 * the time, especially with jumbo frames. We still
1562 * need to fix up the alignment everywhere else though.
1564 #ifndef __NO_STRICT_ALIGNMENT
1567 m->m_pkthdr.rcvif = ifp;
1568 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
1570 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) {
1571 /* Do IP checksum checking. */
1572 if ((extsts & NGE_RXEXTSTS_IPPKT) != 0)
1573 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1574 if ((extsts & NGE_RXEXTSTS_IPCSUMERR) == 0)
1575 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1576 if ((extsts & NGE_RXEXTSTS_TCPPKT &&
1577 !(extsts & NGE_RXEXTSTS_TCPCSUMERR)) ||
1578 (extsts & NGE_RXEXTSTS_UDPPKT &&
1579 !(extsts & NGE_RXEXTSTS_UDPCSUMERR))) {
1580 m->m_pkthdr.csum_flags |=
1581 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
1582 m->m_pkthdr.csum_data = 0xffff;
1587 * If we received a packet with a vlan tag, pass it
1588 * to vlan_input() instead of ether_input().
1590 if ((extsts & NGE_RXEXTSTS_VLANPKT) != 0 &&
1591 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) {
1592 m->m_pkthdr.ether_vtag =
1593 bswap16(extsts & NGE_RXEXTSTS_VTCI);
1594 m->m_flags |= M_VLANTAG;
1597 (*ifp->if_input)(ifp, m);
1603 sc->nge_cdata.nge_rx_cons = cons;
1604 bus_dmamap_sync(sc->nge_cdata.nge_rx_ring_tag,
1605 sc->nge_cdata.nge_rx_ring_map,
1606 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1612 * A frame was downloaded to the chip. It's safe for us to clean up
1616 nge_txeof(struct nge_softc *sc)
1618 struct nge_desc *cur_tx;
1619 struct nge_txdesc *txd;
1624 NGE_LOCK_ASSERT(sc);
1627 cons = sc->nge_cdata.nge_tx_cons;
1628 prod = sc->nge_cdata.nge_tx_prod;
1632 bus_dmamap_sync(sc->nge_cdata.nge_tx_ring_tag,
1633 sc->nge_cdata.nge_tx_ring_map,
1634 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1637 * Go through our tx list and free mbufs for those
1638 * frames that have been transmitted.
1640 for (; cons != prod; NGE_INC(cons, NGE_TX_RING_CNT)) {
1641 cur_tx = &sc->nge_rdata.nge_tx_ring[cons];
1642 cmdsts = le32toh(cur_tx->nge_cmdsts);
1643 if ((cmdsts & NGE_CMDSTS_OWN) != 0)
1645 sc->nge_cdata.nge_tx_cnt--;
1646 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1647 if ((cmdsts & NGE_CMDSTS_MORE) != 0)
1650 txd = &sc->nge_cdata.nge_txdesc[cons];
1651 bus_dmamap_sync(sc->nge_cdata.nge_tx_tag, txd->tx_dmamap,
1652 BUS_DMASYNC_POSTWRITE);
1653 bus_dmamap_unload(sc->nge_cdata.nge_tx_tag, txd->tx_dmamap);
1654 if ((cmdsts & NGE_CMDSTS_PKT_OK) == 0) {
1655 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1656 if ((cmdsts & NGE_TXSTAT_EXCESSCOLLS) != 0)
1657 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
1658 if ((cmdsts & NGE_TXSTAT_OUTOFWINCOLL) != 0)
1659 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
1661 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
1663 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, (cmdsts & NGE_TXSTAT_COLLCNT) >> 16);
1664 KASSERT(txd->tx_m != NULL, ("%s: freeing NULL mbuf!\n",
1670 sc->nge_cdata.nge_tx_cons = cons;
1671 if (sc->nge_cdata.nge_tx_cnt == 0)
1672 sc->nge_watchdog_timer = 0;
1678 struct nge_softc *sc;
1679 struct mii_data *mii;
1682 NGE_LOCK_ASSERT(sc);
1683 mii = device_get_softc(sc->nge_miibus);
1686 * For PHYs that does not reset established link, it is
1687 * necessary to check whether driver still have a valid
1688 * link(e.g link state change callback is not called).
1689 * Otherwise, driver think it lost link because driver
1690 * initialization routine clears link state flag.
1692 if ((sc->nge_flags & NGE_FLAG_LINK) == 0)
1693 nge_miibus_statchg(sc->nge_dev);
1694 nge_stats_update(sc);
1696 callout_reset(&sc->nge_stat_ch, hz, nge_tick, sc);
1700 nge_stats_update(struct nge_softc *sc)
1703 struct nge_stats now, *stats, *nstats;
1705 NGE_LOCK_ASSERT(sc);
1709 stats->rx_pkts_errs =
1710 CSR_READ_4(sc, NGE_MIB_RXERRPKT) & 0xFFFF;
1711 stats->rx_crc_errs =
1712 CSR_READ_4(sc, NGE_MIB_RXERRFCS) & 0xFFFF;
1713 stats->rx_fifo_oflows =
1714 CSR_READ_4(sc, NGE_MIB_RXERRMISSEDPKT) & 0xFFFF;
1715 stats->rx_align_errs =
1716 CSR_READ_4(sc, NGE_MIB_RXERRALIGN) & 0xFFFF;
1717 stats->rx_sym_errs =
1718 CSR_READ_4(sc, NGE_MIB_RXERRSYM) & 0xFFFF;
1719 stats->rx_pkts_jumbos =
1720 CSR_READ_4(sc, NGE_MIB_RXERRGIANT) & 0xFFFF;
1721 stats->rx_len_errs =
1722 CSR_READ_4(sc, NGE_MIB_RXERRRANGLEN) & 0xFFFF;
1723 stats->rx_unctl_frames =
1724 CSR_READ_4(sc, NGE_MIB_RXBADOPCODE) & 0xFFFF;
1726 CSR_READ_4(sc, NGE_MIB_RXPAUSEPKTS) & 0xFFFF;
1728 CSR_READ_4(sc, NGE_MIB_TXPAUSEPKTS) & 0xFFFF;
1729 stats->tx_seq_errs =
1730 CSR_READ_4(sc, NGE_MIB_TXERRSQE) & 0xFF;
1733 * Since we've accept errored frames exclude Rx length errors.
1735 if_inc_counter(ifp, IFCOUNTER_IERRORS,
1736 stats->rx_pkts_errs + stats->rx_crc_errs +
1737 stats->rx_fifo_oflows + stats->rx_sym_errs);
1739 nstats = &sc->nge_stats;
1740 nstats->rx_pkts_errs += stats->rx_pkts_errs;
1741 nstats->rx_crc_errs += stats->rx_crc_errs;
1742 nstats->rx_fifo_oflows += stats->rx_fifo_oflows;
1743 nstats->rx_align_errs += stats->rx_align_errs;
1744 nstats->rx_sym_errs += stats->rx_sym_errs;
1745 nstats->rx_pkts_jumbos += stats->rx_pkts_jumbos;
1746 nstats->rx_len_errs += stats->rx_len_errs;
1747 nstats->rx_unctl_frames += stats->rx_unctl_frames;
1748 nstats->rx_pause += stats->rx_pause;
1749 nstats->tx_pause += stats->tx_pause;
1750 nstats->tx_seq_errs += stats->tx_seq_errs;
1753 #ifdef DEVICE_POLLING
1754 static poll_handler_t nge_poll;
1757 nge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1759 struct nge_softc *sc;
1765 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1771 * On the nge, reading the status register also clears it.
1772 * So before returning to intr mode we must make sure that all
1773 * possible pending sources of interrupts have been served.
1774 * In practice this means run to completion the *eof routines,
1775 * and then call the interrupt routine.
1777 sc->rxcycles = count;
1778 rx_npkts = nge_rxeof(sc);
1780 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1781 nge_start_locked(ifp);
1783 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) {
1786 /* Reading the ISR register clears all interrupts. */
1787 status = CSR_READ_4(sc, NGE_ISR);
1789 if ((status & (NGE_ISR_RX_ERR|NGE_ISR_RX_OFLOW)) != 0)
1790 rx_npkts += nge_rxeof(sc);
1792 if ((status & NGE_ISR_RX_IDLE) != 0)
1793 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE);
1795 if ((status & NGE_ISR_SYSERR) != 0) {
1796 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1797 nge_init_locked(sc);
1803 #endif /* DEVICE_POLLING */
1808 struct nge_softc *sc;
1812 sc = (struct nge_softc *)arg;
1817 if ((sc->nge_flags & NGE_FLAG_SUSPENDED) != 0)
1820 /* Reading the ISR register clears all interrupts. */
1821 status = CSR_READ_4(sc, NGE_ISR);
1822 if (status == 0xffffffff || (status & NGE_INTRS) == 0)
1824 #ifdef DEVICE_POLLING
1825 if ((ifp->if_capenable & IFCAP_POLLING) != 0)
1828 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1831 /* Disable interrupts. */
1832 CSR_WRITE_4(sc, NGE_IER, 0);
1834 /* Data LED on for TBI mode */
1835 if ((sc->nge_flags & NGE_FLAG_TBI) != 0)
1836 CSR_WRITE_4(sc, NGE_GPIO,
1837 CSR_READ_4(sc, NGE_GPIO) | NGE_GPIO_GP3_OUT);
1839 for (; (status & NGE_INTRS) != 0;) {
1840 if ((status & (NGE_ISR_TX_DESC_OK | NGE_ISR_TX_ERR |
1841 NGE_ISR_TX_OK | NGE_ISR_TX_IDLE)) != 0)
1844 if ((status & (NGE_ISR_RX_DESC_OK | NGE_ISR_RX_ERR |
1845 NGE_ISR_RX_OFLOW | NGE_ISR_RX_FIFO_OFLOW |
1846 NGE_ISR_RX_IDLE | NGE_ISR_RX_OK)) != 0)
1849 if ((status & NGE_ISR_RX_IDLE) != 0)
1850 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE);
1852 if ((status & NGE_ISR_SYSERR) != 0) {
1853 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1854 nge_init_locked(sc);
1856 /* Reading the ISR register clears all interrupts. */
1857 status = CSR_READ_4(sc, NGE_ISR);
1860 /* Re-enable interrupts. */
1861 CSR_WRITE_4(sc, NGE_IER, 1);
1863 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1864 nge_start_locked(ifp);
1866 /* Data LED off for TBI mode */
1867 if ((sc->nge_flags & NGE_FLAG_TBI) != 0)
1868 CSR_WRITE_4(sc, NGE_GPIO,
1869 CSR_READ_4(sc, NGE_GPIO) & ~NGE_GPIO_GP3_OUT);
1876 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1877 * pointers to the fragment pointers.
1880 nge_encap(struct nge_softc *sc, struct mbuf **m_head)
1882 struct nge_txdesc *txd, *txd_last;
1883 struct nge_desc *desc;
1886 bus_dma_segment_t txsegs[NGE_MAXTXSEGS];
1887 int error, i, nsegs, prod, si;
1889 NGE_LOCK_ASSERT(sc);
1892 prod = sc->nge_cdata.nge_tx_prod;
1893 txd = &sc->nge_cdata.nge_txdesc[prod];
1895 map = txd->tx_dmamap;
1896 error = bus_dmamap_load_mbuf_sg(sc->nge_cdata.nge_tx_tag, map,
1897 *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT);
1898 if (error == EFBIG) {
1899 m = m_collapse(*m_head, M_NOWAIT, NGE_MAXTXSEGS);
1906 error = bus_dmamap_load_mbuf_sg(sc->nge_cdata.nge_tx_tag,
1907 map, *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT);
1913 } else if (error != 0)
1921 /* Check number of available descriptors. */
1922 if (sc->nge_cdata.nge_tx_cnt + nsegs >= (NGE_TX_RING_CNT - 1)) {
1923 bus_dmamap_unload(sc->nge_cdata.nge_tx_tag, map);
1927 bus_dmamap_sync(sc->nge_cdata.nge_tx_tag, map, BUS_DMASYNC_PREWRITE);
1930 for (i = 0; i < nsegs; i++) {
1931 desc = &sc->nge_rdata.nge_tx_ring[prod];
1932 desc->nge_ptr = htole32(NGE_ADDR_LO(txsegs[i].ds_addr));
1934 desc->nge_cmdsts = htole32(txsegs[i].ds_len |
1937 desc->nge_cmdsts = htole32(txsegs[i].ds_len |
1938 NGE_CMDSTS_MORE | NGE_CMDSTS_OWN);
1939 desc->nge_extsts = 0;
1940 sc->nge_cdata.nge_tx_cnt++;
1941 NGE_INC(prod, NGE_TX_RING_CNT);
1943 /* Update producer index. */
1944 sc->nge_cdata.nge_tx_prod = prod;
1946 prod = (prod + NGE_TX_RING_CNT - 1) % NGE_TX_RING_CNT;
1947 desc = &sc->nge_rdata.nge_tx_ring[prod];
1948 /* Check if we have a VLAN tag to insert. */
1949 if ((m->m_flags & M_VLANTAG) != 0)
1950 desc->nge_extsts |= htole32(NGE_TXEXTSTS_VLANPKT |
1951 bswap16(m->m_pkthdr.ether_vtag));
1952 /* Set EOP on the last desciptor. */
1953 desc->nge_cmdsts &= htole32(~NGE_CMDSTS_MORE);
1955 /* Set checksum offload in the first descriptor. */
1956 desc = &sc->nge_rdata.nge_tx_ring[si];
1957 if ((m->m_pkthdr.csum_flags & NGE_CSUM_FEATURES) != 0) {
1958 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0)
1959 desc->nge_extsts |= htole32(NGE_TXEXTSTS_IPCSUM);
1960 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0)
1961 desc->nge_extsts |= htole32(NGE_TXEXTSTS_TCPCSUM);
1962 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0)
1963 desc->nge_extsts |= htole32(NGE_TXEXTSTS_UDPCSUM);
1965 /* Lastly, turn the first descriptor ownership to hardware. */
1966 desc->nge_cmdsts |= htole32(NGE_CMDSTS_OWN);
1968 txd = &sc->nge_cdata.nge_txdesc[prod];
1969 map = txd_last->tx_dmamap;
1970 txd_last->tx_dmamap = txd->tx_dmamap;
1971 txd->tx_dmamap = map;
1978 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1979 * to the mbuf data regions directly in the transmit lists. We also save a
1980 * copy of the pointers since the transmit list fragment pointers are
1981 * physical addresses.
1985 nge_start(struct ifnet *ifp)
1987 struct nge_softc *sc;
1991 nge_start_locked(ifp);
1996 nge_start_locked(struct ifnet *ifp)
1998 struct nge_softc *sc;
1999 struct mbuf *m_head;
2004 NGE_LOCK_ASSERT(sc);
2006 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
2007 IFF_DRV_RUNNING || (sc->nge_flags & NGE_FLAG_LINK) == 0)
2010 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
2011 sc->nge_cdata.nge_tx_cnt < NGE_TX_RING_CNT - 2; ) {
2012 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2016 * Pack the data into the transmit ring. If we
2017 * don't have room, set the OACTIVE flag and wait
2018 * for the NIC to drain the ring.
2020 if (nge_encap(sc, &m_head)) {
2023 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2024 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2030 * If there's a BPF listener, bounce a copy of this frame
2033 ETHER_BPF_MTAP(ifp, m_head);
2037 bus_dmamap_sync(sc->nge_cdata.nge_tx_ring_tag,
2038 sc->nge_cdata.nge_tx_ring_map,
2039 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2041 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_ENABLE);
2043 /* Set a timeout in case the chip goes out to lunch. */
2044 sc->nge_watchdog_timer = 5;
2051 struct nge_softc *sc = xsc;
2054 nge_init_locked(sc);
2059 nge_init_locked(struct nge_softc *sc)
2061 struct ifnet *ifp = sc->nge_ifp;
2062 struct mii_data *mii;
2066 NGE_LOCK_ASSERT(sc);
2068 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2072 * Cancel pending I/O and free all RX/TX buffers.
2076 /* Reset the adapter. */
2079 /* Disable Rx filter prior to programming Rx filter. */
2080 CSR_WRITE_4(sc, NGE_RXFILT_CTL, 0);
2081 CSR_BARRIER_4(sc, NGE_RXFILT_CTL, BUS_SPACE_BARRIER_WRITE);
2083 mii = device_get_softc(sc->nge_miibus);
2085 /* Set MAC address. */
2086 eaddr = IF_LLADDR(sc->nge_ifp);
2087 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR0);
2088 CSR_WRITE_4(sc, NGE_RXFILT_DATA, (eaddr[1] << 8) | eaddr[0]);
2089 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR1);
2090 CSR_WRITE_4(sc, NGE_RXFILT_DATA, (eaddr[3] << 8) | eaddr[2]);
2091 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR2);
2092 CSR_WRITE_4(sc, NGE_RXFILT_DATA, (eaddr[5] << 8) | eaddr[4]);
2094 /* Init circular RX list. */
2095 if (nge_list_rx_init(sc) == ENOBUFS) {
2096 device_printf(sc->nge_dev, "initialization failed: no "
2097 "memory for rx buffers\n");
2103 * Init tx descriptors.
2105 nge_list_tx_init(sc);
2107 /* Set Rx filter. */
2110 /* Disable PRIQ ctl. */
2111 CSR_WRITE_4(sc, NGE_PRIOQCTL, 0);
2114 * Set pause frames parameters.
2115 * Rx stat FIFO hi-threshold : 2 or more packets
2116 * Rx stat FIFO lo-threshold : less than 2 packets
2117 * Rx data FIFO hi-threshold : 2K or more bytes
2118 * Rx data FIFO lo-threshold : less than 2K bytes
2119 * pause time : (512ns * 0xffff) -> 33.55ms
2121 CSR_WRITE_4(sc, NGE_PAUSECSR,
2122 NGE_PAUSECSR_PAUSE_ON_MCAST |
2123 NGE_PAUSECSR_PAUSE_ON_DA |
2124 ((1 << 24) & NGE_PAUSECSR_RX_STATFIFO_THR_HI) |
2125 ((1 << 22) & NGE_PAUSECSR_RX_STATFIFO_THR_LO) |
2126 ((1 << 20) & NGE_PAUSECSR_RX_DATAFIFO_THR_HI) |
2127 ((1 << 18) & NGE_PAUSECSR_RX_DATAFIFO_THR_LO) |
2131 * Load the address of the RX and TX lists.
2133 CSR_WRITE_4(sc, NGE_RX_LISTPTR_HI,
2134 NGE_ADDR_HI(sc->nge_rdata.nge_rx_ring_paddr));
2135 CSR_WRITE_4(sc, NGE_RX_LISTPTR_LO,
2136 NGE_ADDR_LO(sc->nge_rdata.nge_rx_ring_paddr));
2137 CSR_WRITE_4(sc, NGE_TX_LISTPTR_HI,
2138 NGE_ADDR_HI(sc->nge_rdata.nge_tx_ring_paddr));
2139 CSR_WRITE_4(sc, NGE_TX_LISTPTR_LO,
2140 NGE_ADDR_LO(sc->nge_rdata.nge_tx_ring_paddr));
2142 /* Set RX configuration. */
2143 CSR_WRITE_4(sc, NGE_RX_CFG, NGE_RXCFG);
2145 CSR_WRITE_4(sc, NGE_VLAN_IP_RXCTL, 0);
2147 * Enable hardware checksum validation for all IPv4
2148 * packets, do not reject packets with bad checksums.
2150 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
2151 NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_IPCSUM_ENB);
2154 * Tell the chip to detect and strip VLAN tag info from
2155 * received frames. The tag will be provided in the extsts
2156 * field in the RX descriptors.
2158 NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_TAG_DETECT_ENB);
2159 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
2160 NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_TAG_STRIP_ENB);
2162 /* Set TX configuration. */
2163 CSR_WRITE_4(sc, NGE_TX_CFG, NGE_TXCFG);
2166 * Enable TX IPv4 checksumming on a per-packet basis.
2168 CSR_WRITE_4(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_CSUM_PER_PKT);
2171 * Tell the chip to insert VLAN tags on a per-packet basis as
2172 * dictated by the code in the frame encapsulation routine.
2174 NGE_SETBIT(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_TAG_PER_PKT);
2177 * Enable the delivery of PHY interrupts based on
2178 * link/speed/duplex status changes. Also enable the
2179 * extsts field in the DMA descriptors (needed for
2180 * TCP/IP checksum offload on transmit).
2182 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_PHYINTR_SPD |
2183 NGE_CFG_PHYINTR_LNK | NGE_CFG_PHYINTR_DUP | NGE_CFG_EXTSTS_ENB);
2186 * Configure interrupt holdoff (moderation). We can
2187 * have the chip delay interrupt delivery for a certain
2188 * period. Units are in 100us, and the max setting
2189 * is 25500us (0xFF x 100us). Default is a 100us holdoff.
2191 CSR_WRITE_4(sc, NGE_IHR, sc->nge_int_holdoff);
2194 * Enable MAC statistics counters and clear.
2196 reg = CSR_READ_4(sc, NGE_MIBCTL);
2197 reg &= ~NGE_MIBCTL_FREEZE_CNT;
2198 reg |= NGE_MIBCTL_CLEAR_CNT;
2199 CSR_WRITE_4(sc, NGE_MIBCTL, reg);
2202 * Enable interrupts.
2204 CSR_WRITE_4(sc, NGE_IMR, NGE_INTRS);
2205 #ifdef DEVICE_POLLING
2207 * ... only enable interrupts if we are not polling, make sure
2208 * they are off otherwise.
2210 if ((ifp->if_capenable & IFCAP_POLLING) != 0)
2211 CSR_WRITE_4(sc, NGE_IER, 0);
2214 CSR_WRITE_4(sc, NGE_IER, 1);
2216 sc->nge_flags &= ~NGE_FLAG_LINK;
2219 sc->nge_watchdog_timer = 0;
2220 callout_reset(&sc->nge_stat_ch, hz, nge_tick, sc);
2222 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2223 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2227 * Set media options.
2230 nge_mediachange(struct ifnet *ifp)
2232 struct nge_softc *sc;
2233 struct mii_data *mii;
2234 struct mii_softc *miisc;
2239 mii = device_get_softc(sc->nge_miibus);
2240 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
2242 error = mii_mediachg(mii);
2249 * Report current media status.
2252 nge_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
2254 struct nge_softc *sc;
2255 struct mii_data *mii;
2259 mii = device_get_softc(sc->nge_miibus);
2261 ifmr->ifm_active = mii->mii_media_active;
2262 ifmr->ifm_status = mii->mii_media_status;
2267 nge_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2269 struct nge_softc *sc = ifp->if_softc;
2270 struct ifreq *ifr = (struct ifreq *) data;
2271 struct mii_data *mii;
2272 int error = 0, mask;
2276 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > NGE_JUMBO_MTU)
2280 ifp->if_mtu = ifr->ifr_mtu;
2282 * Workaround: if the MTU is larger than
2283 * 8152 (TX FIFO size minus 64 minus 18), turn off
2284 * TX checksum offloading.
2286 if (ifr->ifr_mtu >= 8152) {
2287 ifp->if_capenable &= ~IFCAP_TXCSUM;
2288 ifp->if_hwassist &= ~NGE_CSUM_FEATURES;
2290 ifp->if_capenable |= IFCAP_TXCSUM;
2291 ifp->if_hwassist |= NGE_CSUM_FEATURES;
2294 VLAN_CAPABILITIES(ifp);
2299 if ((ifp->if_flags & IFF_UP) != 0) {
2300 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2301 if ((ifp->if_flags ^ sc->nge_if_flags) &
2302 (IFF_PROMISC | IFF_ALLMULTI))
2305 if ((sc->nge_flags & NGE_FLAG_DETACH) == 0)
2306 nge_init_locked(sc);
2309 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2312 sc->nge_if_flags = ifp->if_flags;
2319 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2325 mii = device_get_softc(sc->nge_miibus);
2326 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2330 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2331 #ifdef DEVICE_POLLING
2332 if ((mask & IFCAP_POLLING) != 0 &&
2333 (IFCAP_POLLING & ifp->if_capabilities) != 0) {
2334 ifp->if_capenable ^= IFCAP_POLLING;
2335 if ((IFCAP_POLLING & ifp->if_capenable) != 0) {
2336 error = ether_poll_register(nge_poll, ifp);
2341 /* Disable interrupts. */
2342 CSR_WRITE_4(sc, NGE_IER, 0);
2344 error = ether_poll_deregister(ifp);
2345 /* Enable interrupts. */
2346 CSR_WRITE_4(sc, NGE_IER, 1);
2349 #endif /* DEVICE_POLLING */
2350 if ((mask & IFCAP_TXCSUM) != 0 &&
2351 (IFCAP_TXCSUM & ifp->if_capabilities) != 0) {
2352 ifp->if_capenable ^= IFCAP_TXCSUM;
2353 if ((IFCAP_TXCSUM & ifp->if_capenable) != 0)
2354 ifp->if_hwassist |= NGE_CSUM_FEATURES;
2356 ifp->if_hwassist &= ~NGE_CSUM_FEATURES;
2358 if ((mask & IFCAP_RXCSUM) != 0 &&
2359 (IFCAP_RXCSUM & ifp->if_capabilities) != 0)
2360 ifp->if_capenable ^= IFCAP_RXCSUM;
2362 if ((mask & IFCAP_WOL) != 0 &&
2363 (ifp->if_capabilities & IFCAP_WOL) != 0) {
2364 if ((mask & IFCAP_WOL_UCAST) != 0)
2365 ifp->if_capenable ^= IFCAP_WOL_UCAST;
2366 if ((mask & IFCAP_WOL_MCAST) != 0)
2367 ifp->if_capenable ^= IFCAP_WOL_MCAST;
2368 if ((mask & IFCAP_WOL_MAGIC) != 0)
2369 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2372 if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
2373 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0)
2374 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
2375 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
2376 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
2377 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2378 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2379 if ((ifp->if_capenable &
2380 IFCAP_VLAN_HWTAGGING) != 0)
2383 NGE_VIPRXCTL_TAG_STRIP_ENB);
2387 NGE_VIPRXCTL_TAG_STRIP_ENB);
2391 * Both VLAN hardware tagging and checksum offload is
2392 * required to do checksum offload on VLAN interface.
2394 if ((ifp->if_capenable & IFCAP_TXCSUM) == 0)
2395 ifp->if_capenable &= ~IFCAP_VLAN_HWCSUM;
2396 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0)
2397 ifp->if_capenable &= ~IFCAP_VLAN_HWCSUM;
2399 VLAN_CAPABILITIES(ifp);
2402 error = ether_ioctl(ifp, command, data);
2410 nge_watchdog(struct nge_softc *sc)
2414 NGE_LOCK_ASSERT(sc);
2416 if (sc->nge_watchdog_timer == 0 || --sc->nge_watchdog_timer)
2420 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
2421 if_printf(ifp, "watchdog timeout\n");
2423 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2424 nge_init_locked(sc);
2426 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2427 nge_start_locked(ifp);
2431 nge_stop_mac(struct nge_softc *sc)
2436 NGE_LOCK_ASSERT(sc);
2438 reg = CSR_READ_4(sc, NGE_CSR);
2439 if ((reg & (NGE_CSR_TX_ENABLE | NGE_CSR_RX_ENABLE)) != 0) {
2440 reg &= ~(NGE_CSR_TX_ENABLE | NGE_CSR_RX_ENABLE);
2441 reg |= NGE_CSR_TX_DISABLE | NGE_CSR_RX_DISABLE;
2442 CSR_WRITE_4(sc, NGE_CSR, reg);
2443 for (i = 0; i < NGE_TIMEOUT; i++) {
2445 if ((CSR_READ_4(sc, NGE_CSR) &
2446 (NGE_CSR_RX_ENABLE | NGE_CSR_TX_ENABLE)) == 0)
2449 if (i == NGE_TIMEOUT)
2457 * Stop the adapter and free any mbufs allocated to the
2461 nge_stop(struct nge_softc *sc)
2463 struct nge_txdesc *txd;
2464 struct nge_rxdesc *rxd;
2468 NGE_LOCK_ASSERT(sc);
2471 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2472 sc->nge_flags &= ~NGE_FLAG_LINK;
2473 callout_stop(&sc->nge_stat_ch);
2474 sc->nge_watchdog_timer = 0;
2476 CSR_WRITE_4(sc, NGE_IER, 0);
2477 CSR_WRITE_4(sc, NGE_IMR, 0);
2478 if (nge_stop_mac(sc) == ETIMEDOUT)
2479 device_printf(sc->nge_dev,
2480 "%s: unable to stop Tx/Rx MAC\n", __func__);
2481 CSR_WRITE_4(sc, NGE_TX_LISTPTR_HI, 0);
2482 CSR_WRITE_4(sc, NGE_TX_LISTPTR_LO, 0);
2483 CSR_WRITE_4(sc, NGE_RX_LISTPTR_HI, 0);
2484 CSR_WRITE_4(sc, NGE_RX_LISTPTR_LO, 0);
2485 nge_stats_update(sc);
2486 if (sc->nge_head != NULL) {
2487 m_freem(sc->nge_head);
2488 sc->nge_head = sc->nge_tail = NULL;
2492 * Free RX and TX mbufs still in the queues.
2494 for (i = 0; i < NGE_RX_RING_CNT; i++) {
2495 rxd = &sc->nge_cdata.nge_rxdesc[i];
2496 if (rxd->rx_m != NULL) {
2497 bus_dmamap_sync(sc->nge_cdata.nge_rx_tag,
2498 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
2499 bus_dmamap_unload(sc->nge_cdata.nge_rx_tag,
2505 for (i = 0; i < NGE_TX_RING_CNT; i++) {
2506 txd = &sc->nge_cdata.nge_txdesc[i];
2507 if (txd->tx_m != NULL) {
2508 bus_dmamap_sync(sc->nge_cdata.nge_tx_tag,
2509 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2510 bus_dmamap_unload(sc->nge_cdata.nge_tx_tag,
2519 * Before setting WOL bits, caller should have stopped Receiver.
2522 nge_wol(struct nge_softc *sc)
2529 NGE_LOCK_ASSERT(sc);
2531 if (pci_find_cap(sc->nge_dev, PCIY_PMG, &pmc) != 0)
2535 if ((ifp->if_capenable & IFCAP_WOL) == 0) {
2536 /* Disable WOL & disconnect CLKRUN to save power. */
2537 CSR_WRITE_4(sc, NGE_WOLCSR, 0);
2538 CSR_WRITE_4(sc, NGE_CLKRUN, 0);
2540 if (nge_stop_mac(sc) == ETIMEDOUT)
2541 device_printf(sc->nge_dev,
2542 "%s: unable to stop Tx/Rx MAC\n", __func__);
2544 * Make sure wake frames will be buffered in the Rx FIFO.
2545 * (i.e. Silent Rx mode.)
2547 CSR_WRITE_4(sc, NGE_RX_LISTPTR_HI, 0);
2548 CSR_BARRIER_4(sc, NGE_RX_LISTPTR_HI, BUS_SPACE_BARRIER_WRITE);
2549 CSR_WRITE_4(sc, NGE_RX_LISTPTR_LO, 0);
2550 CSR_BARRIER_4(sc, NGE_RX_LISTPTR_LO, BUS_SPACE_BARRIER_WRITE);
2551 /* Enable Rx again. */
2552 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE);
2553 CSR_BARRIER_4(sc, NGE_CSR, BUS_SPACE_BARRIER_WRITE);
2555 /* Configure WOL events. */
2557 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0)
2558 reg |= NGE_WOLCSR_WAKE_ON_UNICAST;
2559 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0)
2560 reg |= NGE_WOLCSR_WAKE_ON_MULTICAST;
2561 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
2562 reg |= NGE_WOLCSR_WAKE_ON_MAGICPKT;
2563 CSR_WRITE_4(sc, NGE_WOLCSR, reg);
2565 /* Activate CLKRUN. */
2566 reg = CSR_READ_4(sc, NGE_CLKRUN);
2567 reg |= NGE_CLKRUN_PMEENB | NGE_CLNRUN_CLKRUN_ENB;
2568 CSR_WRITE_4(sc, NGE_CLKRUN, reg);
2572 pmstat = pci_read_config(sc->nge_dev, pmc + PCIR_POWER_STATUS, 2);
2573 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
2574 if ((ifp->if_capenable & IFCAP_WOL) != 0)
2575 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2576 pci_write_config(sc->nge_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
2580 * Stop all chip I/O so that the kernel's probe routines don't
2581 * get confused by errant DMAs when rebooting.
2584 nge_shutdown(device_t dev)
2587 return (nge_suspend(dev));
2591 nge_suspend(device_t dev)
2593 struct nge_softc *sc;
2595 sc = device_get_softc(dev);
2600 sc->nge_flags |= NGE_FLAG_SUSPENDED;
2607 nge_resume(device_t dev)
2609 struct nge_softc *sc;
2614 sc = device_get_softc(dev);
2618 if (pci_find_cap(sc->nge_dev, PCIY_PMG, &pmc) == 0) {
2619 /* Disable PME and clear PME status. */
2620 pmstat = pci_read_config(sc->nge_dev,
2621 pmc + PCIR_POWER_STATUS, 2);
2622 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) {
2623 pmstat &= ~PCIM_PSTAT_PMEENABLE;
2624 pci_write_config(sc->nge_dev,
2625 pmc + PCIR_POWER_STATUS, pmstat, 2);
2628 if (ifp->if_flags & IFF_UP) {
2629 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2630 nge_init_locked(sc);
2633 sc->nge_flags &= ~NGE_FLAG_SUSPENDED;
2639 #define NGE_SYSCTL_STAT_ADD32(c, h, n, p, d) \
2640 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
2643 nge_sysctl_node(struct nge_softc *sc)
2645 struct sysctl_ctx_list *ctx;
2646 struct sysctl_oid_list *child, *parent;
2647 struct sysctl_oid *tree;
2648 struct nge_stats *stats;
2651 ctx = device_get_sysctl_ctx(sc->nge_dev);
2652 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->nge_dev));
2653 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_holdoff",
2654 CTLTYPE_INT | CTLFLAG_RW, &sc->nge_int_holdoff, 0,
2655 sysctl_hw_nge_int_holdoff, "I", "NGE interrupt moderation");
2656 /* Pull in device tunables. */
2657 sc->nge_int_holdoff = NGE_INT_HOLDOFF_DEFAULT;
2658 error = resource_int_value(device_get_name(sc->nge_dev),
2659 device_get_unit(sc->nge_dev), "int_holdoff", &sc->nge_int_holdoff);
2661 if (sc->nge_int_holdoff < NGE_INT_HOLDOFF_MIN ||
2662 sc->nge_int_holdoff > NGE_INT_HOLDOFF_MAX ) {
2663 device_printf(sc->nge_dev,
2664 "int_holdoff value out of range; "
2665 "using default: %d(%d us)\n",
2666 NGE_INT_HOLDOFF_DEFAULT,
2667 NGE_INT_HOLDOFF_DEFAULT * 100);
2668 sc->nge_int_holdoff = NGE_INT_HOLDOFF_DEFAULT;
2672 stats = &sc->nge_stats;
2673 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD,
2674 NULL, "NGE statistics");
2675 parent = SYSCTL_CHILDREN(tree);
2677 /* Rx statistics. */
2678 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD,
2679 NULL, "Rx MAC statistics");
2680 child = SYSCTL_CHILDREN(tree);
2681 NGE_SYSCTL_STAT_ADD32(ctx, child, "pkts_errs",
2682 &stats->rx_pkts_errs,
2683 "Packet errors including both wire errors and FIFO overruns");
2684 NGE_SYSCTL_STAT_ADD32(ctx, child, "crc_errs",
2685 &stats->rx_crc_errs, "CRC errors");
2686 NGE_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows",
2687 &stats->rx_fifo_oflows, "FIFO overflows");
2688 NGE_SYSCTL_STAT_ADD32(ctx, child, "align_errs",
2689 &stats->rx_align_errs, "Frame alignment errors");
2690 NGE_SYSCTL_STAT_ADD32(ctx, child, "sym_errs",
2691 &stats->rx_sym_errs, "One or more symbol errors");
2692 NGE_SYSCTL_STAT_ADD32(ctx, child, "pkts_jumbos",
2693 &stats->rx_pkts_jumbos,
2694 "Packets received with length greater than 1518 bytes");
2695 NGE_SYSCTL_STAT_ADD32(ctx, child, "len_errs",
2696 &stats->rx_len_errs, "In Range Length errors");
2697 NGE_SYSCTL_STAT_ADD32(ctx, child, "unctl_frames",
2698 &stats->rx_unctl_frames, "Control frames with unsupported opcode");
2699 NGE_SYSCTL_STAT_ADD32(ctx, child, "pause",
2700 &stats->rx_pause, "Pause frames");
2702 /* Tx statistics. */
2703 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD,
2704 NULL, "Tx MAC statistics");
2705 child = SYSCTL_CHILDREN(tree);
2706 NGE_SYSCTL_STAT_ADD32(ctx, child, "pause",
2707 &stats->tx_pause, "Pause frames");
2708 NGE_SYSCTL_STAT_ADD32(ctx, child, "seq_errs",
2709 &stats->tx_seq_errs,
2710 "Loss of collision heartbeat during transmission");
2713 #undef NGE_SYSCTL_STAT_ADD32
2716 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
2722 value = *(int *)arg1;
2723 error = sysctl_handle_int(oidp, &value, 0, req);
2724 if (error != 0 || req->newptr == NULL)
2726 if (value < low || value > high)
2728 *(int *)arg1 = value;
2734 sysctl_hw_nge_int_holdoff(SYSCTL_HANDLER_ARGS)
2737 return (sysctl_int_range(oidp, arg1, arg2, req, NGE_INT_HOLDOFF_MIN,
2738 NGE_INT_HOLDOFF_MAX));