2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2000, 2001
4 * Bill Paul <wpaul@bsdi.com>. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
38 * National Semiconductor DP83820/DP83821 gigabit ethernet driver
39 * for FreeBSD. Datasheets are available from:
41 * http://www.national.com/ds/DP/DP83820.pdf
42 * http://www.national.com/ds/DP/DP83821.pdf
44 * These chips are used on several low cost gigabit ethernet NICs
45 * sold by D-Link, Addtron, SMC and Asante. Both parts are
46 * virtually the same, except the 83820 is a 64-bit/32-bit part,
47 * while the 83821 is 32-bit only.
49 * Many cards also use National gigE transceivers, such as the
50 * DP83891, DP83861 and DP83862 gigPHYTER parts. The DP83861 datasheet
51 * contains a full register description that applies to all of these
54 * http://www.national.com/ds/DP/DP83861.pdf
56 * Written by Bill Paul <wpaul@bsdi.com>
57 * BSDi Open Source Solutions
61 * The NatSemi DP83820 and 83821 controllers are enhanced versions
62 * of the NatSemi MacPHYTER 10/100 devices. They support 10, 100
63 * and 1000Mbps speeds with 1000baseX (ten bit interface), MII and GMII
64 * ports. Other features include 8K TX FIFO and 32K RX FIFO, TCP/IP
65 * hardware checksum offload (IPv4 only), VLAN tagging and filtering,
66 * priority TX and RX queues, a 2048 bit multicast hash filter, 4 RX pattern
67 * matching buffers, one perfect address filter buffer and interrupt
68 * moderation. The 83820 supports both 64-bit and 32-bit addressing
69 * and data transfers: the 64-bit support can be toggled on or off
70 * via software. This affects the size of certain fields in the DMA
73 * There are two bugs/misfeatures in the 83820/83821 that I have
76 * - Receive buffers must be aligned on 64-bit boundaries, which means
77 * you must resort to copying data in order to fix up the payload
80 * - In order to transmit jumbo frames larger than 8170 bytes, you have
81 * to turn off transmit checksum offloading, because the chip can't
82 * compute the checksum on an outgoing frame unless it fits entirely
83 * within the TX FIFO, which is only 8192 bytes in size. If you have
84 * TX checksum offload enabled and you transmit attempt to transmit a
85 * frame larger than 8170 bytes, the transmitter will wedge.
87 * To work around the latter problem, TX checksum offload is disabled
88 * if the user selects an MTU larger than 8152 (8170 - 18).
91 #ifdef HAVE_KERNEL_OPTION_HEADERS
92 #include "opt_device_polling.h"
95 #include <sys/param.h>
96 #include <sys/systm.h>
97 #include <sys/sockio.h>
99 #include <sys/malloc.h>
100 #include <sys/module.h>
101 #include <sys/kernel.h>
102 #include <sys/socket.h>
105 #include <net/if_arp.h>
106 #include <net/ethernet.h>
107 #include <net/if_dl.h>
108 #include <net/if_media.h>
109 #include <net/if_types.h>
110 #include <net/if_vlan_var.h>
114 #include <vm/vm.h> /* for vtophys */
115 #include <vm/pmap.h> /* for vtophys */
116 #include <machine/bus.h>
117 #include <machine/resource.h>
119 #include <sys/rman.h>
121 #include <dev/mii/mii.h>
122 #include <dev/mii/miivar.h>
124 #include <dev/pci/pcireg.h>
125 #include <dev/pci/pcivar.h>
127 #define NGE_USEIOSPACE
129 #include <dev/nge/if_ngereg.h>
131 MODULE_DEPEND(nge, pci, 1, 1, 1);
132 MODULE_DEPEND(nge, ether, 1, 1, 1);
133 MODULE_DEPEND(nge, miibus, 1, 1, 1);
135 /* "device miibus" required. See GENERIC if you get errors here. */
136 #include "miibus_if.h"
138 #define NGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
141 * Various supported device vendors/types and their names.
143 static struct nge_type nge_devs[] = {
144 { NGE_VENDORID, NGE_DEVICEID,
145 "National Semiconductor Gigabit Ethernet" },
149 static int nge_probe(device_t);
150 static int nge_attach(device_t);
151 static int nge_detach(device_t);
153 static int nge_newbuf(struct nge_softc *, struct nge_desc *, struct mbuf *);
154 static int nge_encap(struct nge_softc *, struct mbuf *, u_int32_t *);
156 static __inline void nge_fixup_rx (struct mbuf *);
158 static void nge_rxeof(struct nge_softc *);
159 static void nge_txeof(struct nge_softc *);
160 static void nge_intr(void *);
161 static void nge_tick(void *);
162 static void nge_start(struct ifnet *);
163 static void nge_start_locked(struct ifnet *);
164 static int nge_ioctl(struct ifnet *, u_long, caddr_t);
165 static void nge_init(void *);
166 static void nge_init_locked(struct nge_softc *);
167 static void nge_stop(struct nge_softc *);
168 static void nge_watchdog(struct ifnet *);
169 static int nge_shutdown(device_t);
170 static int nge_ifmedia_upd(struct ifnet *);
171 static void nge_ifmedia_upd_locked(struct ifnet *);
172 static void nge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
174 static void nge_delay(struct nge_softc *);
175 static void nge_eeprom_idle(struct nge_softc *);
176 static void nge_eeprom_putbyte(struct nge_softc *, int);
177 static void nge_eeprom_getword(struct nge_softc *, int, u_int16_t *);
178 static void nge_read_eeprom(struct nge_softc *, caddr_t, int, int, int);
180 static void nge_mii_sync(struct nge_softc *);
181 static void nge_mii_send(struct nge_softc *, u_int32_t, int);
182 static int nge_mii_readreg(struct nge_softc *, struct nge_mii_frame *);
183 static int nge_mii_writereg(struct nge_softc *, struct nge_mii_frame *);
185 static int nge_miibus_readreg(device_t, int, int);
186 static int nge_miibus_writereg(device_t, int, int, int);
187 static void nge_miibus_statchg(device_t);
189 static void nge_setmulti(struct nge_softc *);
190 static void nge_reset(struct nge_softc *);
191 static int nge_list_rx_init(struct nge_softc *);
192 static int nge_list_tx_init(struct nge_softc *);
194 #ifdef NGE_USEIOSPACE
195 #define NGE_RES SYS_RES_IOPORT
196 #define NGE_RID NGE_PCI_LOIO
198 #define NGE_RES SYS_RES_MEMORY
199 #define NGE_RID NGE_PCI_LOMEM
202 static device_method_t nge_methods[] = {
203 /* Device interface */
204 DEVMETHOD(device_probe, nge_probe),
205 DEVMETHOD(device_attach, nge_attach),
206 DEVMETHOD(device_detach, nge_detach),
207 DEVMETHOD(device_shutdown, nge_shutdown),
210 DEVMETHOD(bus_print_child, bus_generic_print_child),
211 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
214 DEVMETHOD(miibus_readreg, nge_miibus_readreg),
215 DEVMETHOD(miibus_writereg, nge_miibus_writereg),
216 DEVMETHOD(miibus_statchg, nge_miibus_statchg),
221 static driver_t nge_driver = {
224 sizeof(struct nge_softc)
227 static devclass_t nge_devclass;
229 DRIVER_MODULE(nge, pci, nge_driver, nge_devclass, 0, 0);
230 DRIVER_MODULE(miibus, nge, miibus_driver, miibus_devclass, 0, 0);
232 #define NGE_SETBIT(sc, reg, x) \
233 CSR_WRITE_4(sc, reg, \
234 CSR_READ_4(sc, reg) | (x))
236 #define NGE_CLRBIT(sc, reg, x) \
237 CSR_WRITE_4(sc, reg, \
238 CSR_READ_4(sc, reg) & ~(x))
241 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | (x))
244 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~(x))
248 struct nge_softc *sc;
252 for (idx = (300 / 33) + 1; idx > 0; idx--)
253 CSR_READ_4(sc, NGE_CSR);
260 struct nge_softc *sc;
264 SIO_SET(NGE_MEAR_EE_CSEL);
266 SIO_SET(NGE_MEAR_EE_CLK);
269 for (i = 0; i < 25; i++) {
270 SIO_CLR(NGE_MEAR_EE_CLK);
272 SIO_SET(NGE_MEAR_EE_CLK);
276 SIO_CLR(NGE_MEAR_EE_CLK);
278 SIO_CLR(NGE_MEAR_EE_CSEL);
280 CSR_WRITE_4(sc, NGE_MEAR, 0x00000000);
286 * Send a read command and address to the EEPROM, check for ACK.
289 nge_eeprom_putbyte(sc, addr)
290 struct nge_softc *sc;
295 d = addr | NGE_EECMD_READ;
298 * Feed in each bit and stobe the clock.
300 for (i = 0x400; i; i >>= 1) {
302 SIO_SET(NGE_MEAR_EE_DIN);
304 SIO_CLR(NGE_MEAR_EE_DIN);
307 SIO_SET(NGE_MEAR_EE_CLK);
309 SIO_CLR(NGE_MEAR_EE_CLK);
317 * Read a word of data stored in the EEPROM at address 'addr.'
320 nge_eeprom_getword(sc, addr, dest)
321 struct nge_softc *sc;
328 /* Force EEPROM to idle state. */
331 /* Enter EEPROM access mode. */
333 SIO_CLR(NGE_MEAR_EE_CLK);
335 SIO_SET(NGE_MEAR_EE_CSEL);
339 * Send address of word we want to read.
341 nge_eeprom_putbyte(sc, addr);
344 * Start reading bits from EEPROM.
346 for (i = 0x8000; i; i >>= 1) {
347 SIO_SET(NGE_MEAR_EE_CLK);
349 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_EE_DOUT)
352 SIO_CLR(NGE_MEAR_EE_CLK);
356 /* Turn off EEPROM access mode. */
365 * Read a sequence of words from the EEPROM.
368 nge_read_eeprom(sc, dest, off, cnt, swap)
369 struct nge_softc *sc;
376 u_int16_t word = 0, *ptr;
378 for (i = 0; i < cnt; i++) {
379 nge_eeprom_getword(sc, off + i, &word);
380 ptr = (u_int16_t *)(dest + (i * 2));
391 * Sync the PHYs by setting data bit and strobing the clock 32 times.
395 struct nge_softc *sc;
399 SIO_SET(NGE_MEAR_MII_DIR|NGE_MEAR_MII_DATA);
401 for (i = 0; i < 32; i++) {
402 SIO_SET(NGE_MEAR_MII_CLK);
404 SIO_CLR(NGE_MEAR_MII_CLK);
412 * Clock a series of bits through the MII.
415 nge_mii_send(sc, bits, cnt)
416 struct nge_softc *sc;
422 SIO_CLR(NGE_MEAR_MII_CLK);
424 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
426 SIO_SET(NGE_MEAR_MII_DATA);
428 SIO_CLR(NGE_MEAR_MII_DATA);
431 SIO_CLR(NGE_MEAR_MII_CLK);
433 SIO_SET(NGE_MEAR_MII_CLK);
438 * Read an PHY register through the MII.
441 nge_mii_readreg(sc, frame)
442 struct nge_softc *sc;
443 struct nge_mii_frame *frame;
449 * Set up frame for RX.
451 frame->mii_stdelim = NGE_MII_STARTDELIM;
452 frame->mii_opcode = NGE_MII_READOP;
453 frame->mii_turnaround = 0;
456 CSR_WRITE_4(sc, NGE_MEAR, 0);
461 SIO_SET(NGE_MEAR_MII_DIR);
466 * Send command/address info.
468 nge_mii_send(sc, frame->mii_stdelim, 2);
469 nge_mii_send(sc, frame->mii_opcode, 2);
470 nge_mii_send(sc, frame->mii_phyaddr, 5);
471 nge_mii_send(sc, frame->mii_regaddr, 5);
474 SIO_CLR((NGE_MEAR_MII_CLK|NGE_MEAR_MII_DATA));
476 SIO_SET(NGE_MEAR_MII_CLK);
480 SIO_CLR(NGE_MEAR_MII_DIR);
482 SIO_CLR(NGE_MEAR_MII_CLK);
484 ack = CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA;
485 SIO_SET(NGE_MEAR_MII_CLK);
489 * Now try reading data bits. If the ack failed, we still
490 * need to clock through 16 cycles to keep the PHY(s) in sync.
493 for(i = 0; i < 16; i++) {
494 SIO_CLR(NGE_MEAR_MII_CLK);
496 SIO_SET(NGE_MEAR_MII_CLK);
502 for (i = 0x8000; i; i >>= 1) {
503 SIO_CLR(NGE_MEAR_MII_CLK);
506 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA)
507 frame->mii_data |= i;
510 SIO_SET(NGE_MEAR_MII_CLK);
516 SIO_CLR(NGE_MEAR_MII_CLK);
518 SIO_SET(NGE_MEAR_MII_CLK);
527 * Write to a PHY register through the MII.
530 nge_mii_writereg(sc, frame)
531 struct nge_softc *sc;
532 struct nge_mii_frame *frame;
537 * Set up frame for TX.
540 frame->mii_stdelim = NGE_MII_STARTDELIM;
541 frame->mii_opcode = NGE_MII_WRITEOP;
542 frame->mii_turnaround = NGE_MII_TURNAROUND;
545 * Turn on data output.
547 SIO_SET(NGE_MEAR_MII_DIR);
551 nge_mii_send(sc, frame->mii_stdelim, 2);
552 nge_mii_send(sc, frame->mii_opcode, 2);
553 nge_mii_send(sc, frame->mii_phyaddr, 5);
554 nge_mii_send(sc, frame->mii_regaddr, 5);
555 nge_mii_send(sc, frame->mii_turnaround, 2);
556 nge_mii_send(sc, frame->mii_data, 16);
559 SIO_SET(NGE_MEAR_MII_CLK);
561 SIO_CLR(NGE_MEAR_MII_CLK);
567 SIO_CLR(NGE_MEAR_MII_DIR);
573 nge_miibus_readreg(dev, phy, reg)
577 struct nge_softc *sc;
578 struct nge_mii_frame frame;
580 sc = device_get_softc(dev);
582 bzero((char *)&frame, sizeof(frame));
584 frame.mii_phyaddr = phy;
585 frame.mii_regaddr = reg;
586 nge_mii_readreg(sc, &frame);
588 return(frame.mii_data);
592 nge_miibus_writereg(dev, phy, reg, data)
596 struct nge_softc *sc;
597 struct nge_mii_frame frame;
599 sc = device_get_softc(dev);
601 bzero((char *)&frame, sizeof(frame));
603 frame.mii_phyaddr = phy;
604 frame.mii_regaddr = reg;
605 frame.mii_data = data;
606 nge_mii_writereg(sc, &frame);
612 nge_miibus_statchg(dev)
616 struct nge_softc *sc;
617 struct mii_data *mii;
619 sc = device_get_softc(dev);
621 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media)
623 status = CSR_READ_4(sc, NGE_TBI_ANLPAR);
624 if (status == 0 || status & NGE_TBIANAR_FDX) {
625 NGE_SETBIT(sc, NGE_TX_CFG,
626 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
627 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
629 NGE_CLRBIT(sc, NGE_TX_CFG,
630 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
631 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
634 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK)
636 NGE_CLRBIT(sc, NGE_TX_CFG,
637 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
638 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
640 NGE_SETBIT(sc, NGE_TX_CFG,
641 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
642 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
645 mii = device_get_softc(sc->nge_miibus);
647 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
648 NGE_SETBIT(sc, NGE_TX_CFG,
649 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
650 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
652 NGE_CLRBIT(sc, NGE_TX_CFG,
653 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
654 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
657 /* If we have a 1000Mbps link, set the mode_1000 bit. */
658 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
659 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
660 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_MODE_1000);
662 NGE_CLRBIT(sc, NGE_CFG, NGE_CFG_MODE_1000);
670 struct nge_softc *sc;
673 struct ifmultiaddr *ifma;
674 u_int32_t h = 0, i, filtsave;
680 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
681 NGE_CLRBIT(sc, NGE_RXFILT_CTL,
682 NGE_RXFILTCTL_MCHASH|NGE_RXFILTCTL_UCHASH);
683 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLMULTI);
688 * We have to explicitly enable the multicast hash table
689 * on the NatSemi chip if we want to use it, which we do.
690 * We also have to tell it that we don't want to use the
691 * hash table for matching unicast addresses.
693 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_MCHASH);
694 NGE_CLRBIT(sc, NGE_RXFILT_CTL,
695 NGE_RXFILTCTL_ALLMULTI|NGE_RXFILTCTL_UCHASH);
697 filtsave = CSR_READ_4(sc, NGE_RXFILT_CTL);
699 /* first, zot all the existing hash bits */
700 for (i = 0; i < NGE_MCAST_FILTER_LEN; i += 2) {
701 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_MCAST_LO + i);
702 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 0);
706 * From the 11 bits returned by the crc routine, the top 7
707 * bits represent the 16-bit word in the mcast hash table
708 * that needs to be updated, and the lower 4 bits represent
709 * which bit within that byte needs to be set.
712 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
713 if (ifma->ifma_addr->sa_family != AF_LINK)
715 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
716 ifma->ifma_addr), ETHER_ADDR_LEN) >> 21;
717 index = (h >> 4) & 0x7F;
719 CSR_WRITE_4(sc, NGE_RXFILT_CTL,
720 NGE_FILTADDR_MCAST_LO + (index * 2));
721 NGE_SETBIT(sc, NGE_RXFILT_DATA, (1 << bit));
725 CSR_WRITE_4(sc, NGE_RXFILT_CTL, filtsave);
732 struct nge_softc *sc;
736 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RESET);
738 for (i = 0; i < NGE_TIMEOUT; i++) {
739 if (!(CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RESET))
743 if (i == NGE_TIMEOUT)
744 device_printf(sc->nge_dev, "reset never completed\n");
746 /* Wait a little while for the chip to get its brains in order. */
750 * If this is a NetSemi chip, make sure to clear
753 CSR_WRITE_4(sc, NGE_CLKRUN, NGE_CLKRUN_PMESTS);
754 CSR_WRITE_4(sc, NGE_CLKRUN, 0);
760 * Probe for a NatSemi chip. Check the PCI vendor and device
761 * IDs against our list and return a device name if we find a match.
771 while(t->nge_name != NULL) {
772 if ((pci_get_vendor(dev) == t->nge_vid) &&
773 (pci_get_device(dev) == t->nge_did)) {
774 device_set_desc(dev, t->nge_name);
775 return(BUS_PROBE_DEFAULT);
784 * Attach the interface. Allocate softc structures, do ifmedia
785 * setup and ethernet/BPF attach.
791 u_char eaddr[ETHER_ADDR_LEN];
792 struct nge_softc *sc;
793 struct ifnet *ifp = NULL;
796 sc = device_get_softc(dev);
799 NGE_LOCK_INIT(sc, device_get_nameunit(dev));
800 callout_init_mtx(&sc->nge_stat_ch, &sc->nge_mtx, 0);
803 * Map control/status registers.
805 pci_enable_busmaster(dev);
808 sc->nge_res = bus_alloc_resource_any(dev, NGE_RES, &rid, RF_ACTIVE);
810 if (sc->nge_res == NULL) {
811 device_printf(dev, "couldn't map ports/memory\n");
816 sc->nge_btag = rman_get_bustag(sc->nge_res);
817 sc->nge_bhandle = rman_get_bushandle(sc->nge_res);
819 /* Allocate interrupt */
821 sc->nge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
822 RF_SHAREABLE | RF_ACTIVE);
824 if (sc->nge_irq == NULL) {
825 device_printf(dev, "couldn't map interrupt\n");
830 /* Reset the adapter. */
834 * Get station address from the EEPROM.
836 nge_read_eeprom(sc, (caddr_t)&eaddr[4], NGE_EE_NODEADDR, 1, 0);
837 nge_read_eeprom(sc, (caddr_t)&eaddr[2], NGE_EE_NODEADDR + 1, 1, 0);
838 nge_read_eeprom(sc, (caddr_t)&eaddr[0], NGE_EE_NODEADDR + 2, 1, 0);
840 sc->nge_ldata = contigmalloc(sizeof(struct nge_list_data), M_DEVBUF,
841 M_NOWAIT|M_ZERO, 0, 0xffffffff, PAGE_SIZE, 0);
843 if (sc->nge_ldata == NULL) {
844 device_printf(dev, "no memory for list buffers!\n");
849 ifp = sc->nge_ifp = if_alloc(IFT_ETHER);
851 device_printf(dev, "can not if_alloc()\n");
856 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
857 ifp->if_mtu = ETHERMTU;
858 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
859 ifp->if_ioctl = nge_ioctl;
860 ifp->if_start = nge_start;
861 ifp->if_watchdog = nge_watchdog;
862 ifp->if_init = nge_init;
863 ifp->if_snd.ifq_maxlen = NGE_TX_LIST_CNT - 1;
864 ifp->if_hwassist = NGE_CSUM_FEATURES;
865 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING;
866 ifp->if_capenable = ifp->if_capabilities;
867 #ifdef DEVICE_POLLING
868 ifp->if_capabilities |= IFCAP_POLLING;
874 /* XXX: leaked on error */
875 if (mii_phy_probe(dev, &sc->nge_miibus,
876 nge_ifmedia_upd, nge_ifmedia_sts)) {
877 if (CSR_READ_4(sc, NGE_CFG) & NGE_CFG_TBI_EN) {
879 device_printf(dev, "Using TBI\n");
881 sc->nge_miibus = dev;
883 ifmedia_init(&sc->nge_ifmedia, 0, nge_ifmedia_upd,
885 #define ADD(m, c) ifmedia_add(&sc->nge_ifmedia, (m), (c), NULL)
886 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, 0), 0);
887 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, 0, 0), 0);
888 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, 0),0);
889 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0), 0);
891 device_printf(dev, " 1000baseSX, 1000baseSX-FDX, auto\n");
893 ifmedia_set(&sc->nge_ifmedia,
894 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0));
896 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
898 | NGE_GPIO_GP1_OUTENB | NGE_GPIO_GP2_OUTENB
899 | NGE_GPIO_GP3_OUTENB
900 | NGE_GPIO_GP3_IN | NGE_GPIO_GP4_IN);
903 device_printf(dev, "MII without any PHY!\n");
910 * Call MI attach routine.
912 ether_ifattach(ifp, eaddr);
917 error = bus_setup_intr(dev, sc->nge_irq, INTR_TYPE_NET | INTR_MPSAFE,
918 NULL, nge_intr, sc, &sc->nge_intrhand);
920 device_printf(dev, "couldn't set up irq\n");
928 contigfree(sc->nge_ldata,
929 sizeof(struct nge_list_data), M_DEVBUF);
933 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
935 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
936 NGE_LOCK_DESTROY(sc);
944 struct nge_softc *sc;
947 sc = device_get_softc(dev);
950 #ifdef DEVICE_POLLING
951 if (ifp->if_capenable & IFCAP_POLLING)
952 ether_poll_deregister(ifp);
958 callout_drain(&sc->nge_stat_ch);
961 bus_generic_detach(dev);
963 device_delete_child(dev, sc->nge_miibus);
965 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand);
966 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
967 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
969 contigfree(sc->nge_ldata, sizeof(struct nge_list_data), M_DEVBUF);
972 NGE_LOCK_DESTROY(sc);
978 * Initialize the transmit descriptors.
982 struct nge_softc *sc;
984 struct nge_list_data *ld;
985 struct nge_ring_data *cd;
991 for (i = 0; i < NGE_TX_LIST_CNT; i++) {
992 if (i == (NGE_TX_LIST_CNT - 1)) {
993 ld->nge_tx_list[i].nge_nextdesc =
995 ld->nge_tx_list[i].nge_next =
996 vtophys(&ld->nge_tx_list[0]);
998 ld->nge_tx_list[i].nge_nextdesc =
999 &ld->nge_tx_list[i + 1];
1000 ld->nge_tx_list[i].nge_next =
1001 vtophys(&ld->nge_tx_list[i + 1]);
1003 ld->nge_tx_list[i].nge_mbuf = NULL;
1004 ld->nge_tx_list[i].nge_ptr = 0;
1005 ld->nge_tx_list[i].nge_ctl = 0;
1008 cd->nge_tx_prod = cd->nge_tx_cons = cd->nge_tx_cnt = 0;
1015 * Initialize the RX descriptors and allocate mbufs for them. Note that
1016 * we arrange the descriptors in a closed ring, so that the last descriptor
1017 * points back to the first.
1020 nge_list_rx_init(sc)
1021 struct nge_softc *sc;
1023 struct nge_list_data *ld;
1024 struct nge_ring_data *cd;
1028 cd = &sc->nge_cdata;
1030 for (i = 0; i < NGE_RX_LIST_CNT; i++) {
1031 if (nge_newbuf(sc, &ld->nge_rx_list[i], NULL) == ENOBUFS)
1033 if (i == (NGE_RX_LIST_CNT - 1)) {
1034 ld->nge_rx_list[i].nge_nextdesc =
1035 &ld->nge_rx_list[0];
1036 ld->nge_rx_list[i].nge_next =
1037 vtophys(&ld->nge_rx_list[0]);
1039 ld->nge_rx_list[i].nge_nextdesc =
1040 &ld->nge_rx_list[i + 1];
1041 ld->nge_rx_list[i].nge_next =
1042 vtophys(&ld->nge_rx_list[i + 1]);
1046 cd->nge_rx_prod = 0;
1047 sc->nge_head = sc->nge_tail = NULL;
1053 * Initialize an RX descriptor and attach an MBUF cluster.
1056 nge_newbuf(sc, c, m)
1057 struct nge_softc *sc;
1063 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1067 m->m_data = m->m_ext.ext_buf;
1069 m->m_len = m->m_pkthdr.len = MCLBYTES;
1071 m_adj(m, sizeof(u_int64_t));
1074 c->nge_ptr = vtophys(mtod(m, caddr_t));
1075 c->nge_ctl = m->m_len;
1082 static __inline void
1087 uint16_t *src, *dst;
1089 src = mtod(m, uint16_t *);
1092 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
1095 m->m_data -= ETHER_ALIGN;
1102 * A frame has been uploaded: pass the resulting mbuf chain up to
1103 * the higher level protocols.
1107 struct nge_softc *sc;
1111 struct nge_desc *cur_rx;
1112 int i, total_len = 0;
1115 NGE_LOCK_ASSERT(sc);
1117 i = sc->nge_cdata.nge_rx_prod;
1119 while(NGE_OWNDESC(&sc->nge_ldata->nge_rx_list[i])) {
1122 #ifdef DEVICE_POLLING
1123 if (ifp->if_capenable & IFCAP_POLLING) {
1124 if (sc->rxcycles <= 0)
1130 cur_rx = &sc->nge_ldata->nge_rx_list[i];
1131 rxstat = cur_rx->nge_rxstat;
1132 extsts = cur_rx->nge_extsts;
1133 m = cur_rx->nge_mbuf;
1134 cur_rx->nge_mbuf = NULL;
1135 total_len = NGE_RXBYTES(cur_rx);
1136 NGE_INC(i, NGE_RX_LIST_CNT);
1138 if (rxstat & NGE_CMDSTS_MORE) {
1139 m->m_len = total_len;
1140 if (sc->nge_head == NULL) {
1141 m->m_pkthdr.len = total_len;
1142 sc->nge_head = sc->nge_tail = m;
1144 m->m_flags &= ~M_PKTHDR;
1145 sc->nge_head->m_pkthdr.len += total_len;
1146 sc->nge_tail->m_next = m;
1149 nge_newbuf(sc, cur_rx, NULL);
1154 * If an error occurs, update stats, clear the
1155 * status word and leave the mbuf cluster in place:
1156 * it should simply get re-used next time this descriptor
1157 * comes up in the ring.
1159 if (!(rxstat & NGE_CMDSTS_PKT_OK)) {
1161 if (sc->nge_head != NULL) {
1162 m_freem(sc->nge_head);
1163 sc->nge_head = sc->nge_tail = NULL;
1165 nge_newbuf(sc, cur_rx, m);
1169 /* Try conjure up a replacement mbuf. */
1171 if (nge_newbuf(sc, cur_rx, NULL)) {
1173 if (sc->nge_head != NULL) {
1174 m_freem(sc->nge_head);
1175 sc->nge_head = sc->nge_tail = NULL;
1177 nge_newbuf(sc, cur_rx, m);
1181 if (sc->nge_head != NULL) {
1182 m->m_len = total_len;
1183 m->m_flags &= ~M_PKTHDR;
1184 sc->nge_tail->m_next = m;
1186 m->m_pkthdr.len += total_len;
1187 sc->nge_head = sc->nge_tail = NULL;
1189 m->m_pkthdr.len = m->m_len = total_len;
1192 * Ok. NatSemi really screwed up here. This is the
1193 * only gigE chip I know of with alignment constraints
1194 * on receive buffers. RX buffers must be 64-bit aligned.
1197 * By popular demand, ignore the alignment problems
1198 * on the Intel x86 platform. The performance hit
1199 * incurred due to unaligned accesses is much smaller
1200 * than the hit produced by forcing buffer copies all
1201 * the time, especially with jumbo frames. We still
1202 * need to fix up the alignment everywhere else though.
1209 m->m_pkthdr.rcvif = ifp;
1211 /* Do IP checksum checking. */
1212 if (extsts & NGE_RXEXTSTS_IPPKT)
1213 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1214 if (!(extsts & NGE_RXEXTSTS_IPCSUMERR))
1215 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1216 if ((extsts & NGE_RXEXTSTS_TCPPKT &&
1217 !(extsts & NGE_RXEXTSTS_TCPCSUMERR)) ||
1218 (extsts & NGE_RXEXTSTS_UDPPKT &&
1219 !(extsts & NGE_RXEXTSTS_UDPCSUMERR))) {
1220 m->m_pkthdr.csum_flags |=
1221 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1222 m->m_pkthdr.csum_data = 0xffff;
1226 * If we received a packet with a vlan tag, pass it
1227 * to vlan_input() instead of ether_input().
1229 if (extsts & NGE_RXEXTSTS_VLANPKT) {
1230 m->m_pkthdr.ether_vtag =
1231 ntohs(extsts & NGE_RXEXTSTS_VTCI);
1232 m->m_flags |= M_VLANTAG;
1235 (*ifp->if_input)(ifp, m);
1239 sc->nge_cdata.nge_rx_prod = i;
1245 * A frame was downloaded to the chip. It's safe for us to clean up
1251 struct nge_softc *sc;
1253 struct nge_desc *cur_tx;
1257 NGE_LOCK_ASSERT(sc);
1261 * Go through our tx list and free mbufs for those
1262 * frames that have been transmitted.
1264 idx = sc->nge_cdata.nge_tx_cons;
1265 while (idx != sc->nge_cdata.nge_tx_prod) {
1266 cur_tx = &sc->nge_ldata->nge_tx_list[idx];
1268 if (NGE_OWNDESC(cur_tx))
1271 if (cur_tx->nge_ctl & NGE_CMDSTS_MORE) {
1272 sc->nge_cdata.nge_tx_cnt--;
1273 NGE_INC(idx, NGE_TX_LIST_CNT);
1277 if (!(cur_tx->nge_ctl & NGE_CMDSTS_PKT_OK)) {
1279 if (cur_tx->nge_txstat & NGE_TXSTAT_EXCESSCOLLS)
1280 ifp->if_collisions++;
1281 if (cur_tx->nge_txstat & NGE_TXSTAT_OUTOFWINCOLL)
1282 ifp->if_collisions++;
1285 ifp->if_collisions +=
1286 (cur_tx->nge_txstat & NGE_TXSTAT_COLLCNT) >> 16;
1289 if (cur_tx->nge_mbuf != NULL) {
1290 m_freem(cur_tx->nge_mbuf);
1291 cur_tx->nge_mbuf = NULL;
1292 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1295 sc->nge_cdata.nge_tx_cnt--;
1296 NGE_INC(idx, NGE_TX_LIST_CNT);
1299 sc->nge_cdata.nge_tx_cons = idx;
1301 if (idx == sc->nge_cdata.nge_tx_prod)
1311 struct nge_softc *sc;
1312 struct mii_data *mii;
1316 NGE_LOCK_ASSERT(sc);
1320 if (!sc->nge_link) {
1321 if (CSR_READ_4(sc, NGE_TBI_BMSR)
1322 & NGE_TBIBMSR_ANEG_DONE) {
1324 device_printf(sc->nge_dev,
1325 "gigabit link up\n");
1326 nge_miibus_statchg(sc->nge_miibus);
1328 if (ifp->if_snd.ifq_head != NULL)
1329 nge_start_locked(ifp);
1333 mii = device_get_softc(sc->nge_miibus);
1336 if (!sc->nge_link) {
1337 if (mii->mii_media_status & IFM_ACTIVE &&
1338 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1340 if (IFM_SUBTYPE(mii->mii_media_active)
1341 == IFM_1000_T && bootverbose)
1342 device_printf(sc->nge_dev,
1343 "gigabit link up\n");
1344 if (ifp->if_snd.ifq_head != NULL)
1345 nge_start_locked(ifp);
1349 callout_reset(&sc->nge_stat_ch, hz, nge_tick, sc);
1354 #ifdef DEVICE_POLLING
1355 static poll_handler_t nge_poll;
1358 nge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1360 struct nge_softc *sc = ifp->if_softc;
1363 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
1369 * On the nge, reading the status register also clears it.
1370 * So before returning to intr mode we must make sure that all
1371 * possible pending sources of interrupts have been served.
1372 * In practice this means run to completion the *eof routines,
1373 * and then call the interrupt routine
1375 sc->rxcycles = count;
1378 if (ifp->if_snd.ifq_head != NULL)
1379 nge_start_locked(ifp);
1381 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) {
1384 /* Reading the ISR register clears all interrupts. */
1385 status = CSR_READ_4(sc, NGE_ISR);
1387 if (status & (NGE_ISR_RX_ERR|NGE_ISR_RX_OFLOW))
1390 if (status & (NGE_ISR_RX_IDLE))
1391 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE);
1393 if (status & NGE_ISR_SYSERR) {
1395 nge_init_locked(sc);
1400 #endif /* DEVICE_POLLING */
1406 struct nge_softc *sc;
1414 #ifdef DEVICE_POLLING
1415 if (ifp->if_capenable & IFCAP_POLLING) {
1421 /* Supress unwanted interrupts */
1422 if (!(ifp->if_flags & IFF_UP)) {
1428 /* Disable interrupts. */
1429 CSR_WRITE_4(sc, NGE_IER, 0);
1431 /* Data LED on for TBI mode */
1433 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
1434 | NGE_GPIO_GP3_OUT);
1437 /* Reading the ISR register clears all interrupts. */
1438 status = CSR_READ_4(sc, NGE_ISR);
1440 if ((status & NGE_INTRS) == 0)
1443 if ((status & NGE_ISR_TX_DESC_OK) ||
1444 (status & NGE_ISR_TX_ERR) ||
1445 (status & NGE_ISR_TX_OK) ||
1446 (status & NGE_ISR_TX_IDLE))
1449 if ((status & NGE_ISR_RX_DESC_OK) ||
1450 (status & NGE_ISR_RX_ERR) ||
1451 (status & NGE_ISR_RX_OFLOW) ||
1452 (status & NGE_ISR_RX_FIFO_OFLOW) ||
1453 (status & NGE_ISR_RX_IDLE) ||
1454 (status & NGE_ISR_RX_OK))
1457 if ((status & NGE_ISR_RX_IDLE))
1458 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE);
1460 if (status & NGE_ISR_SYSERR) {
1462 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1463 nge_init_locked(sc);
1468 * XXX: nge_tick() is not ready to be called this way
1469 * it screws up the aneg timeout because mii_tick() is
1470 * only to be called once per second.
1472 if (status & NGE_IMR_PHY_INTR) {
1479 /* Re-enable interrupts. */
1480 CSR_WRITE_4(sc, NGE_IER, 1);
1482 if (ifp->if_snd.ifq_head != NULL)
1483 nge_start_locked(ifp);
1485 /* Data LED off for TBI mode */
1488 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
1489 & ~NGE_GPIO_GP3_OUT);
1497 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1498 * pointers to the fragment pointers.
1501 nge_encap(sc, m_head, txidx)
1502 struct nge_softc *sc;
1503 struct mbuf *m_head;
1506 struct nge_desc *f = NULL;
1508 int frag, cur, cnt = 0;
1511 * Start packing the mbufs in this chain into
1512 * the fragment pointers. Stop when we run out
1513 * of fragments or hit the end of the mbuf chain.
1516 cur = frag = *txidx;
1518 for (m = m_head; m != NULL; m = m->m_next) {
1519 if (m->m_len != 0) {
1520 if ((NGE_TX_LIST_CNT -
1521 (sc->nge_cdata.nge_tx_cnt + cnt)) < 2)
1523 f = &sc->nge_ldata->nge_tx_list[frag];
1524 f->nge_ctl = NGE_CMDSTS_MORE | m->m_len;
1525 f->nge_ptr = vtophys(mtod(m, vm_offset_t));
1527 f->nge_ctl |= NGE_CMDSTS_OWN;
1529 NGE_INC(frag, NGE_TX_LIST_CNT);
1537 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts = 0;
1538 if (m_head->m_pkthdr.csum_flags) {
1539 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
1540 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |=
1541 NGE_TXEXTSTS_IPCSUM;
1542 if (m_head->m_pkthdr.csum_flags & CSUM_TCP)
1543 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |=
1544 NGE_TXEXTSTS_TCPCSUM;
1545 if (m_head->m_pkthdr.csum_flags & CSUM_UDP)
1546 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |=
1547 NGE_TXEXTSTS_UDPCSUM;
1550 if (m_head->m_flags & M_VLANTAG) {
1551 sc->nge_ldata->nge_tx_list[cur].nge_extsts |=
1552 (NGE_TXEXTSTS_VLANPKT|htons(m_head->m_pkthdr.ether_vtag));
1555 sc->nge_ldata->nge_tx_list[cur].nge_mbuf = m_head;
1556 sc->nge_ldata->nge_tx_list[cur].nge_ctl &= ~NGE_CMDSTS_MORE;
1557 sc->nge_ldata->nge_tx_list[*txidx].nge_ctl |= NGE_CMDSTS_OWN;
1558 sc->nge_cdata.nge_tx_cnt += cnt;
1565 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1566 * to the mbuf data regions directly in the transmit lists. We also save a
1567 * copy of the pointers since the transmit list fragment pointers are
1568 * physical addresses.
1575 struct nge_softc *sc;
1579 nge_start_locked(ifp);
1584 nge_start_locked(ifp)
1587 struct nge_softc *sc;
1588 struct mbuf *m_head = NULL;
1596 idx = sc->nge_cdata.nge_tx_prod;
1598 if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
1601 while(sc->nge_ldata->nge_tx_list[idx].nge_mbuf == NULL) {
1602 IF_DEQUEUE(&ifp->if_snd, m_head);
1606 if (nge_encap(sc, m_head, &idx)) {
1607 IF_PREPEND(&ifp->if_snd, m_head);
1608 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1613 * If there's a BPF listener, bounce a copy of this frame
1616 ETHER_BPF_MTAP(ifp, m_head);
1621 sc->nge_cdata.nge_tx_prod = idx;
1622 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_ENABLE);
1625 * Set a timeout in case the chip goes out to lunch.
1636 struct nge_softc *sc = xsc;
1639 nge_init_locked(sc);
1645 struct nge_softc *sc;
1647 struct ifnet *ifp = sc->nge_ifp;
1648 struct mii_data *mii;
1650 NGE_LOCK_ASSERT(sc);
1652 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1656 * Cancel pending I/O and free all RX/TX buffers.
1663 mii = device_get_softc(sc->nge_miibus);
1666 /* Set MAC address */
1667 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR0);
1668 CSR_WRITE_4(sc, NGE_RXFILT_DATA,
1669 ((u_int16_t *)IF_LLADDR(sc->nge_ifp))[0]);
1670 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR1);
1671 CSR_WRITE_4(sc, NGE_RXFILT_DATA,
1672 ((u_int16_t *)IF_LLADDR(sc->nge_ifp))[1]);
1673 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR2);
1674 CSR_WRITE_4(sc, NGE_RXFILT_DATA,
1675 ((u_int16_t *)IF_LLADDR(sc->nge_ifp))[2]);
1677 /* Init circular RX list. */
1678 if (nge_list_rx_init(sc) == ENOBUFS) {
1679 device_printf(sc->nge_dev, "initialization failed: no "
1680 "memory for rx buffers\n");
1686 * Init tx descriptors.
1688 nge_list_tx_init(sc);
1691 * For the NatSemi chip, we have to explicitly enable the
1692 * reception of ARP frames, as well as turn on the 'perfect
1693 * match' filter where we store the station address, otherwise
1694 * we won't receive unicasts meant for this host.
1696 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ARP);
1697 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_PERFECT);
1699 /* If we want promiscuous mode, set the allframes bit. */
1700 if (ifp->if_flags & IFF_PROMISC) {
1701 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS);
1703 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS);
1707 * Set the capture broadcast bit to capture broadcast frames.
1709 if (ifp->if_flags & IFF_BROADCAST) {
1710 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD);
1712 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD);
1716 * Load the multicast filter.
1720 /* Turn the receive filter on */
1721 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ENABLE);
1724 * Load the address of the RX and TX lists.
1726 CSR_WRITE_4(sc, NGE_RX_LISTPTR,
1727 vtophys(&sc->nge_ldata->nge_rx_list[0]));
1728 CSR_WRITE_4(sc, NGE_TX_LISTPTR,
1729 vtophys(&sc->nge_ldata->nge_tx_list[0]));
1731 /* Set RX configuration */
1732 CSR_WRITE_4(sc, NGE_RX_CFG, NGE_RXCFG);
1734 * Enable hardware checksum validation for all IPv4
1735 * packets, do not reject packets with bad checksums.
1737 CSR_WRITE_4(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_IPCSUM_ENB);
1740 * Tell the chip to detect and strip VLAN tag info from
1741 * received frames. The tag will be provided in the extsts
1742 * field in the RX descriptors.
1744 NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL,
1745 NGE_VIPRXCTL_TAG_DETECT_ENB|NGE_VIPRXCTL_TAG_STRIP_ENB);
1747 /* Set TX configuration */
1748 CSR_WRITE_4(sc, NGE_TX_CFG, NGE_TXCFG);
1751 * Enable TX IPv4 checksumming on a per-packet basis.
1753 CSR_WRITE_4(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_CSUM_PER_PKT);
1756 * Tell the chip to insert VLAN tags on a per-packet basis as
1757 * dictated by the code in the frame encapsulation routine.
1759 NGE_SETBIT(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_TAG_PER_PKT);
1761 /* Set full/half duplex mode. */
1763 if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK)
1765 NGE_SETBIT(sc, NGE_TX_CFG,
1766 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
1767 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1769 NGE_CLRBIT(sc, NGE_TX_CFG,
1770 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
1771 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1774 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1775 NGE_SETBIT(sc, NGE_TX_CFG,
1776 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
1777 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1779 NGE_CLRBIT(sc, NGE_TX_CFG,
1780 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
1781 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1788 * Enable the delivery of PHY interrupts based on
1789 * link/speed/duplex status changes. Also enable the
1790 * extsts field in the DMA descriptors (needed for
1791 * TCP/IP checksum offload on transmit).
1793 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_PHYINTR_SPD|
1794 NGE_CFG_PHYINTR_LNK|NGE_CFG_PHYINTR_DUP|NGE_CFG_EXTSTS_ENB);
1797 * Configure interrupt holdoff (moderation). We can
1798 * have the chip delay interrupt delivery for a certain
1799 * period. Units are in 100us, and the max setting
1800 * is 25500us (0xFF x 100us). Default is a 100us holdoff.
1802 CSR_WRITE_4(sc, NGE_IHR, 0x01);
1805 * Enable interrupts.
1807 CSR_WRITE_4(sc, NGE_IMR, NGE_INTRS);
1808 #ifdef DEVICE_POLLING
1810 * ... only enable interrupts if we are not polling, make sure
1811 * they are off otherwise.
1813 if (ifp->if_capenable & IFCAP_POLLING)
1814 CSR_WRITE_4(sc, NGE_IER, 0);
1817 CSR_WRITE_4(sc, NGE_IER, 1);
1819 /* Enable receiver and transmitter. */
1820 NGE_CLRBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE);
1821 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE);
1823 nge_ifmedia_upd_locked(ifp);
1825 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1826 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1832 * Set media options.
1835 nge_ifmedia_upd(ifp)
1838 struct nge_softc *sc;
1842 nge_ifmedia_upd_locked(ifp);
1848 nge_ifmedia_upd_locked(ifp)
1851 struct nge_softc *sc;
1852 struct mii_data *mii;
1855 NGE_LOCK_ASSERT(sc);
1858 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media)
1860 CSR_WRITE_4(sc, NGE_TBI_ANAR,
1861 CSR_READ_4(sc, NGE_TBI_ANAR)
1862 | NGE_TBIANAR_HDX | NGE_TBIANAR_FDX
1863 | NGE_TBIANAR_PS1 | NGE_TBIANAR_PS2);
1864 CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG
1865 | NGE_TBIBMCR_RESTART_ANEG);
1866 CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG);
1867 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media
1868 & IFM_GMASK) == IFM_FDX) {
1869 NGE_SETBIT(sc, NGE_TX_CFG,
1870 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
1871 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1873 CSR_WRITE_4(sc, NGE_TBI_ANAR, 0);
1874 CSR_WRITE_4(sc, NGE_TBI_BMCR, 0);
1876 NGE_CLRBIT(sc, NGE_TX_CFG,
1877 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
1878 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1880 CSR_WRITE_4(sc, NGE_TBI_ANAR, 0);
1881 CSR_WRITE_4(sc, NGE_TBI_BMCR, 0);
1884 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
1885 & ~NGE_GPIO_GP3_OUT);
1887 mii = device_get_softc(sc->nge_miibus);
1889 if (mii->mii_instance) {
1890 struct mii_softc *miisc;
1892 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1893 mii_phy_reset(miisc);
1900 * Report current media status.
1903 nge_ifmedia_sts(ifp, ifmr)
1905 struct ifmediareq *ifmr;
1907 struct nge_softc *sc;
1908 struct mii_data *mii;
1914 ifmr->ifm_status = IFM_AVALID;
1915 ifmr->ifm_active = IFM_ETHER;
1917 if (CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE) {
1918 ifmr->ifm_status |= IFM_ACTIVE;
1920 if (CSR_READ_4(sc, NGE_TBI_BMCR) & NGE_TBIBMCR_LOOPBACK)
1921 ifmr->ifm_active |= IFM_LOOP;
1922 if (!CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE) {
1923 ifmr->ifm_active |= IFM_NONE;
1924 ifmr->ifm_status = 0;
1928 ifmr->ifm_active |= IFM_1000_SX;
1929 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media)
1931 ifmr->ifm_active |= IFM_AUTO;
1932 if (CSR_READ_4(sc, NGE_TBI_ANLPAR)
1933 & NGE_TBIANAR_FDX) {
1934 ifmr->ifm_active |= IFM_FDX;
1935 }else if (CSR_READ_4(sc, NGE_TBI_ANLPAR)
1936 & NGE_TBIANAR_HDX) {
1937 ifmr->ifm_active |= IFM_HDX;
1939 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK)
1941 ifmr->ifm_active |= IFM_FDX;
1943 ifmr->ifm_active |= IFM_HDX;
1946 mii = device_get_softc(sc->nge_miibus);
1948 ifmr->ifm_active = mii->mii_media_active;
1949 ifmr->ifm_status = mii->mii_media_status;
1957 nge_ioctl(ifp, command, data)
1962 struct nge_softc *sc = ifp->if_softc;
1963 struct ifreq *ifr = (struct ifreq *) data;
1964 struct mii_data *mii;
1969 if (ifr->ifr_mtu > NGE_JUMBO_MTU)
1973 ifp->if_mtu = ifr->ifr_mtu;
1975 * Workaround: if the MTU is larger than
1976 * 8152 (TX FIFO size minus 64 minus 18), turn off
1977 * TX checksum offloading.
1979 if (ifr->ifr_mtu >= 8152) {
1980 ifp->if_capenable &= ~IFCAP_TXCSUM;
1981 ifp->if_hwassist = 0;
1983 ifp->if_capenable |= IFCAP_TXCSUM;
1984 ifp->if_hwassist = NGE_CSUM_FEATURES;
1991 if (ifp->if_flags & IFF_UP) {
1992 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
1993 ifp->if_flags & IFF_PROMISC &&
1994 !(sc->nge_if_flags & IFF_PROMISC)) {
1995 NGE_SETBIT(sc, NGE_RXFILT_CTL,
1996 NGE_RXFILTCTL_ALLPHYS|
1997 NGE_RXFILTCTL_ALLMULTI);
1998 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
1999 !(ifp->if_flags & IFF_PROMISC) &&
2000 sc->nge_if_flags & IFF_PROMISC) {
2001 NGE_CLRBIT(sc, NGE_RXFILT_CTL,
2002 NGE_RXFILTCTL_ALLPHYS);
2003 if (!(ifp->if_flags & IFF_ALLMULTI))
2004 NGE_CLRBIT(sc, NGE_RXFILT_CTL,
2005 NGE_RXFILTCTL_ALLMULTI);
2007 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2008 nge_init_locked(sc);
2011 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2014 sc->nge_if_flags = ifp->if_flags;
2028 error = ifmedia_ioctl(ifp, ifr, &sc->nge_ifmedia,
2031 mii = device_get_softc(sc->nge_miibus);
2032 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
2037 #ifdef DEVICE_POLLING
2038 if (ifr->ifr_reqcap & IFCAP_POLLING &&
2039 !(ifp->if_capenable & IFCAP_POLLING)) {
2040 error = ether_poll_register(nge_poll, ifp);
2044 /* Disable interrupts */
2045 CSR_WRITE_4(sc, NGE_IER, 0);
2046 ifp->if_capenable |= IFCAP_POLLING;
2051 if (!(ifr->ifr_reqcap & IFCAP_POLLING) &&
2052 ifp->if_capenable & IFCAP_POLLING) {
2053 error = ether_poll_deregister(ifp);
2054 /* Enable interrupts. */
2056 CSR_WRITE_4(sc, NGE_IER, 1);
2057 ifp->if_capenable &= ~IFCAP_POLLING;
2061 #endif /* DEVICE_POLLING */
2064 error = ether_ioctl(ifp, command, data);
2075 struct nge_softc *sc;
2080 if_printf(ifp, "watchdog timeout\n");
2085 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2086 nge_init_locked(sc);
2088 if (ifp->if_snd.ifq_head != NULL)
2089 nge_start_locked(ifp);
2097 * Stop the adapter and free any mbufs allocated to the
2102 struct nge_softc *sc;
2106 struct mii_data *mii;
2108 NGE_LOCK_ASSERT(sc);
2114 mii = device_get_softc(sc->nge_miibus);
2117 callout_stop(&sc->nge_stat_ch);
2118 CSR_WRITE_4(sc, NGE_IER, 0);
2119 CSR_WRITE_4(sc, NGE_IMR, 0);
2120 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE);
2122 CSR_WRITE_4(sc, NGE_TX_LISTPTR, 0);
2123 CSR_WRITE_4(sc, NGE_RX_LISTPTR, 0);
2131 * Free data in the RX lists.
2133 for (i = 0; i < NGE_RX_LIST_CNT; i++) {
2134 if (sc->nge_ldata->nge_rx_list[i].nge_mbuf != NULL) {
2135 m_freem(sc->nge_ldata->nge_rx_list[i].nge_mbuf);
2136 sc->nge_ldata->nge_rx_list[i].nge_mbuf = NULL;
2139 bzero((char *)&sc->nge_ldata->nge_rx_list,
2140 sizeof(sc->nge_ldata->nge_rx_list));
2143 * Free the TX list buffers.
2145 for (i = 0; i < NGE_TX_LIST_CNT; i++) {
2146 if (sc->nge_ldata->nge_tx_list[i].nge_mbuf != NULL) {
2147 m_freem(sc->nge_ldata->nge_tx_list[i].nge_mbuf);
2148 sc->nge_ldata->nge_tx_list[i].nge_mbuf = NULL;
2152 bzero((char *)&sc->nge_ldata->nge_tx_list,
2153 sizeof(sc->nge_ldata->nge_tx_list));
2155 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2161 * Stop all chip I/O so that the kernel's probe routines don't
2162 * get confused by errant DMAs when rebooting.
2168 struct nge_softc *sc;
2170 sc = device_get_softc(dev);