2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2000, 2001
4 * Bill Paul <wpaul@bsdi.com>. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
37 * National Semiconductor DP83820/DP83821 gigabit ethernet driver
38 * for FreeBSD. Datasheets are available from:
40 * http://www.national.com/ds/DP/DP83820.pdf
41 * http://www.national.com/ds/DP/DP83821.pdf
43 * These chips are used on several low cost gigabit ethernet NICs
44 * sold by D-Link, Addtron, SMC and Asante. Both parts are
45 * virtually the same, except the 83820 is a 64-bit/32-bit part,
46 * while the 83821 is 32-bit only.
48 * Many cards also use National gigE transceivers, such as the
49 * DP83891, DP83861 and DP83862 gigPHYTER parts. The DP83861 datasheet
50 * contains a full register description that applies to all of these
53 * http://www.national.com/ds/DP/DP83861.pdf
55 * Written by Bill Paul <wpaul@bsdi.com>
56 * BSDi Open Source Solutions
60 * The NatSemi DP83820 and 83821 controllers are enhanced versions
61 * of the NatSemi MacPHYTER 10/100 devices. They support 10, 100
62 * and 1000Mbps speeds with 1000baseX (ten bit interface), MII and GMII
63 * ports. Other features include 8K TX FIFO and 32K RX FIFO, TCP/IP
64 * hardware checksum offload (IPv4 only), VLAN tagging and filtering,
65 * priority TX and RX queues, a 2048 bit multicast hash filter, 4 RX pattern
66 * matching buffers, one perfect address filter buffer and interrupt
67 * moderation. The 83820 supports both 64-bit and 32-bit addressing
68 * and data transfers: the 64-bit support can be toggled on or off
69 * via software. This affects the size of certain fields in the DMA
72 * There are two bugs/misfeatures in the 83820/83821 that I have
75 * - Receive buffers must be aligned on 64-bit boundaries, which means
76 * you must resort to copying data in order to fix up the payload
79 * - In order to transmit jumbo frames larger than 8170 bytes, you have
80 * to turn off transmit checksum offloading, because the chip can't
81 * compute the checksum on an outgoing frame unless it fits entirely
82 * within the TX FIFO, which is only 8192 bytes in size. If you have
83 * TX checksum offload enabled and you transmit attempt to transmit a
84 * frame larger than 8170 bytes, the transmitter will wedge.
86 * To work around the latter problem, TX checksum offload is disabled
87 * if the user selects an MTU larger than 8152 (8170 - 18).
90 #include <sys/param.h>
91 #include <sys/systm.h>
92 #include <sys/sockio.h>
94 #include <sys/malloc.h>
95 #include <sys/kernel.h>
96 #include <sys/socket.h>
99 #include <net/if_arp.h>
100 #include <net/ethernet.h>
101 #include <net/if_dl.h>
102 #include <net/if_media.h>
103 #include <net/if_types.h>
104 #include <net/if_vlan_var.h>
108 #include <vm/vm.h> /* for vtophys */
109 #include <vm/pmap.h> /* for vtophys */
110 #include <machine/clock.h> /* for DELAY */
111 #include <machine/bus_pio.h>
112 #include <machine/bus_memio.h>
113 #include <machine/bus.h>
114 #include <machine/resource.h>
116 #include <sys/rman.h>
118 #include <dev/mii/mii.h>
119 #include <dev/mii/miivar.h>
121 #include <pci/pcireg.h>
122 #include <pci/pcivar.h>
124 #define NGE_USEIOSPACE
126 #include <dev/nge/if_ngereg.h>
128 MODULE_DEPEND(nge, miibus, 1, 1, 1);
130 /* "controller miibus0" required. See GENERIC if you get errors here. */
131 #include "miibus_if.h"
134 static const char rcsid[] =
138 #define NGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
141 * Various supported device vendors/types and their names.
143 static struct nge_type nge_devs[] = {
144 { NGE_VENDORID, NGE_DEVICEID,
145 "National Semiconductor Gigabit Ethernet" },
149 static int nge_probe(device_t);
150 static int nge_attach(device_t);
151 static int nge_detach(device_t);
153 static int nge_alloc_jumbo_mem(struct nge_softc *);
154 static void nge_free_jumbo_mem(struct nge_softc *);
155 static void *nge_jalloc(struct nge_softc *);
156 static void nge_jfree(void *, void *);
158 static int nge_newbuf(struct nge_softc *, struct nge_desc *, struct mbuf *);
159 static int nge_encap(struct nge_softc *, struct mbuf *, u_int32_t *);
160 static void nge_rxeof(struct nge_softc *);
161 static void nge_txeof(struct nge_softc *);
162 static void nge_intr(void *);
163 static void nge_tick(void *);
164 static void nge_start(struct ifnet *);
165 static int nge_ioctl(struct ifnet *, u_long, caddr_t);
166 static void nge_init(void *);
167 static void nge_stop(struct nge_softc *);
168 static void nge_watchdog(struct ifnet *);
169 static void nge_shutdown(device_t);
170 static int nge_ifmedia_upd(struct ifnet *);
171 static void nge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
173 static void nge_delay(struct nge_softc *);
174 static void nge_eeprom_idle(struct nge_softc *);
175 static void nge_eeprom_putbyte(struct nge_softc *, int);
176 static void nge_eeprom_getword(struct nge_softc *, int, u_int16_t *);
177 static void nge_read_eeprom(struct nge_softc *, caddr_t, int, int, int);
179 static void nge_mii_sync(struct nge_softc *);
180 static void nge_mii_send(struct nge_softc *, u_int32_t, int);
181 static int nge_mii_readreg(struct nge_softc *, struct nge_mii_frame *);
182 static int nge_mii_writereg(struct nge_softc *, struct nge_mii_frame *);
184 static int nge_miibus_readreg(device_t, int, int);
185 static int nge_miibus_writereg(device_t, int, int, int);
186 static void nge_miibus_statchg(device_t);
188 static void nge_setmulti(struct nge_softc *);
189 static u_int32_t nge_crc(struct nge_softc *, caddr_t);
190 static void nge_reset(struct nge_softc *);
191 static int nge_list_rx_init(struct nge_softc *);
192 static int nge_list_tx_init(struct nge_softc *);
194 #ifdef NGE_USEIOSPACE
195 #define NGE_RES SYS_RES_IOPORT
196 #define NGE_RID NGE_PCI_LOIO
198 #define NGE_RES SYS_RES_MEMORY
199 #define NGE_RID NGE_PCI_LOMEM
202 static device_method_t nge_methods[] = {
203 /* Device interface */
204 DEVMETHOD(device_probe, nge_probe),
205 DEVMETHOD(device_attach, nge_attach),
206 DEVMETHOD(device_detach, nge_detach),
207 DEVMETHOD(device_shutdown, nge_shutdown),
210 DEVMETHOD(bus_print_child, bus_generic_print_child),
211 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
214 DEVMETHOD(miibus_readreg, nge_miibus_readreg),
215 DEVMETHOD(miibus_writereg, nge_miibus_writereg),
216 DEVMETHOD(miibus_statchg, nge_miibus_statchg),
221 static driver_t nge_driver = {
224 sizeof(struct nge_softc)
227 static devclass_t nge_devclass;
229 DRIVER_MODULE(if_nge, pci, nge_driver, nge_devclass, 0, 0);
230 DRIVER_MODULE(miibus, nge, miibus_driver, miibus_devclass, 0, 0);
232 #define NGE_SETBIT(sc, reg, x) \
233 CSR_WRITE_4(sc, reg, \
234 CSR_READ_4(sc, reg) | (x))
236 #define NGE_CLRBIT(sc, reg, x) \
237 CSR_WRITE_4(sc, reg, \
238 CSR_READ_4(sc, reg) & ~(x))
241 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | x)
244 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~x)
248 struct nge_softc *sc;
252 for (idx = (300 / 33) + 1; idx > 0; idx--)
253 CSR_READ_4(sc, NGE_CSR);
260 struct nge_softc *sc;
264 SIO_SET(NGE_MEAR_EE_CSEL);
266 SIO_SET(NGE_MEAR_EE_CLK);
269 for (i = 0; i < 25; i++) {
270 SIO_CLR(NGE_MEAR_EE_CLK);
272 SIO_SET(NGE_MEAR_EE_CLK);
276 SIO_CLR(NGE_MEAR_EE_CLK);
278 SIO_CLR(NGE_MEAR_EE_CSEL);
280 CSR_WRITE_4(sc, NGE_MEAR, 0x00000000);
286 * Send a read command and address to the EEPROM, check for ACK.
289 nge_eeprom_putbyte(sc, addr)
290 struct nge_softc *sc;
295 d = addr | NGE_EECMD_READ;
298 * Feed in each bit and stobe the clock.
300 for (i = 0x400; i; i >>= 1) {
302 SIO_SET(NGE_MEAR_EE_DIN);
304 SIO_CLR(NGE_MEAR_EE_DIN);
307 SIO_SET(NGE_MEAR_EE_CLK);
309 SIO_CLR(NGE_MEAR_EE_CLK);
317 * Read a word of data stored in the EEPROM at address 'addr.'
320 nge_eeprom_getword(sc, addr, dest)
321 struct nge_softc *sc;
328 /* Force EEPROM to idle state. */
331 /* Enter EEPROM access mode. */
333 SIO_CLR(NGE_MEAR_EE_CLK);
335 SIO_SET(NGE_MEAR_EE_CSEL);
339 * Send address of word we want to read.
341 nge_eeprom_putbyte(sc, addr);
344 * Start reading bits from EEPROM.
346 for (i = 0x8000; i; i >>= 1) {
347 SIO_SET(NGE_MEAR_EE_CLK);
349 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_EE_DOUT)
352 SIO_CLR(NGE_MEAR_EE_CLK);
356 /* Turn off EEPROM access mode. */
365 * Read a sequence of words from the EEPROM.
368 nge_read_eeprom(sc, dest, off, cnt, swap)
369 struct nge_softc *sc;
376 u_int16_t word = 0, *ptr;
378 for (i = 0; i < cnt; i++) {
379 nge_eeprom_getword(sc, off + i, &word);
380 ptr = (u_int16_t *)(dest + (i * 2));
391 * Sync the PHYs by setting data bit and strobing the clock 32 times.
395 struct nge_softc *sc;
399 SIO_SET(NGE_MEAR_MII_DIR|NGE_MEAR_MII_DATA);
401 for (i = 0; i < 32; i++) {
402 SIO_SET(NGE_MEAR_MII_CLK);
404 SIO_CLR(NGE_MEAR_MII_CLK);
412 * Clock a series of bits through the MII.
415 nge_mii_send(sc, bits, cnt)
416 struct nge_softc *sc;
422 SIO_CLR(NGE_MEAR_MII_CLK);
424 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
426 SIO_SET(NGE_MEAR_MII_DATA);
428 SIO_CLR(NGE_MEAR_MII_DATA);
431 SIO_CLR(NGE_MEAR_MII_CLK);
433 SIO_SET(NGE_MEAR_MII_CLK);
438 * Read an PHY register through the MII.
441 nge_mii_readreg(sc, frame)
442 struct nge_softc *sc;
443 struct nge_mii_frame *frame;
451 * Set up frame for RX.
453 frame->mii_stdelim = NGE_MII_STARTDELIM;
454 frame->mii_opcode = NGE_MII_READOP;
455 frame->mii_turnaround = 0;
458 CSR_WRITE_4(sc, NGE_MEAR, 0);
463 SIO_SET(NGE_MEAR_MII_DIR);
468 * Send command/address info.
470 nge_mii_send(sc, frame->mii_stdelim, 2);
471 nge_mii_send(sc, frame->mii_opcode, 2);
472 nge_mii_send(sc, frame->mii_phyaddr, 5);
473 nge_mii_send(sc, frame->mii_regaddr, 5);
476 SIO_CLR((NGE_MEAR_MII_CLK|NGE_MEAR_MII_DATA));
478 SIO_SET(NGE_MEAR_MII_CLK);
482 SIO_CLR(NGE_MEAR_MII_DIR);
484 SIO_CLR(NGE_MEAR_MII_CLK);
486 SIO_SET(NGE_MEAR_MII_CLK);
488 ack = CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA;
491 * Now try reading data bits. If the ack failed, we still
492 * need to clock through 16 cycles to keep the PHY(s) in sync.
495 for(i = 0; i < 16; i++) {
496 SIO_CLR(NGE_MEAR_MII_CLK);
498 SIO_SET(NGE_MEAR_MII_CLK);
504 for (i = 0x8000; i; i >>= 1) {
505 SIO_CLR(NGE_MEAR_MII_CLK);
508 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA)
509 frame->mii_data |= i;
512 SIO_SET(NGE_MEAR_MII_CLK);
518 SIO_CLR(NGE_MEAR_MII_CLK);
520 SIO_SET(NGE_MEAR_MII_CLK);
531 * Write to a PHY register through the MII.
534 nge_mii_writereg(sc, frame)
535 struct nge_softc *sc;
536 struct nge_mii_frame *frame;
543 * Set up frame for TX.
546 frame->mii_stdelim = NGE_MII_STARTDELIM;
547 frame->mii_opcode = NGE_MII_WRITEOP;
548 frame->mii_turnaround = NGE_MII_TURNAROUND;
551 * Turn on data output.
553 SIO_SET(NGE_MEAR_MII_DIR);
557 nge_mii_send(sc, frame->mii_stdelim, 2);
558 nge_mii_send(sc, frame->mii_opcode, 2);
559 nge_mii_send(sc, frame->mii_phyaddr, 5);
560 nge_mii_send(sc, frame->mii_regaddr, 5);
561 nge_mii_send(sc, frame->mii_turnaround, 2);
562 nge_mii_send(sc, frame->mii_data, 16);
565 SIO_SET(NGE_MEAR_MII_CLK);
567 SIO_CLR(NGE_MEAR_MII_CLK);
573 SIO_CLR(NGE_MEAR_MII_DIR);
581 nge_miibus_readreg(dev, phy, reg)
585 struct nge_softc *sc;
586 struct nge_mii_frame frame;
588 sc = device_get_softc(dev);
590 bzero((char *)&frame, sizeof(frame));
592 frame.mii_phyaddr = phy;
593 frame.mii_regaddr = reg;
594 nge_mii_readreg(sc, &frame);
596 return(frame.mii_data);
600 nge_miibus_writereg(dev, phy, reg, data)
604 struct nge_softc *sc;
605 struct nge_mii_frame frame;
607 sc = device_get_softc(dev);
609 bzero((char *)&frame, sizeof(frame));
611 frame.mii_phyaddr = phy;
612 frame.mii_regaddr = reg;
613 frame.mii_data = data;
614 nge_mii_writereg(sc, &frame);
620 nge_miibus_statchg(dev)
624 struct nge_softc *sc;
625 struct mii_data *mii;
627 sc = device_get_softc(dev);
629 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media)
631 status = CSR_READ_4(sc, NGE_TBI_ANLPAR);
632 if (status == 0 || status & NGE_TBIANAR_FDX) {
633 NGE_SETBIT(sc, NGE_TX_CFG,
634 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
635 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
637 NGE_CLRBIT(sc, NGE_TX_CFG,
638 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
639 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
642 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK)
644 NGE_CLRBIT(sc, NGE_TX_CFG,
645 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
646 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
648 NGE_SETBIT(sc, NGE_TX_CFG,
649 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
650 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
653 mii = device_get_softc(sc->nge_miibus);
655 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
656 NGE_SETBIT(sc, NGE_TX_CFG,
657 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
658 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
660 NGE_CLRBIT(sc, NGE_TX_CFG,
661 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
662 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
665 /* If we have a 1000Mbps link, set the mode_1000 bit. */
666 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
667 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
668 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_MODE_1000);
670 NGE_CLRBIT(sc, NGE_CFG, NGE_CFG_MODE_1000);
678 struct nge_softc *sc;
681 u_int32_t crc, carry;
685 /* Compute CRC for the address value. */
686 crc = 0xFFFFFFFF; /* initial value */
688 for (i = 0; i < 6; i++) {
690 for (j = 0; j < 8; j++) {
691 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
695 crc = (crc ^ 0x04c11db6) | carry;
700 * return the filter bit position
703 return((crc >> 21) & 0x00000FFF);
708 struct nge_softc *sc;
711 struct ifmultiaddr *ifma;
712 u_int32_t h = 0, i, filtsave;
715 ifp = &sc->arpcom.ac_if;
717 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
718 NGE_CLRBIT(sc, NGE_RXFILT_CTL,
719 NGE_RXFILTCTL_MCHASH|NGE_RXFILTCTL_UCHASH);
720 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLMULTI);
725 * We have to explicitly enable the multicast hash table
726 * on the NatSemi chip if we want to use it, which we do.
727 * We also have to tell it that we don't want to use the
728 * hash table for matching unicast addresses.
730 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_MCHASH);
731 NGE_CLRBIT(sc, NGE_RXFILT_CTL,
732 NGE_RXFILTCTL_ALLMULTI|NGE_RXFILTCTL_UCHASH);
734 filtsave = CSR_READ_4(sc, NGE_RXFILT_CTL);
736 /* first, zot all the existing hash bits */
737 for (i = 0; i < NGE_MCAST_FILTER_LEN; i += 2) {
738 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_MCAST_LO + i);
739 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 0);
743 * From the 11 bits returned by the crc routine, the top 7
744 * bits represent the 16-bit word in the mcast hash table
745 * that needs to be updated, and the lower 4 bits represent
746 * which bit within that byte needs to be set.
748 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
749 if (ifma->ifma_addr->sa_family != AF_LINK)
751 h = nge_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
752 index = (h >> 4) & 0x7F;
754 CSR_WRITE_4(sc, NGE_RXFILT_CTL,
755 NGE_FILTADDR_MCAST_LO + (index * 2));
756 NGE_SETBIT(sc, NGE_RXFILT_DATA, (1 << bit));
759 CSR_WRITE_4(sc, NGE_RXFILT_CTL, filtsave);
766 struct nge_softc *sc;
770 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RESET);
772 for (i = 0; i < NGE_TIMEOUT; i++) {
773 if (!(CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RESET))
777 if (i == NGE_TIMEOUT)
778 printf("nge%d: reset never completed\n", sc->nge_unit);
780 /* Wait a little while for the chip to get its brains in order. */
784 * If this is a NetSemi chip, make sure to clear
787 CSR_WRITE_4(sc, NGE_CLKRUN, NGE_CLKRUN_PMESTS);
788 CSR_WRITE_4(sc, NGE_CLKRUN, 0);
794 * Probe for an NatSemi chip. Check the PCI vendor and device
795 * IDs against our list and return a device name if we find a match.
805 while(t->nge_name != NULL) {
806 if ((pci_get_vendor(dev) == t->nge_vid) &&
807 (pci_get_device(dev) == t->nge_did)) {
808 device_set_desc(dev, t->nge_name);
818 * Attach the interface. Allocate softc structures, do ifmedia
819 * setup and ethernet/BPF attach.
826 u_char eaddr[ETHER_ADDR_LEN];
828 struct nge_softc *sc;
830 int unit, error = 0, rid;
831 const char *sep = "";
835 sc = device_get_softc(dev);
836 unit = device_get_unit(dev);
837 bzero(sc, sizeof(struct nge_softc));
839 mtx_init(&sc->nge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
840 MTX_DEF | MTX_RECURSE);
843 * Handle power management nonsense.
845 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
846 u_int32_t iobase, membase, irq;
848 /* Save important PCI config data. */
849 iobase = pci_read_config(dev, NGE_PCI_LOIO, 4);
850 membase = pci_read_config(dev, NGE_PCI_LOMEM, 4);
851 irq = pci_read_config(dev, NGE_PCI_INTLINE, 4);
853 /* Reset the power state. */
854 printf("nge%d: chip is in D%d power mode "
855 "-- setting to D0\n", unit,
856 pci_get_powerstate(dev));
857 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
859 /* Restore PCI config data. */
860 pci_write_config(dev, NGE_PCI_LOIO, iobase, 4);
861 pci_write_config(dev, NGE_PCI_LOMEM, membase, 4);
862 pci_write_config(dev, NGE_PCI_INTLINE, irq, 4);
866 * Map control/status registers.
868 pci_enable_busmaster(dev);
869 pci_enable_io(dev, SYS_RES_IOPORT);
870 pci_enable_io(dev, SYS_RES_MEMORY);
871 command = pci_read_config(dev, PCIR_COMMAND, 4);
873 #ifdef NGE_USEIOSPACE
874 if (!(command & PCIM_CMD_PORTEN)) {
875 printf("nge%d: failed to enable I/O ports!\n", unit);
880 if (!(command & PCIM_CMD_MEMEN)) {
881 printf("nge%d: failed to enable memory mapping!\n", unit);
888 sc->nge_res = bus_alloc_resource(dev, NGE_RES, &rid,
889 0, ~0, 1, RF_ACTIVE);
891 if (sc->nge_res == NULL) {
892 printf("nge%d: couldn't map ports/memory\n", unit);
897 sc->nge_btag = rman_get_bustag(sc->nge_res);
898 sc->nge_bhandle = rman_get_bushandle(sc->nge_res);
900 /* Allocate interrupt */
902 sc->nge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
903 RF_SHAREABLE | RF_ACTIVE);
905 if (sc->nge_irq == NULL) {
906 printf("nge%d: couldn't map interrupt\n", unit);
907 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
912 error = bus_setup_intr(dev, sc->nge_irq, INTR_TYPE_NET,
913 nge_intr, sc, &sc->nge_intrhand);
916 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
917 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
918 printf("nge%d: couldn't set up irq\n", unit);
922 /* Reset the adapter. */
926 * Get station address from the EEPROM.
928 nge_read_eeprom(sc, (caddr_t)&eaddr[4], NGE_EE_NODEADDR, 1, 0);
929 nge_read_eeprom(sc, (caddr_t)&eaddr[2], NGE_EE_NODEADDR + 1, 1, 0);
930 nge_read_eeprom(sc, (caddr_t)&eaddr[0], NGE_EE_NODEADDR + 2, 1, 0);
933 * A NatSemi chip was detected. Inform the world.
935 printf("nge%d: Ethernet address: %6D\n", unit, eaddr, ":");
938 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
940 sc->nge_ldata = contigmalloc(sizeof(struct nge_list_data), M_DEVBUF,
941 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
943 if (sc->nge_ldata == NULL) {
944 printf("nge%d: no memory for list buffers!\n", unit);
945 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand);
946 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
947 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
951 bzero(sc->nge_ldata, sizeof(struct nge_list_data));
953 /* Try to allocate memory for jumbo buffers. */
954 if (nge_alloc_jumbo_mem(sc)) {
955 printf("nge%d: jumbo buffer allocation failed\n",
957 contigfree(sc->nge_ldata,
958 sizeof(struct nge_list_data), M_DEVBUF);
959 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand);
960 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
961 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
966 ifp = &sc->arpcom.ac_if;
969 ifp->if_name = "nge";
970 ifp->if_mtu = ETHERMTU;
971 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
972 ifp->if_ioctl = nge_ioctl;
973 ifp->if_output = ether_output;
974 ifp->if_start = nge_start;
975 ifp->if_watchdog = nge_watchdog;
976 ifp->if_init = nge_init;
977 ifp->if_baudrate = 1000000000;
978 ifp->if_snd.ifq_maxlen = NGE_TX_LIST_CNT - 1;
979 ifp->if_hwassist = NGE_CSUM_FEATURES;
980 ifp->if_capabilities = IFCAP_HWCSUM;
981 ifp->if_capenable = ifp->if_capabilities;
986 if (mii_phy_probe(dev, &sc->nge_miibus,
987 nge_ifmedia_upd, nge_ifmedia_sts)) {
988 if (CSR_READ_4(sc, NGE_CFG) & NGE_CFG_TBI_EN) {
990 device_printf(dev, "Using TBI\n");
992 sc->nge_miibus = dev;
994 ifmedia_init(&sc->nge_ifmedia, 0, nge_ifmedia_upd,
996 #define ADD(m, c) ifmedia_add(&sc->nge_ifmedia, (m), (c), NULL)
997 #define PRINT(s) printf("%s%s", sep, s); sep = ", "
998 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, 0), 0);
999 device_printf(dev, " ");
1000 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, 0, 0), 0);
1001 PRINT("1000baseSX");
1002 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, 0),0);
1003 PRINT("1000baseSX-FDX");
1004 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0), 0);
1010 ifmedia_set(&sc->nge_ifmedia,
1011 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0));
1013 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
1015 | NGE_GPIO_GP1_OUTENB | NGE_GPIO_GP2_OUTENB
1016 | NGE_GPIO_GP3_OUTENB
1017 | NGE_GPIO_GP3_IN | NGE_GPIO_GP4_IN);
1020 printf("nge%d: MII without any PHY!\n", sc->nge_unit);
1021 nge_free_jumbo_mem(sc);
1022 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand);
1023 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
1024 bus_release_resource(dev, NGE_RES, NGE_RID,
1032 * Call MI attach routine.
1034 ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
1035 callout_handle_init(&sc->nge_stat_ch);
1040 mtx_destroy(&sc->nge_mtx);
1048 struct nge_softc *sc;
1054 sc = device_get_softc(dev);
1055 ifp = &sc->arpcom.ac_if;
1059 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
1061 bus_generic_detach(dev);
1063 device_delete_child(dev, sc->nge_miibus);
1065 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand);
1066 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
1067 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
1069 contigfree(sc->nge_ldata, sizeof(struct nge_list_data), M_DEVBUF);
1070 nge_free_jumbo_mem(sc);
1073 mtx_destroy(&sc->nge_mtx);
1079 * Initialize the transmit descriptors.
1082 nge_list_tx_init(sc)
1083 struct nge_softc *sc;
1085 struct nge_list_data *ld;
1086 struct nge_ring_data *cd;
1089 cd = &sc->nge_cdata;
1092 for (i = 0; i < NGE_TX_LIST_CNT; i++) {
1093 if (i == (NGE_TX_LIST_CNT - 1)) {
1094 ld->nge_tx_list[i].nge_nextdesc =
1095 &ld->nge_tx_list[0];
1096 ld->nge_tx_list[i].nge_next =
1097 vtophys(&ld->nge_tx_list[0]);
1099 ld->nge_tx_list[i].nge_nextdesc =
1100 &ld->nge_tx_list[i + 1];
1101 ld->nge_tx_list[i].nge_next =
1102 vtophys(&ld->nge_tx_list[i + 1]);
1104 ld->nge_tx_list[i].nge_mbuf = NULL;
1105 ld->nge_tx_list[i].nge_ptr = 0;
1106 ld->nge_tx_list[i].nge_ctl = 0;
1109 cd->nge_tx_prod = cd->nge_tx_cons = cd->nge_tx_cnt = 0;
1116 * Initialize the RX descriptors and allocate mbufs for them. Note that
1117 * we arrange the descriptors in a closed ring, so that the last descriptor
1118 * points back to the first.
1121 nge_list_rx_init(sc)
1122 struct nge_softc *sc;
1124 struct nge_list_data *ld;
1125 struct nge_ring_data *cd;
1129 cd = &sc->nge_cdata;
1131 for (i = 0; i < NGE_RX_LIST_CNT; i++) {
1132 if (nge_newbuf(sc, &ld->nge_rx_list[i], NULL) == ENOBUFS)
1134 if (i == (NGE_RX_LIST_CNT - 1)) {
1135 ld->nge_rx_list[i].nge_nextdesc =
1136 &ld->nge_rx_list[0];
1137 ld->nge_rx_list[i].nge_next =
1138 vtophys(&ld->nge_rx_list[0]);
1140 ld->nge_rx_list[i].nge_nextdesc =
1141 &ld->nge_rx_list[i + 1];
1142 ld->nge_rx_list[i].nge_next =
1143 vtophys(&ld->nge_rx_list[i + 1]);
1147 cd->nge_rx_prod = 0;
1153 * Initialize an RX descriptor and attach an MBUF cluster.
1156 nge_newbuf(sc, c, m)
1157 struct nge_softc *sc;
1161 struct mbuf *m_new = NULL;
1162 caddr_t *buf = NULL;
1165 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1166 if (m_new == NULL) {
1167 printf("nge%d: no memory for rx list "
1168 "-- packet dropped!\n", sc->nge_unit);
1172 /* Allocate the jumbo buffer */
1173 buf = nge_jalloc(sc);
1176 printf("nge%d: jumbo allocation failed "
1177 "-- packet dropped!\n", sc->nge_unit);
1182 /* Attach the buffer to the mbuf */
1183 m_new->m_data = (void *)buf;
1184 m_new->m_len = m_new->m_pkthdr.len = NGE_JUMBO_FRAMELEN;
1185 MEXTADD(m_new, buf, NGE_JUMBO_FRAMELEN, nge_jfree,
1186 (struct nge_softc *)sc, 0, EXT_NET_DRV);
1189 m_new->m_len = m_new->m_pkthdr.len = NGE_JUMBO_FRAMELEN;
1190 m_new->m_data = m_new->m_ext.ext_buf;
1193 m_adj(m_new, sizeof(u_int64_t));
1195 c->nge_mbuf = m_new;
1196 c->nge_ptr = vtophys(mtod(m_new, caddr_t));
1197 c->nge_ctl = m_new->m_len;
1204 nge_alloc_jumbo_mem(sc)
1205 struct nge_softc *sc;
1209 struct nge_jpool_entry *entry;
1211 /* Grab a big chunk o' storage. */
1212 sc->nge_cdata.nge_jumbo_buf = contigmalloc(NGE_JMEM, M_DEVBUF,
1213 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1215 if (sc->nge_cdata.nge_jumbo_buf == NULL) {
1216 printf("nge%d: no memory for jumbo buffers!\n", sc->nge_unit);
1220 SLIST_INIT(&sc->nge_jfree_listhead);
1221 SLIST_INIT(&sc->nge_jinuse_listhead);
1224 * Now divide it up into 9K pieces and save the addresses
1227 ptr = sc->nge_cdata.nge_jumbo_buf;
1228 for (i = 0; i < NGE_JSLOTS; i++) {
1229 sc->nge_cdata.nge_jslots[i] = ptr;
1231 entry = malloc(sizeof(struct nge_jpool_entry),
1232 M_DEVBUF, M_NOWAIT);
1233 if (entry == NULL) {
1234 printf("nge%d: no memory for jumbo "
1235 "buffer queue!\n", sc->nge_unit);
1239 SLIST_INSERT_HEAD(&sc->nge_jfree_listhead,
1240 entry, jpool_entries);
1247 nge_free_jumbo_mem(sc)
1248 struct nge_softc *sc;
1251 struct nge_jpool_entry *entry;
1253 for (i = 0; i < NGE_JSLOTS; i++) {
1254 entry = SLIST_FIRST(&sc->nge_jfree_listhead);
1255 SLIST_REMOVE_HEAD(&sc->nge_jfree_listhead, jpool_entries);
1256 free(entry, M_DEVBUF);
1259 contigfree(sc->nge_cdata.nge_jumbo_buf, NGE_JMEM, M_DEVBUF);
1265 * Allocate a jumbo buffer.
1269 struct nge_softc *sc;
1271 struct nge_jpool_entry *entry;
1273 entry = SLIST_FIRST(&sc->nge_jfree_listhead);
1275 if (entry == NULL) {
1277 printf("nge%d: no free jumbo buffers\n", sc->nge_unit);
1282 SLIST_REMOVE_HEAD(&sc->nge_jfree_listhead, jpool_entries);
1283 SLIST_INSERT_HEAD(&sc->nge_jinuse_listhead, entry, jpool_entries);
1284 return(sc->nge_cdata.nge_jslots[entry->slot]);
1288 * Release a jumbo buffer.
1291 nge_jfree(buf, args)
1295 struct nge_softc *sc;
1297 struct nge_jpool_entry *entry;
1299 /* Extract the softc struct pointer. */
1303 panic("nge_jfree: can't find softc pointer!");
1305 /* calculate the slot this buffer belongs to */
1306 i = ((vm_offset_t)buf
1307 - (vm_offset_t)sc->nge_cdata.nge_jumbo_buf) / NGE_JLEN;
1309 if ((i < 0) || (i >= NGE_JSLOTS))
1310 panic("nge_jfree: asked to free buffer that we don't manage!");
1312 entry = SLIST_FIRST(&sc->nge_jinuse_listhead);
1314 panic("nge_jfree: buffer not in use!");
1316 SLIST_REMOVE_HEAD(&sc->nge_jinuse_listhead, jpool_entries);
1317 SLIST_INSERT_HEAD(&sc->nge_jfree_listhead, entry, jpool_entries);
1322 * A frame has been uploaded: pass the resulting mbuf chain up to
1323 * the higher level protocols.
1327 struct nge_softc *sc;
1329 struct ether_header *eh;
1332 struct nge_desc *cur_rx;
1333 int i, total_len = 0;
1336 ifp = &sc->arpcom.ac_if;
1337 i = sc->nge_cdata.nge_rx_prod;
1339 while(NGE_OWNDESC(&sc->nge_ldata->nge_rx_list[i])) {
1340 struct mbuf *m0 = NULL;
1343 cur_rx = &sc->nge_ldata->nge_rx_list[i];
1344 rxstat = cur_rx->nge_rxstat;
1345 extsts = cur_rx->nge_extsts;
1346 m = cur_rx->nge_mbuf;
1347 cur_rx->nge_mbuf = NULL;
1348 total_len = NGE_RXBYTES(cur_rx);
1349 NGE_INC(i, NGE_RX_LIST_CNT);
1351 * If an error occurs, update stats, clear the
1352 * status word and leave the mbuf cluster in place:
1353 * it should simply get re-used next time this descriptor
1354 * comes up in the ring.
1356 if (!(rxstat & NGE_CMDSTS_PKT_OK)) {
1358 nge_newbuf(sc, cur_rx, m);
1363 * Ok. NatSemi really screwed up here. This is the
1364 * only gigE chip I know of with alignment constraints
1365 * on receive buffers. RX buffers must be 64-bit aligned.
1369 * By popular demand, ignore the alignment problems
1370 * on the Intel x86 platform. The performance hit
1371 * incurred due to unaligned accesses is much smaller
1372 * than the hit produced by forcing buffer copies all
1373 * the time, especially with jumbo frames. We still
1374 * need to fix up the alignment everywhere else though.
1376 if (nge_newbuf(sc, cur_rx, NULL) == ENOBUFS) {
1378 m0 = m_devget(mtod(m, char *), total_len,
1379 ETHER_ALIGN, ifp, NULL);
1380 nge_newbuf(sc, cur_rx, m);
1382 printf("nge%d: no receive buffers "
1383 "available -- packet dropped!\n",
1391 m->m_pkthdr.rcvif = ifp;
1392 m->m_pkthdr.len = m->m_len = total_len;
1397 eh = mtod(m, struct ether_header *);
1399 /* Remove header from mbuf and pass it on. */
1400 m_adj(m, sizeof(struct ether_header));
1402 /* Do IP checksum checking. */
1403 if (extsts & NGE_RXEXTSTS_IPPKT)
1404 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1405 if (!(extsts & NGE_RXEXTSTS_IPCSUMERR))
1406 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1407 if ((extsts & NGE_RXEXTSTS_TCPPKT &&
1408 !(extsts & NGE_RXEXTSTS_TCPCSUMERR)) ||
1409 (extsts & NGE_RXEXTSTS_UDPPKT &&
1410 !(extsts & NGE_RXEXTSTS_UDPCSUMERR))) {
1411 m->m_pkthdr.csum_flags |=
1412 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1413 m->m_pkthdr.csum_data = 0xffff;
1417 * If we received a packet with a vlan tag, pass it
1418 * to vlan_input() instead of ether_input().
1420 if (extsts & NGE_RXEXTSTS_VLANPKT) {
1421 VLAN_INPUT_TAG(eh, m, extsts & NGE_RXEXTSTS_VTCI);
1425 ether_input(ifp, eh, m);
1428 sc->nge_cdata.nge_rx_prod = i;
1434 * A frame was downloaded to the chip. It's safe for us to clean up
1440 struct nge_softc *sc;
1442 struct nge_desc *cur_tx = NULL;
1446 ifp = &sc->arpcom.ac_if;
1448 /* Clear the timeout timer. */
1452 * Go through our tx list and free mbufs for those
1453 * frames that have been transmitted.
1455 idx = sc->nge_cdata.nge_tx_cons;
1456 while (idx != sc->nge_cdata.nge_tx_prod) {
1457 cur_tx = &sc->nge_ldata->nge_tx_list[idx];
1459 if (NGE_OWNDESC(cur_tx))
1462 if (cur_tx->nge_ctl & NGE_CMDSTS_MORE) {
1463 sc->nge_cdata.nge_tx_cnt--;
1464 NGE_INC(idx, NGE_TX_LIST_CNT);
1468 if (!(cur_tx->nge_ctl & NGE_CMDSTS_PKT_OK)) {
1470 if (cur_tx->nge_txstat & NGE_TXSTAT_EXCESSCOLLS)
1471 ifp->if_collisions++;
1472 if (cur_tx->nge_txstat & NGE_TXSTAT_OUTOFWINCOLL)
1473 ifp->if_collisions++;
1476 ifp->if_collisions +=
1477 (cur_tx->nge_txstat & NGE_TXSTAT_COLLCNT) >> 16;
1480 if (cur_tx->nge_mbuf != NULL) {
1481 m_freem(cur_tx->nge_mbuf);
1482 cur_tx->nge_mbuf = NULL;
1485 sc->nge_cdata.nge_tx_cnt--;
1486 NGE_INC(idx, NGE_TX_LIST_CNT);
1490 sc->nge_cdata.nge_tx_cons = idx;
1493 ifp->if_flags &= ~IFF_OACTIVE;
1502 struct nge_softc *sc;
1503 struct mii_data *mii;
1510 ifp = &sc->arpcom.ac_if;
1513 if (!sc->nge_link) {
1514 if (CSR_READ_4(sc, NGE_TBI_BMSR)
1515 & NGE_TBIBMSR_ANEG_DONE) {
1516 printf("nge%d: gigabit link up\n",
1518 nge_miibus_statchg(sc->nge_miibus);
1520 if (ifp->if_snd.ifq_head != NULL)
1525 mii = device_get_softc(sc->nge_miibus);
1528 if (!sc->nge_link) {
1529 if (mii->mii_media_status & IFM_ACTIVE &&
1530 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1532 if (IFM_SUBTYPE(mii->mii_media_active)
1534 printf("nge%d: gigabit link up\n",
1536 if (ifp->if_snd.ifq_head != NULL)
1541 sc->nge_stat_ch = timeout(nge_tick, sc, hz);
1552 struct nge_softc *sc;
1557 ifp = &sc->arpcom.ac_if;
1559 /* Supress unwanted interrupts */
1560 if (!(ifp->if_flags & IFF_UP)) {
1565 /* Disable interrupts. */
1566 CSR_WRITE_4(sc, NGE_IER, 0);
1568 /* Data LED on for TBI mode */
1570 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
1571 | NGE_GPIO_GP3_OUT);
1574 /* Reading the ISR register clears all interrupts. */
1575 status = CSR_READ_4(sc, NGE_ISR);
1577 if ((status & NGE_INTRS) == 0)
1580 if ((status & NGE_ISR_TX_DESC_OK) ||
1581 (status & NGE_ISR_TX_ERR) ||
1582 (status & NGE_ISR_TX_OK) ||
1583 (status & NGE_ISR_TX_IDLE))
1586 if ((status & NGE_ISR_RX_DESC_OK) ||
1587 (status & NGE_ISR_RX_ERR) ||
1588 (status & NGE_ISR_RX_OFLOW) ||
1589 (status & NGE_ISR_RX_FIFO_OFLOW) ||
1590 (status & NGE_ISR_RX_IDLE) ||
1591 (status & NGE_ISR_RX_OK))
1594 if ((status & NGE_ISR_RX_IDLE))
1595 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE);
1597 if (status & NGE_ISR_SYSERR) {
1599 ifp->if_flags &= ~IFF_RUNNING;
1605 * XXX: nge_tick() is not ready to be called this way
1606 * it screws up the aneg timeout because mii_tick() is
1607 * only to be called once per second.
1609 if (status & NGE_IMR_PHY_INTR) {
1616 /* Re-enable interrupts. */
1617 CSR_WRITE_4(sc, NGE_IER, 1);
1619 if (ifp->if_snd.ifq_head != NULL)
1622 /* Data LED off for TBI mode */
1625 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
1626 & ~NGE_GPIO_GP3_OUT);
1632 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1633 * pointers to the fragment pointers.
1636 nge_encap(sc, m_head, txidx)
1637 struct nge_softc *sc;
1638 struct mbuf *m_head;
1641 struct nge_desc *f = NULL;
1643 int frag, cur, cnt = 0;
1644 struct ifvlan *ifv = NULL;
1646 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
1647 m_head->m_pkthdr.rcvif != NULL &&
1648 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN)
1649 ifv = m_head->m_pkthdr.rcvif->if_softc;
1652 * Start packing the mbufs in this chain into
1653 * the fragment pointers. Stop when we run out
1654 * of fragments or hit the end of the mbuf chain.
1657 cur = frag = *txidx;
1659 for (m = m_head; m != NULL; m = m->m_next) {
1660 if (m->m_len != 0) {
1661 if ((NGE_TX_LIST_CNT -
1662 (sc->nge_cdata.nge_tx_cnt + cnt)) < 2)
1664 f = &sc->nge_ldata->nge_tx_list[frag];
1665 f->nge_ctl = NGE_CMDSTS_MORE | m->m_len;
1666 f->nge_ptr = vtophys(mtod(m, vm_offset_t));
1668 f->nge_ctl |= NGE_CMDSTS_OWN;
1670 NGE_INC(frag, NGE_TX_LIST_CNT);
1678 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts = 0;
1679 if (m_head->m_pkthdr.csum_flags) {
1680 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
1681 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |=
1682 NGE_TXEXTSTS_IPCSUM;
1683 if (m_head->m_pkthdr.csum_flags & CSUM_TCP)
1684 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |=
1685 NGE_TXEXTSTS_TCPCSUM;
1686 if (m_head->m_pkthdr.csum_flags & CSUM_UDP)
1687 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |=
1688 NGE_TXEXTSTS_UDPCSUM;
1692 sc->nge_ldata->nge_tx_list[cur].nge_extsts |=
1693 (NGE_TXEXTSTS_VLANPKT|ifv->ifv_tag);
1696 sc->nge_ldata->nge_tx_list[cur].nge_mbuf = m_head;
1697 sc->nge_ldata->nge_tx_list[cur].nge_ctl &= ~NGE_CMDSTS_MORE;
1698 sc->nge_ldata->nge_tx_list[*txidx].nge_ctl |= NGE_CMDSTS_OWN;
1699 sc->nge_cdata.nge_tx_cnt += cnt;
1706 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1707 * to the mbuf data regions directly in the transmit lists. We also save a
1708 * copy of the pointers since the transmit list fragment pointers are
1709 * physical addresses.
1716 struct nge_softc *sc;
1717 struct mbuf *m_head = NULL;
1725 idx = sc->nge_cdata.nge_tx_prod;
1727 if (ifp->if_flags & IFF_OACTIVE)
1730 while(sc->nge_ldata->nge_tx_list[idx].nge_mbuf == NULL) {
1731 IF_DEQUEUE(&ifp->if_snd, m_head);
1735 if (nge_encap(sc, m_head, &idx)) {
1736 IF_PREPEND(&ifp->if_snd, m_head);
1737 ifp->if_flags |= IFF_OACTIVE;
1742 * If there's a BPF listener, bounce a copy of this frame
1746 bpf_mtap(ifp, m_head);
1751 sc->nge_cdata.nge_tx_prod = idx;
1752 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_ENABLE);
1755 * Set a timeout in case the chip goes out to lunch.
1766 struct nge_softc *sc = xsc;
1767 struct ifnet *ifp = &sc->arpcom.ac_if;
1768 struct mii_data *mii;
1771 if (ifp->if_flags & IFF_RUNNING)
1777 * Cancel pending I/O and free all RX/TX buffers.
1784 mii = device_get_softc(sc->nge_miibus);
1787 /* Set MAC address */
1788 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR0);
1789 CSR_WRITE_4(sc, NGE_RXFILT_DATA,
1790 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]);
1791 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR1);
1792 CSR_WRITE_4(sc, NGE_RXFILT_DATA,
1793 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]);
1794 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR2);
1795 CSR_WRITE_4(sc, NGE_RXFILT_DATA,
1796 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]);
1798 /* Init circular RX list. */
1799 if (nge_list_rx_init(sc) == ENOBUFS) {
1800 printf("nge%d: initialization failed: no "
1801 "memory for rx buffers\n", sc->nge_unit);
1808 * Init tx descriptors.
1810 nge_list_tx_init(sc);
1813 * For the NatSemi chip, we have to explicitly enable the
1814 * reception of ARP frames, as well as turn on the 'perfect
1815 * match' filter where we store the station address, otherwise
1816 * we won't receive unicasts meant for this host.
1818 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ARP);
1819 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_PERFECT);
1821 /* If we want promiscuous mode, set the allframes bit. */
1822 if (ifp->if_flags & IFF_PROMISC) {
1823 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS);
1825 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS);
1829 * Set the capture broadcast bit to capture broadcast frames.
1831 if (ifp->if_flags & IFF_BROADCAST) {
1832 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD);
1834 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD);
1838 * Load the multicast filter.
1842 /* Turn the receive filter on */
1843 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ENABLE);
1846 * Load the address of the RX and TX lists.
1848 CSR_WRITE_4(sc, NGE_RX_LISTPTR,
1849 vtophys(&sc->nge_ldata->nge_rx_list[0]));
1850 CSR_WRITE_4(sc, NGE_TX_LISTPTR,
1851 vtophys(&sc->nge_ldata->nge_tx_list[0]));
1853 /* Set RX configuration */
1854 CSR_WRITE_4(sc, NGE_RX_CFG, NGE_RXCFG);
1856 * Enable hardware checksum validation for all IPv4
1857 * packets, do not reject packets with bad checksums.
1859 CSR_WRITE_4(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_IPCSUM_ENB);
1862 * Tell the chip to detect and strip VLAN tag info from
1863 * received frames. The tag will be provided in the extsts
1864 * field in the RX descriptors.
1866 NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL,
1867 NGE_VIPRXCTL_TAG_DETECT_ENB|NGE_VIPRXCTL_TAG_STRIP_ENB);
1869 /* Set TX configuration */
1870 CSR_WRITE_4(sc, NGE_TX_CFG, NGE_TXCFG);
1873 * Enable TX IPv4 checksumming on a per-packet basis.
1875 CSR_WRITE_4(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_CSUM_PER_PKT);
1878 * Tell the chip to insert VLAN tags on a per-packet basis as
1879 * dictated by the code in the frame encapsulation routine.
1881 NGE_SETBIT(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_TAG_PER_PKT);
1883 /* Set full/half duplex mode. */
1885 if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK)
1887 NGE_SETBIT(sc, NGE_TX_CFG,
1888 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
1889 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1891 NGE_CLRBIT(sc, NGE_TX_CFG,
1892 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
1893 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1896 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1897 NGE_SETBIT(sc, NGE_TX_CFG,
1898 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
1899 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1901 NGE_CLRBIT(sc, NGE_TX_CFG,
1902 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
1903 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1910 * Enable the delivery of PHY interrupts based on
1911 * link/speed/duplex status changes. Also enable the
1912 * extsts field in the DMA descriptors (needed for
1913 * TCP/IP checksum offload on transmit).
1915 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_PHYINTR_SPD|
1916 NGE_CFG_PHYINTR_LNK|NGE_CFG_PHYINTR_DUP|NGE_CFG_EXTSTS_ENB);
1919 * Configure interrupt holdoff (moderation). We can
1920 * have the chip delay interrupt delivery for a certain
1921 * period. Units are in 100us, and the max setting
1922 * is 25500us (0xFF x 100us). Default is a 100us holdoff.
1924 CSR_WRITE_4(sc, NGE_IHR, 0x01);
1927 * Enable interrupts.
1929 CSR_WRITE_4(sc, NGE_IMR, NGE_INTRS);
1930 CSR_WRITE_4(sc, NGE_IER, 1);
1932 /* Enable receiver and transmitter. */
1933 NGE_CLRBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE);
1934 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE);
1936 nge_ifmedia_upd(ifp);
1938 ifp->if_flags |= IFF_RUNNING;
1939 ifp->if_flags &= ~IFF_OACTIVE;
1947 * Set media options.
1950 nge_ifmedia_upd(ifp)
1953 struct nge_softc *sc;
1954 struct mii_data *mii;
1959 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media)
1961 CSR_WRITE_4(sc, NGE_TBI_ANAR,
1962 CSR_READ_4(sc, NGE_TBI_ANAR)
1963 | NGE_TBIANAR_HDX | NGE_TBIANAR_FDX
1964 | NGE_TBIANAR_PS1 | NGE_TBIANAR_PS2);
1965 CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG
1966 | NGE_TBIBMCR_RESTART_ANEG);
1967 CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG);
1968 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media
1969 & IFM_GMASK) == IFM_FDX) {
1970 NGE_SETBIT(sc, NGE_TX_CFG,
1971 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
1972 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1974 CSR_WRITE_4(sc, NGE_TBI_ANAR, 0);
1975 CSR_WRITE_4(sc, NGE_TBI_BMCR, 0);
1977 NGE_CLRBIT(sc, NGE_TX_CFG,
1978 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
1979 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1981 CSR_WRITE_4(sc, NGE_TBI_ANAR, 0);
1982 CSR_WRITE_4(sc, NGE_TBI_BMCR, 0);
1985 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
1986 & ~NGE_GPIO_GP3_OUT);
1988 mii = device_get_softc(sc->nge_miibus);
1990 if (mii->mii_instance) {
1991 struct mii_softc *miisc;
1992 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
1993 miisc = LIST_NEXT(miisc, mii_list))
1994 mii_phy_reset(miisc);
2003 * Report current media status.
2006 nge_ifmedia_sts(ifp, ifmr)
2008 struct ifmediareq *ifmr;
2010 struct nge_softc *sc;
2011 struct mii_data *mii;
2016 ifmr->ifm_status = IFM_AVALID;
2017 ifmr->ifm_active = IFM_ETHER;
2019 if (CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE) {
2020 ifmr->ifm_status |= IFM_ACTIVE;
2022 if (CSR_READ_4(sc, NGE_TBI_BMCR) & NGE_TBIBMCR_LOOPBACK)
2023 ifmr->ifm_active |= IFM_LOOP;
2024 if (!CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE) {
2025 ifmr->ifm_active |= IFM_NONE;
2026 ifmr->ifm_status = 0;
2029 ifmr->ifm_active |= IFM_1000_SX;
2030 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media)
2032 ifmr->ifm_active |= IFM_AUTO;
2033 if (CSR_READ_4(sc, NGE_TBI_ANLPAR)
2034 & NGE_TBIANAR_FDX) {
2035 ifmr->ifm_active |= IFM_FDX;
2036 }else if (CSR_READ_4(sc, NGE_TBI_ANLPAR)
2037 & NGE_TBIANAR_HDX) {
2038 ifmr->ifm_active |= IFM_HDX;
2040 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK)
2042 ifmr->ifm_active |= IFM_FDX;
2044 ifmr->ifm_active |= IFM_HDX;
2047 mii = device_get_softc(sc->nge_miibus);
2049 ifmr->ifm_active = mii->mii_media_active;
2050 ifmr->ifm_status = mii->mii_media_status;
2057 nge_ioctl(ifp, command, data)
2062 struct nge_softc *sc = ifp->if_softc;
2063 struct ifreq *ifr = (struct ifreq *) data;
2064 struct mii_data *mii;
2072 error = ether_ioctl(ifp, command, data);
2075 if (ifr->ifr_mtu > NGE_JUMBO_MTU)
2078 ifp->if_mtu = ifr->ifr_mtu;
2080 * Workaround: if the MTU is larger than
2081 * 8152 (TX FIFO size minus 64 minus 18), turn off
2082 * TX checksum offloading.
2084 if (ifr->ifr_mtu >= 8152)
2085 ifp->if_hwassist = 0;
2087 ifp->if_hwassist = NGE_CSUM_FEATURES;
2091 if (ifp->if_flags & IFF_UP) {
2092 if (ifp->if_flags & IFF_RUNNING &&
2093 ifp->if_flags & IFF_PROMISC &&
2094 !(sc->nge_if_flags & IFF_PROMISC)) {
2095 NGE_SETBIT(sc, NGE_RXFILT_CTL,
2096 NGE_RXFILTCTL_ALLPHYS|
2097 NGE_RXFILTCTL_ALLMULTI);
2098 } else if (ifp->if_flags & IFF_RUNNING &&
2099 !(ifp->if_flags & IFF_PROMISC) &&
2100 sc->nge_if_flags & IFF_PROMISC) {
2101 NGE_CLRBIT(sc, NGE_RXFILT_CTL,
2102 NGE_RXFILTCTL_ALLPHYS);
2103 if (!(ifp->if_flags & IFF_ALLMULTI))
2104 NGE_CLRBIT(sc, NGE_RXFILT_CTL,
2105 NGE_RXFILTCTL_ALLMULTI);
2107 ifp->if_flags &= ~IFF_RUNNING;
2111 if (ifp->if_flags & IFF_RUNNING)
2114 sc->nge_if_flags = ifp->if_flags;
2125 error = ifmedia_ioctl(ifp, ifr, &sc->nge_ifmedia,
2128 mii = device_get_softc(sc->nge_miibus);
2129 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
2147 struct nge_softc *sc;
2152 printf("nge%d: watchdog timeout\n", sc->nge_unit);
2156 ifp->if_flags &= ~IFF_RUNNING;
2159 if (ifp->if_snd.ifq_head != NULL)
2166 * Stop the adapter and free any mbufs allocated to the
2171 struct nge_softc *sc;
2175 struct mii_data *mii;
2177 ifp = &sc->arpcom.ac_if;
2182 mii = device_get_softc(sc->nge_miibus);
2185 untimeout(nge_tick, sc, sc->nge_stat_ch);
2186 CSR_WRITE_4(sc, NGE_IER, 0);
2187 CSR_WRITE_4(sc, NGE_IMR, 0);
2188 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE);
2190 CSR_WRITE_4(sc, NGE_TX_LISTPTR, 0);
2191 CSR_WRITE_4(sc, NGE_RX_LISTPTR, 0);
2199 * Free data in the RX lists.
2201 for (i = 0; i < NGE_RX_LIST_CNT; i++) {
2202 if (sc->nge_ldata->nge_rx_list[i].nge_mbuf != NULL) {
2203 m_freem(sc->nge_ldata->nge_rx_list[i].nge_mbuf);
2204 sc->nge_ldata->nge_rx_list[i].nge_mbuf = NULL;
2207 bzero((char *)&sc->nge_ldata->nge_rx_list,
2208 sizeof(sc->nge_ldata->nge_rx_list));
2211 * Free the TX list buffers.
2213 for (i = 0; i < NGE_TX_LIST_CNT; i++) {
2214 if (sc->nge_ldata->nge_tx_list[i].nge_mbuf != NULL) {
2215 m_freem(sc->nge_ldata->nge_tx_list[i].nge_mbuf);
2216 sc->nge_ldata->nge_tx_list[i].nge_mbuf = NULL;
2220 bzero((char *)&sc->nge_ldata->nge_tx_list,
2221 sizeof(sc->nge_ldata->nge_tx_list));
2223 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2229 * Stop all chip I/O so that the kernel's probe routines don't
2230 * get confused by errant DMAs when rebooting.
2236 struct nge_softc *sc;
2238 sc = device_get_softc(dev);