2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2000, 2001
4 * Bill Paul <wpaul@bsdi.com>. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
39 #define NGE_PCITST 0x0C
44 #define NGE_TX_LISTPTR_LO 0x20
45 #define NGE_TX_LISTPTR_HI 0x24
46 #define NGE_TX_LISTPTR NGE_TX_LISTPTR_LO
47 #define NGE_TX_CFG 0x28
49 #define NGE_RX_LISTPTR_LO 0x30
50 #define NGE_RX_LISTPTR_HI 0x34
51 #define NGE_RX_LISTPTR NGE_RX_LISTPTR_LO
52 #define NGE_RX_CFG 0x38
53 #define NGE_PRIOQCTL 0x3C
54 #define NGE_WOLCSR 0x40
55 #define NGE_PAUSECSR 0x44
56 #define NGE_RXFILT_CTL 0x48
57 #define NGE_RXFILT_DATA 0x4C
58 #define NGE_BOOTROM_ADDR 0x50
59 #define NGE_BOOTROM_DATA 0x54
60 #define NGE_SILICONREV 0x58
61 #define NGE_MIBCTL 0x5C
62 #define NGE_MIB_RXERRPKT 0x60
63 #define NGE_MIB_RXERRFCS 0x64
64 #define NGE_MIB_RXERRMISSEDPKT 0x68
65 #define NGE_MIB_RXERRALIGN 0x6C
66 #define NGE_MIB_RXERRSYM 0x70
67 #define NGE_MIB_RXERRGIANT 0x74
68 #define NGE_MIB_RXERRRANGLEN 0x78
69 #define NGE_MIB_RXBADOPCODE 0x7C
70 #define NGE_MIB_RXPAUSEPKTS 0x80
71 #define NGE_MIB_TXPAUSEPKTS 0x84
72 #define NGE_MIB_TXERRSQE 0x88
73 #define NGE_TXPRIOQ_PTR1 0xA0
74 #define NGE_TXPRIOQ_PTR2 0xA4
75 #define NGE_TXPRIOQ_PTR3 0xA8
76 #define NGE_RXPRIOQ_PTR1 0xB0
77 #define NGE_RXPRIOQ_PTR2 0xB4
78 #define NGE_RXPRIOQ_PTR3 0xB8
79 #define NGE_VLAN_IP_RXCTL 0xBC
80 #define NGE_VLAN_IP_TXCTL 0xC0
81 #define NGE_VLAN_DATA 0xC4
82 #define NGE_CLKRUN 0xCC
83 #define NGE_TBI_BMCR 0xE0
84 #define NGE_TBI_BMSR 0xE4
85 #define NGE_TBI_ANAR 0xE8
86 #define NGE_TBI_ANLPAR 0xEC
87 #define NGE_TBI_ANER 0xF0
88 #define NGE_TBI_ESR 0xF4
90 /* Control/status register */
91 #define NGE_CSR_TX_ENABLE 0x00000001
92 #define NGE_CSR_TX_DISABLE 0x00000002
93 #define NGE_CSR_RX_ENABLE 0x00000004
94 #define NGE_CSR_RX_DISABLE 0x00000008
95 #define NGE_CSR_TX_RESET 0x00000010
96 #define NGE_CSR_RX_RESET 0x00000020
97 #define NGE_CSR_SOFTINTR 0x00000080
98 #define NGE_CSR_RESET 0x00000100
99 #define NGE_CSR_TX_PRIOQ_ENB0 0x00000200
100 #define NGE_CSR_TX_PRIOQ_ENB1 0x00000400
101 #define NGE_CSR_TX_PRIOQ_ENB2 0x00000800
102 #define NGE_CSR_TX_PRIOQ_ENB3 0x00001000
103 #define NGE_CSR_RX_PRIOQ_ENB0 0x00002000
104 #define NGE_CSR_RX_PRIOQ_ENB1 0x00004000
105 #define NGE_CSR_RX_PRIOQ_ENB2 0x00008000
106 #define NGE_CSR_RX_PRIOQ_ENB3 0x00010000
108 /* Configuration register */
109 #define NGE_CFG_BIGENDIAN 0x00000001
110 #define NGE_CFG_EXT_125MHZ 0x00000002
111 #define NGE_CFG_BOOTROM_DIS 0x00000004
112 #define NGE_CFG_PERR_DETECT 0x00000008
113 #define NGE_CFG_DEFER_DISABLE 0x00000010
114 #define NGE_CFG_OUTOFWIN_TIMER 0x00000020
115 #define NGE_CFG_SINGLE_BACKOFF 0x00000040
116 #define NGE_CFG_PCIREQ_ALG 0x00000080
117 #define NGE_CFG_EXTSTS_ENB 0x00000100
118 #define NGE_CFG_PHY_DIS 0x00000200
119 #define NGE_CFG_PHY_RST 0x00000400
120 #define NGE_CFG_64BIT_ADDR_ENB 0x00000800
121 #define NGE_CFG_64BIT_DATA_ENB 0x00001000
122 #define NGE_CFG_64BIT_PCI_DET 0x00002000
123 #define NGE_CFG_64BIT_TARG 0x00004000
124 #define NGE_CFG_MWI_DIS 0x00008000
125 #define NGE_CFG_MRM_DIS 0x00010000
126 #define NGE_CFG_TMRTST 0x00020000
127 #define NGE_CFG_PHYINTR_SPD 0x00040000
128 #define NGE_CFG_PHYINTR_LNK 0x00080000
129 #define NGE_CFG_PHYINTR_DUP 0x00100000
130 #define NGE_CFG_MODE_1000 0x00400000
131 #define NGE_CFG_DUPLEX_STS 0x10000000
132 #define NGE_CFG_SPEED_STS 0x60000000
133 #define NGE_CFG_LINK_STS 0x80000000
135 /* MII/EEPROM control register */
136 #define NGE_MEAR_EE_DIN 0x00000001
137 #define NGE_MEAR_EE_DOUT 0x00000002
138 #define NGE_MEAR_EE_CLK 0x00000004
139 #define NGE_MEAR_EE_CSEL 0x00000008
140 #define NGE_MEAR_MII_DATA 0x00000010
141 #define NGE_MEAR_MII_DIR 0x00000020
142 #define NGE_MEAR_MII_CLK 0x00000040
144 #define NGE_EECMD_WRITE 0x140
145 #define NGE_EECMD_READ 0x180
146 #define NGE_EECMD_ERASE 0x1c0
148 #define NGE_EE_NODEADDR 0xA
150 /* PCI control register */
151 #define NGE_PCICTL_SRAMADDR 0x0000001F
152 #define NGE_PCICTL_RAMTSTENB 0x00000020
153 #define NGE_PCICTL_TXTSTENB 0x00000040
154 #define NGE_PCICTL_RXTSTENB 0x00000080
155 #define NGE_PCICTL_BMTSTENB 0x00000200
156 #define NGE_PCICTL_RAMADDR 0x001F0000
157 #define NGE_PCICTL_ROMTIME 0x0F000000
158 #define NGE_PCICTL_DISCTEST 0x40000000
160 /* Interrupt/status register */
161 #define NGE_ISR_RX_OK 0x00000001
162 #define NGE_ISR_RX_DESC_OK 0x00000002
163 #define NGE_ISR_RX_ERR 0x00000004
164 #define NGE_ISR_RX_EARLY 0x00000008
165 #define NGE_ISR_RX_IDLE 0x00000010
166 #define NGE_ISR_RX_OFLOW 0x00000020
167 #define NGE_ISR_TX_OK 0x00000040
168 #define NGE_ISR_TX_DESC_OK 0x00000080
169 #define NGE_ISR_TX_ERR 0x00000100
170 #define NGE_ISR_TX_IDLE 0x00000200
171 #define NGE_ISR_TX_UFLOW 0x00000400
172 #define NGE_ISR_MIB_SERVICE 0x00000800
173 #define NGE_ISR_SOFTINTR 0x00001000
174 #define NGE_ISR_PME_EVENT 0x00002000
175 #define NGE_ISR_PHY_INTR 0x00004000
176 #define NGE_ISR_HIBITS 0x00008000
177 #define NGE_ISR_RX_FIFO_OFLOW 0x00010000
178 #define NGE_ISR_TGT_ABRT 0x00020000
179 #define NGE_ISR_BM_ABRT 0x00040000
180 #define NGE_ISR_SYSERR 0x00080000
181 #define NGE_ISR_PARITY_ERR 0x00100000
182 #define NGE_ISR_RX_RESET_DONE 0x00200000
183 #define NGE_ISR_TX_RESET_DONE 0x00400000
184 #define NGE_ISR_RX_PRIOQ_DESC0 0x00800000
185 #define NGE_ISR_RX_PRIOQ_DESC1 0x01000000
186 #define NGE_ISR_RX_PRIOQ_DESC2 0x02000000
187 #define NGE_ISR_RX_PRIOQ_DESC3 0x04000000
188 #define NGE_ISR_TX_PRIOQ_DESC0 0x08000000
189 #define NGE_ISR_TX_PRIOQ_DESC1 0x10000000
190 #define NGE_ISR_TX_PRIOQ_DESC2 0x20000000
191 #define NGE_ISR_TX_PRIOQ_DESC3 0x40000000
193 /* Interrupt mask register */
194 #define NGE_IMR_RX_OK 0x00000001
195 #define NGE_IMR_RX_DESC_OK 0x00000002
196 #define NGE_IMR_RX_ERR 0x00000004
197 #define NGE_IMR_RX_EARLY 0x00000008
198 #define NGE_IMR_RX_IDLE 0x00000010
199 #define NGE_IMR_RX_OFLOW 0x00000020
200 #define NGE_IMR_TX_OK 0x00000040
201 #define NGE_IMR_TX_DESC_OK 0x00000080
202 #define NGE_IMR_TX_ERR 0x00000100
203 #define NGE_IMR_TX_IDLE 0x00000200
204 #define NGE_IMR_TX_UFLOW 0x00000400
205 #define NGE_IMR_MIB_SERVICE 0x00000800
206 #define NGE_IMR_SOFTINTR 0x00001000
207 #define NGE_IMR_PME_EVENT 0x00002000
208 #define NGE_IMR_PHY_INTR 0x00004000
209 #define NGE_IMR_HIBITS 0x00008000
210 #define NGE_IMR_RX_FIFO_OFLOW 0x00010000
211 #define NGE_IMR_TGT_ABRT 0x00020000
212 #define NGE_IMR_BM_ABRT 0x00040000
213 #define NGE_IMR_SYSERR 0x00080000
214 #define NGE_IMR_PARITY_ERR 0x00100000
215 #define NGE_IMR_RX_RESET_DONE 0x00200000
216 #define NGE_IMR_TX_RESET_DONE 0x00400000
217 #define NGE_IMR_RX_PRIOQ_DESC0 0x00800000
218 #define NGE_IMR_RX_PRIOQ_DESC1 0x01000000
219 #define NGE_IMR_RX_PRIOQ_DESC2 0x02000000
220 #define NGE_IMR_RX_PRIOQ_DESC3 0x04000000
221 #define NGE_IMR_TX_PRIOQ_DESC0 0x08000000
222 #define NGE_IMR_TX_PRIOQ_DESC1 0x10000000
223 #define NGE_IMR_TX_PRIOQ_DESC2 0x20000000
224 #define NGE_IMR_TX_PRIOQ_DESC3 0x40000000
227 (NGE_IMR_RX_OFLOW|NGE_IMR_TX_UFLOW|NGE_IMR_TX_OK|\
228 NGE_IMR_TX_IDLE|NGE_IMR_RX_OK|NGE_IMR_RX_ERR|\
229 NGE_IMR_SYSERR|NGE_IMR_PHY_INTR|\
230 NGE_IMR_RX_IDLE|NGE_IMR_RX_FIFO_OFLOW)
232 /* Interrupt enable register */
233 #define NGE_IER_INTRENB 0x00000001
235 /* Interrupt moderation timer register */
236 #define NGE_IHR_HOLDOFF 0x000000FF
237 #define NGE_IHR_HOLDCTL 0x00000100
239 /* Transmit configuration register */
240 #define NGE_TXCFG_DRAIN_THRESH 0x000000FF /* 32-byte units */
241 #define NGE_TXCFG_FILL_THRESH 0x0000FF00 /* 32-byte units */
242 #define NGE_1000MB_BURST_DIS 0x00080000
243 #define NGE_TXCFG_DMABURST 0x00700000
244 #define NGE_TXCFG_ECRETRY 0x00800000
245 #define NGE_TXCFG_AUTOPAD 0x10000000
246 #define NGE_TXCFG_LOOPBK 0x20000000
247 #define NGE_TXCFG_IGN_HBEAT 0x40000000
248 #define NGE_TXCFG_IGN_CARR 0x80000000
250 #define NGE_TXCFG_DRAIN(x) (((x) >> 5) & NGE_TXCFG_DRAIN_THRESH)
251 #define NGE_TXCFG_FILL(x) ((((x) >> 5) << 8) & NGE_TXCFG_FILL_THRESH)
253 #define NGE_TXDMA_1024BYTES 0x00000000
254 #define NGE_TXDMA_8BYTES 0x00100000
255 #define NGE_TXDMA_16BYTES 0x00200000
256 #define NGE_TXDMA_32BYTES 0x00300000
257 #define NGE_TXDMA_64BYTES 0x00400000
258 #define NGE_TXDMA_128BYTES 0x00500000
259 #define NGE_TXDMA_256BYTES 0x00600000
260 #define NGE_TXDMA_512BYTES 0x00700000
263 (NGE_TXDMA_512BYTES|NGE_TXCFG_AUTOPAD|\
264 NGE_TXCFG_FILL(64)|NGE_TXCFG_DRAIN(6400))
267 #define NGE_GPIO_GP1_OUT 0x00000001
268 #define NGE_GPIO_GP2_OUT 0x00000002
269 #define NGE_GPIO_GP3_OUT 0x00000004
270 #define NGE_GPIO_GP4_OUT 0x00000008
271 #define NGE_GPIO_GP5_OUT 0x00000010
272 #define NGE_GPIO_GP1_OUTENB 0x00000020
273 #define NGE_GPIO_GP2_OUTENB 0x00000040
274 #define NGE_GPIO_GP3_OUTENB 0x00000080
275 #define NGE_GPIO_GP4_OUTENB 0x00000100
276 #define NGE_GPIO_GP5_OUTENB 0x00000200
277 #define NGE_GPIO_GP1_IN 0x00000400
278 #define NGE_GPIO_GP2_IN 0x00000800
279 #define NGE_GPIO_GP3_IN 0x00001000
280 #define NGE_GPIO_GP4_IN 0x00002000
281 #define NGE_GPIO_GP5_IN 0x00004000
283 /* Receive configuration register */
284 #define NGE_RXCFG_DRAIN_THRESH 0x0000003E /* 8-byte units */
285 #define NGE_RXCFG_DMABURST 0x00700000
286 #define NGE_RXCFG_RX_RANGEERR 0x04000000 /* accept in-range err frames */
287 #define NGE_RXCFG_RX_GIANTS 0x08000000 /* accept packets > 1518 bytes */
288 #define NGE_RXCFG_RX_FDX 0x10000000 /* full duplex receive */
289 #define NGE_RXCFG_RX_NOCRC 0x20000000 /* strip CRC */
290 #define NGE_RXCFG_RX_RUNT 0x40000000 /* accept short frames */
291 #define NGE_RXCFG_RX_BADPKTS 0x80000000 /* accept error frames */
293 #define NGE_RXCFG_DRAIN(x) ((((x) >> 3) << 1) & NGE_RXCFG_DRAIN_THRESH)
295 #define NGE_RXDMA_1024BYTES 0x00000000
296 #define NGE_RXDMA_8BYTES 0x00100000
297 #define NGE_RXDMA_16BYTES 0x00200000
298 #define NGE_RXDMA_32YTES 0x00300000
299 #define NGE_RXDMA_64BYTES 0x00400000
300 #define NGE_RXDMA_128BYTES 0x00500000
301 #define NGE_RXDMA_256BYTES 0x00600000
302 #define NGE_RXDMA_512BYTES 0x00700000
305 (NGE_RXCFG_DRAIN(64)|NGE_RXDMA_256BYTES|\
306 NGE_RXCFG_RX_GIANTS|NGE_RXCFG_RX_NOCRC)
308 /* Priority queue control */
309 #define NGE_PRIOQCTL_TXPRIO_ENB 0x00000001
310 #define NGE_PRIOQCTL_TXFAIR_ENB 0x00000002
311 #define NGE_PRIOQCTL_RXPRIO 0x0000000C
313 #define NGE_RXPRIOQ_DISABLED 0x00000000
314 #define NGE_RXPRIOQ_TWOQS 0x00000004
315 #define NGE_RXPRIOQ_THREEQS 0x00000008
316 #define NGE_RXPRIOQ_FOURQS 0x0000000C
318 /* Wake On LAN command/status register */
319 #define NGE_WOLCSR_WAKE_ON_PHYINTR 0x00000001
320 #define NGE_WOLCSR_WAKE_ON_UNICAST 0x00000002
321 #define NGE_WOLCSR_WAKE_ON_MULTICAST 0x00000004
322 #define NGR_WOLCSR_WAKE_ON_BROADCAST 0x00000008
323 #define NGE_WOLCSR_WAKE_ON_ARP 0x00000010
324 #define NGE_WOLCSR_WAKE_ON_PAT0_MATCH 0x00000020
325 #define NGE_WOLCSR_WAKE_ON_PAT1_MATCH 0x00000040
326 #define NGE_WOLCSR_WAKE_ON_PAT2_MATCH 0x00000080
327 #define NGE_WOLCSR_WAKE_ON_PAT3_MATCH 0x00000100
328 #define NGE_WOLCSR_SECUREON_ENB 0x00000200
329 #define NGE_WOLCSR_SECUREON_HACK 0x00200000
330 #define NGE_WOLCSR_PHYINTR 0x00400000
331 #define NGE_WOLCSR_UNICAST 0x00800000
332 #define NGE_WOLCSR_MULTICAST 0x01000000
333 #define NGE_WOLCSR_BROADCAST 0x02000000
334 #define NGE_WOLCSR_ARP_RCVD 0x04000000
335 #define NGE_WOLCSR_PAT0_MATCH 0x08000000
336 #define NGE_WOLCSR_PAT1_MATCH 0x10000000
337 #define NGE_WOLCSR_PAT2_MATCH 0x20000000
338 #define NGE_WOLCSR_PAT3_MATCH 0x40000000
339 #define NGE_WOLCSR_MAGICPKT 0x80000000
341 /* Pause control/status register */
342 #define NGE_PAUSECSR_CNT 0x0000FFFF
343 #define NGE_PAUSECSR_PFRAME_SENT 0x00020000
344 #define NGE_PAUSECSR_RX_DATAFIFO_THR_LO 0x000C0000
345 #define NGE_PAUSECSR_RX_DATAFIFO_THR_HI 0x00300000
346 #define NGE_PAUSECSR_RX_STATFIFO_THR_LO 0x00C00000
347 #define NGE_PAUSECSR_RX_STATFIFO_THR_HI 0x03000000
348 #define NGE_PAUSECSR_PFRAME_RCVD 0x08000000
349 #define NGE_PAUSECSR_PAUSE_ACTIVE 0x10000000
350 #define NGE_PAUSECSR_PAUSE_ON_DA 0x20000000 /* pause on direct addr */
351 #define NGE_PAUSECSR_PAUSE_ON_MCAST 0x40000000 /* pause on mcast */
352 #define NGE_PAUSECSR_PAUSE_ENB 0x80000000
354 /* Receive filter/match control message */
355 #define MGE_RXFILTCTL_ADDR 0x000003FF
356 #define NGE_RXFILTCTL_ULMASK 0x00080000
357 #define NGE_RXFILTCTL_UCHASH 0x00100000
358 #define NGE_RXFILTCTL_MCHASH 0x00200000
359 #define NGE_RXFILTCTL_ARP 0x00400000
360 #define NGE_RXFILTCTL_PMATCH0 0x00800000
361 #define NGE_RXFILTCTL_PMATCH1 0x01000000
362 #define NGE_RXFILTCTL_PMATCH2 0x02000000
363 #define NGE_RXFILTCTL_PMATCH3 0x04000000
364 #define NGE_RXFILTCTL_PERFECT 0x08000000
365 #define NGE_RXFILTCTL_ALLPHYS 0x10000000
366 #define NGE_RXFILTCTL_ALLMULTI 0x20000000
367 #define NGE_RXFILTCTL_BROAD 0x40000000
368 #define NGE_RXFILTCTL_ENABLE 0x80000000
371 #define NGE_FILTADDR_PAR0 0x00000000
372 #define NGE_FILTADDR_PAR1 0x00000002
373 #define NGE_FILTADDR_PAR2 0x00000004
374 #define NGE_FILTADDR_PMATCH0 0x00000006
375 #define NGE_FILTADDR_PMATCH1 0x00000008
376 #define NGE_FILTADDR_SOPASS0 0x0000000A
377 #define NGE_FILTADDR_SOPASS1 0x0000000C
378 #define NGE_FILTADDR_SOPASS2 0x0000000E
379 #define NGE_FILTADDR_FMEM_LO 0x00000100
380 #define NGE_FILTADDR_FMEM_HI 0x000003FE
381 #define NGE_FILTADDR_MCAST_LO 0x00000100 /* start of multicast filter */
382 #define NGE_FILTADDR_MCAST_HI 0x000001FE /* end of multicast filter */
383 #define NGE_MCAST_FILTER_LEN 256 /* bytes */
384 #define NGE_FILTADDR_PBUF0 0x00000200 /* pattern buffer 0 */
385 #define NGE_FILTADDR_PBUF1 0x00000280 /* pattern buffer 1 */
386 #define NGE_FILTADDR_PBUF2 0x00000300 /* pattern buffer 2 */
387 #define NGE_FILTADDR_PBUF3 0x00000380 /* pattern buffer 3 */
389 /* MIB control register */
390 #define NGE_MIBCTL_WARNTEST 0x00000001
391 #define NGE_MIBCTL_FREEZE_CNT 0x00000002
392 #define NGE_MIBCTL_CLEAR_CNT 0x00000004
393 #define NGE_MIBCTL_STROBE_CNT 0x00000008
395 /* VLAN/IP RX control register */
396 #define NGE_VIPRXCTL_TAG_DETECT_ENB 0x00000001
397 #define NGE_VIPRXCTL_TAG_STRIP_ENB 0x00000002
398 #define NGE_VIPRXCTL_DROP_TAGGEDPKTS 0x00000004
399 #define NGE_VIPRXCTL_DROP_UNTAGGEDPKTS 0x00000008
400 #define NGE_VIPRXCTL_IPCSUM_ENB 0x00000010
401 #define NGE_VIPRXCTL_REJECT_BADIPCSUM 0x00000020
402 #define NGE_VIPRXCTL_REJECT_BADTCPCSUM 0x00000040
403 #define NGE_VIPRXCTL_REJECT_BADUDPCSUM 0x00000080
405 /* VLAN/IP TX control register */
406 #define NGE_VIPTXCTL_TAG_ALL 0x00000001
407 #define NGE_VIPTXCTL_TAG_PER_PKT 0x00000002
408 #define NGE_VIPTXCTL_CSUM_ALL 0x00000004
409 #define NGE_VIPTXCTL_CSUM_PER_PKT 0x00000008
411 /* VLAN data register */
412 #define NGE_VLANDATA_VTYPE 0x0000FFFF
413 #define NGE_VLANDATA_VTCI 0xFFFF0000
415 /* Clockrun register */
416 #define NGE_CLKRUN_PMESTS 0x00008000
417 #define NGE_CLKRUN_PMEENB 0x00000100
418 #define NGE_CLNRUN_CLKRUN_ENB 0x00000001
422 #define NGE_TBIBMCR_RESTART_ANEG 0x00000200
423 #define NGE_TBIBMCR_ENABLE_ANEG 0x00001000
424 #define NGE_TBIBMCR_LOOPBACK 0x00004000
427 #define NGE_TBIBMSR_ANEG_DONE 0x00000004
428 #define NGE_TBIBMSR_LINKSTAT 0x00000020
431 #define NGE_TBIANAR_HDX 0x00000020
432 #define NGE_TBIANAR_FDX 0x00000040
433 #define NGE_TBIANAR_PCAP 0x00000180
434 #define NGE_TBIANAR_REMFAULT 0x00003000
435 #define NGE_TBIANAR_NEXTPAGE 0x00008000
438 #define NGE_TBIANLPAR_HDX 0x00000020
439 #define NGE_TBIANLPAR_FDX 0x00000040
440 #define NGE_TBIANLPAR_PCAP 0x00000180
441 #define NGE_TBIANLPAR_REMFAULT 0x00003000
442 #define NGE_TBIANLPAR_NEXTPAGE 0x00008000
445 #define NGE_TBIANER_PAGERCVD 0x00000002
446 #define NGE_TBIANER_NEXTPGABLE 0x00000004
449 #define NGE_TBIEXTSTS_HXD 0x00004000
450 #define NGE_TBIEXTSTS_FXD 0x00008000
453 * DMA descriptor structures. The RX and TX descriptor formats are
454 * deliberately designed to be similar to facilitate passing them between
455 * RX and TX queues on multiple controllers, in the case where you have
456 * multiple MACs in a switching configuration. With the 83820, the pointer
457 * values can be either 64 bits or 32 bits depending on how the chip is
458 * configured. For the 83821, the fields are always 32-bits. There is
459 * also an optional extended status field for VLAN and TCP/IP checksum
460 * functions. We use the checksum feature so we enable the use of this
461 * field. Descriptors must be 64-bit aligned.
462 * After this, we include some additional structure members for
463 * use by the driver. Note that for this structure will be a different
464 * size on the alpha, but that's okay as long as it's a multiple of 4
469 /* Hardware descriptor section */
470 u_int32_t nge_next_lo;
471 u_int32_t nge_next_hi;
472 u_int32_t nge_ptr_lo;
473 u_int32_t nge_ptr_hi;
474 u_int32_t nge_cmdsts;
475 #define nge_rxstat nge_cmdsts
476 #define nge_txstat nge_cmdsts
477 #define nge_ctl nge_cmdsts
478 u_int32_t nge_extsts;
479 /* Driver software section */
481 struct mbuf *nge_mbuf;
485 struct nge_desc_64 *nge_nextdesc;
491 /* Hardware descriptor section */
494 u_int32_t nge_cmdsts;
495 #define nge_rxstat nge_cmdsts
496 #define nge_txstat nge_cmdsts
497 #define nge_ctl nge_cmdsts
498 u_int32_t nge_extsts;
499 /* Driver software section */
501 struct mbuf *nge_mbuf;
505 struct nge_desc_32 *nge_nextdesc;
510 #define nge_desc nge_desc_32
511 #define nge_mbuf nge_mb_u.nge_mbuf
512 #define nge_nextdesc nge_nd_u.nge_nextdesc
514 #define NGE_CMDSTS_BUFLEN 0x0000FFFF
515 #define NGE_CMDSTS_PKT_OK 0x08000000
516 #define NGE_CMDSTS_CRC 0x10000000
517 #define NGE_CMDSTS_INTR 0x20000000
518 #define NGE_CMDSTS_MORE 0x40000000
519 #define NGE_CMDSTS_OWN 0x80000000
521 #define NGE_LASTDESC(x) (!((x)->nge_ctl & NGE_CMDSTS_MORE)))
522 #define NGE_OWNDESC(x) ((x)->nge_ctl & NGE_CMDSTS_OWN)
523 #define NGE_INC(x, y) (x) = (x + 1) % y
524 #define NGE_RXBYTES(x) ((x)->nge_ctl & NGE_CMDSTS_BUFLEN)
526 #define NGE_RXSTAT_RANGELENERR 0x00010000
527 #define NGE_RXSTAT_LOOPBK 0x00020000
528 #define NGE_RXSTAT_ALIGNERR 0x00040000
529 #define NGE_RXSTAT_CRCERR 0x00080000
530 #define NGE_RXSTAT_SYMBOLERR 0x00100000
531 #define NGE_RXSTAT_RUNT 0x00200000
532 #define NGE_RXSTAT_GIANT 0x00400000
533 #define NGE_RXSTAT_DSTCLASS 0x01800000
534 #define NGE_RXSTAT_OVERRUN 0x02000000
535 #define NGE_RXSTAT_RX_ABORT 0x04000000
537 #define NGE_DSTCLASS_REJECT 0x00000000
538 #define NGE_DSTCLASS_UNICAST 0x00800000
539 #define NGE_DSTCLASS_MULTICAST 0x01000000
540 #define NGE_DSTCLASS_BROADCAST 0x02000000
542 #define NGE_TXSTAT_COLLCNT 0x000F0000
543 #define NGE_TXSTAT_EXCESSCOLLS 0x00100000
544 #define NGE_TXSTAT_OUTOFWINCOLL 0x00200000
545 #define NGE_TXSTAT_EXCESS_DEFER 0x00400000
546 #define NGE_TXSTAT_DEFERED 0x00800000
547 #define NGE_TXSTAT_CARR_LOST 0x01000000
548 #define NGE_TXSTAT_UNDERRUN 0x02000000
549 #define NGE_TXSTAT_TX_ABORT 0x04000000
551 #define NGE_TXEXTSTS_VLAN_TCI 0x0000FFFF
552 #define NGE_TXEXTSTS_VLANPKT 0x00010000
553 #define NGE_TXEXTSTS_IPCSUM 0x00020000
554 #define NGE_TXEXTSTS_TCPCSUM 0x00080000
555 #define NGE_TXEXTSTS_UDPCSUM 0x00200000
557 #define NGE_RXEXTSTS_VTCI 0x0000FFFF
558 #define NGE_RXEXTSTS_VLANPKT 0x00010000
559 #define NGE_RXEXTSTS_IPPKT 0x00020000
560 #define NGE_RXEXTSTS_IPCSUMERR 0x00040000
561 #define NGE_RXEXTSTS_TCPPKT 0x00080000
562 #define NGE_RXEXTSTS_TCPCSUMERR 0x00100000
563 #define NGE_RXEXTSTS_UDPPKT 0x00200000
564 #define NGE_RXEXTSTS_UDPCSUMERR 0x00400000
566 #define NGE_RX_LIST_CNT 128
567 #define NGE_TX_LIST_CNT 128
569 struct nge_list_data {
570 struct nge_desc nge_rx_list[NGE_RX_LIST_CNT];
571 struct nge_desc nge_tx_list[NGE_TX_LIST_CNT];
576 * NatSemi PCI vendor ID.
578 #define NGE_VENDORID 0x100B
581 * 83820/83821 PCI device IDs
583 #define NGE_DEVICEID 0x0022
591 struct nge_mii_frame {
592 u_int8_t mii_stdelim;
594 u_int8_t mii_phyaddr;
595 u_int8_t mii_regaddr;
596 u_int8_t mii_turnaround;
603 #define NGE_MII_STARTDELIM 0x01
604 #define NGE_MII_READOP 0x02
605 #define NGE_MII_WRITEOP 0x01
606 #define NGE_MII_TURNAROUND 0x02
608 #define NGE_JUMBO_FRAMELEN 9018
609 #define NGE_JUMBO_MTU (NGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
610 #define NGE_JSLOTS 384
612 #define NGE_JRAWLEN (NGE_JUMBO_FRAMELEN + ETHER_ALIGN)
613 #define NGE_JLEN (NGE_JRAWLEN + (sizeof(u_int64_t) - \
614 (NGE_JRAWLEN % sizeof(u_int64_t))))
615 #define NGE_JPAGESZ PAGE_SIZE
616 #define NGE_RESID (NGE_JPAGESZ - (NGE_JLEN * NGE_JSLOTS) % NGE_JPAGESZ)
617 #define NGE_JMEM ((NGE_JLEN * NGE_JSLOTS) + NGE_RESID)
619 struct nge_jpool_entry {
621 SLIST_ENTRY(nge_jpool_entry) jpool_entries;
624 struct nge_ring_data {
629 /* Stick the jumbo mem management stuff here too. */
630 caddr_t nge_jslots[NGE_JSLOTS];
635 struct arpcom arpcom; /* interface info */
636 bus_space_handle_t nge_bhandle;
637 bus_space_tag_t nge_btag;
638 struct resource *nge_res;
639 struct resource *nge_irq;
647 #define NGE_WIDTH_32BITS 0
648 #define NGE_WIDTH_64BITS 1
649 struct nge_list_data *nge_ldata;
650 struct nge_ring_data nge_cdata;
651 struct callout_handle nge_stat_ch;
652 SLIST_HEAD(__nge_jfreehead, nge_jpool_entry) nge_jfree_listhead;
653 SLIST_HEAD(__nge_jinusehead, nge_jpool_entry) nge_jinuse_listhead;
658 * register space access macros
660 #define CSR_WRITE_4(sc, reg, val) \
661 bus_space_write_4(sc->nge_btag, sc->nge_bhandle, reg, val)
663 #define CSR_READ_4(sc, reg) \
664 bus_space_read_4(sc->nge_btag, sc->nge_bhandle, reg)
666 #define NGE_TIMEOUT 1000
667 #define ETHER_ALIGN 2
668 #define NGE_RXLEN 1536
669 #define NGE_MIN_FRAMELEN 60
672 * PCI low memory base and low I/O base register, and
673 * other PCI registers.
676 #define NGE_PCI_VENDOR_ID 0x00
677 #define NGE_PCI_DEVICE_ID 0x02
678 #define NGE_PCI_COMMAND 0x04
679 #define NGE_PCI_STATUS 0x06
680 #define NGE_PCI_REVID 0x08
681 #define NGE_PCI_CLASSCODE 0x09
682 #define NGE_PCI_CACHELEN 0x0C
683 #define NGE_PCI_LATENCY_TIMER 0x0D
684 #define NGE_PCI_HEADER_TYPE 0x0E
685 #define NGE_PCI_LOIO 0x10
686 #define NGE_PCI_LOMEM 0x14
687 #define NGE_PCI_BIOSROM 0x30
688 #define NGE_PCI_INTLINE 0x3C
689 #define NGE_PCI_INTPIN 0x3D
690 #define NGE_PCI_MINGNT 0x3E
691 #define NGE_PCI_MINLAT 0x0F
692 #define NGE_PCI_RESETOPT 0x48
693 #define NGE_PCI_EEPROM_DATA 0x4C
695 /* power management registers */
696 #define NGE_PCI_CAPID 0x50 /* 8 bits */
697 #define NGE_PCI_NEXTPTR 0x51 /* 8 bits */
698 #define NGE_PCI_PWRMGMTCAP 0x52 /* 16 bits */
699 #define NGE_PCI_PWRMGMTCTRL 0x54 /* 16 bits */
701 #define NGE_PSTATE_MASK 0x0003
702 #define NGE_PSTATE_D0 0x0000
703 #define NGE_PSTATE_D1 0x0001
704 #define NGE_PSTATE_D2 0x0002
705 #define NGE_PSTATE_D3 0x0003
706 #define NGE_PME_EN 0x0010
707 #define NGE_PME_STATUS 0x8000
711 #define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va)