2 * Copyright (c) 2016 Alexander Motin <mav@FreeBSD.org>
3 * Copyright (C) 2013 Intel Corporation
4 * Copyright (C) 2015 EMC Corporation
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * The Non-Transparent Bridge (NTB) is a device that allows you to connect
31 * two or more systems using a PCI-e links, providing remote memory access.
33 * This module contains a driver for NTB hardware in Intel Xeon/Atom CPUs.
35 * NOTE: Much of the code in this module is shared with Linux. Any patches may
36 * be picked up and redistributed in Linux with a dual GPL/BSD license.
39 #include <sys/cdefs.h>
40 __FBSDID("$FreeBSD$");
42 #include <sys/param.h>
43 #include <sys/kernel.h>
44 #include <sys/systm.h>
46 #include <sys/endian.h>
47 #include <sys/malloc.h>
48 #include <sys/module.h>
49 #include <sys/mutex.h>
50 #include <sys/pciio.h>
51 #include <sys/queue.h>
53 #include <sys/rmlock.h>
55 #include <sys/sysctl.h>
58 #include <machine/bus.h>
59 #include <machine/intr_machdep.h>
60 #include <machine/pmap.h>
61 #include <machine/resource.h>
62 #include <dev/pci/pcireg.h>
63 #include <dev/pci/pcivar.h>
68 #define MAX_MSIX_INTERRUPTS MAX(XEON_DB_COUNT, ATOM_DB_COUNT)
70 #define NTB_HB_TIMEOUT 1 /* second */
71 #define ATOM_LINK_RECOVERY_TIME 500 /* ms */
72 #define BAR_HIGH_MASK (~((1ull << 12) - 1))
74 #define NTB_MSIX_VER_GUARD 0xaabbccdd
75 #define NTB_MSIX_RECEIVED 0xe0f0e0f0
78 * PCI constants could be somewhere more generic, but aren't defined/used in
81 #define PCI_MSIX_ENTRY_SIZE 16
82 #define PCI_MSIX_ENTRY_LOWER_ADDR 0
83 #define PCI_MSIX_ENTRY_UPPER_ADDR 4
84 #define PCI_MSIX_ENTRY_DATA 8
86 enum ntb_device_type {
91 /* ntb_conn_type are hardware numbers, cannot change. */
93 NTB_CONN_TRANSPARENT = 0,
98 enum ntb_b2b_direction {
123 /* Device features and workarounds */
124 #define HAS_FEATURE(ntb, feature) \
125 (((ntb)->features & (feature)) != 0)
130 enum ntb_device_type type;
134 struct ntb_pci_bar_info {
135 bus_space_tag_t pci_bus_tag;
136 bus_space_handle_t pci_bus_handle;
138 struct resource *pci_resource;
142 vm_memattr_t map_mode;
144 /* Configuration register offsets */
147 uint32_t pbarxlat_off;
150 struct ntb_int_info {
151 struct resource *res;
157 struct ntb_softc *ntb;
166 unsigned mw_bar[NTB_MAX_BARS];
175 struct ntb_xlat_reg {
190 struct ntb_b2b_addr {
192 uint64_t bar2_addr64;
193 uint64_t bar4_addr64;
194 uint64_t bar4_addr32;
195 uint64_t bar5_addr32;
198 struct ntb_msix_data {
205 enum ntb_device_type type;
208 struct ntb_pci_bar_info bar_info[NTB_MAX_BARS];
209 struct ntb_int_info int_info[MAX_MSIX_INTERRUPTS];
210 uint32_t allocated_interrupts;
212 struct ntb_msix_data peer_msix_data[XEON_NONLINK_DB_MSIX_BITS];
213 struct ntb_msix_data msix_data[XEON_NONLINK_DB_MSIX_BITS];
216 struct ntb_pci_bar_info *peer_lapic_bar;
217 struct callout peer_msix_work;
219 struct callout heartbeat_timer;
220 struct callout lr_timer;
223 const struct ntb_ctx_ops *ctx_ops;
224 struct ntb_vec *msix_vec;
225 struct rmlock ctx_lock;
228 enum ntb_conn_type conn_type;
229 enum ntb_b2b_direction dev_type;
231 /* Offset of peer bar0 in B2B BAR */
233 /* Memory window used to access peer bar0 */
234 #define B2B_MW_DISABLED UINT8_MAX
242 uint8_t db_vec_count;
243 uint8_t db_vec_shift;
245 /* Protects local db_mask. */
246 #define DB_MASK_LOCK(sc) mtx_lock_spin(&(sc)->db_mask_lock)
247 #define DB_MASK_UNLOCK(sc) mtx_unlock_spin(&(sc)->db_mask_lock)
248 #define DB_MASK_ASSERT(sc,f) mtx_assert(&(sc)->db_mask_lock, (f))
249 struct mtx db_mask_lock;
251 volatile uint32_t ntb_ctl;
252 volatile uint32_t lnk_sta;
254 uint64_t db_valid_mask;
255 uint64_t db_link_mask;
258 int last_ts; /* ticks @ last irq */
260 const struct ntb_reg *reg;
261 const struct ntb_alt_reg *self_reg;
262 const struct ntb_alt_reg *peer_reg;
263 const struct ntb_xlat_reg *xlat_reg;
267 static __inline uint64_t
268 bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle,
272 return (bus_space_read_4(tag, handle, offset) |
273 ((uint64_t)bus_space_read_4(tag, handle, offset + 4)) << 32);
277 bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t handle,
278 bus_size_t offset, uint64_t val)
281 bus_space_write_4(tag, handle, offset, val);
282 bus_space_write_4(tag, handle, offset + 4, val >> 32);
286 #define ntb_bar_read(SIZE, bar, offset) \
287 bus_space_read_ ## SIZE (ntb->bar_info[(bar)].pci_bus_tag, \
288 ntb->bar_info[(bar)].pci_bus_handle, (offset))
289 #define ntb_bar_write(SIZE, bar, offset, val) \
290 bus_space_write_ ## SIZE (ntb->bar_info[(bar)].pci_bus_tag, \
291 ntb->bar_info[(bar)].pci_bus_handle, (offset), (val))
292 #define ntb_reg_read(SIZE, offset) ntb_bar_read(SIZE, NTB_CONFIG_BAR, offset)
293 #define ntb_reg_write(SIZE, offset, val) \
294 ntb_bar_write(SIZE, NTB_CONFIG_BAR, offset, val)
295 #define ntb_mw_read(SIZE, offset) \
296 ntb_bar_read(SIZE, ntb_mw_to_bar(ntb, ntb->b2b_mw_idx), offset)
297 #define ntb_mw_write(SIZE, offset, val) \
298 ntb_bar_write(SIZE, ntb_mw_to_bar(ntb, ntb->b2b_mw_idx), \
301 static int ntb_probe(device_t device);
302 static int ntb_attach(device_t device);
303 static int ntb_detach(device_t device);
304 static uint64_t ntb_db_valid_mask(device_t dev);
305 static void ntb_spad_clear(device_t dev);
306 static uint64_t ntb_db_vector_mask(device_t dev, uint32_t vector);
307 static bool ntb_link_is_up(device_t dev, enum ntb_speed *speed,
308 enum ntb_width *width);
309 static int ntb_link_enable(device_t dev, enum ntb_speed speed,
310 enum ntb_width width);
311 static int ntb_link_disable(device_t dev);
312 static int ntb_spad_read(device_t dev, unsigned int idx, uint32_t *val);
313 static int ntb_peer_spad_write(device_t dev, unsigned int idx, uint32_t val);
315 static unsigned ntb_user_mw_to_idx(struct ntb_softc *, unsigned uidx);
316 static inline enum ntb_bar ntb_mw_to_bar(struct ntb_softc *, unsigned mw);
317 static inline bool bar_is_64bit(struct ntb_softc *, enum ntb_bar);
318 static inline void bar_get_xlat_params(struct ntb_softc *, enum ntb_bar,
319 uint32_t *base, uint32_t *xlat, uint32_t *lmt);
320 static int ntb_map_pci_bars(struct ntb_softc *ntb);
321 static int ntb_mw_set_wc_internal(struct ntb_softc *, unsigned idx,
323 static void print_map_success(struct ntb_softc *, struct ntb_pci_bar_info *,
325 static int map_mmr_bar(struct ntb_softc *ntb, struct ntb_pci_bar_info *bar);
326 static int map_memory_window_bar(struct ntb_softc *ntb,
327 struct ntb_pci_bar_info *bar);
328 static void ntb_unmap_pci_bar(struct ntb_softc *ntb);
329 static int ntb_remap_msix(device_t, uint32_t desired, uint32_t avail);
330 static int ntb_init_isr(struct ntb_softc *ntb);
331 static int ntb_setup_legacy_interrupt(struct ntb_softc *ntb);
332 static int ntb_setup_msix(struct ntb_softc *ntb, uint32_t num_vectors);
333 static void ntb_teardown_interrupts(struct ntb_softc *ntb);
334 static inline uint64_t ntb_vec_mask(struct ntb_softc *, uint64_t db_vector);
335 static void ntb_interrupt(struct ntb_softc *, uint32_t vec);
336 static void ndev_vec_isr(void *arg);
337 static void ndev_irq_isr(void *arg);
338 static inline uint64_t db_ioread(struct ntb_softc *, uint64_t regoff);
339 static inline void db_iowrite(struct ntb_softc *, uint64_t regoff, uint64_t);
340 static inline void db_iowrite_raw(struct ntb_softc *, uint64_t regoff, uint64_t);
341 static int ntb_create_msix_vec(struct ntb_softc *ntb, uint32_t num_vectors);
342 static void ntb_free_msix_vec(struct ntb_softc *ntb);
343 static void ntb_get_msix_info(struct ntb_softc *ntb);
344 static void ntb_exchange_msix(void *);
345 static struct ntb_hw_info *ntb_get_device_info(uint32_t device_id);
346 static void ntb_detect_max_mw(struct ntb_softc *ntb);
347 static int ntb_detect_xeon(struct ntb_softc *ntb);
348 static int ntb_detect_atom(struct ntb_softc *ntb);
349 static int ntb_xeon_init_dev(struct ntb_softc *ntb);
350 static int ntb_atom_init_dev(struct ntb_softc *ntb);
351 static void ntb_teardown_xeon(struct ntb_softc *ntb);
352 static void configure_atom_secondary_side_bars(struct ntb_softc *ntb);
353 static void xeon_reset_sbar_size(struct ntb_softc *, enum ntb_bar idx,
354 enum ntb_bar regbar);
355 static void xeon_set_sbar_base_and_limit(struct ntb_softc *,
356 uint64_t base_addr, enum ntb_bar idx, enum ntb_bar regbar);
357 static void xeon_set_pbar_xlat(struct ntb_softc *, uint64_t base_addr,
359 static int xeon_setup_b2b_mw(struct ntb_softc *,
360 const struct ntb_b2b_addr *addr, const struct ntb_b2b_addr *peer_addr);
361 static int xeon_setup_msix_bar(struct ntb_softc *);
362 static inline bool link_is_up(struct ntb_softc *ntb);
363 static inline bool _xeon_link_is_up(struct ntb_softc *ntb);
364 static inline bool atom_link_is_err(struct ntb_softc *ntb);
365 static inline enum ntb_speed ntb_link_sta_speed(struct ntb_softc *);
366 static inline enum ntb_width ntb_link_sta_width(struct ntb_softc *);
367 static void atom_link_hb(void *arg);
368 static void ntb_link_event(device_t dev);
369 static void ntb_db_event(device_t dev, uint32_t vec);
370 static void recover_atom_link(void *arg);
371 static bool ntb_poll_link(struct ntb_softc *ntb);
372 static void save_bar_parameters(struct ntb_pci_bar_info *bar);
373 static void ntb_sysctl_init(struct ntb_softc *);
374 static int sysctl_handle_features(SYSCTL_HANDLER_ARGS);
375 static int sysctl_handle_link_admin(SYSCTL_HANDLER_ARGS);
376 static int sysctl_handle_link_status_human(SYSCTL_HANDLER_ARGS);
377 static int sysctl_handle_link_status(SYSCTL_HANDLER_ARGS);
378 static int sysctl_handle_register(SYSCTL_HANDLER_ARGS);
380 static unsigned g_ntb_hw_debug_level;
381 TUNABLE_INT("hw.ntb.debug_level", &g_ntb_hw_debug_level);
382 SYSCTL_UINT(_hw_ntb, OID_AUTO, debug_level, CTLFLAG_RWTUN,
383 &g_ntb_hw_debug_level, 0, "ntb_hw log level -- higher is more verbose");
384 #define ntb_printf(lvl, ...) do { \
385 if ((lvl) <= g_ntb_hw_debug_level) { \
386 device_printf(ntb->device, __VA_ARGS__); \
390 #define _NTB_PAT_UC 0
391 #define _NTB_PAT_WC 1
392 #define _NTB_PAT_WT 4
393 #define _NTB_PAT_WP 5
394 #define _NTB_PAT_WB 6
395 #define _NTB_PAT_UCM 7
396 static unsigned g_ntb_mw_pat = _NTB_PAT_UC;
397 TUNABLE_INT("hw.ntb.default_mw_pat", &g_ntb_mw_pat);
398 SYSCTL_UINT(_hw_ntb, OID_AUTO, default_mw_pat, CTLFLAG_RDTUN,
399 &g_ntb_mw_pat, 0, "Configure the default memory window cache flags (PAT): "
400 "UC: " __XSTRING(_NTB_PAT_UC) ", "
401 "WC: " __XSTRING(_NTB_PAT_WC) ", "
402 "WT: " __XSTRING(_NTB_PAT_WT) ", "
403 "WP: " __XSTRING(_NTB_PAT_WP) ", "
404 "WB: " __XSTRING(_NTB_PAT_WB) ", "
405 "UC-: " __XSTRING(_NTB_PAT_UCM));
407 static inline vm_memattr_t
411 switch (g_ntb_mw_pat) {
413 return (VM_MEMATTR_WRITE_COMBINING);
415 return (VM_MEMATTR_WRITE_THROUGH);
417 return (VM_MEMATTR_WRITE_PROTECTED);
419 return (VM_MEMATTR_WRITE_BACK);
421 return (VM_MEMATTR_WEAK_UNCACHEABLE);
425 return (VM_MEMATTR_UNCACHEABLE);
430 * Well, this obviously doesn't belong here, but it doesn't seem to exist
431 * anywhere better yet.
433 static inline const char *
434 ntb_vm_memattr_to_str(vm_memattr_t pat)
438 case VM_MEMATTR_WRITE_COMBINING:
439 return ("WRITE_COMBINING");
440 case VM_MEMATTR_WRITE_THROUGH:
441 return ("WRITE_THROUGH");
442 case VM_MEMATTR_WRITE_PROTECTED:
443 return ("WRITE_PROTECTED");
444 case VM_MEMATTR_WRITE_BACK:
445 return ("WRITE_BACK");
446 case VM_MEMATTR_WEAK_UNCACHEABLE:
448 case VM_MEMATTR_UNCACHEABLE:
449 return ("UNCACHEABLE");
455 static int g_ntb_msix_idx = 0;
456 TUNABLE_INT("hw.ntb.msix_mw_idx", &g_ntb_msix_idx);
457 SYSCTL_INT(_hw_ntb, OID_AUTO, msix_mw_idx, CTLFLAG_RDTUN, &g_ntb_msix_idx,
458 0, "Use this memory window to access the peer MSIX message complex on "
459 "certain Xeon-based NTB systems, as a workaround for a hardware errata. "
460 "Like b2b_mw_idx, negative values index from the last available memory "
461 "window. (Applies on Xeon platforms with SB01BASE_LOCKUP errata.)");
463 static int g_ntb_mw_idx = -1;
464 TUNABLE_INT("hw.ntb.b2b_mw_idx", &g_ntb_mw_idx);
465 SYSCTL_INT(_hw_ntb, OID_AUTO, b2b_mw_idx, CTLFLAG_RDTUN, &g_ntb_mw_idx,
466 0, "Use this memory window to access the peer NTB registers. A "
467 "non-negative value starts from the first MW index; a negative value "
468 "starts from the last MW index. The default is -1, i.e., the last "
469 "available memory window. Both sides of the NTB MUST set the same "
470 "value here! (Applies on Xeon platforms with SDOORBELL_LOCKUP errata.)");
472 /* Hardware owns the low 16 bits of features. */
473 #define NTB_BAR_SIZE_4K (1 << 0)
474 #define NTB_SDOORBELL_LOCKUP (1 << 1)
475 #define NTB_SB01BASE_LOCKUP (1 << 2)
476 #define NTB_B2BDOORBELL_BIT14 (1 << 3)
477 /* Software/configuration owns the top 16 bits. */
478 #define NTB_SPLIT_BAR (1ull << 16)
480 #define NTB_FEATURES_STR \
481 "\20\21SPLIT_BAR4\04B2B_DOORBELL_BIT14\03SB01BASE_LOCKUP" \
482 "\02SDOORBELL_LOCKUP\01BAR_SIZE_4K"
484 static struct ntb_hw_info pci_ids[] = {
485 /* XXX: PS/SS IDs left out until they are supported. */
486 { 0x0C4E8086, "BWD Atom Processor S1200 Non-Transparent Bridge B2B",
489 { 0x37258086, "JSF Xeon C35xx/C55xx Non-Transparent Bridge B2B",
490 NTB_XEON, NTB_SDOORBELL_LOCKUP | NTB_B2BDOORBELL_BIT14 },
491 { 0x3C0D8086, "SNB Xeon E5/Core i7 Non-Transparent Bridge B2B",
492 NTB_XEON, NTB_SDOORBELL_LOCKUP | NTB_B2BDOORBELL_BIT14 },
493 { 0x0E0D8086, "IVT Xeon E5 V2 Non-Transparent Bridge B2B", NTB_XEON,
494 NTB_SDOORBELL_LOCKUP | NTB_B2BDOORBELL_BIT14 |
495 NTB_SB01BASE_LOCKUP | NTB_BAR_SIZE_4K },
496 { 0x2F0D8086, "HSX Xeon E5 V3 Non-Transparent Bridge B2B", NTB_XEON,
497 NTB_SDOORBELL_LOCKUP | NTB_B2BDOORBELL_BIT14 |
498 NTB_SB01BASE_LOCKUP },
499 { 0x6F0D8086, "BDX Xeon E5 V4 Non-Transparent Bridge B2B", NTB_XEON,
500 NTB_SDOORBELL_LOCKUP | NTB_B2BDOORBELL_BIT14 |
501 NTB_SB01BASE_LOCKUP },
503 { 0x00000000, NULL, NTB_ATOM, 0 }
506 static const struct ntb_reg atom_reg = {
507 .ntb_ctl = ATOM_NTBCNTL_OFFSET,
508 .lnk_sta = ATOM_LINK_STATUS_OFFSET,
509 .db_size = sizeof(uint64_t),
510 .mw_bar = { NTB_B2B_BAR_1, NTB_B2B_BAR_2 },
513 static const struct ntb_alt_reg atom_pri_reg = {
514 .db_bell = ATOM_PDOORBELL_OFFSET,
515 .db_mask = ATOM_PDBMSK_OFFSET,
516 .spad = ATOM_SPAD_OFFSET,
519 static const struct ntb_alt_reg atom_b2b_reg = {
520 .db_bell = ATOM_B2B_DOORBELL_OFFSET,
521 .spad = ATOM_B2B_SPAD_OFFSET,
524 static const struct ntb_xlat_reg atom_sec_xlat = {
526 /* "FIXME" says the Linux driver. */
527 .bar0_base = ATOM_SBAR0BASE_OFFSET,
528 .bar2_base = ATOM_SBAR2BASE_OFFSET,
529 .bar4_base = ATOM_SBAR4BASE_OFFSET,
531 .bar2_limit = ATOM_SBAR2LMT_OFFSET,
532 .bar4_limit = ATOM_SBAR4LMT_OFFSET,
535 .bar2_xlat = ATOM_SBAR2XLAT_OFFSET,
536 .bar4_xlat = ATOM_SBAR4XLAT_OFFSET,
539 static const struct ntb_reg xeon_reg = {
540 .ntb_ctl = XEON_NTBCNTL_OFFSET,
541 .lnk_sta = XEON_LINK_STATUS_OFFSET,
542 .db_size = sizeof(uint16_t),
543 .mw_bar = { NTB_B2B_BAR_1, NTB_B2B_BAR_2, NTB_B2B_BAR_3 },
546 static const struct ntb_alt_reg xeon_pri_reg = {
547 .db_bell = XEON_PDOORBELL_OFFSET,
548 .db_mask = XEON_PDBMSK_OFFSET,
549 .spad = XEON_SPAD_OFFSET,
552 static const struct ntb_alt_reg xeon_b2b_reg = {
553 .db_bell = XEON_B2B_DOORBELL_OFFSET,
554 .spad = XEON_B2B_SPAD_OFFSET,
557 static const struct ntb_xlat_reg xeon_sec_xlat = {
558 .bar0_base = XEON_SBAR0BASE_OFFSET,
559 .bar2_base = XEON_SBAR2BASE_OFFSET,
560 .bar4_base = XEON_SBAR4BASE_OFFSET,
561 .bar5_base = XEON_SBAR5BASE_OFFSET,
563 .bar2_limit = XEON_SBAR2LMT_OFFSET,
564 .bar4_limit = XEON_SBAR4LMT_OFFSET,
565 .bar5_limit = XEON_SBAR5LMT_OFFSET,
567 .bar2_xlat = XEON_SBAR2XLAT_OFFSET,
568 .bar4_xlat = XEON_SBAR4XLAT_OFFSET,
569 .bar5_xlat = XEON_SBAR5XLAT_OFFSET,
572 static struct ntb_b2b_addr xeon_b2b_usd_addr = {
573 .bar0_addr = XEON_B2B_BAR0_ADDR,
574 .bar2_addr64 = XEON_B2B_BAR2_ADDR64,
575 .bar4_addr64 = XEON_B2B_BAR4_ADDR64,
576 .bar4_addr32 = XEON_B2B_BAR4_ADDR32,
577 .bar5_addr32 = XEON_B2B_BAR5_ADDR32,
580 static struct ntb_b2b_addr xeon_b2b_dsd_addr = {
581 .bar0_addr = XEON_B2B_BAR0_ADDR,
582 .bar2_addr64 = XEON_B2B_BAR2_ADDR64,
583 .bar4_addr64 = XEON_B2B_BAR4_ADDR64,
584 .bar4_addr32 = XEON_B2B_BAR4_ADDR32,
585 .bar5_addr32 = XEON_B2B_BAR5_ADDR32,
588 SYSCTL_NODE(_hw_ntb, OID_AUTO, xeon_b2b, CTLFLAG_RW, 0,
589 "B2B MW segment overrides -- MUST be the same on both sides");
591 TUNABLE_QUAD("hw.ntb.usd_bar2_addr64", &xeon_b2b_usd_addr.bar2_addr64);
592 SYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, usd_bar2_addr64, CTLFLAG_RDTUN,
593 &xeon_b2b_usd_addr.bar2_addr64, 0, "If using B2B topology on Xeon "
594 "hardware, use this 64-bit address on the bus between the NTB devices for "
595 "the window at BAR2, on the upstream side of the link. MUST be the same "
596 "address on both sides.");
597 TUNABLE_QUAD("hw.ntb.usd_bar4_addr64", &xeon_b2b_usd_addr.bar4_addr64);
598 SYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, usd_bar4_addr64, CTLFLAG_RDTUN,
599 &xeon_b2b_usd_addr.bar4_addr64, 0, "See usd_bar2_addr64, but BAR4.");
600 TUNABLE_QUAD("hw.ntb.usd_bar4_addr32", &xeon_b2b_usd_addr.bar4_addr32);
601 SYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, usd_bar4_addr32, CTLFLAG_RDTUN,
602 &xeon_b2b_usd_addr.bar4_addr32, 0, "See usd_bar2_addr64, but BAR4 "
603 "(split-BAR mode).");
604 TUNABLE_QUAD("hw.ntb.usd_bar5_addr32", &xeon_b2b_usd_addr.bar5_addr32);
605 SYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, usd_bar5_addr32, CTLFLAG_RDTUN,
606 &xeon_b2b_usd_addr.bar5_addr32, 0, "See usd_bar2_addr64, but BAR5 "
607 "(split-BAR mode).");
609 TUNABLE_QUAD("hw.ntb.dsd_bar2_addr64", &xeon_b2b_dsd_addr.bar2_addr64);
610 SYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, dsd_bar2_addr64, CTLFLAG_RDTUN,
611 &xeon_b2b_dsd_addr.bar2_addr64, 0, "If using B2B topology on Xeon "
612 "hardware, use this 64-bit address on the bus between the NTB devices for "
613 "the window at BAR2, on the downstream side of the link. MUST be the same"
614 " address on both sides.");
615 TUNABLE_QUAD("hw.ntb.dsd_bar4_addr64", &xeon_b2b_dsd_addr.bar4_addr64);
616 SYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, dsd_bar4_addr64, CTLFLAG_RDTUN,
617 &xeon_b2b_dsd_addr.bar4_addr64, 0, "See dsd_bar2_addr64, but BAR4.");
618 TUNABLE_QUAD("hw.ntb.dsd_bar4_addr32", &xeon_b2b_dsd_addr.bar4_addr32);
619 SYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, dsd_bar4_addr32, CTLFLAG_RDTUN,
620 &xeon_b2b_dsd_addr.bar4_addr32, 0, "See dsd_bar2_addr64, but BAR4 "
621 "(split-BAR mode).");
622 TUNABLE_QUAD("hw.ntb.dsd_bar5_addr32", &xeon_b2b_dsd_addr.bar5_addr32);
623 SYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, dsd_bar5_addr32, CTLFLAG_RDTUN,
624 &xeon_b2b_dsd_addr.bar5_addr32, 0, "See dsd_bar2_addr64, but BAR5 "
625 "(split-BAR mode).");
628 * OS <-> Driver interface structures
630 MALLOC_DEFINE(M_NTB, "ntb_hw", "ntb_hw driver memory allocations");
632 SYSCTL_NODE(_hw, OID_AUTO, ntb, CTLFLAG_RW, 0, "NTB sysctls");
635 * OS <-> Driver linkage functions
638 ntb_probe(device_t device)
640 struct ntb_hw_info *p;
642 p = ntb_get_device_info(pci_get_devid(device));
646 device_set_desc(device, p->desc);
651 ntb_attach(device_t device)
653 struct ntb_softc *ntb;
654 struct ntb_hw_info *p;
657 ntb = device_get_softc(device);
658 p = ntb_get_device_info(pci_get_devid(device));
660 ntb->device = device;
662 ntb->features = p->features;
663 ntb->b2b_mw_idx = B2B_MW_DISABLED;
664 ntb->msix_mw_idx = B2B_MW_DISABLED;
666 /* Heartbeat timer for NTB_ATOM since there is no link interrupt */
667 callout_init(&ntb->heartbeat_timer, CALLOUT_MPSAFE);
668 callout_init(&ntb->lr_timer, CALLOUT_MPSAFE);
669 callout_init(&ntb->peer_msix_work, 1);
670 mtx_init(&ntb->db_mask_lock, "ntb hw bits", NULL, MTX_SPIN);
671 rm_init(&ntb->ctx_lock, "ntb ctx");
673 if (ntb->type == NTB_ATOM)
674 error = ntb_detect_atom(ntb);
676 error = ntb_detect_xeon(ntb);
680 ntb_detect_max_mw(ntb);
682 pci_enable_busmaster(ntb->device);
684 error = ntb_map_pci_bars(ntb);
687 if (ntb->type == NTB_ATOM)
688 error = ntb_atom_init_dev(ntb);
690 error = ntb_xeon_init_dev(ntb);
694 ntb_spad_clear(device);
698 ntb_sysctl_init(ntb);
700 /* Attach children to this controller */
701 device_add_child(device, NULL, -1);
702 bus_generic_attach(device);
711 ntb_detach(device_t device)
713 struct ntb_softc *ntb;
715 ntb = device_get_softc(device);
717 /* Detach & delete all children */
718 device_delete_children(device);
720 if (ntb->self_reg != NULL) {
722 db_iowrite(ntb, ntb->self_reg->db_mask, ntb->db_valid_mask);
725 callout_drain(&ntb->heartbeat_timer);
726 callout_drain(&ntb->lr_timer);
727 callout_drain(&ntb->peer_msix_work);
728 pci_disable_busmaster(ntb->device);
729 if (ntb->type == NTB_XEON)
730 ntb_teardown_xeon(ntb);
731 ntb_teardown_interrupts(ntb);
733 mtx_destroy(&ntb->db_mask_lock);
734 rm_destroy(&ntb->ctx_lock);
736 ntb_unmap_pci_bar(ntb);
742 * Driver internal routines
744 static inline enum ntb_bar
745 ntb_mw_to_bar(struct ntb_softc *ntb, unsigned mw)
748 KASSERT(mw < ntb->mw_count,
749 ("%s: mw:%u > count:%u", __func__, mw, (unsigned)ntb->mw_count));
750 KASSERT(ntb->reg->mw_bar[mw] != 0, ("invalid mw"));
752 return (ntb->reg->mw_bar[mw]);
756 bar_is_64bit(struct ntb_softc *ntb, enum ntb_bar bar)
758 /* XXX This assertion could be stronger. */
759 KASSERT(bar < NTB_MAX_BARS, ("bogus bar"));
760 return (bar < NTB_B2B_BAR_2 || !HAS_FEATURE(ntb, NTB_SPLIT_BAR));
764 bar_get_xlat_params(struct ntb_softc *ntb, enum ntb_bar bar, uint32_t *base,
765 uint32_t *xlat, uint32_t *lmt)
767 uint32_t basev, lmtv, xlatv;
771 basev = ntb->xlat_reg->bar2_base;
772 lmtv = ntb->xlat_reg->bar2_limit;
773 xlatv = ntb->xlat_reg->bar2_xlat;
776 basev = ntb->xlat_reg->bar4_base;
777 lmtv = ntb->xlat_reg->bar4_limit;
778 xlatv = ntb->xlat_reg->bar4_xlat;
781 basev = ntb->xlat_reg->bar5_base;
782 lmtv = ntb->xlat_reg->bar5_limit;
783 xlatv = ntb->xlat_reg->bar5_xlat;
786 KASSERT(bar >= NTB_B2B_BAR_1 && bar < NTB_MAX_BARS,
788 basev = lmtv = xlatv = 0;
801 ntb_map_pci_bars(struct ntb_softc *ntb)
805 ntb->bar_info[NTB_CONFIG_BAR].pci_resource_id = PCIR_BAR(0);
806 rc = map_mmr_bar(ntb, &ntb->bar_info[NTB_CONFIG_BAR]);
810 ntb->bar_info[NTB_B2B_BAR_1].pci_resource_id = PCIR_BAR(2);
811 rc = map_memory_window_bar(ntb, &ntb->bar_info[NTB_B2B_BAR_1]);
814 ntb->bar_info[NTB_B2B_BAR_1].psz_off = XEON_PBAR23SZ_OFFSET;
815 ntb->bar_info[NTB_B2B_BAR_1].ssz_off = XEON_SBAR23SZ_OFFSET;
816 ntb->bar_info[NTB_B2B_BAR_1].pbarxlat_off = XEON_PBAR2XLAT_OFFSET;
818 ntb->bar_info[NTB_B2B_BAR_2].pci_resource_id = PCIR_BAR(4);
819 rc = map_memory_window_bar(ntb, &ntb->bar_info[NTB_B2B_BAR_2]);
822 ntb->bar_info[NTB_B2B_BAR_2].psz_off = XEON_PBAR4SZ_OFFSET;
823 ntb->bar_info[NTB_B2B_BAR_2].ssz_off = XEON_SBAR4SZ_OFFSET;
824 ntb->bar_info[NTB_B2B_BAR_2].pbarxlat_off = XEON_PBAR4XLAT_OFFSET;
826 if (!HAS_FEATURE(ntb, NTB_SPLIT_BAR))
829 ntb->bar_info[NTB_B2B_BAR_3].pci_resource_id = PCIR_BAR(5);
830 rc = map_memory_window_bar(ntb, &ntb->bar_info[NTB_B2B_BAR_3]);
831 ntb->bar_info[NTB_B2B_BAR_3].psz_off = XEON_PBAR5SZ_OFFSET;
832 ntb->bar_info[NTB_B2B_BAR_3].ssz_off = XEON_SBAR5SZ_OFFSET;
833 ntb->bar_info[NTB_B2B_BAR_3].pbarxlat_off = XEON_PBAR5XLAT_OFFSET;
837 device_printf(ntb->device,
838 "unable to allocate pci resource\n");
843 print_map_success(struct ntb_softc *ntb, struct ntb_pci_bar_info *bar,
847 device_printf(ntb->device,
848 "Mapped BAR%d v:[%p-%p] p:[%p-%p] (0x%jx bytes) (%s)\n",
849 PCI_RID2BAR(bar->pci_resource_id), bar->vbase,
850 (char *)bar->vbase + bar->size - 1,
851 (void *)bar->pbase, (void *)(bar->pbase + bar->size - 1),
852 (uintmax_t)bar->size, kind);
856 map_mmr_bar(struct ntb_softc *ntb, struct ntb_pci_bar_info *bar)
859 bar->pci_resource = bus_alloc_resource_any(ntb->device, SYS_RES_MEMORY,
860 &bar->pci_resource_id, RF_ACTIVE);
861 if (bar->pci_resource == NULL)
864 save_bar_parameters(bar);
865 bar->map_mode = VM_MEMATTR_UNCACHEABLE;
866 print_map_success(ntb, bar, "mmr");
871 map_memory_window_bar(struct ntb_softc *ntb, struct ntb_pci_bar_info *bar)
874 vm_memattr_t mapmode;
875 uint8_t bar_size_bits = 0;
877 bar->pci_resource = bus_alloc_resource_any(ntb->device, SYS_RES_MEMORY,
878 &bar->pci_resource_id, RF_ACTIVE);
880 if (bar->pci_resource == NULL)
883 save_bar_parameters(bar);
885 * Ivytown NTB BAR sizes are misreported by the hardware due to a
886 * hardware issue. To work around this, query the size it should be
887 * configured to by the device and modify the resource to correspond to
888 * this new size. The BIOS on systems with this problem is required to
889 * provide enough address space to allow the driver to make this change
892 * Ideally I could have just specified the size when I allocated the
894 * bus_alloc_resource(ntb->device,
895 * SYS_RES_MEMORY, &bar->pci_resource_id, 0ul, ~0ul,
896 * 1ul << bar_size_bits, RF_ACTIVE);
897 * but the PCI driver does not honor the size in this call, so we have
898 * to modify it after the fact.
900 if (HAS_FEATURE(ntb, NTB_BAR_SIZE_4K)) {
901 if (bar->pci_resource_id == PCIR_BAR(2))
902 bar_size_bits = pci_read_config(ntb->device,
903 XEON_PBAR23SZ_OFFSET, 1);
905 bar_size_bits = pci_read_config(ntb->device,
906 XEON_PBAR45SZ_OFFSET, 1);
908 rc = bus_adjust_resource(ntb->device, SYS_RES_MEMORY,
909 bar->pci_resource, bar->pbase,
910 bar->pbase + (1ul << bar_size_bits) - 1);
912 device_printf(ntb->device,
913 "unable to resize bar\n");
917 save_bar_parameters(bar);
920 bar->map_mode = VM_MEMATTR_UNCACHEABLE;
921 print_map_success(ntb, bar, "mw");
924 * Optionally, mark MW BARs as anything other than UC to improve
927 mapmode = ntb_pat_flags();
928 if (mapmode == bar->map_mode)
931 rc = pmap_change_attr((vm_offset_t)bar->vbase, bar->size, mapmode);
933 bar->map_mode = mapmode;
934 device_printf(ntb->device,
935 "Marked BAR%d v:[%p-%p] p:[%p-%p] as "
937 PCI_RID2BAR(bar->pci_resource_id), bar->vbase,
938 (char *)bar->vbase + bar->size - 1,
939 (void *)bar->pbase, (void *)(bar->pbase + bar->size - 1),
940 ntb_vm_memattr_to_str(mapmode));
942 device_printf(ntb->device,
943 "Unable to mark BAR%d v:[%p-%p] p:[%p-%p] as "
945 PCI_RID2BAR(bar->pci_resource_id), bar->vbase,
946 (char *)bar->vbase + bar->size - 1,
947 (void *)bar->pbase, (void *)(bar->pbase + bar->size - 1),
948 ntb_vm_memattr_to_str(mapmode), rc);
954 ntb_unmap_pci_bar(struct ntb_softc *ntb)
956 struct ntb_pci_bar_info *current_bar;
959 for (i = 0; i < NTB_MAX_BARS; i++) {
960 current_bar = &ntb->bar_info[i];
961 if (current_bar->pci_resource != NULL)
962 bus_release_resource(ntb->device, SYS_RES_MEMORY,
963 current_bar->pci_resource_id,
964 current_bar->pci_resource);
969 ntb_setup_msix(struct ntb_softc *ntb, uint32_t num_vectors)
974 for (i = 0; i < num_vectors; i++) {
975 ntb->int_info[i].rid = i + 1;
976 ntb->int_info[i].res = bus_alloc_resource_any(ntb->device,
977 SYS_RES_IRQ, &ntb->int_info[i].rid, RF_ACTIVE);
978 if (ntb->int_info[i].res == NULL) {
979 device_printf(ntb->device,
980 "bus_alloc_resource failed\n");
983 ntb->int_info[i].tag = NULL;
984 ntb->allocated_interrupts++;
985 rc = bus_setup_intr(ntb->device, ntb->int_info[i].res,
986 INTR_MPSAFE | INTR_TYPE_MISC, NULL, ndev_vec_isr,
987 &ntb->msix_vec[i], &ntb->int_info[i].tag);
989 device_printf(ntb->device, "bus_setup_intr failed\n");
997 * The Linux NTB driver drops from MSI-X to legacy INTx if a unique vector
998 * cannot be allocated for each MSI-X message. JHB seems to think remapping
999 * should be okay. This tunable should enable us to test that hypothesis
1000 * when someone gets their hands on some Xeon hardware.
1002 static int ntb_force_remap_mode;
1003 TUNABLE_INT("hw.ntb.force_remap_mode", &ntb_force_remap_mode);
1004 SYSCTL_INT(_hw_ntb, OID_AUTO, force_remap_mode, CTLFLAG_RDTUN,
1005 &ntb_force_remap_mode, 0, "If enabled, force MSI-X messages to be remapped"
1006 " to a smaller number of ithreads, even if the desired number are "
1010 * In case it is NOT ok, give consumers an abort button.
1012 static int ntb_prefer_intx;
1013 TUNABLE_INT("hw.ntb.prefer_intx_to_remap", &ntb_prefer_intx);
1014 SYSCTL_INT(_hw_ntb, OID_AUTO, prefer_intx_to_remap, CTLFLAG_RDTUN,
1015 &ntb_prefer_intx, 0, "If enabled, prefer to use legacy INTx mode rather "
1016 "than remapping MSI-X messages over available slots (match Linux driver "
1020 * Remap the desired number of MSI-X messages to available ithreads in a simple
1021 * round-robin fashion.
1024 ntb_remap_msix(device_t dev, uint32_t desired, uint32_t avail)
1030 if (ntb_prefer_intx != 0)
1033 vectors = malloc(desired * sizeof(*vectors), M_NTB, M_ZERO | M_WAITOK);
1035 for (i = 0; i < desired; i++)
1036 vectors[i] = (i % avail) + 1;
1038 rc = pci_remap_msix(dev, desired, vectors);
1039 free(vectors, M_NTB);
1044 ntb_init_isr(struct ntb_softc *ntb)
1046 uint32_t desired_vectors, num_vectors;
1049 ntb->allocated_interrupts = 0;
1050 ntb->last_ts = ticks;
1053 * Mask all doorbell interrupts. (Except link events!)
1056 ntb->db_mask = ntb->db_valid_mask;
1057 db_iowrite(ntb, ntb->self_reg->db_mask, ntb->db_mask);
1058 DB_MASK_UNLOCK(ntb);
1060 num_vectors = desired_vectors = MIN(pci_msix_count(ntb->device),
1062 if (desired_vectors >= 1) {
1063 rc = pci_alloc_msix(ntb->device, &num_vectors);
1065 if (ntb_force_remap_mode != 0 && rc == 0 &&
1066 num_vectors == desired_vectors)
1069 if (rc == 0 && num_vectors < desired_vectors) {
1070 rc = ntb_remap_msix(ntb->device, desired_vectors,
1073 num_vectors = desired_vectors;
1075 pci_release_msi(ntb->device);
1082 if (ntb->type == NTB_XEON && num_vectors < ntb->db_vec_count) {
1083 if (HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP)) {
1084 device_printf(ntb->device,
1085 "Errata workaround does not support MSI or INTX\n");
1089 ntb->db_vec_count = 1;
1090 ntb->db_vec_shift = XEON_DB_TOTAL_SHIFT;
1091 rc = ntb_setup_legacy_interrupt(ntb);
1093 if (num_vectors - 1 != XEON_NONLINK_DB_MSIX_BITS &&
1094 HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP)) {
1095 device_printf(ntb->device,
1096 "Errata workaround expects %d doorbell bits\n",
1097 XEON_NONLINK_DB_MSIX_BITS);
1101 ntb_create_msix_vec(ntb, num_vectors);
1102 rc = ntb_setup_msix(ntb, num_vectors);
1103 if (rc == 0 && HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP))
1104 ntb_get_msix_info(ntb);
1107 device_printf(ntb->device,
1108 "Error allocating interrupts: %d\n", rc);
1109 ntb_free_msix_vec(ntb);
1116 ntb_setup_legacy_interrupt(struct ntb_softc *ntb)
1120 ntb->int_info[0].rid = 0;
1121 ntb->int_info[0].res = bus_alloc_resource_any(ntb->device, SYS_RES_IRQ,
1122 &ntb->int_info[0].rid, RF_SHAREABLE|RF_ACTIVE);
1123 if (ntb->int_info[0].res == NULL) {
1124 device_printf(ntb->device, "bus_alloc_resource failed\n");
1128 ntb->int_info[0].tag = NULL;
1129 ntb->allocated_interrupts = 1;
1131 rc = bus_setup_intr(ntb->device, ntb->int_info[0].res,
1132 INTR_MPSAFE | INTR_TYPE_MISC, NULL, ndev_irq_isr,
1133 ntb, &ntb->int_info[0].tag);
1135 device_printf(ntb->device, "bus_setup_intr failed\n");
1143 ntb_teardown_interrupts(struct ntb_softc *ntb)
1145 struct ntb_int_info *current_int;
1148 for (i = 0; i < ntb->allocated_interrupts; i++) {
1149 current_int = &ntb->int_info[i];
1150 if (current_int->tag != NULL)
1151 bus_teardown_intr(ntb->device, current_int->res,
1154 if (current_int->res != NULL)
1155 bus_release_resource(ntb->device, SYS_RES_IRQ,
1156 rman_get_rid(current_int->res), current_int->res);
1159 ntb_free_msix_vec(ntb);
1160 pci_release_msi(ntb->device);
1164 * Doorbell register and mask are 64-bit on Atom, 16-bit on Xeon. Abstract it
1165 * out to make code clearer.
1167 static inline uint64_t
1168 db_ioread(struct ntb_softc *ntb, uint64_t regoff)
1171 if (ntb->type == NTB_ATOM)
1172 return (ntb_reg_read(8, regoff));
1174 KASSERT(ntb->type == NTB_XEON, ("bad ntb type"));
1176 return (ntb_reg_read(2, regoff));
1180 db_iowrite(struct ntb_softc *ntb, uint64_t regoff, uint64_t val)
1183 KASSERT((val & ~ntb->db_valid_mask) == 0,
1184 ("%s: Invalid bits 0x%jx (valid: 0x%jx)", __func__,
1185 (uintmax_t)(val & ~ntb->db_valid_mask),
1186 (uintmax_t)ntb->db_valid_mask));
1188 if (regoff == ntb->self_reg->db_mask)
1189 DB_MASK_ASSERT(ntb, MA_OWNED);
1190 db_iowrite_raw(ntb, regoff, val);
1194 db_iowrite_raw(struct ntb_softc *ntb, uint64_t regoff, uint64_t val)
1197 if (ntb->type == NTB_ATOM) {
1198 ntb_reg_write(8, regoff, val);
1202 KASSERT(ntb->type == NTB_XEON, ("bad ntb type"));
1203 ntb_reg_write(2, regoff, (uint16_t)val);
1207 ntb_db_set_mask(device_t dev, uint64_t bits)
1209 struct ntb_softc *ntb = device_get_softc(dev);
1211 if (HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP))
1215 ntb->db_mask |= bits;
1216 db_iowrite(ntb, ntb->self_reg->db_mask, ntb->db_mask);
1217 DB_MASK_UNLOCK(ntb);
1221 ntb_db_clear_mask(device_t dev, uint64_t bits)
1223 struct ntb_softc *ntb = device_get_softc(dev);
1225 KASSERT((bits & ~ntb->db_valid_mask) == 0,
1226 ("%s: Invalid bits 0x%jx (valid: 0x%jx)", __func__,
1227 (uintmax_t)(bits & ~ntb->db_valid_mask),
1228 (uintmax_t)ntb->db_valid_mask));
1230 if (HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP))
1234 ntb->db_mask &= ~bits;
1235 db_iowrite(ntb, ntb->self_reg->db_mask, ntb->db_mask);
1236 DB_MASK_UNLOCK(ntb);
1240 ntb_db_read(device_t dev)
1242 struct ntb_softc *ntb = device_get_softc(dev);
1244 if (HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP)) {
1249 for (i = 0; i < XEON_NONLINK_DB_MSIX_BITS; i++) {
1250 if (ntb->msix_vec[i].masked != 0)
1251 res |= ntb_db_vector_mask(dev, i);
1256 return (db_ioread(ntb, ntb->self_reg->db_bell));
1260 ntb_db_clear(device_t dev, uint64_t bits)
1262 struct ntb_softc *ntb = device_get_softc(dev);
1264 KASSERT((bits & ~ntb->db_valid_mask) == 0,
1265 ("%s: Invalid bits 0x%jx (valid: 0x%jx)", __func__,
1266 (uintmax_t)(bits & ~ntb->db_valid_mask),
1267 (uintmax_t)ntb->db_valid_mask));
1269 if (HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP)) {
1272 for (i = 0; i < XEON_NONLINK_DB_MSIX_BITS; i++) {
1273 if ((bits & ntb_db_vector_mask(dev, i)) != 0) {
1275 if (ntb->msix_vec[i].masked != 0) {
1276 /* XXX These need a public API. */
1278 pci_unmask_msix(ntb->device, i);
1280 ntb->msix_vec[i].masked = 0;
1282 DB_MASK_UNLOCK(ntb);
1288 db_iowrite(ntb, ntb->self_reg->db_bell, bits);
1291 static inline uint64_t
1292 ntb_vec_mask(struct ntb_softc *ntb, uint64_t db_vector)
1294 uint64_t shift, mask;
1296 shift = ntb->db_vec_shift;
1297 mask = (1ull << shift) - 1;
1298 return (mask << (shift * db_vector));
1302 ntb_interrupt(struct ntb_softc *ntb, uint32_t vec)
1306 ntb->last_ts = ticks;
1307 vec_mask = ntb_vec_mask(ntb, vec);
1309 if ((vec_mask & ntb->db_link_mask) != 0) {
1310 if (ntb_poll_link(ntb))
1311 ntb_link_event(ntb->device);
1314 if (HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP) &&
1315 (vec_mask & ntb->db_link_mask) == 0) {
1317 if (ntb->msix_vec[vec].masked == 0) {
1318 /* XXX These need a public API. */
1320 pci_mask_msix(ntb->device, vec);
1322 ntb->msix_vec[vec].masked = 1;
1324 DB_MASK_UNLOCK(ntb);
1327 if ((vec_mask & ntb->db_valid_mask) != 0)
1328 ntb_db_event(ntb->device, vec);
1332 ndev_vec_isr(void *arg)
1334 struct ntb_vec *nvec = arg;
1336 ntb_interrupt(nvec->ntb, nvec->num);
1340 ndev_irq_isr(void *arg)
1342 /* If we couldn't set up MSI-X, we only have the one vector. */
1343 ntb_interrupt(arg, 0);
1347 ntb_create_msix_vec(struct ntb_softc *ntb, uint32_t num_vectors)
1351 ntb->msix_vec = malloc(num_vectors * sizeof(*ntb->msix_vec), M_NTB,
1353 for (i = 0; i < num_vectors; i++) {
1354 ntb->msix_vec[i].num = i;
1355 ntb->msix_vec[i].ntb = ntb;
1362 ntb_free_msix_vec(struct ntb_softc *ntb)
1365 if (ntb->msix_vec == NULL)
1368 free(ntb->msix_vec, M_NTB);
1369 ntb->msix_vec = NULL;
1373 ntb_get_msix_info(struct ntb_softc *ntb)
1375 struct pci_devinfo *dinfo;
1376 struct pcicfg_msix *msix;
1377 uint32_t laddr, data, i, offset;
1379 dinfo = device_get_ivars(ntb->device);
1380 msix = &dinfo->cfg.msix;
1382 CTASSERT(XEON_NONLINK_DB_MSIX_BITS == nitems(ntb->msix_data));
1384 for (i = 0; i < XEON_NONLINK_DB_MSIX_BITS; i++) {
1385 offset = msix->msix_table_offset + i * PCI_MSIX_ENTRY_SIZE;
1387 laddr = bus_read_4(msix->msix_table_res, offset +
1388 PCI_MSIX_ENTRY_LOWER_ADDR);
1389 ntb_printf(2, "local MSIX addr(%u): 0x%x\n", i, laddr);
1391 KASSERT((laddr & MSI_INTEL_ADDR_BASE) == MSI_INTEL_ADDR_BASE,
1392 ("local MSIX addr 0x%x not in MSI base 0x%x", laddr,
1393 MSI_INTEL_ADDR_BASE));
1394 ntb->msix_data[i].nmd_ofs = laddr;
1396 data = bus_read_4(msix->msix_table_res, offset +
1397 PCI_MSIX_ENTRY_DATA);
1398 ntb_printf(2, "local MSIX data(%u): 0x%x\n", i, data);
1400 ntb->msix_data[i].nmd_data = data;
1404 static struct ntb_hw_info *
1405 ntb_get_device_info(uint32_t device_id)
1407 struct ntb_hw_info *ep = pci_ids;
1409 while (ep->device_id) {
1410 if (ep->device_id == device_id)
1418 ntb_teardown_xeon(struct ntb_softc *ntb)
1421 if (ntb->reg != NULL)
1422 ntb_link_disable(ntb->device);
1426 ntb_detect_max_mw(struct ntb_softc *ntb)
1429 if (ntb->type == NTB_ATOM) {
1430 ntb->mw_count = ATOM_MW_COUNT;
1434 if (HAS_FEATURE(ntb, NTB_SPLIT_BAR))
1435 ntb->mw_count = XEON_HSX_SPLIT_MW_COUNT;
1437 ntb->mw_count = XEON_SNB_MW_COUNT;
1441 ntb_detect_xeon(struct ntb_softc *ntb)
1443 uint8_t ppd, conn_type;
1445 ppd = pci_read_config(ntb->device, NTB_PPD_OFFSET, 1);
1448 if ((ppd & XEON_PPD_DEV_TYPE) != 0)
1449 ntb->dev_type = NTB_DEV_DSD;
1451 ntb->dev_type = NTB_DEV_USD;
1453 if ((ppd & XEON_PPD_SPLIT_BAR) != 0)
1454 ntb->features |= NTB_SPLIT_BAR;
1457 * SDOORBELL errata workaround gets in the way of SB01BASE_LOCKUP
1458 * errata workaround; only do one at a time.
1460 if (HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP))
1461 ntb->features &= ~NTB_SDOORBELL_LOCKUP;
1463 conn_type = ppd & XEON_PPD_CONN_TYPE;
1464 switch (conn_type) {
1466 ntb->conn_type = conn_type;
1469 case NTB_CONN_TRANSPARENT:
1471 device_printf(ntb->device, "Unsupported connection type: %u\n",
1472 (unsigned)conn_type);
1479 ntb_detect_atom(struct ntb_softc *ntb)
1481 uint32_t ppd, conn_type;
1483 ppd = pci_read_config(ntb->device, NTB_PPD_OFFSET, 4);
1486 if ((ppd & ATOM_PPD_DEV_TYPE) != 0)
1487 ntb->dev_type = NTB_DEV_DSD;
1489 ntb->dev_type = NTB_DEV_USD;
1491 conn_type = (ppd & ATOM_PPD_CONN_TYPE) >> 8;
1492 switch (conn_type) {
1494 ntb->conn_type = conn_type;
1497 device_printf(ntb->device, "Unsupported NTB configuration\n");
1504 ntb_xeon_init_dev(struct ntb_softc *ntb)
1508 ntb->spad_count = XEON_SPAD_COUNT;
1509 ntb->db_count = XEON_DB_COUNT;
1510 ntb->db_link_mask = XEON_DB_LINK_BIT;
1511 ntb->db_vec_count = XEON_DB_MSIX_VECTOR_COUNT;
1512 ntb->db_vec_shift = XEON_DB_MSIX_VECTOR_SHIFT;
1514 if (ntb->conn_type != NTB_CONN_B2B) {
1515 device_printf(ntb->device, "Connection type %d not supported\n",
1520 ntb->reg = &xeon_reg;
1521 ntb->self_reg = &xeon_pri_reg;
1522 ntb->peer_reg = &xeon_b2b_reg;
1523 ntb->xlat_reg = &xeon_sec_xlat;
1525 if (HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP)) {
1526 ntb->msix_mw_idx = (ntb->mw_count + g_ntb_msix_idx) %
1528 ntb_printf(2, "Setting up MSIX mw idx %d means %u\n",
1529 g_ntb_msix_idx, ntb->msix_mw_idx);
1530 rc = ntb_mw_set_wc_internal(ntb, ntb->msix_mw_idx,
1531 VM_MEMATTR_UNCACHEABLE);
1532 KASSERT(rc == 0, ("shouldn't fail"));
1533 } else if (HAS_FEATURE(ntb, NTB_SDOORBELL_LOCKUP)) {
1535 * There is a Xeon hardware errata related to writes to SDOORBELL or
1536 * B2BDOORBELL in conjunction with inbound access to NTB MMIO space,
1537 * which may hang the system. To workaround this, use a memory
1538 * window to access the interrupt and scratch pad registers on the
1541 ntb->b2b_mw_idx = (ntb->mw_count + g_ntb_mw_idx) %
1543 ntb_printf(2, "Setting up b2b mw idx %d means %u\n",
1544 g_ntb_mw_idx, ntb->b2b_mw_idx);
1545 rc = ntb_mw_set_wc_internal(ntb, ntb->b2b_mw_idx,
1546 VM_MEMATTR_UNCACHEABLE);
1547 KASSERT(rc == 0, ("shouldn't fail"));
1548 } else if (HAS_FEATURE(ntb, NTB_B2BDOORBELL_BIT14))
1550 * HW Errata on bit 14 of b2bdoorbell register. Writes will not be
1551 * mirrored to the remote system. Shrink the number of bits by one,
1552 * since bit 14 is the last bit.
1554 * On REGS_THRU_MW errata mode, we don't use the b2bdoorbell register
1555 * anyway. Nor for non-B2B connection types.
1557 ntb->db_count = XEON_DB_COUNT - 1;
1559 ntb->db_valid_mask = (1ull << ntb->db_count) - 1;
1561 if (ntb->dev_type == NTB_DEV_USD)
1562 rc = xeon_setup_b2b_mw(ntb, &xeon_b2b_dsd_addr,
1563 &xeon_b2b_usd_addr);
1565 rc = xeon_setup_b2b_mw(ntb, &xeon_b2b_usd_addr,
1566 &xeon_b2b_dsd_addr);
1570 /* Enable Bus Master and Memory Space on the secondary side */
1571 ntb_reg_write(2, XEON_SPCICMD_OFFSET,
1572 PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
1575 * Mask all doorbell interrupts.
1578 ntb->db_mask = ntb->db_valid_mask;
1579 db_iowrite(ntb, ntb->self_reg->db_mask, ntb->db_mask);
1580 DB_MASK_UNLOCK(ntb);
1582 rc = xeon_setup_msix_bar(ntb);
1586 rc = ntb_init_isr(ntb);
1591 ntb_atom_init_dev(struct ntb_softc *ntb)
1595 KASSERT(ntb->conn_type == NTB_CONN_B2B,
1596 ("Unsupported NTB configuration (%d)\n", ntb->conn_type));
1598 ntb->spad_count = ATOM_SPAD_COUNT;
1599 ntb->db_count = ATOM_DB_COUNT;
1600 ntb->db_vec_count = ATOM_DB_MSIX_VECTOR_COUNT;
1601 ntb->db_vec_shift = ATOM_DB_MSIX_VECTOR_SHIFT;
1602 ntb->db_valid_mask = (1ull << ntb->db_count) - 1;
1604 ntb->reg = &atom_reg;
1605 ntb->self_reg = &atom_pri_reg;
1606 ntb->peer_reg = &atom_b2b_reg;
1607 ntb->xlat_reg = &atom_sec_xlat;
1610 * FIXME - MSI-X bug on early Atom HW, remove once internal issue is
1611 * resolved. Mask transaction layer internal parity errors.
1613 pci_write_config(ntb->device, 0xFC, 0x4, 4);
1615 configure_atom_secondary_side_bars(ntb);
1617 /* Enable Bus Master and Memory Space on the secondary side */
1618 ntb_reg_write(2, ATOM_SPCICMD_OFFSET,
1619 PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
1621 error = ntb_init_isr(ntb);
1625 /* Initiate PCI-E link training */
1626 ntb_link_enable(ntb->device, NTB_SPEED_AUTO, NTB_WIDTH_AUTO);
1628 callout_reset(&ntb->heartbeat_timer, 0, atom_link_hb, ntb);
1633 /* XXX: Linux driver doesn't seem to do any of this for Atom. */
1635 configure_atom_secondary_side_bars(struct ntb_softc *ntb)
1638 if (ntb->dev_type == NTB_DEV_USD) {
1639 ntb_reg_write(8, ATOM_PBAR2XLAT_OFFSET,
1640 XEON_B2B_BAR2_ADDR64);
1641 ntb_reg_write(8, ATOM_PBAR4XLAT_OFFSET,
1642 XEON_B2B_BAR4_ADDR64);
1643 ntb_reg_write(8, ATOM_MBAR23_OFFSET, XEON_B2B_BAR2_ADDR64);
1644 ntb_reg_write(8, ATOM_MBAR45_OFFSET, XEON_B2B_BAR4_ADDR64);
1646 ntb_reg_write(8, ATOM_PBAR2XLAT_OFFSET,
1647 XEON_B2B_BAR2_ADDR64);
1648 ntb_reg_write(8, ATOM_PBAR4XLAT_OFFSET,
1649 XEON_B2B_BAR4_ADDR64);
1650 ntb_reg_write(8, ATOM_MBAR23_OFFSET, XEON_B2B_BAR2_ADDR64);
1651 ntb_reg_write(8, ATOM_MBAR45_OFFSET, XEON_B2B_BAR4_ADDR64);
1657 * When working around Xeon SDOORBELL errata by remapping remote registers in a
1658 * MW, limit the B2B MW to half a MW. By sharing a MW, half the shared MW
1659 * remains for use by a higher layer.
1661 * Will only be used if working around SDOORBELL errata and the BIOS-configured
1662 * MW size is sufficiently large.
1664 static unsigned int ntb_b2b_mw_share;
1665 TUNABLE_INT("hw.ntb.b2b_mw_share", &ntb_b2b_mw_share);
1666 SYSCTL_UINT(_hw_ntb, OID_AUTO, b2b_mw_share, CTLFLAG_RDTUN, &ntb_b2b_mw_share,
1667 0, "If enabled (non-zero), prefer to share half of the B2B peer register "
1668 "MW with higher level consumers. Both sides of the NTB MUST set the same "
1672 xeon_reset_sbar_size(struct ntb_softc *ntb, enum ntb_bar idx,
1673 enum ntb_bar regbar)
1675 struct ntb_pci_bar_info *bar;
1678 if (!HAS_FEATURE(ntb, NTB_SPLIT_BAR) && idx >= NTB_B2B_BAR_3)
1681 bar = &ntb->bar_info[idx];
1682 bar_sz = pci_read_config(ntb->device, bar->psz_off, 1);
1683 if (idx == regbar) {
1684 if (ntb->b2b_off != 0)
1689 pci_write_config(ntb->device, bar->ssz_off, bar_sz, 1);
1690 bar_sz = pci_read_config(ntb->device, bar->ssz_off, 1);
1695 xeon_set_sbar_base_and_limit(struct ntb_softc *ntb, uint64_t bar_addr,
1696 enum ntb_bar idx, enum ntb_bar regbar)
1699 uint32_t base_reg, lmt_reg;
1701 bar_get_xlat_params(ntb, idx, &base_reg, NULL, &lmt_reg);
1702 if (idx == regbar) {
1704 bar_addr += ntb->b2b_off;
1710 * Set limit registers first to avoid an errata where setting the base
1711 * registers locks the limit registers.
1713 if (!bar_is_64bit(ntb, idx)) {
1714 ntb_reg_write(4, lmt_reg, bar_addr);
1715 reg_val = ntb_reg_read(4, lmt_reg);
1718 ntb_reg_write(4, base_reg, bar_addr);
1719 reg_val = ntb_reg_read(4, base_reg);
1722 ntb_reg_write(8, lmt_reg, bar_addr);
1723 reg_val = ntb_reg_read(8, lmt_reg);
1726 ntb_reg_write(8, base_reg, bar_addr);
1727 reg_val = ntb_reg_read(8, base_reg);
1733 xeon_set_pbar_xlat(struct ntb_softc *ntb, uint64_t base_addr, enum ntb_bar idx)
1735 struct ntb_pci_bar_info *bar;
1737 bar = &ntb->bar_info[idx];
1738 if (HAS_FEATURE(ntb, NTB_SPLIT_BAR) && idx >= NTB_B2B_BAR_2) {
1739 ntb_reg_write(4, bar->pbarxlat_off, base_addr);
1740 base_addr = ntb_reg_read(4, bar->pbarxlat_off);
1742 ntb_reg_write(8, bar->pbarxlat_off, base_addr);
1743 base_addr = ntb_reg_read(8, bar->pbarxlat_off);
1749 xeon_setup_msix_bar(struct ntb_softc *ntb)
1751 enum ntb_bar bar_num;
1753 if (!HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP))
1756 bar_num = ntb_mw_to_bar(ntb, ntb->msix_mw_idx);
1757 ntb->peer_lapic_bar = &ntb->bar_info[bar_num];
1762 xeon_setup_b2b_mw(struct ntb_softc *ntb, const struct ntb_b2b_addr *addr,
1763 const struct ntb_b2b_addr *peer_addr)
1765 struct ntb_pci_bar_info *b2b_bar;
1768 enum ntb_bar b2b_bar_num, i;
1770 if (ntb->b2b_mw_idx == B2B_MW_DISABLED) {
1772 b2b_bar_num = NTB_CONFIG_BAR;
1775 b2b_bar_num = ntb_mw_to_bar(ntb, ntb->b2b_mw_idx);
1776 KASSERT(b2b_bar_num > 0 && b2b_bar_num < NTB_MAX_BARS,
1777 ("invalid b2b mw bar"));
1779 b2b_bar = &ntb->bar_info[b2b_bar_num];
1780 bar_size = b2b_bar->size;
1782 if (ntb_b2b_mw_share != 0 &&
1783 (bar_size >> 1) >= XEON_B2B_MIN_SIZE)
1784 ntb->b2b_off = bar_size >> 1;
1785 else if (bar_size >= XEON_B2B_MIN_SIZE) {
1788 device_printf(ntb->device,
1789 "B2B bar size is too small!\n");
1795 * Reset the secondary bar sizes to match the primary bar sizes.
1796 * (Except, disable or halve the size of the B2B secondary bar.)
1798 for (i = NTB_B2B_BAR_1; i < NTB_MAX_BARS; i++)
1799 xeon_reset_sbar_size(ntb, i, b2b_bar_num);
1802 if (b2b_bar_num == NTB_CONFIG_BAR)
1803 bar_addr = addr->bar0_addr;
1804 else if (b2b_bar_num == NTB_B2B_BAR_1)
1805 bar_addr = addr->bar2_addr64;
1806 else if (b2b_bar_num == NTB_B2B_BAR_2 && !HAS_FEATURE(ntb, NTB_SPLIT_BAR))
1807 bar_addr = addr->bar4_addr64;
1808 else if (b2b_bar_num == NTB_B2B_BAR_2)
1809 bar_addr = addr->bar4_addr32;
1810 else if (b2b_bar_num == NTB_B2B_BAR_3)
1811 bar_addr = addr->bar5_addr32;
1813 KASSERT(false, ("invalid bar"));
1815 ntb_reg_write(8, XEON_SBAR0BASE_OFFSET, bar_addr);
1818 * Other SBARs are normally hit by the PBAR xlat, except for the b2b
1819 * register BAR. The B2B BAR is either disabled above or configured
1820 * half-size. It starts at PBAR xlat + offset.
1822 * Also set up incoming BAR limits == base (zero length window).
1824 xeon_set_sbar_base_and_limit(ntb, addr->bar2_addr64, NTB_B2B_BAR_1,
1826 if (HAS_FEATURE(ntb, NTB_SPLIT_BAR)) {
1827 xeon_set_sbar_base_and_limit(ntb, addr->bar4_addr32,
1828 NTB_B2B_BAR_2, b2b_bar_num);
1829 xeon_set_sbar_base_and_limit(ntb, addr->bar5_addr32,
1830 NTB_B2B_BAR_3, b2b_bar_num);
1832 xeon_set_sbar_base_and_limit(ntb, addr->bar4_addr64,
1833 NTB_B2B_BAR_2, b2b_bar_num);
1835 /* Zero incoming translation addrs */
1836 ntb_reg_write(8, XEON_SBAR2XLAT_OFFSET, 0);
1837 ntb_reg_write(8, XEON_SBAR4XLAT_OFFSET, 0);
1839 if (HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP)) {
1840 size_t size, xlatoffset;
1842 switch (ntb_mw_to_bar(ntb, ntb->msix_mw_idx)) {
1845 xlatoffset = XEON_SBAR2XLAT_OFFSET;
1848 xlatoffset = XEON_SBAR4XLAT_OFFSET;
1849 if (HAS_FEATURE(ntb, NTB_SPLIT_BAR))
1855 xlatoffset = XEON_SBAR5XLAT_OFFSET;
1859 KASSERT(false, ("Bogus msix mw idx: %u",
1865 * We point the chosen MSIX MW BAR xlat to remote LAPIC for
1869 ntb_reg_write(4, xlatoffset, MSI_INTEL_ADDR_BASE);
1870 ntb->msix_xlat = ntb_reg_read(4, xlatoffset);
1872 ntb_reg_write(8, xlatoffset, MSI_INTEL_ADDR_BASE);
1873 ntb->msix_xlat = ntb_reg_read(8, xlatoffset);
1876 (void)ntb_reg_read(8, XEON_SBAR2XLAT_OFFSET);
1877 (void)ntb_reg_read(8, XEON_SBAR4XLAT_OFFSET);
1879 /* Zero outgoing translation limits (whole bar size windows) */
1880 ntb_reg_write(8, XEON_PBAR2LMT_OFFSET, 0);
1881 ntb_reg_write(8, XEON_PBAR4LMT_OFFSET, 0);
1883 /* Set outgoing translation offsets */
1884 xeon_set_pbar_xlat(ntb, peer_addr->bar2_addr64, NTB_B2B_BAR_1);
1885 if (HAS_FEATURE(ntb, NTB_SPLIT_BAR)) {
1886 xeon_set_pbar_xlat(ntb, peer_addr->bar4_addr32, NTB_B2B_BAR_2);
1887 xeon_set_pbar_xlat(ntb, peer_addr->bar5_addr32, NTB_B2B_BAR_3);
1889 xeon_set_pbar_xlat(ntb, peer_addr->bar4_addr64, NTB_B2B_BAR_2);
1891 /* Set the translation offset for B2B registers */
1893 if (b2b_bar_num == NTB_CONFIG_BAR)
1894 bar_addr = peer_addr->bar0_addr;
1895 else if (b2b_bar_num == NTB_B2B_BAR_1)
1896 bar_addr = peer_addr->bar2_addr64;
1897 else if (b2b_bar_num == NTB_B2B_BAR_2 && !HAS_FEATURE(ntb, NTB_SPLIT_BAR))
1898 bar_addr = peer_addr->bar4_addr64;
1899 else if (b2b_bar_num == NTB_B2B_BAR_2)
1900 bar_addr = peer_addr->bar4_addr32;
1901 else if (b2b_bar_num == NTB_B2B_BAR_3)
1902 bar_addr = peer_addr->bar5_addr32;
1904 KASSERT(false, ("invalid bar"));
1907 * B2B_XLAT_OFFSET is a 64-bit register but can only be written 32 bits
1910 ntb_reg_write(4, XEON_B2B_XLAT_OFFSETL, bar_addr & 0xffffffff);
1911 ntb_reg_write(4, XEON_B2B_XLAT_OFFSETU, bar_addr >> 32);
1916 _xeon_link_is_up(struct ntb_softc *ntb)
1919 if (ntb->conn_type == NTB_CONN_TRANSPARENT)
1921 return ((ntb->lnk_sta & NTB_LINK_STATUS_ACTIVE) != 0);
1925 link_is_up(struct ntb_softc *ntb)
1928 if (ntb->type == NTB_XEON)
1929 return (_xeon_link_is_up(ntb) && (ntb->peer_msix_good ||
1930 !HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP)));
1932 KASSERT(ntb->type == NTB_ATOM, ("ntb type"));
1933 return ((ntb->ntb_ctl & ATOM_CNTL_LINK_DOWN) == 0);
1937 atom_link_is_err(struct ntb_softc *ntb)
1941 KASSERT(ntb->type == NTB_ATOM, ("ntb type"));
1943 status = ntb_reg_read(4, ATOM_LTSSMSTATEJMP_OFFSET);
1944 if ((status & ATOM_LTSSMSTATEJMP_FORCEDETECT) != 0)
1947 status = ntb_reg_read(4, ATOM_IBSTERRRCRVSTS0_OFFSET);
1948 return ((status & ATOM_IBIST_ERR_OFLOW) != 0);
1951 /* Atom does not have link status interrupt, poll on that platform */
1953 atom_link_hb(void *arg)
1955 struct ntb_softc *ntb = arg;
1956 sbintime_t timo, poll_ts;
1958 timo = NTB_HB_TIMEOUT * hz;
1959 poll_ts = ntb->last_ts + timo;
1962 * Delay polling the link status if an interrupt was received, unless
1963 * the cached link status says the link is down.
1965 if ((sbintime_t)ticks - poll_ts < 0 && link_is_up(ntb)) {
1966 timo = poll_ts - ticks;
1970 if (ntb_poll_link(ntb))
1971 ntb_link_event(ntb->device);
1973 if (!link_is_up(ntb) && atom_link_is_err(ntb)) {
1974 /* Link is down with error, proceed with recovery */
1975 callout_reset(&ntb->lr_timer, 0, recover_atom_link, ntb);
1980 callout_reset(&ntb->heartbeat_timer, timo, atom_link_hb, ntb);
1984 atom_perform_link_restart(struct ntb_softc *ntb)
1988 /* Driver resets the NTB ModPhy lanes - magic! */
1989 ntb_reg_write(1, ATOM_MODPHY_PCSREG6, 0xe0);
1990 ntb_reg_write(1, ATOM_MODPHY_PCSREG4, 0x40);
1991 ntb_reg_write(1, ATOM_MODPHY_PCSREG4, 0x60);
1992 ntb_reg_write(1, ATOM_MODPHY_PCSREG6, 0x60);
1994 /* Driver waits 100ms to allow the NTB ModPhy to settle */
1995 pause("ModPhy", hz / 10);
1997 /* Clear AER Errors, write to clear */
1998 status = ntb_reg_read(4, ATOM_ERRCORSTS_OFFSET);
1999 status &= PCIM_AER_COR_REPLAY_ROLLOVER;
2000 ntb_reg_write(4, ATOM_ERRCORSTS_OFFSET, status);
2002 /* Clear unexpected electrical idle event in LTSSM, write to clear */
2003 status = ntb_reg_read(4, ATOM_LTSSMERRSTS0_OFFSET);
2004 status |= ATOM_LTSSMERRSTS0_UNEXPECTEDEI;
2005 ntb_reg_write(4, ATOM_LTSSMERRSTS0_OFFSET, status);
2007 /* Clear DeSkew Buffer error, write to clear */
2008 status = ntb_reg_read(4, ATOM_DESKEWSTS_OFFSET);
2009 status |= ATOM_DESKEWSTS_DBERR;
2010 ntb_reg_write(4, ATOM_DESKEWSTS_OFFSET, status);
2012 status = ntb_reg_read(4, ATOM_IBSTERRRCRVSTS0_OFFSET);
2013 status &= ATOM_IBIST_ERR_OFLOW;
2014 ntb_reg_write(4, ATOM_IBSTERRRCRVSTS0_OFFSET, status);
2016 /* Releases the NTB state machine to allow the link to retrain */
2017 status = ntb_reg_read(4, ATOM_LTSSMSTATEJMP_OFFSET);
2018 status &= ~ATOM_LTSSMSTATEJMP_FORCEDETECT;
2019 ntb_reg_write(4, ATOM_LTSSMSTATEJMP_OFFSET, status);
2023 ntb_set_ctx(device_t dev, void *ctx, const struct ntb_ctx_ops *ops)
2025 struct ntb_softc *ntb = device_get_softc(dev);
2027 if (ctx == NULL || ops == NULL)
2030 rm_wlock(&ntb->ctx_lock);
2031 if (ntb->ctx_ops != NULL) {
2032 rm_wunlock(&ntb->ctx_lock);
2037 rm_wunlock(&ntb->ctx_lock);
2043 * It is expected that this will only be used from contexts where the ctx_lock
2044 * is not needed to protect ntb_ctx lifetime.
2047 ntb_get_ctx(device_t dev, const struct ntb_ctx_ops **ops)
2049 struct ntb_softc *ntb = device_get_softc(dev);
2051 KASSERT(ntb->ntb_ctx != NULL && ntb->ctx_ops != NULL, ("bogus"));
2053 *ops = ntb->ctx_ops;
2054 return (ntb->ntb_ctx);
2058 ntb_clear_ctx(device_t dev)
2060 struct ntb_softc *ntb = device_get_softc(dev);
2062 rm_wlock(&ntb->ctx_lock);
2063 ntb->ntb_ctx = NULL;
2064 ntb->ctx_ops = NULL;
2065 rm_wunlock(&ntb->ctx_lock);
2069 * ntb_link_event() - notify driver context of a change in link status
2070 * @ntb: NTB device context
2072 * Notify the driver context that the link status may have changed. The driver
2073 * should call ntb_link_is_up() to get the current status.
2076 ntb_link_event(device_t dev)
2078 struct ntb_softc *ntb = device_get_softc(dev);
2079 struct rm_priotracker ctx_tracker;
2081 rm_rlock(&ntb->ctx_lock, &ctx_tracker);
2082 if (ntb->ctx_ops != NULL && ntb->ctx_ops->link_event != NULL)
2083 ntb->ctx_ops->link_event(ntb->ntb_ctx);
2084 rm_runlock(&ntb->ctx_lock, &ctx_tracker);
2088 * ntb_db_event() - notify driver context of a doorbell event
2089 * @ntb: NTB device context
2090 * @vector: Interrupt vector number
2092 * Notify the driver context of a doorbell event. If hardware supports
2093 * multiple interrupt vectors for doorbells, the vector number indicates which
2094 * vector received the interrupt. The vector number is relative to the first
2095 * vector used for doorbells, starting at zero, and must be less than
2096 * ntb_db_vector_count(). The driver may call ntb_db_read() to check which
2097 * doorbell bits need service, and ntb_db_vector_mask() to determine which of
2098 * those bits are associated with the vector number.
2101 ntb_db_event(device_t dev, uint32_t vec)
2103 struct ntb_softc *ntb = device_get_softc(dev);
2104 struct rm_priotracker ctx_tracker;
2106 rm_rlock(&ntb->ctx_lock, &ctx_tracker);
2107 if (ntb->ctx_ops != NULL && ntb->ctx_ops->db_event != NULL)
2108 ntb->ctx_ops->db_event(ntb->ntb_ctx, vec);
2109 rm_runlock(&ntb->ctx_lock, &ctx_tracker);
2113 ntb_link_enable(device_t dev, enum ntb_speed speed __unused,
2114 enum ntb_width width __unused)
2116 struct ntb_softc *ntb = device_get_softc(dev);
2119 ntb_printf(2, "%s\n", __func__);
2121 if (ntb->type == NTB_ATOM) {
2122 pci_write_config(ntb->device, NTB_PPD_OFFSET,
2123 ntb->ppd | ATOM_PPD_INIT_LINK, 4);
2127 if (ntb->conn_type == NTB_CONN_TRANSPARENT) {
2128 ntb_link_event(dev);
2132 cntl = ntb_reg_read(4, ntb->reg->ntb_ctl);
2133 cntl &= ~(NTB_CNTL_LINK_DISABLE | NTB_CNTL_CFG_LOCK);
2134 cntl |= NTB_CNTL_P2S_BAR23_SNOOP | NTB_CNTL_S2P_BAR23_SNOOP;
2135 cntl |= NTB_CNTL_P2S_BAR4_SNOOP | NTB_CNTL_S2P_BAR4_SNOOP;
2136 if (HAS_FEATURE(ntb, NTB_SPLIT_BAR))
2137 cntl |= NTB_CNTL_P2S_BAR5_SNOOP | NTB_CNTL_S2P_BAR5_SNOOP;
2138 ntb_reg_write(4, ntb->reg->ntb_ctl, cntl);
2143 ntb_link_disable(device_t dev)
2145 struct ntb_softc *ntb = device_get_softc(dev);
2148 ntb_printf(2, "%s\n", __func__);
2150 if (ntb->conn_type == NTB_CONN_TRANSPARENT) {
2151 ntb_link_event(dev);
2155 cntl = ntb_reg_read(4, ntb->reg->ntb_ctl);
2156 cntl &= ~(NTB_CNTL_P2S_BAR23_SNOOP | NTB_CNTL_S2P_BAR23_SNOOP);
2157 cntl &= ~(NTB_CNTL_P2S_BAR4_SNOOP | NTB_CNTL_S2P_BAR4_SNOOP);
2158 if (HAS_FEATURE(ntb, NTB_SPLIT_BAR))
2159 cntl &= ~(NTB_CNTL_P2S_BAR5_SNOOP | NTB_CNTL_S2P_BAR5_SNOOP);
2160 cntl |= NTB_CNTL_LINK_DISABLE | NTB_CNTL_CFG_LOCK;
2161 ntb_reg_write(4, ntb->reg->ntb_ctl, cntl);
2166 ntb_link_enabled(device_t dev)
2168 struct ntb_softc *ntb = device_get_softc(dev);
2171 if (ntb->type == NTB_ATOM) {
2172 cntl = pci_read_config(ntb->device, NTB_PPD_OFFSET, 4);
2173 return ((cntl & ATOM_PPD_INIT_LINK) != 0);
2176 if (ntb->conn_type == NTB_CONN_TRANSPARENT)
2179 cntl = ntb_reg_read(4, ntb->reg->ntb_ctl);
2180 return ((cntl & NTB_CNTL_LINK_DISABLE) == 0);
2184 recover_atom_link(void *arg)
2186 struct ntb_softc *ntb = arg;
2187 unsigned speed, width, oldspeed, oldwidth;
2190 atom_perform_link_restart(ntb);
2193 * There is a potential race between the 2 NTB devices recovering at
2194 * the same time. If the times are the same, the link will not recover
2195 * and the driver will be stuck in this loop forever. Add a random
2196 * interval to the recovery time to prevent this race.
2198 status32 = arc4random() % ATOM_LINK_RECOVERY_TIME;
2199 pause("Link", (ATOM_LINK_RECOVERY_TIME + status32) * hz / 1000);
2201 if (atom_link_is_err(ntb))
2204 status32 = ntb_reg_read(4, ntb->reg->ntb_ctl);
2205 if ((status32 & ATOM_CNTL_LINK_DOWN) != 0)
2208 status32 = ntb_reg_read(4, ntb->reg->lnk_sta);
2209 width = NTB_LNK_STA_WIDTH(status32);
2210 speed = status32 & NTB_LINK_SPEED_MASK;
2212 oldwidth = NTB_LNK_STA_WIDTH(ntb->lnk_sta);
2213 oldspeed = ntb->lnk_sta & NTB_LINK_SPEED_MASK;
2214 if (oldwidth != width || oldspeed != speed)
2218 callout_reset(&ntb->heartbeat_timer, NTB_HB_TIMEOUT * hz, atom_link_hb,
2223 callout_reset(&ntb->lr_timer, NTB_HB_TIMEOUT * hz, recover_atom_link,
2228 * Polls the HW link status register(s); returns true if something has changed.
2231 ntb_poll_link(struct ntb_softc *ntb)
2236 if (ntb->type == NTB_ATOM) {
2237 ntb_cntl = ntb_reg_read(4, ntb->reg->ntb_ctl);
2238 if (ntb_cntl == ntb->ntb_ctl)
2241 ntb->ntb_ctl = ntb_cntl;
2242 ntb->lnk_sta = ntb_reg_read(4, ntb->reg->lnk_sta);
2244 db_iowrite_raw(ntb, ntb->self_reg->db_bell, ntb->db_link_mask);
2246 reg_val = pci_read_config(ntb->device, ntb->reg->lnk_sta, 2);
2247 if (reg_val == ntb->lnk_sta)
2250 ntb->lnk_sta = reg_val;
2252 if (HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP)) {
2253 if (_xeon_link_is_up(ntb)) {
2254 if (!ntb->peer_msix_good) {
2255 callout_reset(&ntb->peer_msix_work, 0,
2256 ntb_exchange_msix, ntb);
2260 ntb->peer_msix_good = false;
2261 ntb->peer_msix_done = false;
2268 static inline enum ntb_speed
2269 ntb_link_sta_speed(struct ntb_softc *ntb)
2272 if (!link_is_up(ntb))
2273 return (NTB_SPEED_NONE);
2274 return (ntb->lnk_sta & NTB_LINK_SPEED_MASK);
2277 static inline enum ntb_width
2278 ntb_link_sta_width(struct ntb_softc *ntb)
2281 if (!link_is_up(ntb))
2282 return (NTB_WIDTH_NONE);
2283 return (NTB_LNK_STA_WIDTH(ntb->lnk_sta));
2286 SYSCTL_NODE(_hw_ntb, OID_AUTO, debug_info, CTLFLAG_RW, 0,
2287 "Driver state, statistics, and HW registers");
2289 #define NTB_REGSZ_MASK (3ul << 30)
2290 #define NTB_REG_64 (1ul << 30)
2291 #define NTB_REG_32 (2ul << 30)
2292 #define NTB_REG_16 (3ul << 30)
2293 #define NTB_REG_8 (0ul << 30)
2295 #define NTB_DB_READ (1ul << 29)
2296 #define NTB_PCI_REG (1ul << 28)
2297 #define NTB_REGFLAGS_MASK (NTB_REGSZ_MASK | NTB_DB_READ | NTB_PCI_REG)
2300 ntb_sysctl_init(struct ntb_softc *ntb)
2302 struct sysctl_oid_list *globals, *tree_par, *regpar, *statpar, *errpar;
2303 struct sysctl_ctx_list *ctx;
2304 struct sysctl_oid *tree, *tmptree;
2306 ctx = device_get_sysctl_ctx(ntb->device);
2307 globals = SYSCTL_CHILDREN(device_get_sysctl_tree(ntb->device));
2309 SYSCTL_ADD_PROC(ctx, globals, OID_AUTO, "link_status",
2310 CTLFLAG_RD | CTLTYPE_STRING, ntb, 0,
2311 sysctl_handle_link_status_human, "A",
2312 "Link status (human readable)");
2313 SYSCTL_ADD_PROC(ctx, globals, OID_AUTO, "active",
2314 CTLFLAG_RD | CTLTYPE_UINT, ntb, 0, sysctl_handle_link_status,
2315 "IU", "Link status (1=active, 0=inactive)");
2316 SYSCTL_ADD_PROC(ctx, globals, OID_AUTO, "admin_up",
2317 CTLFLAG_RW | CTLTYPE_UINT, ntb, 0, sysctl_handle_link_admin,
2318 "IU", "Set/get interface status (1=UP, 0=DOWN)");
2320 tree = SYSCTL_ADD_NODE(ctx, globals, OID_AUTO, "debug_info",
2321 CTLFLAG_RD, NULL, "Driver state, statistics, and HW registers");
2322 tree_par = SYSCTL_CHILDREN(tree);
2324 SYSCTL_ADD_UINT(ctx, tree_par, OID_AUTO, "conn_type", CTLFLAG_RD,
2325 &ntb->conn_type, 0, "0 - Transparent; 1 - B2B; 2 - Root Port");
2326 SYSCTL_ADD_UINT(ctx, tree_par, OID_AUTO, "dev_type", CTLFLAG_RD,
2327 &ntb->dev_type, 0, "0 - USD; 1 - DSD");
2328 SYSCTL_ADD_UINT(ctx, tree_par, OID_AUTO, "ppd", CTLFLAG_RD,
2329 &ntb->ppd, 0, "Raw PPD register (cached)");
2331 if (ntb->b2b_mw_idx != B2B_MW_DISABLED) {
2333 SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "b2b_idx", CTLFLAG_RD,
2334 &ntb->b2b_mw_idx, 0,
2335 "Index of the MW used for B2B remote register access");
2337 SYSCTL_ADD_UQUAD(ctx, tree_par, OID_AUTO, "b2b_off",
2338 CTLFLAG_RD, &ntb->b2b_off,
2339 "If non-zero, offset of B2B register region in shared MW");
2342 SYSCTL_ADD_PROC(ctx, tree_par, OID_AUTO, "features",
2343 CTLFLAG_RD | CTLTYPE_STRING, ntb, 0, sysctl_handle_features, "A",
2344 "Features/errata of this NTB device");
2346 SYSCTL_ADD_UINT(ctx, tree_par, OID_AUTO, "ntb_ctl", CTLFLAG_RD,
2347 __DEVOLATILE(uint32_t *, &ntb->ntb_ctl), 0,
2348 "NTB CTL register (cached)");
2349 SYSCTL_ADD_UINT(ctx, tree_par, OID_AUTO, "lnk_sta", CTLFLAG_RD,
2350 __DEVOLATILE(uint32_t *, &ntb->lnk_sta), 0,
2351 "LNK STA register (cached)");
2354 SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "mw_count", CTLFLAG_RD,
2355 &ntb->mw_count, 0, "MW count");
2356 SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "spad_count", CTLFLAG_RD,
2357 &ntb->spad_count, 0, "Scratchpad count");
2358 SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "db_count", CTLFLAG_RD,
2359 &ntb->db_count, 0, "Doorbell count");
2360 SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "db_vec_count", CTLFLAG_RD,
2361 &ntb->db_vec_count, 0, "Doorbell vector count");
2362 SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "db_vec_shift", CTLFLAG_RD,
2363 &ntb->db_vec_shift, 0, "Doorbell vector shift");
2366 SYSCTL_ADD_UQUAD(ctx, tree_par, OID_AUTO, "db_valid_mask", CTLFLAG_RD,
2367 &ntb->db_valid_mask, "Doorbell valid mask");
2368 SYSCTL_ADD_UQUAD(ctx, tree_par, OID_AUTO, "db_link_mask", CTLFLAG_RD,
2369 &ntb->db_link_mask, "Doorbell link mask");
2370 SYSCTL_ADD_UQUAD(ctx, tree_par, OID_AUTO, "db_mask", CTLFLAG_RD,
2371 &ntb->db_mask, "Doorbell mask (cached)");
2373 tmptree = SYSCTL_ADD_NODE(ctx, tree_par, OID_AUTO, "registers",
2374 CTLFLAG_RD, NULL, "Raw HW registers (big-endian)");
2375 regpar = SYSCTL_CHILDREN(tmptree);
2377 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "ntbcntl",
2378 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, NTB_REG_32 |
2379 ntb->reg->ntb_ctl, sysctl_handle_register, "IU",
2380 "NTB Control register");
2381 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "lnkcap",
2382 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, NTB_REG_32 |
2383 0x19c, sysctl_handle_register, "IU",
2384 "NTB Link Capabilities");
2385 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "lnkcon",
2386 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, NTB_REG_32 |
2387 0x1a0, sysctl_handle_register, "IU",
2388 "NTB Link Control register");
2390 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "db_mask",
2391 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2392 NTB_REG_64 | NTB_DB_READ | ntb->self_reg->db_mask,
2393 sysctl_handle_register, "QU", "Doorbell mask register");
2394 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "db_bell",
2395 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2396 NTB_REG_64 | NTB_DB_READ | ntb->self_reg->db_bell,
2397 sysctl_handle_register, "QU", "Doorbell register");
2399 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_xlat23",
2400 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2401 NTB_REG_64 | ntb->xlat_reg->bar2_xlat,
2402 sysctl_handle_register, "QU", "Incoming XLAT23 register");
2403 if (HAS_FEATURE(ntb, NTB_SPLIT_BAR)) {
2404 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_xlat4",
2405 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2406 NTB_REG_32 | ntb->xlat_reg->bar4_xlat,
2407 sysctl_handle_register, "IU", "Incoming XLAT4 register");
2408 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_xlat5",
2409 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2410 NTB_REG_32 | ntb->xlat_reg->bar5_xlat,
2411 sysctl_handle_register, "IU", "Incoming XLAT5 register");
2413 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_xlat45",
2414 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2415 NTB_REG_64 | ntb->xlat_reg->bar4_xlat,
2416 sysctl_handle_register, "QU", "Incoming XLAT45 register");
2419 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_lmt23",
2420 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2421 NTB_REG_64 | ntb->xlat_reg->bar2_limit,
2422 sysctl_handle_register, "QU", "Incoming LMT23 register");
2423 if (HAS_FEATURE(ntb, NTB_SPLIT_BAR)) {
2424 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_lmt4",
2425 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2426 NTB_REG_32 | ntb->xlat_reg->bar4_limit,
2427 sysctl_handle_register, "IU", "Incoming LMT4 register");
2428 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_lmt5",
2429 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2430 NTB_REG_32 | ntb->xlat_reg->bar5_limit,
2431 sysctl_handle_register, "IU", "Incoming LMT5 register");
2433 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_lmt45",
2434 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2435 NTB_REG_64 | ntb->xlat_reg->bar4_limit,
2436 sysctl_handle_register, "QU", "Incoming LMT45 register");
2439 if (ntb->type == NTB_ATOM)
2442 tmptree = SYSCTL_ADD_NODE(ctx, regpar, OID_AUTO, "xeon_stats",
2443 CTLFLAG_RD, NULL, "Xeon HW statistics");
2444 statpar = SYSCTL_CHILDREN(tmptree);
2445 SYSCTL_ADD_PROC(ctx, statpar, OID_AUTO, "upstream_mem_miss",
2446 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2447 NTB_REG_16 | XEON_USMEMMISS_OFFSET,
2448 sysctl_handle_register, "SU", "Upstream Memory Miss");
2450 tmptree = SYSCTL_ADD_NODE(ctx, regpar, OID_AUTO, "xeon_hw_err",
2451 CTLFLAG_RD, NULL, "Xeon HW errors");
2452 errpar = SYSCTL_CHILDREN(tmptree);
2454 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "ppd",
2455 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2456 NTB_REG_8 | NTB_PCI_REG | NTB_PPD_OFFSET,
2457 sysctl_handle_register, "CU", "PPD");
2459 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "pbar23_sz",
2460 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2461 NTB_REG_8 | NTB_PCI_REG | XEON_PBAR23SZ_OFFSET,
2462 sysctl_handle_register, "CU", "PBAR23 SZ (log2)");
2463 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "pbar4_sz",
2464 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2465 NTB_REG_8 | NTB_PCI_REG | XEON_PBAR4SZ_OFFSET,
2466 sysctl_handle_register, "CU", "PBAR4 SZ (log2)");
2467 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "pbar5_sz",
2468 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2469 NTB_REG_8 | NTB_PCI_REG | XEON_PBAR5SZ_OFFSET,
2470 sysctl_handle_register, "CU", "PBAR5 SZ (log2)");
2472 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar23_sz",
2473 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2474 NTB_REG_8 | NTB_PCI_REG | XEON_SBAR23SZ_OFFSET,
2475 sysctl_handle_register, "CU", "SBAR23 SZ (log2)");
2476 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar4_sz",
2477 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2478 NTB_REG_8 | NTB_PCI_REG | XEON_SBAR4SZ_OFFSET,
2479 sysctl_handle_register, "CU", "SBAR4 SZ (log2)");
2480 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar5_sz",
2481 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2482 NTB_REG_8 | NTB_PCI_REG | XEON_SBAR5SZ_OFFSET,
2483 sysctl_handle_register, "CU", "SBAR5 SZ (log2)");
2485 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "devsts",
2486 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2487 NTB_REG_16 | NTB_PCI_REG | XEON_DEVSTS_OFFSET,
2488 sysctl_handle_register, "SU", "DEVSTS");
2489 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "lnksts",
2490 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2491 NTB_REG_16 | NTB_PCI_REG | XEON_LINK_STATUS_OFFSET,
2492 sysctl_handle_register, "SU", "LNKSTS");
2493 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "slnksts",
2494 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2495 NTB_REG_16 | NTB_PCI_REG | XEON_SLINK_STATUS_OFFSET,
2496 sysctl_handle_register, "SU", "SLNKSTS");
2498 SYSCTL_ADD_PROC(ctx, errpar, OID_AUTO, "uncerrsts",
2499 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2500 NTB_REG_32 | NTB_PCI_REG | XEON_UNCERRSTS_OFFSET,
2501 sysctl_handle_register, "IU", "UNCERRSTS");
2502 SYSCTL_ADD_PROC(ctx, errpar, OID_AUTO, "corerrsts",
2503 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2504 NTB_REG_32 | NTB_PCI_REG | XEON_CORERRSTS_OFFSET,
2505 sysctl_handle_register, "IU", "CORERRSTS");
2507 if (ntb->conn_type != NTB_CONN_B2B)
2510 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_xlat23",
2511 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2512 NTB_REG_64 | ntb->bar_info[NTB_B2B_BAR_1].pbarxlat_off,
2513 sysctl_handle_register, "QU", "Outgoing XLAT23 register");
2514 if (HAS_FEATURE(ntb, NTB_SPLIT_BAR)) {
2515 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_xlat4",
2516 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2517 NTB_REG_32 | ntb->bar_info[NTB_B2B_BAR_2].pbarxlat_off,
2518 sysctl_handle_register, "IU", "Outgoing XLAT4 register");
2519 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_xlat5",
2520 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2521 NTB_REG_32 | ntb->bar_info[NTB_B2B_BAR_3].pbarxlat_off,
2522 sysctl_handle_register, "IU", "Outgoing XLAT5 register");
2524 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_xlat45",
2525 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2526 NTB_REG_64 | ntb->bar_info[NTB_B2B_BAR_2].pbarxlat_off,
2527 sysctl_handle_register, "QU", "Outgoing XLAT45 register");
2530 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_lmt23",
2531 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2532 NTB_REG_64 | XEON_PBAR2LMT_OFFSET,
2533 sysctl_handle_register, "QU", "Outgoing LMT23 register");
2534 if (HAS_FEATURE(ntb, NTB_SPLIT_BAR)) {
2535 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_lmt4",
2536 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2537 NTB_REG_32 | XEON_PBAR4LMT_OFFSET,
2538 sysctl_handle_register, "IU", "Outgoing LMT4 register");
2539 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_lmt5",
2540 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2541 NTB_REG_32 | XEON_PBAR5LMT_OFFSET,
2542 sysctl_handle_register, "IU", "Outgoing LMT5 register");
2544 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_lmt45",
2545 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2546 NTB_REG_64 | XEON_PBAR4LMT_OFFSET,
2547 sysctl_handle_register, "QU", "Outgoing LMT45 register");
2550 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar01_base",
2551 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2552 NTB_REG_64 | ntb->xlat_reg->bar0_base,
2553 sysctl_handle_register, "QU", "Secondary BAR01 base register");
2554 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar23_base",
2555 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2556 NTB_REG_64 | ntb->xlat_reg->bar2_base,
2557 sysctl_handle_register, "QU", "Secondary BAR23 base register");
2558 if (HAS_FEATURE(ntb, NTB_SPLIT_BAR)) {
2559 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar4_base",
2560 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2561 NTB_REG_32 | ntb->xlat_reg->bar4_base,
2562 sysctl_handle_register, "IU",
2563 "Secondary BAR4 base register");
2564 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar5_base",
2565 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2566 NTB_REG_32 | ntb->xlat_reg->bar5_base,
2567 sysctl_handle_register, "IU",
2568 "Secondary BAR5 base register");
2570 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar45_base",
2571 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2572 NTB_REG_64 | ntb->xlat_reg->bar4_base,
2573 sysctl_handle_register, "QU",
2574 "Secondary BAR45 base register");
2579 sysctl_handle_features(SYSCTL_HANDLER_ARGS)
2581 struct ntb_softc *ntb = arg1;
2585 sbuf_new_for_sysctl(&sb, NULL, 256, req);
2587 sbuf_printf(&sb, "%b", ntb->features, NTB_FEATURES_STR);
2588 error = sbuf_finish(&sb);
2591 if (error || !req->newptr)
2597 sysctl_handle_link_admin(SYSCTL_HANDLER_ARGS)
2599 struct ntb_softc *ntb = arg1;
2603 old = ntb_link_enabled(ntb->device);
2605 error = SYSCTL_OUT(req, &old, sizeof(old));
2606 if (error != 0 || req->newptr == NULL)
2609 error = SYSCTL_IN(req, &new, sizeof(new));
2613 ntb_printf(0, "Admin set interface state to '%sabled'\n",
2614 (new != 0)? "en" : "dis");
2617 error = ntb_link_enable(ntb->device, NTB_SPEED_AUTO, NTB_WIDTH_AUTO);
2619 error = ntb_link_disable(ntb->device);
2624 sysctl_handle_link_status_human(SYSCTL_HANDLER_ARGS)
2626 struct ntb_softc *ntb = arg1;
2628 enum ntb_speed speed;
2629 enum ntb_width width;
2632 sbuf_new_for_sysctl(&sb, NULL, 32, req);
2634 if (ntb_link_is_up(ntb->device, &speed, &width))
2635 sbuf_printf(&sb, "up / PCIe Gen %u / Width x%u",
2636 (unsigned)speed, (unsigned)width);
2638 sbuf_printf(&sb, "down");
2640 error = sbuf_finish(&sb);
2643 if (error || !req->newptr)
2649 sysctl_handle_link_status(SYSCTL_HANDLER_ARGS)
2651 struct ntb_softc *ntb = arg1;
2655 res = ntb_link_is_up(ntb->device, NULL, NULL);
2657 error = SYSCTL_OUT(req, &res, sizeof(res));
2658 if (error || !req->newptr)
2664 sysctl_handle_register(SYSCTL_HANDLER_ARGS)
2666 struct ntb_softc *ntb;
2670 char be[sizeof(umv)];
2677 reg = arg2 & ~NTB_REGFLAGS_MASK;
2678 sz = arg2 & NTB_REGSZ_MASK;
2679 db = (arg2 & NTB_DB_READ) != 0;
2680 pci = (arg2 & NTB_PCI_REG) != 0;
2682 KASSERT(!(db && pci), ("bogus"));
2685 KASSERT(sz == NTB_REG_64, ("bogus"));
2686 umv = db_ioread(ntb, reg);
2687 outsz = sizeof(uint64_t);
2692 umv = pci_read_config(ntb->device, reg, 8);
2694 umv = ntb_reg_read(8, reg);
2695 outsz = sizeof(uint64_t);
2699 umv = pci_read_config(ntb->device, reg, 4);
2701 umv = ntb_reg_read(4, reg);
2702 outsz = sizeof(uint32_t);
2706 umv = pci_read_config(ntb->device, reg, 2);
2708 umv = ntb_reg_read(2, reg);
2709 outsz = sizeof(uint16_t);
2713 umv = pci_read_config(ntb->device, reg, 1);
2715 umv = ntb_reg_read(1, reg);
2716 outsz = sizeof(uint8_t);
2724 /* Encode bigendian so that sysctl -x is legible. */
2726 outp = ((char *)be) + sizeof(umv) - outsz;
2728 error = SYSCTL_OUT(req, outp, outsz);
2729 if (error || !req->newptr)
2735 ntb_user_mw_to_idx(struct ntb_softc *ntb, unsigned uidx)
2738 if ((ntb->b2b_mw_idx != B2B_MW_DISABLED && ntb->b2b_off == 0 &&
2739 uidx >= ntb->b2b_mw_idx) ||
2740 (ntb->msix_mw_idx != B2B_MW_DISABLED && uidx >= ntb->msix_mw_idx))
2742 if ((ntb->b2b_mw_idx != B2B_MW_DISABLED && ntb->b2b_off == 0 &&
2743 uidx >= ntb->b2b_mw_idx) &&
2744 (ntb->msix_mw_idx != B2B_MW_DISABLED && uidx >= ntb->msix_mw_idx))
2750 ntb_exchange_msix(void *ctx)
2752 struct ntb_softc *ntb;
2758 if (ntb->peer_msix_good)
2760 if (ntb->peer_msix_done)
2763 for (i = 0; i < XEON_NONLINK_DB_MSIX_BITS; i++) {
2764 ntb_peer_spad_write(ntb->device, NTB_MSIX_DATA0 + i,
2765 ntb->msix_data[i].nmd_data);
2766 ntb_peer_spad_write(ntb->device, NTB_MSIX_OFS0 + i,
2767 ntb->msix_data[i].nmd_ofs - ntb->msix_xlat);
2769 ntb_peer_spad_write(ntb->device, NTB_MSIX_GUARD, NTB_MSIX_VER_GUARD);
2771 ntb_spad_read(ntb->device, NTB_MSIX_GUARD, &val);
2772 if (val != NTB_MSIX_VER_GUARD)
2775 for (i = 0; i < XEON_NONLINK_DB_MSIX_BITS; i++) {
2776 ntb_spad_read(ntb->device, NTB_MSIX_DATA0 + i, &val);
2777 ntb_printf(2, "remote MSIX data(%u): 0x%x\n", i, val);
2778 ntb->peer_msix_data[i].nmd_data = val;
2779 ntb_spad_read(ntb->device, NTB_MSIX_OFS0 + i, &val);
2780 ntb_printf(2, "remote MSIX addr(%u): 0x%x\n", i, val);
2781 ntb->peer_msix_data[i].nmd_ofs = val;
2784 ntb->peer_msix_done = true;
2787 ntb_peer_spad_write(ntb->device, NTB_MSIX_DONE, NTB_MSIX_RECEIVED);
2788 ntb_spad_read(ntb->device, NTB_MSIX_DONE, &val);
2789 if (val != NTB_MSIX_RECEIVED)
2792 ntb->peer_msix_good = true;
2793 /* Give peer time to see our NTB_MSIX_RECEIVED. */
2798 ntb_link_event(ntb->device);
2802 ntb->lnk_sta = pci_read_config(ntb->device, ntb->reg->lnk_sta, 2);
2803 if (_xeon_link_is_up(ntb)) {
2804 callout_reset(&ntb->peer_msix_work,
2805 hz * (ntb->peer_msix_good ? 2 : 1) / 100,
2806 ntb_exchange_msix, ntb);
2808 ntb_spad_clear(ntb->device);
2812 * Public API to the rest of the OS
2816 ntb_spad_count(device_t dev)
2818 struct ntb_softc *ntb = device_get_softc(dev);
2820 return (ntb->spad_count);
2824 ntb_mw_count(device_t dev)
2826 struct ntb_softc *ntb = device_get_softc(dev);
2829 res = ntb->mw_count;
2830 if (ntb->b2b_mw_idx != B2B_MW_DISABLED && ntb->b2b_off == 0)
2832 if (ntb->msix_mw_idx != B2B_MW_DISABLED)
2838 ntb_spad_write(device_t dev, unsigned int idx, uint32_t val)
2840 struct ntb_softc *ntb = device_get_softc(dev);
2842 if (idx >= ntb->spad_count)
2845 ntb_reg_write(4, ntb->self_reg->spad + idx * 4, val);
2851 * Zeros the local scratchpad.
2854 ntb_spad_clear(device_t dev)
2856 struct ntb_softc *ntb = device_get_softc(dev);
2859 for (i = 0; i < ntb->spad_count; i++)
2860 ntb_spad_write(dev, i, 0);
2864 ntb_spad_read(device_t dev, unsigned int idx, uint32_t *val)
2866 struct ntb_softc *ntb = device_get_softc(dev);
2868 if (idx >= ntb->spad_count)
2871 *val = ntb_reg_read(4, ntb->self_reg->spad + idx * 4);
2877 ntb_peer_spad_write(device_t dev, unsigned int idx, uint32_t val)
2879 struct ntb_softc *ntb = device_get_softc(dev);
2881 if (idx >= ntb->spad_count)
2884 if (HAS_FEATURE(ntb, NTB_SDOORBELL_LOCKUP))
2885 ntb_mw_write(4, XEON_SPAD_OFFSET + idx * 4, val);
2887 ntb_reg_write(4, ntb->peer_reg->spad + idx * 4, val);
2893 ntb_peer_spad_read(device_t dev, unsigned int idx, uint32_t *val)
2895 struct ntb_softc *ntb = device_get_softc(dev);
2897 if (idx >= ntb->spad_count)
2900 if (HAS_FEATURE(ntb, NTB_SDOORBELL_LOCKUP))
2901 *val = ntb_mw_read(4, XEON_SPAD_OFFSET + idx * 4);
2903 *val = ntb_reg_read(4, ntb->peer_reg->spad + idx * 4);
2909 ntb_mw_get_range(device_t dev, unsigned mw_idx, vm_paddr_t *base,
2910 caddr_t *vbase, size_t *size, size_t *align, size_t *align_size,
2913 struct ntb_softc *ntb = device_get_softc(dev);
2914 struct ntb_pci_bar_info *bar;
2917 enum ntb_bar bar_num;
2919 if (mw_idx >= ntb_mw_count(dev))
2921 mw_idx = ntb_user_mw_to_idx(ntb, mw_idx);
2923 bar_num = ntb_mw_to_bar(ntb, mw_idx);
2924 bar = &ntb->bar_info[bar_num];
2926 if (mw_idx == ntb->b2b_mw_idx) {
2927 KASSERT(ntb->b2b_off != 0,
2928 ("user shouldn't get non-shared b2b mw"));
2929 bar_b2b_off = ntb->b2b_off;
2932 if (bar_is_64bit(ntb, bar_num))
2933 limit = BUS_SPACE_MAXADDR;
2935 limit = BUS_SPACE_MAXADDR_32BIT;
2938 *base = bar->pbase + bar_b2b_off;
2940 *vbase = bar->vbase + bar_b2b_off;
2942 *size = bar->size - bar_b2b_off;
2945 if (align_size != NULL)
2953 ntb_mw_set_trans(device_t dev, unsigned idx, bus_addr_t addr, size_t size)
2955 struct ntb_softc *ntb = device_get_softc(dev);
2956 struct ntb_pci_bar_info *bar;
2957 uint64_t base, limit, reg_val;
2958 size_t bar_size, mw_size;
2959 uint32_t base_reg, xlat_reg, limit_reg;
2960 enum ntb_bar bar_num;
2962 if (idx >= ntb_mw_count(dev))
2964 idx = ntb_user_mw_to_idx(ntb, idx);
2966 bar_num = ntb_mw_to_bar(ntb, idx);
2967 bar = &ntb->bar_info[bar_num];
2969 bar_size = bar->size;
2970 if (idx == ntb->b2b_mw_idx)
2971 mw_size = bar_size - ntb->b2b_off;
2975 /* Hardware requires that addr is aligned to bar size */
2976 if ((addr & (bar_size - 1)) != 0)
2982 bar_get_xlat_params(ntb, bar_num, &base_reg, &xlat_reg, &limit_reg);
2985 if (bar_is_64bit(ntb, bar_num)) {
2986 base = ntb_reg_read(8, base_reg) & BAR_HIGH_MASK;
2988 if (limit_reg != 0 && size != mw_size)
2989 limit = base + size;
2991 /* Set and verify translation address */
2992 ntb_reg_write(8, xlat_reg, addr);
2993 reg_val = ntb_reg_read(8, xlat_reg) & BAR_HIGH_MASK;
2994 if (reg_val != addr) {
2995 ntb_reg_write(8, xlat_reg, 0);
2999 /* Set and verify the limit */
3000 ntb_reg_write(8, limit_reg, limit);
3001 reg_val = ntb_reg_read(8, limit_reg) & BAR_HIGH_MASK;
3002 if (reg_val != limit) {
3003 ntb_reg_write(8, limit_reg, base);
3004 ntb_reg_write(8, xlat_reg, 0);
3008 /* Configure 32-bit (split) BAR MW */
3010 if ((addr & UINT32_MAX) != addr)
3012 if (((addr + size) & UINT32_MAX) != (addr + size))
3015 base = ntb_reg_read(4, base_reg) & BAR_HIGH_MASK;
3017 if (limit_reg != 0 && size != mw_size)
3018 limit = base + size;
3020 /* Set and verify translation address */
3021 ntb_reg_write(4, xlat_reg, addr);
3022 reg_val = ntb_reg_read(4, xlat_reg) & BAR_HIGH_MASK;
3023 if (reg_val != addr) {
3024 ntb_reg_write(4, xlat_reg, 0);
3028 /* Set and verify the limit */
3029 ntb_reg_write(4, limit_reg, limit);
3030 reg_val = ntb_reg_read(4, limit_reg) & BAR_HIGH_MASK;
3031 if (reg_val != limit) {
3032 ntb_reg_write(4, limit_reg, base);
3033 ntb_reg_write(4, xlat_reg, 0);
3041 ntb_mw_clear_trans(device_t dev, unsigned mw_idx)
3044 return (ntb_mw_set_trans(dev, mw_idx, 0, 0));
3048 ntb_mw_get_wc(device_t dev, unsigned idx, vm_memattr_t *mode)
3050 struct ntb_softc *ntb = device_get_softc(dev);
3051 struct ntb_pci_bar_info *bar;
3053 if (idx >= ntb_mw_count(dev))
3055 idx = ntb_user_mw_to_idx(ntb, idx);
3057 bar = &ntb->bar_info[ntb_mw_to_bar(ntb, idx)];
3058 *mode = bar->map_mode;
3063 ntb_mw_set_wc(device_t dev, unsigned idx, vm_memattr_t mode)
3065 struct ntb_softc *ntb = device_get_softc(dev);
3067 if (idx >= ntb_mw_count(dev))
3070 idx = ntb_user_mw_to_idx(ntb, idx);
3071 return (ntb_mw_set_wc_internal(ntb, idx, mode));
3075 ntb_mw_set_wc_internal(struct ntb_softc *ntb, unsigned idx, vm_memattr_t mode)
3077 struct ntb_pci_bar_info *bar;
3080 bar = &ntb->bar_info[ntb_mw_to_bar(ntb, idx)];
3081 if (bar->map_mode == mode)
3084 rc = pmap_change_attr((vm_offset_t)bar->vbase, bar->size, mode);
3086 bar->map_mode = mode;
3092 ntb_peer_db_set(device_t dev, uint64_t bit)
3094 struct ntb_softc *ntb = device_get_softc(dev);
3096 if (HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP)) {
3097 struct ntb_pci_bar_info *lapic;
3100 lapic = ntb->peer_lapic_bar;
3102 for (i = 0; i < XEON_NONLINK_DB_MSIX_BITS; i++) {
3103 if ((bit & ntb_db_vector_mask(dev, i)) != 0)
3104 bus_space_write_4(lapic->pci_bus_tag,
3105 lapic->pci_bus_handle,
3106 ntb->peer_msix_data[i].nmd_ofs,
3107 ntb->peer_msix_data[i].nmd_data);
3112 if (HAS_FEATURE(ntb, NTB_SDOORBELL_LOCKUP)) {
3113 ntb_mw_write(2, XEON_PDOORBELL_OFFSET, bit);
3117 db_iowrite(ntb, ntb->peer_reg->db_bell, bit);
3121 ntb_peer_db_addr(device_t dev, bus_addr_t *db_addr, vm_size_t *db_size)
3123 struct ntb_softc *ntb = device_get_softc(dev);
3124 struct ntb_pci_bar_info *bar;
3127 KASSERT((db_addr != NULL && db_size != NULL), ("must be non-NULL"));
3129 if (!HAS_FEATURE(ntb, NTB_SDOORBELL_LOCKUP)) {
3130 bar = &ntb->bar_info[NTB_CONFIG_BAR];
3131 regoff = ntb->peer_reg->db_bell;
3133 KASSERT(ntb->b2b_mw_idx != B2B_MW_DISABLED,
3134 ("invalid b2b idx"));
3136 bar = &ntb->bar_info[ntb_mw_to_bar(ntb, ntb->b2b_mw_idx)];
3137 regoff = XEON_PDOORBELL_OFFSET;
3139 KASSERT(bar->pci_bus_tag != X86_BUS_SPACE_IO, ("uh oh"));
3141 /* HACK: Specific to current x86 bus implementation. */
3142 *db_addr = ((uint64_t)bar->pci_bus_handle + regoff);
3143 *db_size = ntb->reg->db_size;
3148 ntb_db_valid_mask(device_t dev)
3150 struct ntb_softc *ntb = device_get_softc(dev);
3152 return (ntb->db_valid_mask);
3156 ntb_db_vector_count(device_t dev)
3158 struct ntb_softc *ntb = device_get_softc(dev);
3160 return (ntb->db_vec_count);
3164 ntb_db_vector_mask(device_t dev, uint32_t vector)
3166 struct ntb_softc *ntb = device_get_softc(dev);
3168 if (vector > ntb->db_vec_count)
3170 return (ntb->db_valid_mask & ntb_vec_mask(ntb, vector));
3174 ntb_link_is_up(device_t dev, enum ntb_speed *speed, enum ntb_width *width)
3176 struct ntb_softc *ntb = device_get_softc(dev);
3179 *speed = ntb_link_sta_speed(ntb);
3181 *width = ntb_link_sta_width(ntb);
3182 return (link_is_up(ntb));
3186 save_bar_parameters(struct ntb_pci_bar_info *bar)
3189 bar->pci_bus_tag = rman_get_bustag(bar->pci_resource);
3190 bar->pci_bus_handle = rman_get_bushandle(bar->pci_resource);
3191 bar->pbase = rman_get_start(bar->pci_resource);
3192 bar->size = rman_get_size(bar->pci_resource);
3193 bar->vbase = rman_get_virtual(bar->pci_resource);
3196 static device_method_t ntb_intel_methods[] = {
3197 /* Device interface */
3198 DEVMETHOD(device_probe, ntb_probe),
3199 DEVMETHOD(device_attach, ntb_attach),
3200 DEVMETHOD(device_detach, ntb_detach),
3202 DEVMETHOD(ntb_link_is_up, ntb_link_is_up),
3203 DEVMETHOD(ntb_link_enable, ntb_link_enable),
3204 DEVMETHOD(ntb_link_disable, ntb_link_disable),
3205 DEVMETHOD(ntb_link_enabled, ntb_link_enabled),
3206 DEVMETHOD(ntb_set_ctx, ntb_set_ctx),
3207 DEVMETHOD(ntb_get_ctx, ntb_get_ctx),
3208 DEVMETHOD(ntb_clear_ctx, ntb_clear_ctx),
3209 DEVMETHOD(ntb_mw_count, ntb_mw_count),
3210 DEVMETHOD(ntb_mw_get_range, ntb_mw_get_range),
3211 DEVMETHOD(ntb_mw_set_trans, ntb_mw_set_trans),
3212 DEVMETHOD(ntb_mw_clear_trans, ntb_mw_clear_trans),
3213 DEVMETHOD(ntb_mw_get_wc, ntb_mw_get_wc),
3214 DEVMETHOD(ntb_mw_set_wc, ntb_mw_set_wc),
3215 DEVMETHOD(ntb_spad_count, ntb_spad_count),
3216 DEVMETHOD(ntb_spad_clear, ntb_spad_clear),
3217 DEVMETHOD(ntb_spad_write, ntb_spad_write),
3218 DEVMETHOD(ntb_spad_read, ntb_spad_read),
3219 DEVMETHOD(ntb_peer_spad_write, ntb_peer_spad_write),
3220 DEVMETHOD(ntb_peer_spad_read, ntb_peer_spad_read),
3221 DEVMETHOD(ntb_db_valid_mask, ntb_db_valid_mask),
3222 DEVMETHOD(ntb_db_vector_count, ntb_db_vector_count),
3223 DEVMETHOD(ntb_db_vector_mask, ntb_db_vector_mask),
3224 DEVMETHOD(ntb_db_clear, ntb_db_clear),
3225 DEVMETHOD(ntb_db_clear_mask, ntb_db_clear_mask),
3226 DEVMETHOD(ntb_db_read, ntb_db_read),
3227 DEVMETHOD(ntb_db_set_mask, ntb_db_set_mask),
3228 DEVMETHOD(ntb_peer_db_addr, ntb_peer_db_addr),
3229 DEVMETHOD(ntb_peer_db_set, ntb_peer_db_set),
3233 static DEFINE_CLASS_0(ntb_hw, ntb_intel_driver, ntb_intel_methods,
3234 sizeof(struct ntb_softc));
3235 DRIVER_MODULE(ntb_intel, pci, ntb_intel_driver, ntb_hw_devclass, NULL, NULL);
3236 MODULE_DEPEND(ntb_intel, ntb, 1, 1, 1);
3237 MODULE_VERSION(ntb_intel, 1);