2 * Copyright (c) 2016 Alexander Motin <mav@FreeBSD.org>
3 * Copyright (C) 2013 Intel Corporation
4 * Copyright (C) 2015 EMC Corporation
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 #define NTB_LINK_STATUS_ACTIVE 0x2000
35 #define NTB_LINK_SPEED_MASK 0x000f
36 #define NTB_LINK_WIDTH_MASK 0x03f0
37 #define NTB_LNK_STA_WIDTH(sta) (((sta) & NTB_LINK_WIDTH_MASK) >> 4)
39 #define XEON_SNB_MW_COUNT 2
40 #define XEON_HSX_SPLIT_MW_COUNT 3
41 /* Reserve the uppermost bit for link interrupt */
42 #define XEON_DB_COUNT 15
43 #define XEON_DB_TOTAL_SHIFT 16
44 #define XEON_DB_LINK 15
45 #define XEON_DB_MSIX_VECTOR_COUNT 4
46 #define XEON_DB_MSIX_VECTOR_SHIFT 5
47 #define XEON_DB_LINK_BIT (1 << XEON_DB_LINK)
48 #define XEON_NONLINK_DB_MSIX_BITS 3
50 #define XEON_SPCICMD_OFFSET 0x0504
51 #define XEON_DEVCTRL_OFFSET 0x0598
52 #define XEON_DEVSTS_OFFSET 0x059a
53 #define XEON_LINK_STATUS_OFFSET 0x01a2
54 #define XEON_SLINK_STATUS_OFFSET 0x05a2
56 #define XEON_PBAR2LMT_OFFSET 0x0000
57 #define XEON_PBAR4LMT_OFFSET 0x0008
58 #define XEON_PBAR5LMT_OFFSET 0x000c
59 #define XEON_PBAR2XLAT_OFFSET 0x0010
60 #define XEON_PBAR4XLAT_OFFSET 0x0018
61 #define XEON_PBAR5XLAT_OFFSET 0x001c
62 #define XEON_SBAR2LMT_OFFSET 0x0020
63 #define XEON_SBAR4LMT_OFFSET 0x0028
64 #define XEON_SBAR5LMT_OFFSET 0x002c
65 #define XEON_SBAR2XLAT_OFFSET 0x0030
66 #define XEON_SBAR4XLAT_OFFSET 0x0038
67 #define XEON_SBAR5XLAT_OFFSET 0x003c
68 #define XEON_SBAR0BASE_OFFSET 0x0040
69 #define XEON_SBAR2BASE_OFFSET 0x0048
70 #define XEON_SBAR4BASE_OFFSET 0x0050
71 #define XEON_SBAR5BASE_OFFSET 0x0054
72 #define XEON_NTBCNTL_OFFSET 0x0058
73 #define XEON_SBDF_OFFSET 0x005c
74 #define XEON_PDOORBELL_OFFSET 0x0060
75 #define XEON_PDBMSK_OFFSET 0x0062
76 #define XEON_SDOORBELL_OFFSET 0x0064
77 #define XEON_SDBMSK_OFFSET 0x0066
78 #define XEON_USMEMMISS_OFFSET 0x0070
79 #define XEON_SPAD_OFFSET 0x0080
80 #define XEON_SPAD_COUNT 16
81 #define XEON_SPADSEMA4_OFFSET 0x00c0
82 #define XEON_WCCNTRL_OFFSET 0x00e0
83 #define XEON_UNCERRSTS_OFFSET 0x014c
84 #define XEON_CORERRSTS_OFFSET 0x0158
85 #define XEON_B2B_SPAD_OFFSET 0x0100
86 #define XEON_B2B_DOORBELL_OFFSET 0x0140
87 #define XEON_B2B_XLAT_OFFSETL 0x0144
88 #define XEON_B2B_XLAT_OFFSETU 0x0148
90 #define ATOM_MW_COUNT 2
91 #define ATOM_DB_COUNT 34
92 #define ATOM_DB_MSIX_VECTOR_COUNT 34
93 #define ATOM_DB_MSIX_VECTOR_SHIFT 1
95 #define ATOM_SPCICMD_OFFSET 0xb004
96 #define ATOM_MBAR23_OFFSET 0xb018
97 #define ATOM_MBAR45_OFFSET 0xb020
98 #define ATOM_DEVCTRL_OFFSET 0xb048
99 #define ATOM_LINK_STATUS_OFFSET 0xb052
100 #define ATOM_ERRCORSTS_OFFSET 0xb110
102 #define ATOM_SBAR2XLAT_OFFSET 0x0008
103 #define ATOM_SBAR4XLAT_OFFSET 0x0010
104 #define ATOM_PDOORBELL_OFFSET 0x0020
105 #define ATOM_PDBMSK_OFFSET 0x0028
106 #define ATOM_NTBCNTL_OFFSET 0x0060
107 #define ATOM_EBDF_OFFSET 0x0064
108 #define ATOM_SPAD_OFFSET 0x0080
109 #define ATOM_SPAD_COUNT 16
110 #define ATOM_SPADSEMA_OFFSET 0x00c0
111 #define ATOM_STKYSPAD_OFFSET 0x00c4
112 #define ATOM_PBAR2XLAT_OFFSET 0x8008
113 #define ATOM_PBAR4XLAT_OFFSET 0x8010
114 #define ATOM_B2B_DOORBELL_OFFSET 0x8020
115 #define ATOM_B2B_SPAD_OFFSET 0x8080
116 #define ATOM_B2B_SPADSEMA_OFFSET 0x80c0
117 #define ATOM_B2B_STKYSPAD_OFFSET 0x80c4
119 #define ATOM_MODPHY_PCSREG4 0x1c004
120 #define ATOM_MODPHY_PCSREG6 0x1c006
122 #define ATOM_IP_BASE 0xc000
123 #define ATOM_DESKEWSTS_OFFSET (ATOM_IP_BASE + 0x3024)
124 #define ATOM_LTSSMERRSTS0_OFFSET (ATOM_IP_BASE + 0x3180)
125 #define ATOM_LTSSMSTATEJMP_OFFSET (ATOM_IP_BASE + 0x3040)
126 #define ATOM_IBSTERRRCRVSTS0_OFFSET (ATOM_IP_BASE + 0x3324)
128 #define ATOM_DESKEWSTS_DBERR (1 << 15)
129 #define ATOM_LTSSMERRSTS0_UNEXPECTEDEI (1 << 20)
130 #define ATOM_LTSSMSTATEJMP_FORCEDETECT (1 << 2)
131 #define ATOM_IBIST_ERR_OFLOW 0x7fff7fff
133 #define NTB_CNTL_CFG_LOCK (1 << 0)
134 #define NTB_CNTL_LINK_DISABLE (1 << 1)
135 #define NTB_CNTL_S2P_BAR23_SNOOP (1 << 2)
136 #define NTB_CNTL_P2S_BAR23_SNOOP (1 << 4)
137 #define NTB_CNTL_S2P_BAR4_SNOOP (1 << 6)
138 #define NTB_CNTL_P2S_BAR4_SNOOP (1 << 8)
139 #define NTB_CNTL_S2P_BAR5_SNOOP (1 << 12)
140 #define NTB_CNTL_P2S_BAR5_SNOOP (1 << 14)
141 #define ATOM_CNTL_LINK_DOWN (1 << 16)
143 #define XEON_PBAR23SZ_OFFSET 0x00d0
144 #define XEON_PBAR45SZ_OFFSET 0x00d1
145 #define XEON_PBAR4SZ_OFFSET 0x00d1
146 #define XEON_PBAR5SZ_OFFSET 0x00d5
147 #define XEON_SBAR23SZ_OFFSET 0x00d2
148 #define XEON_SBAR4SZ_OFFSET 0x00d3
149 #define XEON_SBAR5SZ_OFFSET 0x00d6
150 #define NTB_PPD_OFFSET 0x00d4
151 #define XEON_PPD_CONN_TYPE 0x0003
152 #define XEON_PPD_DEV_TYPE 0x0010
153 #define XEON_PPD_SPLIT_BAR 0x0040
154 #define ATOM_PPD_INIT_LINK 0x0008
155 #define ATOM_PPD_CONN_TYPE 0x0300
156 #define ATOM_PPD_DEV_TYPE 0x1000
158 /* All addresses are in low 32-bit space so 32-bit BARs can function */
159 #define XEON_B2B_BAR0_ADDR 0x1000000000000000ull
160 #define XEON_B2B_BAR2_ADDR64 0x2000000000000000ull
161 #define XEON_B2B_BAR4_ADDR64 0x4000000000000000ull
162 #define XEON_B2B_BAR4_ADDR32 0x20000000ull
163 #define XEON_B2B_BAR5_ADDR32 0x40000000ull
165 /* The peer ntb secondary config space is 32KB fixed size */
166 #define XEON_B2B_MIN_SIZE 0x8000
168 #endif /* _NTB_REGS_H_ */