2 * Copyright (C) 2013 Intel Corporation
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #define NTB_LINK_STATUS_ACTIVE 0x2000
33 #define NTB_LINK_SPEED_MASK 0x000f
34 #define NTB_LINK_WIDTH_MASK 0x03f0
36 #define XEON_SNB_MAX_MW 2
37 #define XEON_HSXSPLIT_MAX_MW 3
38 /* Reserve the uppermost bit for link interrupt */
39 #define XEON_DB_COUNT 15
40 #define XEON_DB_LINK 15
41 #define XEON_DB_MSIX_VECTOR_COUNT 4
42 #define XEON_DB_MSIX_VECTOR_SHIFT 5
43 #define XEON_DB_LINK_BIT (1 << XEON_DB_LINK)
44 #define XEON_SPAD_COUNT 16
46 #define XEON_PCICMD_OFFSET 0x0504
47 #define XEON_DEVCTRL_OFFSET 0x0598
48 #define XEON_LINK_STATUS_OFFSET 0x01a2
49 #define XEON_SLINK_STATUS_OFFSET 0x05a2
51 #define XEON_PBAR2LMT_OFFSET 0x0000
52 #define XEON_PBAR4LMT_OFFSET 0x0008
53 #define XEON_PBAR5LMT_OFFSET 0x000c
54 #define XEON_PBAR2XLAT_OFFSET 0x0010
55 #define XEON_PBAR4XLAT_OFFSET 0x0018
56 #define XEON_PBAR5XLAT_OFFSET 0x001c
57 #define XEON_SBAR2LMT_OFFSET 0x0020
58 #define XEON_SBAR4LMT_OFFSET 0x0028
59 #define XEON_SBAR5LMT_OFFSET 0x002c
60 #define XEON_SBAR2XLAT_OFFSET 0x0030
61 #define XEON_SBAR4XLAT_OFFSET 0x0038
62 #define XEON_SBAR5XLAT_OFFSET 0x003c
63 #define XEON_SBAR0BASE_OFFSET 0x0040
64 #define XEON_SBAR2BASE_OFFSET 0x0048
65 #define XEON_SBAR4BASE_OFFSET 0x0050
66 #define XEON_SBAR5BASE_OFFSET 0x0054
67 #define XEON_NTBCNTL_OFFSET 0x0058
68 #define XEON_SBDF_OFFSET 0x005c
69 #define XEON_PDOORBELL_OFFSET 0x0060
70 #define XEON_PDBMSK_OFFSET 0x0062
71 #define XEON_SDOORBELL_OFFSET 0x0064
72 #define XEON_SDBMSK_OFFSET 0x0066
73 #define XEON_USMEMMISS 0x0070
74 #define XEON_SPAD_OFFSET 0x0080
75 #define XEON_SPADSEMA4_OFFSET 0x00c0
76 #define XEON_WCCNTRL_OFFSET 0x00e0
77 #define XEON_B2B_SPAD_OFFSET 0x0100
78 #define XEON_B2B_DOORBELL_OFFSET 0x0140
79 #define XEON_B2B_XLAT_OFFSETL 0x0144
80 #define XEON_B2B_XLAT_OFFSETU 0x0148
83 #define SOC_DB_COUNT 34
84 #define SOC_DB_MSIX_VECTOR_COUNT 34
85 #define SOC_DB_MSIX_VECTOR_SHIFT 1
86 #define SOC_SPAD_COUNT 16
88 #define SOC_PCICMD_OFFSET 0xb004
89 #define SOC_MBAR23_OFFSET 0xb018
90 #define SOC_MBAR45_OFFSET 0xb020
91 #define SOC_DEVCTRL_OFFSET 0xb048
92 #define SOC_LINK_STATUS_OFFSET 0xb052
93 #define SOC_ERRCORSTS_OFFSET 0xb110
95 #define SOC_SBAR2XLAT_OFFSET 0x0008
96 #define SOC_SBAR4XLAT_OFFSET 0x0010
97 #define SOC_PDOORBELL_OFFSET 0x0020
98 #define SOC_PDBMSK_OFFSET 0x0028
99 #define SOC_NTBCNTL_OFFSET 0x0060
100 #define SOC_EBDF_OFFSET 0x0064
101 #define SOC_SPAD_OFFSET 0x0080
102 #define SOC_SPADSEMA_OFFSET 0x00c0
103 #define SOC_STKYSPAD_OFFSET 0x00c4
104 #define SOC_PBAR2XLAT_OFFSET 0x8008
105 #define SOC_PBAR4XLAT_OFFSET 0x8010
106 #define SOC_B2B_DOORBELL_OFFSET 0x8020
107 #define SOC_B2B_SPAD_OFFSET 0x8080
108 #define SOC_B2B_SPADSEMA_OFFSET 0x80c0
109 #define SOC_B2B_STKYSPAD_OFFSET 0x80c4
111 #define SOC_MODPHY_PCSREG4 0x1c004
112 #define SOC_MODPHY_PCSREG6 0x1c006
114 #define SOC_IP_BASE 0xc000
115 #define SOC_DESKEWSTS_OFFSET (SOC_IP_BASE + 0x3024)
116 #define SOC_LTSSMERRSTS0_OFFSET (SOC_IP_BASE + 0x3180)
117 #define SOC_LTSSMSTATEJMP_OFFSET (SOC_IP_BASE + 0x3040)
118 #define SOC_IBSTERRRCRVSTS0_OFFSET (SOC_IP_BASE + 0x3324)
120 #define SOC_DESKEWSTS_DBERR (1 << 15)
121 #define SOC_LTSSMERRSTS0_UNEXPECTEDEI (1 << 20)
122 #define SOC_LTSSMSTATEJMP_FORCEDETECT (1 << 2)
123 #define SOC_IBIST_ERR_OFLOW 0x7fff7fff
125 #define NTB_CNTL_CFG_LOCK (1 << 0)
126 #define NTB_CNTL_LINK_DISABLE (1 << 1)
127 #define NTB_CNTL_S2P_BAR23_SNOOP (1 << 2)
128 #define NTB_CNTL_P2S_BAR23_SNOOP (1 << 4)
129 #define NTB_CNTL_S2P_BAR4_SNOOP (1 << 6)
130 #define NTB_CNTL_P2S_BAR4_SNOOP (1 << 8)
131 #define NTB_CNTL_S2P_BAR5_SNOOP (1 << 12)
132 #define NTB_CNTL_P2S_BAR5_SNOOP (1 << 14)
133 #define SOC_CNTL_LINK_DOWN (1 << 16)
135 #define XEON_PBAR23SZ_OFFSET 0x00d0
136 #define XEON_PBAR45SZ_OFFSET 0x00d1
137 #define NTB_PPD_OFFSET 0x00d4
138 #define XEON_PPD_CONN_TYPE 0x0003
139 #define XEON_PPD_DEV_TYPE 0x0010
140 #define XEON_PPD_SPLIT_BAR 0x0040
141 #define SOC_PPD_INIT_LINK 0x0008
142 #define SOC_PPD_CONN_TYPE 0x0300
143 #define SOC_PPD_DEV_TYPE 0x1000
145 #define NTB_CONN_TRANSPARENT 0
146 #define NTB_CONN_B2B 1
147 #define NTB_CONN_RP 2
149 #define NTB_DEV_DSD 1
150 #define NTB_DEV_USD 0
152 /* All addresses are in low 32-bit space so 32-bit BARs can function */
153 #define XEON_B2B_BAR0_USD_ADDR 0x2100000cull
154 #define XEON_B2B_BAR2_USD_ADDR 0x4100000cull
155 #define XEON_B2B_BAR4_USD_ADDR 0x8100000cull
156 #define XEON_B2B_BAR5_USD_ADDR 0xa100000cull
157 #define XEON_B2B_BAR0_DSD_ADDR 0x2000000cull
158 #define XEON_B2B_BAR2_DSD_ADDR 0x4000000cull
159 #define XEON_B2B_BAR4_DSD_ADDR 0x8000000cull
160 #define XEON_B2B_BAR5_DSD_ADDR 0xa000000cull
162 /* XEON Shadowed MMIO Space */
163 #define XEON_SHADOW_PDOORBELL_OFFSET 0x60
164 #define XEON_SHADOW_SPAD_OFFSET 0x80
166 #endif /* _NTB_REGS_H_ */