2 * Copyright (C) 2013 Intel Corporation
3 * Copyright (C) 2015 EMC Corporation
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 #define NTB_LINK_STATUS_ACTIVE 0x2000
34 #define NTB_LINK_SPEED_MASK 0x000f
35 #define NTB_LINK_WIDTH_MASK 0x03f0
36 #define NTB_LNK_STA_WIDTH(sta) (((sta) & NTB_LINK_WIDTH_MASK) >> 4)
38 #define XEON_SNB_MW_COUNT 2
39 #define XEON_HSX_SPLIT_MW_COUNT 3
40 /* Reserve the uppermost bit for link interrupt */
41 #define XEON_DB_COUNT 15
42 #define XEON_DB_LINK 15
43 #define XEON_DB_MSIX_VECTOR_COUNT 4
44 #define XEON_DB_MSIX_VECTOR_SHIFT 5
45 #define XEON_DB_LINK_BIT (1 << XEON_DB_LINK)
46 #define XEON_SPAD_COUNT 16
48 #define XEON_PCICMD_OFFSET 0x0504
49 #define XEON_DEVCTRL_OFFSET 0x0598
50 #define XEON_DEVSTS_OFFSET 0x059a
51 #define XEON_LINK_STATUS_OFFSET 0x01a2
52 #define XEON_SLINK_STATUS_OFFSET 0x05a2
54 #define XEON_PBAR2LMT_OFFSET 0x0000
55 #define XEON_PBAR4LMT_OFFSET 0x0008
56 #define XEON_PBAR5LMT_OFFSET 0x000c
57 #define XEON_PBAR2XLAT_OFFSET 0x0010
58 #define XEON_PBAR4XLAT_OFFSET 0x0018
59 #define XEON_PBAR5XLAT_OFFSET 0x001c
60 #define XEON_SBAR2LMT_OFFSET 0x0020
61 #define XEON_SBAR4LMT_OFFSET 0x0028
62 #define XEON_SBAR5LMT_OFFSET 0x002c
63 #define XEON_SBAR2XLAT_OFFSET 0x0030
64 #define XEON_SBAR4XLAT_OFFSET 0x0038
65 #define XEON_SBAR5XLAT_OFFSET 0x003c
66 #define XEON_SBAR0BASE_OFFSET 0x0040
67 #define XEON_SBAR2BASE_OFFSET 0x0048
68 #define XEON_SBAR4BASE_OFFSET 0x0050
69 #define XEON_SBAR5BASE_OFFSET 0x0054
70 #define XEON_NTBCNTL_OFFSET 0x0058
71 #define XEON_SBDF_OFFSET 0x005c
72 #define XEON_PDOORBELL_OFFSET 0x0060
73 #define XEON_PDBMSK_OFFSET 0x0062
74 #define XEON_SDOORBELL_OFFSET 0x0064
75 #define XEON_SDBMSK_OFFSET 0x0066
76 #define XEON_USMEMMISS_OFFSET 0x0070
77 #define XEON_SPAD_OFFSET 0x0080
78 #define XEON_SPADSEMA4_OFFSET 0x00c0
79 #define XEON_WCCNTRL_OFFSET 0x00e0
80 #define XEON_UNCERRSTS_OFFSET 0x014c
81 #define XEON_CORERRSTS_OFFSET 0x0158
82 #define XEON_B2B_SPAD_OFFSET 0x0100
83 #define XEON_B2B_DOORBELL_OFFSET 0x0140
84 #define XEON_B2B_XLAT_OFFSETL 0x0144
85 #define XEON_B2B_XLAT_OFFSETU 0x0148
87 #define ATOM_MW_COUNT 2
88 #define ATOM_DB_COUNT 34
89 #define ATOM_DB_MSIX_VECTOR_COUNT 34
90 #define ATOM_DB_MSIX_VECTOR_SHIFT 1
91 #define ATOM_SPAD_COUNT 16
93 #define ATOM_PCICMD_OFFSET 0xb004
94 #define ATOM_MBAR23_OFFSET 0xb018
95 #define ATOM_MBAR45_OFFSET 0xb020
96 #define ATOM_DEVCTRL_OFFSET 0xb048
97 #define ATOM_LINK_STATUS_OFFSET 0xb052
98 #define ATOM_ERRCORSTS_OFFSET 0xb110
100 #define ATOM_SBAR2XLAT_OFFSET 0x0008
101 #define ATOM_SBAR4XLAT_OFFSET 0x0010
102 #define ATOM_PDOORBELL_OFFSET 0x0020
103 #define ATOM_PDBMSK_OFFSET 0x0028
104 #define ATOM_NTBCNTL_OFFSET 0x0060
105 #define ATOM_EBDF_OFFSET 0x0064
106 #define ATOM_SPAD_OFFSET 0x0080
107 #define ATOM_SPADSEMA_OFFSET 0x00c0
108 #define ATOM_STKYSPAD_OFFSET 0x00c4
109 #define ATOM_PBAR2XLAT_OFFSET 0x8008
110 #define ATOM_PBAR4XLAT_OFFSET 0x8010
111 #define ATOM_B2B_DOORBELL_OFFSET 0x8020
112 #define ATOM_B2B_SPAD_OFFSET 0x8080
113 #define ATOM_B2B_SPADSEMA_OFFSET 0x80c0
114 #define ATOM_B2B_STKYSPAD_OFFSET 0x80c4
116 #define ATOM_MODPHY_PCSREG4 0x1c004
117 #define ATOM_MODPHY_PCSREG6 0x1c006
119 #define ATOM_IP_BASE 0xc000
120 #define ATOM_DESKEWSTS_OFFSET (ATOM_IP_BASE + 0x3024)
121 #define ATOM_LTSSMERRSTS0_OFFSET (ATOM_IP_BASE + 0x3180)
122 #define ATOM_LTSSMSTATEJMP_OFFSET (ATOM_IP_BASE + 0x3040)
123 #define ATOM_IBSTERRRCRVSTS0_OFFSET (ATOM_IP_BASE + 0x3324)
125 #define ATOM_DESKEWSTS_DBERR (1 << 15)
126 #define ATOM_LTSSMERRSTS0_UNEXPECTEDEI (1 << 20)
127 #define ATOM_LTSSMSTATEJMP_FORCEDETECT (1 << 2)
128 #define ATOM_IBIST_ERR_OFLOW 0x7fff7fff
130 #define NTB_CNTL_CFG_LOCK (1 << 0)
131 #define NTB_CNTL_LINK_DISABLE (1 << 1)
132 #define NTB_CNTL_S2P_BAR23_SNOOP (1 << 2)
133 #define NTB_CNTL_P2S_BAR23_SNOOP (1 << 4)
134 #define NTB_CNTL_S2P_BAR4_SNOOP (1 << 6)
135 #define NTB_CNTL_P2S_BAR4_SNOOP (1 << 8)
136 #define NTB_CNTL_S2P_BAR5_SNOOP (1 << 12)
137 #define NTB_CNTL_P2S_BAR5_SNOOP (1 << 14)
138 #define ATOM_CNTL_LINK_DOWN (1 << 16)
140 #define XEON_PBAR23SZ_OFFSET 0x00d0
141 #define XEON_PBAR45SZ_OFFSET 0x00d1
142 #define XEON_PBAR4SZ_OFFSET 0x00d1
143 #define XEON_PBAR5SZ_OFFSET 0x00d5
144 #define XEON_SBAR23SZ_OFFSET 0x00d2
145 #define XEON_SBAR4SZ_OFFSET 0x00d3
146 #define XEON_SBAR5SZ_OFFSET 0x00d6
147 #define NTB_PPD_OFFSET 0x00d4
148 #define XEON_PPD_CONN_TYPE 0x0003
149 #define XEON_PPD_DEV_TYPE 0x0010
150 #define XEON_PPD_SPLIT_BAR 0x0040
151 #define ATOM_PPD_INIT_LINK 0x0008
152 #define ATOM_PPD_CONN_TYPE 0x0300
153 #define ATOM_PPD_DEV_TYPE 0x1000
155 /* All addresses are in low 32-bit space so 32-bit BARs can function */
156 #define XEON_B2B_BAR0_USD_ADDR 0x1000000000000000ull
157 #define XEON_B2B_BAR2_USD_ADDR64 0x2000000000000000ull
158 #define XEON_B2B_BAR4_USD_ADDR64 0x4000000000000000ull
159 #define XEON_B2B_BAR4_USD_ADDR32 0x20000000ull
160 #define XEON_B2B_BAR5_USD_ADDR32 0x40000000ull
161 #define XEON_B2B_BAR0_DSD_ADDR 0x9000000000000000ull
162 #define XEON_B2B_BAR2_DSD_ADDR64 0xa000000000000000ull
163 #define XEON_B2B_BAR4_DSD_ADDR64 0xc000000000000000ull
164 #define XEON_B2B_BAR4_DSD_ADDR32 0xa0000000ull
165 #define XEON_B2B_BAR5_DSD_ADDR32 0xc0000000ull
167 /* The peer ntb secondary config space is 32KB fixed size */
168 #define XEON_B2B_MIN_SIZE 0x8000
170 /* XEON Shadowed MMIO Space */
171 #define XEON_SHADOW_PDOORBELL_OFFSET 0x60
172 #define XEON_SHADOW_SPAD_OFFSET 0x80
174 #endif /* _NTB_REGS_H_ */