2 * Copyright (c) 2005 by David E. O'Brien <obrien@FreeBSD.org>.
3 * Copyright (c) 2003 by Quinton Dolan <q@onthenet.com.au>.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS `AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * $Id: if_nvreg.h,v 1.6 2004/08/12 14:00:05 q Exp $
34 #ifndef NVIDIA_VENDORID
35 #define NVIDIA_VENDORID 0x10DE
38 #define NFORCE_MCPNET1_DEVICEID 0x01C3
39 #define NFORCE_MCPNET2_DEVICEID 0x0066
40 #define NFORCE_MCPNET3_DEVICEID 0x00D6
41 #define NFORCE_MCPNET4_DEVICEID 0x0086
42 #define NFORCE_MCPNET5_DEVICEID 0x008C
43 #define NFORCE_MCPNET6_DEVICEID 0x00E6
44 #define NFORCE_MCPNET7_DEVICEID 0x00DF
45 #define NFORCE_MCPNET8_DEVICEID 0x0056
46 #define NFORCE_MCPNET9_DEVICEID 0x0057
47 #define NFORCE_MCPNET10_DEVICEID 0x0037
48 #define NFORCE_MCPNET11_DEVICEID 0x0038
49 #define NFORCE_MCPNET12_DEVICEID 0x0268
50 #define NFORCE_MCPNET13_DEVICEID 0x0269
54 #define TX_RING_SIZE 64
55 #define RX_RING_SIZE 64
56 #define NV_MAX_FRAGS 32 // match adapter.h:ADAPTER_WRITE_DATA.sElement[]
60 #define NVE_DEBUG 0x0000
61 #define NVE_DEBUG_INIT 0x0001
62 #define NVE_DEBUG_RUNNING 0x0002
63 #define NVE_DEBUG_DEINIT 0x0004
64 #define NVE_DEBUG_IOCTL 0x0008
65 #define NVE_DEBUG_INTERRUPT 0x0010
66 #define NVE_DEBUG_API 0x0020
67 #define NVE_DEBUG_LOCK 0x0040
68 #define NVE_DEBUG_BROKEN 0x0080
69 #define NVE_DEBUG_MII 0x0100
70 #define NVE_DEBUG_ALL 0xFFFF
73 #define DEBUGOUT(level, fmt, args...) if (NVE_DEBUG & level) \
76 #define DEBUGOUT(level, fmt, args...)
79 typedef unsigned long ulong;
81 struct nve_map_buffer {
82 struct mbuf *mbuf; /* mbuf receiving packet */
83 bus_dmamap_t map; /* DMA map */
88 struct nve_map_buffer buf;
90 caddr_t vaddr; /* Virtual memory address */
91 bus_addr_t paddr; /* DMA physical address */
95 struct nve_rx_desc *next;
96 struct nve_map_buffer buf;
103 /* Don't add anything above this structure */
104 TX_INFO_ADAP TxInfoAdap;
105 struct nve_tx_desc *next;
106 struct nve_map_buffer buf;
109 bus_dma_segment_t frags[NV_MAX_FRAGS + 1];
113 struct ifnet *ifp; /* interface info */
114 struct resource *res;
115 struct resource *irq;
122 struct callout stat_callout;
125 bus_space_tag_t sc_st;
126 bus_space_handle_t sc_sh;
133 struct nve_rx_desc *rx_desc;
134 struct nve_tx_desc *tx_desc;
137 u_int16_t rx_ring_full;
138 u_int16_t tx_ring_full;
141 u_int32_t pending_rxs;
142 u_int32_t pending_txs;
146 /* Stuff for dealing with the NVIDIA OS API */
147 struct callout ostimer;
148 PTIMER_FUNC ostimer_func;
149 void *ostimer_params;
153 NV_UINT32 max_frame_size;
156 CMNDATA_OS_ADAPTER adapterdata;
157 unsigned char original_mac_addr[6];
166 #define NVE_LOCK(_sc) mtx_lock(&(_sc)->mtx)
167 #define NVE_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx)
168 #define NVE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->mtx, MA_OWNED)
170 #define IF_Kbps(x) ((x) * 1000) /* kilobits/sec. */
171 #define IF_Mbps(x) (IF_Kbps((x) * 1000)) /* megabits/sec. */
172 #define ETHER_ALIGN 2
174 extern int ADAPTER_ReadPhy (PVOID pContext, ULONG ulPhyAddr, ULONG ulReg, ULONG *pulVal);
175 extern int ADAPTER_WritePhy (PVOID pContext, ULONG ulPhyAddr, ULONG ulReg, ULONG ulVal);
176 extern int ADAPTER_Init (PVOID pContext, USHORT usForcedSpeed, UCHAR ucForceDpx, UCHAR ucForceMode, UINT *puiLinkState);
178 #endif /* _IF_NVEREG_H_ */