sys/dev/nvme/nvme.h

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (C) 2012-2013 Intel Corporation
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  *
  28  * $FreeBSD$
  29  */
  30
  31 #ifndef __NVME_H__
  32 #define __NVME_H__
  33
  34 #ifdef _KERNEL
  35 #include <sys/types.h>
  36 #endif
  37
  38 #include <sys/param.h>
  39 #include <sys/endian.h>
  40
  41 #define NVME_PASSTHROUGH_CMD            _IOWR('n', 0, struct nvme_pt_command)
  42 #define NVME_RESET_CONTROLLER           _IO('n', 1)
  43 #define NVME_GET_NSID                   _IOR('n', 2, struct nvme_get_nsid)
  44 #define NVME_GET_MAX_XFER_SIZE          _IOR('n', 3, uint64_t)
  45
  46 #define NVME_IO_TEST                    _IOWR('n', 100, struct nvme_io_test)
  47 #define NVME_BIO_TEST                   _IOWR('n', 101, struct nvme_io_test)
  48
  49 /*
  50  * Macros to deal with NVME revisions, as defined VS register
  51  */
  52 #define NVME_REV(x, y)                  (((x) << 16) | ((y) << 8))
  53 #define NVME_MAJOR(r)                   (((r) >> 16) & 0xffff)
  54 #define NVME_MINOR(r)                   (((r) >> 8) & 0xff)
  55
  56 /*
  57  * Use to mark a command to apply to all namespaces, or to retrieve global
  58  *  log pages.
  59  */
  60 #define NVME_GLOBAL_NAMESPACE_TAG       ((uint32_t)0xFFFFFFFF)
  61
  62 /* Cap nvme to 1MB transfers driver explodes with larger sizes */
  63 #define NVME_MAX_XFER_SIZE              (maxphys < (1<<20) ? maxphys : (1<<20))
  64
  65 /* Register field definitions */
  66 #define NVME_CAP_LO_REG_MQES_SHIFT                      (0)
  67 #define NVME_CAP_LO_REG_MQES_MASK                       (0xFFFF)
  68 #define NVME_CAP_LO_REG_CQR_SHIFT                       (16)
  69 #define NVME_CAP_LO_REG_CQR_MASK                        (0x1)
  70 #define NVME_CAP_LO_REG_AMS_SHIFT                       (17)
  71 #define NVME_CAP_LO_REG_AMS_MASK                        (0x3)
  72 #define NVME_CAP_LO_REG_TO_SHIFT                        (24)
  73 #define NVME_CAP_LO_REG_TO_MASK                         (0xFF)
  74 #define NVME_CAP_LO_MQES(x) \
  75         (((x) >> NVME_CAP_LO_REG_MQES_SHIFT) & NVME_CAP_LO_REG_MQES_MASK)
  76 #define NVME_CAP_LO_CQR(x) \
  77         (((x) >> NVME_CAP_LO_REG_CQR_SHIFT) & NVME_CAP_LO_REG_CQR_MASK)
  78 #define NVME_CAP_LO_AMS(x) \
  79         (((x) >> NVME_CAP_LO_REG_AMS_SHIFT) & NVME_CAP_LO_REG_AMS_MASK)
  80 #define NVME_CAP_LO_TO(x) \
  81         (((x) >> NVME_CAP_LO_REG_TO_SHIFT) & NVME_CAP_LO_REG_TO_MASK)
  82
  83 #define NVME_CAP_HI_REG_DSTRD_SHIFT                     (0)
  84 #define NVME_CAP_HI_REG_DSTRD_MASK                      (0xF)
  85 #define NVME_CAP_HI_REG_NSSRS_SHIFT                     (4)
  86 #define NVME_CAP_HI_REG_NSSRS_MASK                      (0x1)
  87 #define NVME_CAP_HI_REG_CSS_SHIFT                       (5)
  88 #define NVME_CAP_HI_REG_CSS_MASK                        (0xff)
  89 #define NVME_CAP_HI_REG_CSS_NVM_SHIFT                   (5)
  90 #define NVME_CAP_HI_REG_CSS_NVM_MASK                    (0x1)
  91 #define NVME_CAP_HI_REG_BPS_SHIFT                       (13)
  92 #define NVME_CAP_HI_REG_BPS_MASK                        (0x1)
  93 #define NVME_CAP_HI_REG_MPSMIN_SHIFT                    (16)
  94 #define NVME_CAP_HI_REG_MPSMIN_MASK                     (0xF)
  95 #define NVME_CAP_HI_REG_MPSMAX_SHIFT                    (20)
  96 #define NVME_CAP_HI_REG_MPSMAX_MASK                     (0xF)
  97 #define NVME_CAP_HI_REG_PMRS_SHIFT                      (24)
  98 #define NVME_CAP_HI_REG_PMRS_MASK                       (0x1)
  99 #define NVME_CAP_HI_REG_CMBS_SHIFT                      (25)
 100 #define NVME_CAP_HI_REG_CMBS_MASK                       (0x1)
 101 #define NVME_CAP_HI_DSTRD(x) \
 102         (((x) >> NVME_CAP_HI_REG_DSTRD_SHIFT) & NVME_CAP_HI_REG_DSTRD_MASK)
 103 #define NVME_CAP_HI_NSSRS(x) \
 104         (((x) >> NVME_CAP_HI_REG_NSSRS_SHIFT) & NVME_CAP_HI_REG_NSSRS_MASK)
 105 #define NVME_CAP_HI_CSS(x) \
 106         (((x) >> NVME_CAP_HI_REG_CSS_SHIFT) & NVME_CAP_HI_REG_CSS_MASK)
 107 #define NVME_CAP_HI_CSS_NVM(x) \
 108         (((x) >> NVME_CAP_HI_REG_CSS_NVM_SHIFT) & NVME_CAP_HI_REG_CSS_NVM_MASK)
 109 #define NVME_CAP_HI_BPS(x) \
 110         (((x) >> NVME_CAP_HI_REG_BPS_SHIFT) & NVME_CAP_HI_REG_BPS_MASK)
 111 #define NVME_CAP_HI_MPSMIN(x) \
 112         (((x) >> NVME_CAP_HI_REG_MPSMIN_SHIFT) & NVME_CAP_HI_REG_MPSMIN_MASK)
 113 #define NVME_CAP_HI_MPSMAX(x) \
 114         (((x) >> NVME_CAP_HI_REG_MPSMAX_SHIFT) & NVME_CAP_HI_REG_MPSMAX_MASK)
 115 #define NVME_CAP_HI_PMRS(x) \
 116         (((x) >> NVME_CAP_HI_REG_PMRS_SHIFT) & NVME_CAP_HI_REG_PMRS_MASK)
 117 #define NVME_CAP_HI_CMBS(x) \
 118         (((x) >> NVME_CAP_HI_REG_CMBS_SHIFT) & NVME_CAP_HI_REG_CMBS_MASK)
 119
 120 #define NVME_CC_REG_EN_SHIFT                            (0)
 121 #define NVME_CC_REG_EN_MASK                             (0x1)
 122 #define NVME_CC_REG_CSS_SHIFT                           (4)
 123 #define NVME_CC_REG_CSS_MASK                            (0x7)
 124 #define NVME_CC_REG_MPS_SHIFT                           (7)
 125 #define NVME_CC_REG_MPS_MASK                            (0xF)
 126 #define NVME_CC_REG_AMS_SHIFT                           (11)
 127 #define NVME_CC_REG_AMS_MASK                            (0x7)
 128 #define NVME_CC_REG_SHN_SHIFT                           (14)
 129 #define NVME_CC_REG_SHN_MASK                            (0x3)
 130 #define NVME_CC_REG_IOSQES_SHIFT                        (16)
 131 #define NVME_CC_REG_IOSQES_MASK                         (0xF)
 132 #define NVME_CC_REG_IOCQES_SHIFT                        (20)
 133 #define NVME_CC_REG_IOCQES_MASK                         (0xF)
 134
 135 #define NVME_CSTS_REG_RDY_SHIFT                         (0)
 136 #define NVME_CSTS_REG_RDY_MASK                          (0x1)
 137 #define NVME_CSTS_REG_CFS_SHIFT                         (1)
 138 #define NVME_CSTS_REG_CFS_MASK                          (0x1)
 139 #define NVME_CSTS_REG_SHST_SHIFT                        (2)
 140 #define NVME_CSTS_REG_SHST_MASK                         (0x3)
 141 #define NVME_CSTS_REG_NVSRO_SHIFT                       (4)
 142 #define NVME_CSTS_REG_NVSRO_MASK                        (0x1)
 143 #define NVME_CSTS_REG_PP_SHIFT                          (5)
 144 #define NVME_CSTS_REG_PP_MASK                           (0x1)
 145
 146 #define NVME_CSTS_GET_SHST(csts)                        (((csts) >> NVME_CSTS_REG_SHST_SHIFT) & NVME_CSTS_REG_SHST_MASK)
 147
 148 #define NVME_AQA_REG_ASQS_SHIFT                         (0)
 149 #define NVME_AQA_REG_ASQS_MASK                          (0xFFF)
 150 #define NVME_AQA_REG_ACQS_SHIFT                         (16)
 151 #define NVME_AQA_REG_ACQS_MASK                          (0xFFF)
 152
 153 #define NVME_PMRCAP_REG_RDS_SHIFT                       (3)
 154 #define NVME_PMRCAP_REG_RDS_MASK                        (0x1)
 155 #define NVME_PMRCAP_REG_WDS_SHIFT                       (4)
 156 #define NVME_PMRCAP_REG_WDS_MASK                        (0x1)
 157 #define NVME_PMRCAP_REG_BIR_SHIFT                       (5)
 158 #define NVME_PMRCAP_REG_BIR_MASK                        (0x7)
 159 #define NVME_PMRCAP_REG_PMRTU_SHIFT                     (8)
 160 #define NVME_PMRCAP_REG_PMRTU_MASK                      (0x3)
 161 #define NVME_PMRCAP_REG_PMRWBM_SHIFT                    (10)
 162 #define NVME_PMRCAP_REG_PMRWBM_MASK                     (0xf)
 163 #define NVME_PMRCAP_REG_PMRTO_SHIFT                     (16)
 164 #define NVME_PMRCAP_REG_PMRTO_MASK                      (0xff)
 165 #define NVME_PMRCAP_REG_CMSS_SHIFT                      (24)
 166 #define NVME_PMRCAP_REG_CMSS_MASK                       (0x1)
 167
 168 #define NVME_PMRCAP_RDS(x) \
 169         (((x) >> NVME_PMRCAP_REG_RDS_SHIFT) & NVME_PMRCAP_REG_RDS_MASK)
 170 #define NVME_PMRCAP_WDS(x) \
 171         (((x) >> NVME_PMRCAP_REG_WDS_SHIFT) & NVME_PMRCAP_REG_WDS_MASK)
 172 #define NVME_PMRCAP_BIR(x) \
 173         (((x) >> NVME_PMRCAP_REG_BIR_SHIFT) & NVME_PMRCAP_REG_BIR_MASK)
 174 #define NVME_PMRCAP_PMRTU(x) \
 175         (((x) >> NVME_PMRCAP_REG_PMRTU_SHIFT) & NVME_PMRCAP_REG_PMRTU_MASK)
 176 #define NVME_PMRCAP_PMRWBM(x) \
 177         (((x) >> NVME_PMRCAP_REG_PMRWBM_SHIFT) & NVME_PMRCAP_REG_PMRWBM_MASK)
 178 #define NVME_PMRCAP_PMRTO(x) \
 179         (((x) >> NVME_PMRCAP_REG_PMRTO_SHIFT) & NVME_PMRCAP_REG_PMRTO_MASK)
 180 #define NVME_PMRCAP_CMSS(x) \
 181         (((x) >> NVME_PMRCAP_REG_CMSS_SHIFT) & NVME_PMRCAP_REG_CMSS_MASK)
 182
 183 /* Command field definitions */
 184
 185 #define NVME_CMD_FUSE_SHIFT                             (8)
 186 #define NVME_CMD_FUSE_MASK                              (0x3)
 187
 188 #define NVME_STATUS_P_SHIFT                             (0)
 189 #define NVME_STATUS_P_MASK                              (0x1)
 190 #define NVME_STATUS_SC_SHIFT                            (1)
 191 #define NVME_STATUS_SC_MASK                             (0xFF)
 192 #define NVME_STATUS_SCT_SHIFT                           (9)
 193 #define NVME_STATUS_SCT_MASK                            (0x7)
 194 #define NVME_STATUS_CRD_SHIFT                           (12)
 195 #define NVME_STATUS_CRD_MASK                            (0x3)
 196 #define NVME_STATUS_M_SHIFT                             (14)
 197 #define NVME_STATUS_M_MASK                              (0x1)
 198 #define NVME_STATUS_DNR_SHIFT                           (15)
 199 #define NVME_STATUS_DNR_MASK                            (0x1)
 200
 201 #define NVME_STATUS_GET_P(st)                           (((st) >> NVME_STATUS_P_SHIFT) & NVME_STATUS_P_MASK)
 202 #define NVME_STATUS_GET_SC(st)                          (((st) >> NVME_STATUS_SC_SHIFT) & NVME_STATUS_SC_MASK)
 203 #define NVME_STATUS_GET_SCT(st)                         (((st) >> NVME_STATUS_SCT_SHIFT) & NVME_STATUS_SCT_MASK)
 204 #define NVME_STATUS_GET_M(st)                           (((st) >> NVME_STATUS_M_SHIFT) & NVME_STATUS_M_MASK)
 205 #define NVME_STATUS_GET_DNR(st)                         (((st) >> NVME_STATUS_DNR_SHIFT) & NVME_STATUS_DNR_MASK)
 206
 207 #define NVME_PWR_ST_MPS_SHIFT                           (0)
 208 #define NVME_PWR_ST_MPS_MASK                            (0x1)
 209 #define NVME_PWR_ST_NOPS_SHIFT                          (1)
 210 #define NVME_PWR_ST_NOPS_MASK                           (0x1)
 211 #define NVME_PWR_ST_RRT_SHIFT                           (0)
 212 #define NVME_PWR_ST_RRT_MASK                            (0x1F)
 213 #define NVME_PWR_ST_RRL_SHIFT                           (0)
 214 #define NVME_PWR_ST_RRL_MASK                            (0x1F)
 215 #define NVME_PWR_ST_RWT_SHIFT                           (0)
 216 #define NVME_PWR_ST_RWT_MASK                            (0x1F)
 217 #define NVME_PWR_ST_RWL_SHIFT                           (0)
 218 #define NVME_PWR_ST_RWL_MASK                            (0x1F)
 219 #define NVME_PWR_ST_IPS_SHIFT                           (6)
 220 #define NVME_PWR_ST_IPS_MASK                            (0x3)
 221 #define NVME_PWR_ST_APW_SHIFT                           (0)
 222 #define NVME_PWR_ST_APW_MASK                            (0x7)
 223 #define NVME_PWR_ST_APS_SHIFT                           (6)
 224 #define NVME_PWR_ST_APS_MASK                            (0x3)
 225
 226 /** Controller Multi-path I/O and Namespace Sharing Capabilities */
 227 /* More then one port */
 228 #define NVME_CTRLR_DATA_MIC_MPORTS_SHIFT                (0)
 229 #define NVME_CTRLR_DATA_MIC_MPORTS_MASK                 (0x1)
 230 /* More then one controller */
 231 #define NVME_CTRLR_DATA_MIC_MCTRLRS_SHIFT               (1)
 232 #define NVME_CTRLR_DATA_MIC_MCTRLRS_MASK                (0x1)
 233 /* SR-IOV Virtual Function */
 234 #define NVME_CTRLR_DATA_MIC_SRIOVVF_SHIFT               (2)
 235 #define NVME_CTRLR_DATA_MIC_SRIOVVF_MASK                (0x1)
 236 /* Asymmetric Namespace Access Reporting */
 237 #define NVME_CTRLR_DATA_MIC_ANAR_SHIFT                  (3)
 238 #define NVME_CTRLR_DATA_MIC_ANAR_MASK                   (0x1)
 239
 240 /** OACS - optional admin command support */
 241 /* supports security send/receive commands */
 242 #define NVME_CTRLR_DATA_OACS_SECURITY_SHIFT             (0)
 243 #define NVME_CTRLR_DATA_OACS_SECURITY_MASK              (0x1)
 244 /* supports format nvm command */
 245 #define NVME_CTRLR_DATA_OACS_FORMAT_SHIFT               (1)
 246 #define NVME_CTRLR_DATA_OACS_FORMAT_MASK                (0x1)
 247 /* supports firmware activate/download commands */
 248 #define NVME_CTRLR_DATA_OACS_FIRMWARE_SHIFT             (2)
 249 #define NVME_CTRLR_DATA_OACS_FIRMWARE_MASK              (0x1)
 250 /* supports namespace management commands */
 251 #define NVME_CTRLR_DATA_OACS_NSMGMT_SHIFT               (3)
 252 #define NVME_CTRLR_DATA_OACS_NSMGMT_MASK                (0x1)
 253 /* supports Device Self-test command */
 254 #define NVME_CTRLR_DATA_OACS_SELFTEST_SHIFT             (4)
 255 #define NVME_CTRLR_DATA_OACS_SELFTEST_MASK              (0x1)
 256 /* supports Directives */
 257 #define NVME_CTRLR_DATA_OACS_DIRECTIVES_SHIFT           (5)
 258 #define NVME_CTRLR_DATA_OACS_DIRECTIVES_MASK            (0x1)
 259 /* supports NVMe-MI Send/Receive */
 260 #define NVME_CTRLR_DATA_OACS_NVMEMI_SHIFT               (6)
 261 #define NVME_CTRLR_DATA_OACS_NVMEMI_MASK                (0x1)
 262 /* supports Virtualization Management */
 263 #define NVME_CTRLR_DATA_OACS_VM_SHIFT                   (7)
 264 #define NVME_CTRLR_DATA_OACS_VM_MASK                    (0x1)
 265 /* supports Doorbell Buffer Config */
 266 #define NVME_CTRLR_DATA_OACS_DBBUFFER_SHIFT             (8)
 267 #define NVME_CTRLR_DATA_OACS_DBBUFFER_MASK              (0x1)
 268 /* supports Get LBA Status */
 269 #define NVME_CTRLR_DATA_OACS_GETLBA_SHIFT               (9)
 270 #define NVME_CTRLR_DATA_OACS_GETLBA_MASK                (0x1)
 271
 272 /** firmware updates */
 273 /* first slot is read-only */
 274 #define NVME_CTRLR_DATA_FRMW_SLOT1_RO_SHIFT             (0)
 275 #define NVME_CTRLR_DATA_FRMW_SLOT1_RO_MASK              (0x1)
 276 /* number of firmware slots */
 277 #define NVME_CTRLR_DATA_FRMW_NUM_SLOTS_SHIFT            (1)
 278 #define NVME_CTRLR_DATA_FRMW_NUM_SLOTS_MASK             (0x7)
 279 /* firmware activation without reset */
 280 #define NVME_CTRLR_DATA_FRMW_ACT_WO_RESET_SHIFT         (4)
 281 #define NVME_CTRLR_DATA_FRMW_ACT_WO_RESET_MASK          (0x1)
 282
 283 /** log page attributes */
 284 /* per namespace smart/health log page */
 285 #define NVME_CTRLR_DATA_LPA_NS_SMART_SHIFT              (0)
 286 #define NVME_CTRLR_DATA_LPA_NS_SMART_MASK               (0x1)
 287
 288 /** AVSCC - admin vendor specific command configuration */
 289 /* admin vendor specific commands use spec format */
 290 #define NVME_CTRLR_DATA_AVSCC_SPEC_FORMAT_SHIFT         (0)
 291 #define NVME_CTRLR_DATA_AVSCC_SPEC_FORMAT_MASK          (0x1)
 292
 293 /** Autonomous Power State Transition Attributes */
 294 /* Autonomous Power State Transitions supported */
 295 #define NVME_CTRLR_DATA_APSTA_APST_SUPP_SHIFT           (0)
 296 #define NVME_CTRLR_DATA_APSTA_APST_SUPP_MASK            (0x1)
 297
 298 /** Sanitize Capabilities */
 299 /* Crypto Erase Support  */
 300 #define NVME_CTRLR_DATA_SANICAP_CES_SHIFT               (0)
 301 #define NVME_CTRLR_DATA_SANICAP_CES_MASK                (0x1)
 302 /* Block Erase Support */
 303 #define NVME_CTRLR_DATA_SANICAP_BES_SHIFT               (1)
 304 #define NVME_CTRLR_DATA_SANICAP_BES_MASK                (0x1)
 305 /* Overwrite Support */
 306 #define NVME_CTRLR_DATA_SANICAP_OWS_SHIFT               (2)
 307 #define NVME_CTRLR_DATA_SANICAP_OWS_MASK                (0x1)
 308 /* No-Deallocate Inhibited  */
 309 #define NVME_CTRLR_DATA_SANICAP_NDI_SHIFT               (29)
 310 #define NVME_CTRLR_DATA_SANICAP_NDI_MASK                (0x1)
 311 /* No-Deallocate Modifies Media After Sanitize */
 312 #define NVME_CTRLR_DATA_SANICAP_NODMMAS_SHIFT           (30)
 313 #define NVME_CTRLR_DATA_SANICAP_NODMMAS_MASK            (0x3)
 314 #define NVME_CTRLR_DATA_SANICAP_NODMMAS_UNDEF           (0)
 315 #define NVME_CTRLR_DATA_SANICAP_NODMMAS_NO              (1)
 316 #define NVME_CTRLR_DATA_SANICAP_NODMMAS_YES             (2)
 317
 318 /** submission queue entry size */
 319 #define NVME_CTRLR_DATA_SQES_MIN_SHIFT                  (0)
 320 #define NVME_CTRLR_DATA_SQES_MIN_MASK                   (0xF)
 321 #define NVME_CTRLR_DATA_SQES_MAX_SHIFT                  (4)
 322 #define NVME_CTRLR_DATA_SQES_MAX_MASK                   (0xF)
 323
 324 /** completion queue entry size */
 325 #define NVME_CTRLR_DATA_CQES_MIN_SHIFT                  (0)
 326 #define NVME_CTRLR_DATA_CQES_MIN_MASK                   (0xF)
 327 #define NVME_CTRLR_DATA_CQES_MAX_SHIFT                  (4)
 328 #define NVME_CTRLR_DATA_CQES_MAX_MASK                   (0xF)
 329
 330 /** optional nvm command support */
 331 #define NVME_CTRLR_DATA_ONCS_COMPARE_SHIFT              (0)
 332 #define NVME_CTRLR_DATA_ONCS_COMPARE_MASK               (0x1)
 333 #define NVME_CTRLR_DATA_ONCS_WRITE_UNC_SHIFT            (1)
 334 #define NVME_CTRLR_DATA_ONCS_WRITE_UNC_MASK             (0x1)
 335 #define NVME_CTRLR_DATA_ONCS_DSM_SHIFT                  (2)
 336 #define NVME_CTRLR_DATA_ONCS_DSM_MASK                   (0x1)
 337 #define NVME_CTRLR_DATA_ONCS_WRZERO_SHIFT               (3)
 338 #define NVME_CTRLR_DATA_ONCS_WRZERO_MASK                (0x1)
 339 #define NVME_CTRLR_DATA_ONCS_SAVEFEAT_SHIFT             (4)
 340 #define NVME_CTRLR_DATA_ONCS_SAVEFEAT_MASK              (0x1)
 341 #define NVME_CTRLR_DATA_ONCS_RESERV_SHIFT               (5)
 342 #define NVME_CTRLR_DATA_ONCS_RESERV_MASK                (0x1)
 343 #define NVME_CTRLR_DATA_ONCS_TIMESTAMP_SHIFT            (6)
 344 #define NVME_CTRLR_DATA_ONCS_TIMESTAMP_MASK             (0x1)
 345 #define NVME_CTRLR_DATA_ONCS_VERIFY_SHIFT               (7)
 346 #define NVME_CTRLR_DATA_ONCS_VERIFY_MASK                (0x1)
 347
 348 /** Fused Operation Support */
 349 #define NVME_CTRLR_DATA_FUSES_CNW_SHIFT         (0)
 350 #define NVME_CTRLR_DATA_FUSES_CNW_MASK          (0x1)
 351
 352 /** Format NVM Attributes */
 353 #define NVME_CTRLR_DATA_FNA_FORMAT_ALL_SHIFT            (0)
 354 #define NVME_CTRLR_DATA_FNA_FORMAT_ALL_MASK             (0x1)
 355 #define NVME_CTRLR_DATA_FNA_ERASE_ALL_SHIFT             (1)
 356 #define NVME_CTRLR_DATA_FNA_ERASE_ALL_MASK              (0x1)
 357 #define NVME_CTRLR_DATA_FNA_CRYPTO_ERASE_SHIFT          (2)
 358 #define NVME_CTRLR_DATA_FNA_CRYPTO_ERASE_MASK           (0x1)
 359
 360 /** volatile write cache */
 361 /* volatile write cache present */
 362 #define NVME_CTRLR_DATA_VWC_PRESENT_SHIFT               (0)
 363 #define NVME_CTRLR_DATA_VWC_PRESENT_MASK                (0x1)
 364 /* flush all namespaces supported */
 365 #define NVME_CTRLR_DATA_VWC_ALL_SHIFT                   (1)
 366 #define NVME_CTRLR_DATA_VWC_ALL_MASK                    (0x3)
 367 #define NVME_CTRLR_DATA_VWC_ALL_UNKNOWN                 (0)
 368 #define NVME_CTRLR_DATA_VWC_ALL_NO                      (2)
 369 #define NVME_CTRLR_DATA_VWC_ALL_YES                     (3)
 370
 371 /** namespace features */
 372 /* thin provisioning */
 373 #define NVME_NS_DATA_NSFEAT_THIN_PROV_SHIFT             (0)
 374 #define NVME_NS_DATA_NSFEAT_THIN_PROV_MASK              (0x1)
 375 /* NAWUN, NAWUPF, and NACWU fields are valid */
 376 #define NVME_NS_DATA_NSFEAT_NA_FIELDS_SHIFT             (1)
 377 #define NVME_NS_DATA_NSFEAT_NA_FIELDS_MASK              (0x1)
 378 /* Deallocated or Unwritten Logical Block errors supported */
 379 #define NVME_NS_DATA_NSFEAT_DEALLOC_SHIFT               (2)
 380 #define NVME_NS_DATA_NSFEAT_DEALLOC_MASK                (0x1)
 381 /* NGUID and EUI64 fields are not reusable */
 382 #define NVME_NS_DATA_NSFEAT_NO_ID_REUSE_SHIFT           (3)
 383 #define NVME_NS_DATA_NSFEAT_NO_ID_REUSE_MASK            (0x1)
 384 /* NPWG, NPWA, NPDG, NPDA, and NOWS are valid */
 385 #define NVME_NS_DATA_NSFEAT_NPVALID_SHIFT               (4)
 386 #define NVME_NS_DATA_NSFEAT_NPVALID_MASK                (0x1)
 387
 388 /** formatted lba size */
 389 #define NVME_NS_DATA_FLBAS_FORMAT_SHIFT                 (0)
 390 #define NVME_NS_DATA_FLBAS_FORMAT_MASK                  (0xF)
 391 #define NVME_NS_DATA_FLBAS_EXTENDED_SHIFT               (4)
 392 #define NVME_NS_DATA_FLBAS_EXTENDED_MASK                (0x1)
 393
 394 /** metadata capabilities */
 395 /* metadata can be transferred as part of data prp list */
 396 #define NVME_NS_DATA_MC_EXTENDED_SHIFT                  (0)
 397 #define NVME_NS_DATA_MC_EXTENDED_MASK                   (0x1)
 398 /* metadata can be transferred with separate metadata pointer */
 399 #define NVME_NS_DATA_MC_POINTER_SHIFT                   (1)
 400 #define NVME_NS_DATA_MC_POINTER_MASK                    (0x1)
 401
 402 /** end-to-end data protection capabilities */
 403 /* protection information type 1 */
 404 #define NVME_NS_DATA_DPC_PIT1_SHIFT                     (0)
 405 #define NVME_NS_DATA_DPC_PIT1_MASK                      (0x1)
 406 /* protection information type 2 */
 407 #define NVME_NS_DATA_DPC_PIT2_SHIFT                     (1)
 408 #define NVME_NS_DATA_DPC_PIT2_MASK                      (0x1)
 409 /* protection information type 3 */
 410 #define NVME_NS_DATA_DPC_PIT3_SHIFT                     (2)
 411 #define NVME_NS_DATA_DPC_PIT3_MASK                      (0x1)
 412 /* first eight bytes of metadata */
 413 #define NVME_NS_DATA_DPC_MD_START_SHIFT                 (3)
 414 #define NVME_NS_DATA_DPC_MD_START_MASK                  (0x1)
 415 /* last eight bytes of metadata */
 416 #define NVME_NS_DATA_DPC_MD_END_SHIFT                   (4)
 417 #define NVME_NS_DATA_DPC_MD_END_MASK                    (0x1)
 418
 419 /** end-to-end data protection type settings */
 420 /* protection information type */
 421 #define NVME_NS_DATA_DPS_PIT_SHIFT                      (0)
 422 #define NVME_NS_DATA_DPS_PIT_MASK                       (0x7)
 423 /* 1 == protection info transferred at start of metadata */
 424 /* 0 == protection info transferred at end of metadata */
 425 #define NVME_NS_DATA_DPS_MD_START_SHIFT                 (3)
 426 #define NVME_NS_DATA_DPS_MD_START_MASK                  (0x1)
 427
 428 /** Namespace Multi-path I/O and Namespace Sharing Capabilities */
 429 /* the namespace may be attached to two or more controllers */
 430 #define NVME_NS_DATA_NMIC_MAY_BE_SHARED_SHIFT           (0)
 431 #define NVME_NS_DATA_NMIC_MAY_BE_SHARED_MASK            (0x1)
 432
 433 /** Reservation Capabilities */
 434 /* Persist Through Power Loss */
 435 #define NVME_NS_DATA_RESCAP_PTPL_SHIFT          (0)
 436 #define NVME_NS_DATA_RESCAP_PTPL_MASK           (0x1)
 437 /* supports the Write Exclusive */
 438 #define NVME_NS_DATA_RESCAP_WR_EX_SHIFT         (1)
 439 #define NVME_NS_DATA_RESCAP_WR_EX_MASK          (0x1)
 440 /* supports the Exclusive Access */
 441 #define NVME_NS_DATA_RESCAP_EX_AC_SHIFT         (2)
 442 #define NVME_NS_DATA_RESCAP_EX_AC_MASK          (0x1)
 443 /* supports the Write Exclusive – Registrants Only */
 444 #define NVME_NS_DATA_RESCAP_WR_EX_RO_SHIFT      (3)
 445 #define NVME_NS_DATA_RESCAP_WR_EX_RO_MASK       (0x1)
 446 /* supports the Exclusive Access - Registrants Only */
 447 #define NVME_NS_DATA_RESCAP_EX_AC_RO_SHIFT      (4)
 448 #define NVME_NS_DATA_RESCAP_EX_AC_RO_MASK       (0x1)
 449 /* supports the Write Exclusive – All Registrants */
 450 #define NVME_NS_DATA_RESCAP_WR_EX_AR_SHIFT      (5)
 451 #define NVME_NS_DATA_RESCAP_WR_EX_AR_MASK       (0x1)
 452 /* supports the Exclusive Access - All Registrants */
 453 #define NVME_NS_DATA_RESCAP_EX_AC_AR_SHIFT      (6)
 454 #define NVME_NS_DATA_RESCAP_EX_AC_AR_MASK       (0x1)
 455 /* Ignore Existing Key is used as defined in revision 1.3 or later */
 456 #define NVME_NS_DATA_RESCAP_IEKEY13_SHIFT       (7)
 457 #define NVME_NS_DATA_RESCAP_IEKEY13_MASK        (0x1)
 458
 459 /** Format Progress Indicator */
 460 /* percentage of the Format NVM command that remains to be completed */
 461 #define NVME_NS_DATA_FPI_PERC_SHIFT             (0)
 462 #define NVME_NS_DATA_FPI_PERC_MASK              (0x7f)
 463 /* namespace supports the Format Progress Indicator */
 464 #define NVME_NS_DATA_FPI_SUPP_SHIFT             (7)
 465 #define NVME_NS_DATA_FPI_SUPP_MASK              (0x1)
 466
 467 /** Deallocate Logical Block Features */
 468 /* deallocated logical block read behavior */
 469 #define NVME_NS_DATA_DLFEAT_READ_SHIFT          (0)
 470 #define NVME_NS_DATA_DLFEAT_READ_MASK           (0x07)
 471 #define NVME_NS_DATA_DLFEAT_READ_NR             (0x00)
 472 #define NVME_NS_DATA_DLFEAT_READ_00             (0x01)
 473 #define NVME_NS_DATA_DLFEAT_READ_FF             (0x02)
 474 /* supports the Deallocate bit in the Write Zeroes */
 475 #define NVME_NS_DATA_DLFEAT_DWZ_SHIFT           (3)
 476 #define NVME_NS_DATA_DLFEAT_DWZ_MASK            (0x01)
 477 /* Guard field for deallocated logical blocks is set to the CRC  */
 478 #define NVME_NS_DATA_DLFEAT_GCRC_SHIFT          (4)
 479 #define NVME_NS_DATA_DLFEAT_GCRC_MASK           (0x01)
 480
 481 /** lba format support */
 482 /* metadata size */
 483 #define NVME_NS_DATA_LBAF_MS_SHIFT                      (0)
 484 #define NVME_NS_DATA_LBAF_MS_MASK                       (0xFFFF)
 485 /* lba data size */
 486 #define NVME_NS_DATA_LBAF_LBADS_SHIFT                   (16)
 487 #define NVME_NS_DATA_LBAF_LBADS_MASK                    (0xFF)
 488 /* relative performance */
 489 #define NVME_NS_DATA_LBAF_RP_SHIFT                      (24)
 490 #define NVME_NS_DATA_LBAF_RP_MASK                       (0x3)
 491
 492 enum nvme_critical_warning_state {
 493         NVME_CRIT_WARN_ST_AVAILABLE_SPARE               = 0x1,
 494         NVME_CRIT_WARN_ST_TEMPERATURE                   = 0x2,
 495         NVME_CRIT_WARN_ST_DEVICE_RELIABILITY            = 0x4,
 496         NVME_CRIT_WARN_ST_READ_ONLY                     = 0x8,
 497         NVME_CRIT_WARN_ST_VOLATILE_MEMORY_BACKUP        = 0x10,
 498 };
 499 #define NVME_CRIT_WARN_ST_RESERVED_MASK                 (0xE0)
 500 #define NVME_ASYNC_EVENT_NS_ATTRIBUTE                   (0x100)
 501 #define NVME_ASYNC_EVENT_FW_ACTIVATE                    (0x200)
 502
 503 /* slot for current FW */
 504 #define NVME_FIRMWARE_PAGE_AFI_SLOT_SHIFT               (0)
 505 #define NVME_FIRMWARE_PAGE_AFI_SLOT_MASK                (0x7)
 506
 507 /* Commands Supported and Effects */
 508 #define NVME_CE_PAGE_CSUP_SHIFT                         (0)
 509 #define NVME_CE_PAGE_CSUP_MASK                          (0x1)
 510 #define NVME_CE_PAGE_LBCC_SHIFT                         (1)
 511 #define NVME_CE_PAGE_LBCC_MASK                          (0x1)
 512 #define NVME_CE_PAGE_NCC_SHIFT                          (2)
 513 #define NVME_CE_PAGE_NCC_MASK                           (0x1)
 514 #define NVME_CE_PAGE_NIC_SHIFT                          (3)
 515 #define NVME_CE_PAGE_NIC_MASK                           (0x1)
 516 #define NVME_CE_PAGE_CCC_SHIFT                          (4)
 517 #define NVME_CE_PAGE_CCC_MASK                           (0x1)
 518 #define NVME_CE_PAGE_CSE_SHIFT                          (16)
 519 #define NVME_CE_PAGE_CSE_MASK                           (0x7)
 520 #define NVME_CE_PAGE_UUID_SHIFT                         (19)
 521 #define NVME_CE_PAGE_UUID_MASK                          (0x1)
 522
 523 /* Sanitize Status */
 524 #define NVME_SS_PAGE_SSTAT_STATUS_SHIFT                 (0)
 525 #define NVME_SS_PAGE_SSTAT_STATUS_MASK                  (0x7)
 526 #define NVME_SS_PAGE_SSTAT_STATUS_NEVER                 (0)
 527 #define NVME_SS_PAGE_SSTAT_STATUS_COMPLETED             (1)
 528 #define NVME_SS_PAGE_SSTAT_STATUS_INPROG                (2)
 529 #define NVME_SS_PAGE_SSTAT_STATUS_FAILED                (3)
 530 #define NVME_SS_PAGE_SSTAT_STATUS_COMPLETEDWD           (4)
 531 #define NVME_SS_PAGE_SSTAT_PASSES_SHIFT                 (3)
 532 #define NVME_SS_PAGE_SSTAT_PASSES_MASK                  (0x1f)
 533 #define NVME_SS_PAGE_SSTAT_GDE_SHIFT                    (8)
 534 #define NVME_SS_PAGE_SSTAT_GDE_MASK                     (0x1)
 535
 536 /* CC register SHN field values */
 537 enum shn_value {
 538         NVME_SHN_NORMAL         = 0x1,
 539         NVME_SHN_ABRUPT         = 0x2,
 540 };
 541
 542 /* CSTS register SHST field values */
 543 enum shst_value {
 544         NVME_SHST_NORMAL        = 0x0,
 545         NVME_SHST_OCCURRING     = 0x1,
 546         NVME_SHST_COMPLETE      = 0x2,
 547 };
 548
 549 struct nvme_registers
 550 {
 551         uint32_t        cap_lo; /* controller capabilities */
 552         uint32_t        cap_hi;
 553         uint32_t        vs;     /* version */
 554         uint32_t        intms;  /* interrupt mask set */
 555         uint32_t        intmc;  /* interrupt mask clear */
 556         uint32_t        cc;     /* controller configuration */
 557         uint32_t        reserved1;
 558         uint32_t        csts;   /* controller status */
 559         uint32_t        nssr;   /* NVM Subsystem Reset */
 560         uint32_t        aqa;    /* admin queue attributes */
 561         uint64_t        asq;    /* admin submission queue base addr */
 562         uint64_t        acq;    /* admin completion queue base addr */
 563         uint32_t        cmbloc; /* Controller Memory Buffer Location */
 564         uint32_t        cmbsz;  /* Controller Memory Buffer Size */
 565         uint32_t        bpinfo; /* Boot Partition Information */
 566         uint32_t        bprsel; /* Boot Partition Read Select */
 567         uint64_t        bpmbl;  /* Boot Partition Memory Buffer Location */
 568         uint64_t        cmbmsc; /* Controller Memory Buffer Memory Space Control */
 569         uint32_t        cmbsts; /* Controller Memory Buffer Status */
 570         uint8_t         reserved3[3492]; /* 5Ch - DFFh */
 571         uint32_t        pmrcap; /* Persistent Memory Capabilities */
 572         uint32_t        pmrctl; /* Persistent Memory Region Control */
 573         uint32_t        pmrsts; /* Persistent Memory Region Status */
 574         uint32_t        pmrebs; /* Persistent Memory Region Elasticity Buffer Size */
 575         uint32_t        pmrswtp; /* Persistent Memory Region Sustained Write Throughput */
 576         uint32_t        pmrmsc_lo; /* Persistent Memory Region Controller Memory Space Control */
 577         uint32_t        pmrmsc_hi;
 578         uint8_t         reserved4[484]; /* E1Ch - FFFh */
 579         struct {
 580             uint32_t    sq_tdbl; /* submission queue tail doorbell */
 581             uint32_t    cq_hdbl; /* completion queue head doorbell */
 582         } doorbell[1] __packed;
 583 } __packed;
 584
 585 _Static_assert(sizeof(struct nvme_registers) == 0x1008, "bad size for nvme_registers");
 586
 587 struct nvme_command
 588 {
 589         /* dword 0 */
 590         uint8_t opc;            /* opcode */
 591         uint8_t fuse;           /* fused operation */
 592         uint16_t cid;           /* command identifier */
 593
 594         /* dword 1 */
 595         uint32_t nsid;          /* namespace identifier */
 596
 597         /* dword 2-3 */
 598         uint32_t rsvd2;
 599         uint32_t rsvd3;
 600
 601         /* dword 4-5 */
 602         uint64_t mptr;          /* metadata pointer */
 603
 604         /* dword 6-7 */
 605         uint64_t prp1;          /* prp entry 1 */
 606
 607         /* dword 8-9 */
 608         uint64_t prp2;          /* prp entry 2 */
 609
 610         /* dword 10-15 */
 611         uint32_t cdw10;         /* command-specific */
 612         uint32_t cdw11;         /* command-specific */
 613         uint32_t cdw12;         /* command-specific */
 614         uint32_t cdw13;         /* command-specific */
 615         uint32_t cdw14;         /* command-specific */
 616         uint32_t cdw15;         /* command-specific */
 617 } __packed;
 618
 619 _Static_assert(sizeof(struct nvme_command) == 16 * 4, "bad size for nvme_command");
 620
 621 struct nvme_completion {
 622         /* dword 0 */
 623         uint32_t                cdw0;   /* command-specific */
 624
 625         /* dword 1 */
 626         uint32_t                rsvd1;
 627
 628         /* dword 2 */
 629         uint16_t                sqhd;   /* submission queue head pointer */
 630         uint16_t                sqid;   /* submission queue identifier */
 631
 632         /* dword 3 */
 633         uint16_t                cid;    /* command identifier */
 634         uint16_t                status;
 635 } __packed;
 636
 637 _Static_assert(sizeof(struct nvme_completion) == 4 * 4, "bad size for nvme_completion");
 638
 639 struct nvme_dsm_range {
 640         uint32_t attributes;
 641         uint32_t length;
 642         uint64_t starting_lba;
 643 } __packed;
 644
 645 /* Largest DSM Trim that can be done */
 646 #define NVME_MAX_DSM_TRIM               4096
 647
 648 _Static_assert(sizeof(struct nvme_dsm_range) == 16, "bad size for nvme_dsm_ranage");
 649
 650 /* status code types */
 651 enum nvme_status_code_type {
 652         NVME_SCT_GENERIC                = 0x0,
 653         NVME_SCT_COMMAND_SPECIFIC       = 0x1,
 654         NVME_SCT_MEDIA_ERROR            = 0x2,
 655         NVME_SCT_PATH_RELATED           = 0x3,
 656         /* 0x3-0x6 - reserved */
 657         NVME_SCT_VENDOR_SPECIFIC        = 0x7,
 658 };
 659
 660 /* generic command status codes */
 661 enum nvme_generic_command_status_code {
 662         NVME_SC_SUCCESS                         = 0x00,
 663         NVME_SC_INVALID_OPCODE                  = 0x01,
 664         NVME_SC_INVALID_FIELD                   = 0x02,
 665         NVME_SC_COMMAND_ID_CONFLICT             = 0x03,
 666         NVME_SC_DATA_TRANSFER_ERROR             = 0x04,
 667         NVME_SC_ABORTED_POWER_LOSS              = 0x05,
 668         NVME_SC_INTERNAL_DEVICE_ERROR           = 0x06,
 669         NVME_SC_ABORTED_BY_REQUEST              = 0x07,
 670         NVME_SC_ABORTED_SQ_DELETION             = 0x08,
 671         NVME_SC_ABORTED_FAILED_FUSED            = 0x09,
 672         NVME_SC_ABORTED_MISSING_FUSED           = 0x0a,
 673         NVME_SC_INVALID_NAMESPACE_OR_FORMAT     = 0x0b,
 674         NVME_SC_COMMAND_SEQUENCE_ERROR          = 0x0c,
 675         NVME_SC_INVALID_SGL_SEGMENT_DESCR       = 0x0d,
 676         NVME_SC_INVALID_NUMBER_OF_SGL_DESCR     = 0x0e,
 677         NVME_SC_DATA_SGL_LENGTH_INVALID         = 0x0f,
 678         NVME_SC_METADATA_SGL_LENGTH_INVALID     = 0x10,
 679         NVME_SC_SGL_DESCRIPTOR_TYPE_INVALID     = 0x11,
 680         NVME_SC_INVALID_USE_OF_CMB              = 0x12,
 681         NVME_SC_PRP_OFFET_INVALID               = 0x13,
 682         NVME_SC_ATOMIC_WRITE_UNIT_EXCEEDED      = 0x14,
 683         NVME_SC_OPERATION_DENIED                = 0x15,
 684         NVME_SC_SGL_OFFSET_INVALID              = 0x16,
 685         /* 0x17 - reserved */
 686         NVME_SC_HOST_ID_INCONSISTENT_FORMAT     = 0x18,
 687         NVME_SC_KEEP_ALIVE_TIMEOUT_EXPIRED      = 0x19,
 688         NVME_SC_KEEP_ALIVE_TIMEOUT_INVALID      = 0x1a,
 689         NVME_SC_ABORTED_DUE_TO_PREEMPT          = 0x1b,
 690         NVME_SC_SANITIZE_FAILED                 = 0x1c,
 691         NVME_SC_SANITIZE_IN_PROGRESS            = 0x1d,
 692         NVME_SC_SGL_DATA_BLOCK_GRAN_INVALID     = 0x1e,
 693         NVME_SC_NOT_SUPPORTED_IN_CMB            = 0x1f,
 694         NVME_SC_NAMESPACE_IS_WRITE_PROTECTED    = 0x20,
 695         NVME_SC_COMMAND_INTERRUPTED             = 0x21,
 696         NVME_SC_TRANSIENT_TRANSPORT_ERROR       = 0x22,
 697
 698         NVME_SC_LBA_OUT_OF_RANGE                = 0x80,
 699         NVME_SC_CAPACITY_EXCEEDED               = 0x81,
 700         NVME_SC_NAMESPACE_NOT_READY             = 0x82,
 701         NVME_SC_RESERVATION_CONFLICT            = 0x83,
 702         NVME_SC_FORMAT_IN_PROGRESS              = 0x84,
 703 };
 704
 705 /* command specific status codes */
 706 enum nvme_command_specific_status_code {
 707         NVME_SC_COMPLETION_QUEUE_INVALID        = 0x00,
 708         NVME_SC_INVALID_QUEUE_IDENTIFIER        = 0x01,
 709         NVME_SC_MAXIMUM_QUEUE_SIZE_EXCEEDED     = 0x02,
 710         NVME_SC_ABORT_COMMAND_LIMIT_EXCEEDED    = 0x03,
 711         /* 0x04 - reserved */
 712         NVME_SC_ASYNC_EVENT_REQUEST_LIMIT_EXCEEDED = 0x05,
 713         NVME_SC_INVALID_FIRMWARE_SLOT           = 0x06,
 714         NVME_SC_INVALID_FIRMWARE_IMAGE          = 0x07,
 715         NVME_SC_INVALID_INTERRUPT_VECTOR        = 0x08,
 716         NVME_SC_INVALID_LOG_PAGE                = 0x09,
 717         NVME_SC_INVALID_FORMAT                  = 0x0a,
 718         NVME_SC_FIRMWARE_REQUIRES_RESET         = 0x0b,
 719         NVME_SC_INVALID_QUEUE_DELETION          = 0x0c,
 720         NVME_SC_FEATURE_NOT_SAVEABLE            = 0x0d,
 721         NVME_SC_FEATURE_NOT_CHANGEABLE          = 0x0e,
 722         NVME_SC_FEATURE_NOT_NS_SPECIFIC         = 0x0f,
 723         NVME_SC_FW_ACT_REQUIRES_NVMS_RESET      = 0x10,
 724         NVME_SC_FW_ACT_REQUIRES_RESET           = 0x11,
 725         NVME_SC_FW_ACT_REQUIRES_TIME            = 0x12,
 726         NVME_SC_FW_ACT_PROHIBITED               = 0x13,
 727         NVME_SC_OVERLAPPING_RANGE               = 0x14,
 728         NVME_SC_NS_INSUFFICIENT_CAPACITY        = 0x15,
 729         NVME_SC_NS_ID_UNAVAILABLE               = 0x16,
 730         /* 0x17 - reserved */
 731         NVME_SC_NS_ALREADY_ATTACHED             = 0x18,
 732         NVME_SC_NS_IS_PRIVATE                   = 0x19,
 733         NVME_SC_NS_NOT_ATTACHED                 = 0x1a,
 734         NVME_SC_THIN_PROV_NOT_SUPPORTED         = 0x1b,
 735         NVME_SC_CTRLR_LIST_INVALID              = 0x1c,
 736         NVME_SC_SELT_TEST_IN_PROGRESS           = 0x1d,
 737         NVME_SC_BOOT_PART_WRITE_PROHIB          = 0x1e,
 738         NVME_SC_INVALID_CTRLR_ID                = 0x1f,
 739         NVME_SC_INVALID_SEC_CTRLR_STATE         = 0x20,
 740         NVME_SC_INVALID_NUM_OF_CTRLR_RESRC      = 0x21,
 741         NVME_SC_INVALID_RESOURCE_ID             = 0x22,
 742         NVME_SC_SANITIZE_PROHIBITED_WPMRE       = 0x23,
 743         NVME_SC_ANA_GROUP_ID_INVALID            = 0x24,
 744         NVME_SC_ANA_ATTACH_FAILED               = 0x25,
 745
 746         NVME_SC_CONFLICTING_ATTRIBUTES          = 0x80,
 747         NVME_SC_INVALID_PROTECTION_INFO         = 0x81,
 748         NVME_SC_ATTEMPTED_WRITE_TO_RO_PAGE      = 0x82,
 749 };
 750
 751 /* media error status codes */
 752 enum nvme_media_error_status_code {
 753         NVME_SC_WRITE_FAULTS                    = 0x80,
 754         NVME_SC_UNRECOVERED_READ_ERROR          = 0x81,
 755         NVME_SC_GUARD_CHECK_ERROR               = 0x82,
 756         NVME_SC_APPLICATION_TAG_CHECK_ERROR     = 0x83,
 757         NVME_SC_REFERENCE_TAG_CHECK_ERROR       = 0x84,
 758         NVME_SC_COMPARE_FAILURE                 = 0x85,
 759         NVME_SC_ACCESS_DENIED                   = 0x86,
 760         NVME_SC_DEALLOCATED_OR_UNWRITTEN        = 0x87,
 761 };
 762
 763 /* path related status codes */
 764 enum nvme_path_related_status_code {
 765         NVME_SC_INTERNAL_PATH_ERROR             = 0x00,
 766         NVME_SC_ASYMMETRIC_ACCESS_PERSISTENT_LOSS = 0x01,
 767         NVME_SC_ASYMMETRIC_ACCESS_INACCESSIBLE  = 0x02,
 768         NVME_SC_ASYMMETRIC_ACCESS_TRANSITION    = 0x03,
 769         NVME_SC_CONTROLLER_PATHING_ERROR        = 0x60,
 770         NVME_SC_HOST_PATHING_ERROR              = 0x70,
 771         NVME_SC_COMMAND_ABOTHED_BY_HOST         = 0x71,
 772 };
 773
 774 /* admin opcodes */
 775 enum nvme_admin_opcode {
 776         NVME_OPC_DELETE_IO_SQ                   = 0x00,
 777         NVME_OPC_CREATE_IO_SQ                   = 0x01,
 778         NVME_OPC_GET_LOG_PAGE                   = 0x02,
 779         /* 0x03 - reserved */
 780         NVME_OPC_DELETE_IO_CQ                   = 0x04,
 781         NVME_OPC_CREATE_IO_CQ                   = 0x05,
 782         NVME_OPC_IDENTIFY                       = 0x06,
 783         /* 0x07 - reserved */
 784         NVME_OPC_ABORT                          = 0x08,
 785         NVME_OPC_SET_FEATURES                   = 0x09,
 786         NVME_OPC_GET_FEATURES                   = 0x0a,
 787         /* 0x0b - reserved */
 788         NVME_OPC_ASYNC_EVENT_REQUEST            = 0x0c,
 789         NVME_OPC_NAMESPACE_MANAGEMENT           = 0x0d,
 790         /* 0x0e-0x0f - reserved */
 791         NVME_OPC_FIRMWARE_ACTIVATE              = 0x10,
 792         NVME_OPC_FIRMWARE_IMAGE_DOWNLOAD        = 0x11,
 793         /* 0x12-0x13 - reserved */
 794         NVME_OPC_DEVICE_SELF_TEST               = 0x14,
 795         NVME_OPC_NAMESPACE_ATTACHMENT           = 0x15,
 796         /* 0x16-0x17 - reserved */
 797         NVME_OPC_KEEP_ALIVE                     = 0x18,
 798         NVME_OPC_DIRECTIVE_SEND                 = 0x19,
 799         NVME_OPC_DIRECTIVE_RECEIVE              = 0x1a,
 800         /* 0x1b - reserved */
 801         NVME_OPC_VIRTUALIZATION_MANAGEMENT      = 0x1c,
 802         NVME_OPC_NVME_MI_SEND                   = 0x1d,
 803         NVME_OPC_NVME_MI_RECEIVE                = 0x1e,
 804         /* 0x1f-0x7b - reserved */
 805         NVME_OPC_DOORBELL_BUFFER_CONFIG         = 0x7c,
 806
 807         NVME_OPC_FORMAT_NVM                     = 0x80,
 808         NVME_OPC_SECURITY_SEND                  = 0x81,
 809         NVME_OPC_SECURITY_RECEIVE               = 0x82,
 810         /* 0x83 - reserved */
 811         NVME_OPC_SANITIZE                       = 0x84,
 812         /* 0x85 - reserved */
 813         NVME_OPC_GET_LBA_STATUS                 = 0x86,
 814 };
 815
 816 /* nvme nvm opcodes */
 817 enum nvme_nvm_opcode {
 818         NVME_OPC_FLUSH                          = 0x00,
 819         NVME_OPC_WRITE                          = 0x01,
 820         NVME_OPC_READ                           = 0x02,
 821         /* 0x03 - reserved */
 822         NVME_OPC_WRITE_UNCORRECTABLE            = 0x04,
 823         NVME_OPC_COMPARE                        = 0x05,
 824         /* 0x06-0x07 - reserved */
 825         NVME_OPC_WRITE_ZEROES                   = 0x08,
 826         NVME_OPC_DATASET_MANAGEMENT             = 0x09,
 827         /* 0x0a-0x0b - reserved */
 828         NVME_OPC_VERIFY                         = 0x0c,
 829         NVME_OPC_RESERVATION_REGISTER           = 0x0d,
 830         NVME_OPC_RESERVATION_REPORT             = 0x0e,
 831         /* 0x0f-0x10 - reserved */
 832         NVME_OPC_RESERVATION_ACQUIRE            = 0x11,
 833         /* 0x12-0x14 - reserved */
 834         NVME_OPC_RESERVATION_RELEASE            = 0x15,
 835 };
 836
 837 enum nvme_feature {
 838         /* 0x00 - reserved */
 839         NVME_FEAT_ARBITRATION                   = 0x01,
 840         NVME_FEAT_POWER_MANAGEMENT              = 0x02,
 841         NVME_FEAT_LBA_RANGE_TYPE                = 0x03,
 842         NVME_FEAT_TEMPERATURE_THRESHOLD         = 0x04,
 843         NVME_FEAT_ERROR_RECOVERY                = 0x05,
 844         NVME_FEAT_VOLATILE_WRITE_CACHE          = 0x06,
 845         NVME_FEAT_NUMBER_OF_QUEUES              = 0x07,
 846         NVME_FEAT_INTERRUPT_COALESCING          = 0x08,
 847         NVME_FEAT_INTERRUPT_VECTOR_CONFIGURATION = 0x09,
 848         NVME_FEAT_WRITE_ATOMICITY               = 0x0A,
 849         NVME_FEAT_ASYNC_EVENT_CONFIGURATION     = 0x0B,
 850         NVME_FEAT_AUTONOMOUS_POWER_STATE_TRANSITION = 0x0C,
 851         NVME_FEAT_HOST_MEMORY_BUFFER            = 0x0D,
 852         NVME_FEAT_TIMESTAMP                     = 0x0E,
 853         NVME_FEAT_KEEP_ALIVE_TIMER              = 0x0F,
 854         NVME_FEAT_HOST_CONTROLLED_THERMAL_MGMT  = 0x10,
 855         NVME_FEAT_NON_OP_POWER_STATE_CONFIG     = 0x11,
 856         NVME_FEAT_READ_RECOVERY_LEVEL_CONFIG    = 0x12,
 857         NVME_FEAT_PREDICTABLE_LATENCY_MODE_CONFIG = 0x13,
 858         NVME_FEAT_PREDICTABLE_LATENCY_MODE_WINDOW = 0x14,
 859         NVME_FEAT_LBA_STATUS_INFORMATION_ATTRIBUTES = 0x15,
 860         NVME_FEAT_HOST_BEHAVIOR_SUPPORT         = 0x16,
 861         NVME_FEAT_SANITIZE_CONFIG               = 0x17,
 862         NVME_FEAT_ENDURANCE_GROUP_EVENT_CONFIGURATION = 0x18,
 863         /* 0x19-0x77 - reserved */
 864         /* 0x78-0x7f - NVMe Management Interface */
 865         NVME_FEAT_SOFTWARE_PROGRESS_MARKER      = 0x80,
 866         NVME_FEAT_HOST_IDENTIFIER               = 0x81,
 867         NVME_FEAT_RESERVATION_NOTIFICATION_MASK = 0x82,
 868         NVME_FEAT_RESERVATION_PERSISTENCE       = 0x83,
 869         NVME_FEAT_NAMESPACE_WRITE_PROTECTION_CONFIG = 0x84,
 870         /* 0x85-0xBF - command set specific (reserved) */
 871         /* 0xC0-0xFF - vendor specific */
 872 };
 873
 874 enum nvme_dsm_attribute {
 875         NVME_DSM_ATTR_INTEGRAL_READ             = 0x1,
 876         NVME_DSM_ATTR_INTEGRAL_WRITE            = 0x2,
 877         NVME_DSM_ATTR_DEALLOCATE                = 0x4,
 878 };
 879
 880 enum nvme_activate_action {
 881         NVME_AA_REPLACE_NO_ACTIVATE             = 0x0,
 882         NVME_AA_REPLACE_ACTIVATE                = 0x1,
 883         NVME_AA_ACTIVATE                        = 0x2,
 884 };
 885
 886 struct nvme_power_state {
 887         /** Maximum Power */
 888         uint16_t        mp;                     /* Maximum Power */
 889         uint8_t         ps_rsvd1;
 890         uint8_t         mps_nops;               /* Max Power Scale, Non-Operational State */
 891
 892         uint32_t        enlat;                  /* Entry Latency */
 893         uint32_t        exlat;                  /* Exit Latency */
 894
 895         uint8_t         rrt;                    /* Relative Read Throughput */
 896         uint8_t         rrl;                    /* Relative Read Latency */
 897         uint8_t         rwt;                    /* Relative Write Throughput */
 898         uint8_t         rwl;                    /* Relative Write Latency */
 899
 900         uint16_t        idlp;                   /* Idle Power */
 901         uint8_t         ips;                    /* Idle Power Scale */
 902         uint8_t         ps_rsvd8;
 903
 904         uint16_t        actp;                   /* Active Power */
 905         uint8_t         apw_aps;                /* Active Power Workload, Active Power Scale */
 906         uint8_t         ps_rsvd10[9];
 907 } __packed;
 908
 909 _Static_assert(sizeof(struct nvme_power_state) == 32, "bad size for nvme_power_state");
 910
 911 #define NVME_SERIAL_NUMBER_LENGTH       20
 912 #define NVME_MODEL_NUMBER_LENGTH        40
 913 #define NVME_FIRMWARE_REVISION_LENGTH   8
 914
 915 struct nvme_controller_data {
 916         /* bytes 0-255: controller capabilities and features */
 917
 918         /** pci vendor id */
 919         uint16_t                vid;
 920
 921         /** pci subsystem vendor id */
 922         uint16_t                ssvid;
 923
 924         /** serial number */
 925         uint8_t                 sn[NVME_SERIAL_NUMBER_LENGTH];
 926
 927         /** model number */
 928         uint8_t                 mn[NVME_MODEL_NUMBER_LENGTH];
 929
 930         /** firmware revision */
 931         uint8_t                 fr[NVME_FIRMWARE_REVISION_LENGTH];
 932
 933         /** recommended arbitration burst */
 934         uint8_t                 rab;
 935
 936         /** ieee oui identifier */
 937         uint8_t                 ieee[3];
 938
 939         /** multi-interface capabilities */
 940         uint8_t                 mic;
 941
 942         /** maximum data transfer size */
 943         uint8_t                 mdts;
 944
 945         /** Controller ID */
 946         uint16_t                ctrlr_id;
 947
 948         /** Version */
 949         uint32_t                ver;
 950
 951         /** RTD3 Resume Latency */
 952         uint32_t                rtd3r;
 953
 954         /** RTD3 Enter Latency */
 955         uint32_t                rtd3e;
 956
 957         /** Optional Asynchronous Events Supported */
 958         uint32_t                oaes;   /* bitfield really */
 959
 960         /** Controller Attributes */
 961         uint32_t                ctratt; /* bitfield really */
 962
 963         /** Read Recovery Levels Supported */
 964         uint16_t                rrls;
 965
 966         uint8_t                 reserved1[9];
 967
 968         /** Controller Type */
 969         uint8_t                 cntrltype;
 970
 971         /** FRU Globally Unique Identifier */
 972         uint8_t                 fguid[16];
 973
 974         /** Command Retry Delay Time 1 */
 975         uint16_t                crdt1;
 976
 977         /** Command Retry Delay Time 2 */
 978         uint16_t                crdt2;
 979
 980         /** Command Retry Delay Time 3 */
 981         uint16_t                crdt3;
 982
 983         uint8_t                 reserved2[122];
 984
 985         /* bytes 256-511: admin command set attributes */
 986
 987         /** optional admin command support */
 988         uint16_t                oacs;
 989
 990         /** abort command limit */
 991         uint8_t                 acl;
 992
 993         /** asynchronous event request limit */
 994         uint8_t                 aerl;
 995
 996         /** firmware updates */
 997         uint8_t                 frmw;
 998
 999         /** log page attributes */
1000         uint8_t                 lpa;
1001
1002         /** error log page entries */
1003         uint8_t                 elpe;
1004
1005         /** number of power states supported */
1006         uint8_t                 npss;
1007
1008         /** admin vendor specific command configuration */
1009         uint8_t                 avscc;
1010
1011         /** Autonomous Power State Transition Attributes */
1012         uint8_t                 apsta;
1013
1014         /** Warning Composite Temperature Threshold */
1015         uint16_t                wctemp;
1016
1017         /** Critical Composite Temperature Threshold */
1018         uint16_t                cctemp;
1019
1020         /** Maximum Time for Firmware Activation */
1021         uint16_t                mtfa;
1022
1023         /** Host Memory Buffer Preferred Size */
1024         uint32_t                hmpre;
1025
1026         /** Host Memory Buffer Minimum Size */
1027         uint32_t                hmmin;
1028
1029         /** Name space capabilities  */
1030         struct {
1031                 /* if nsmgmt, report tnvmcap and unvmcap */
1032                 uint8_t    tnvmcap[16];
1033                 uint8_t    unvmcap[16];
1034         } __packed untncap;
1035
1036         /** Replay Protected Memory Block Support */
1037         uint32_t                rpmbs; /* Really a bitfield */
1038
1039         /** Extended Device Self-test Time */
1040         uint16_t                edstt;
1041
1042         /** Device Self-test Options */
1043         uint8_t                 dsto; /* Really a bitfield */
1044
1045         /** Firmware Update Granularity */
1046         uint8_t                 fwug;
1047
1048         /** Keep Alive Support */
1049         uint16_t                kas;
1050
1051         /** Host Controlled Thermal Management Attributes */
1052         uint16_t                hctma; /* Really a bitfield */
1053
1054         /** Minimum Thermal Management Temperature */
1055         uint16_t                mntmt;
1056
1057         /** Maximum Thermal Management Temperature */
1058         uint16_t                mxtmt;
1059
1060         /** Sanitize Capabilities */
1061         uint32_t                sanicap; /* Really a bitfield */
1062
1063         /** Host Memory Buffer Minimum Descriptor Entry Size */
1064         uint32_t                hmminds;
1065
1066         /** Host Memory Maximum Descriptors Entries */
1067         uint16_t                hmmaxd;
1068
1069         /** NVM Set Identifier Maximum */
1070         uint16_t                nsetidmax;
1071
1072         /** Endurance Group Identifier Maximum */
1073         uint16_t                endgidmax;
1074
1075         /** ANA Transition Time */
1076         uint8_t                 anatt;
1077
1078         /** Asymmetric Namespace Access Capabilities */
1079         uint8_t                 anacap;
1080
1081         /** ANA Group Identifier Maximum */
1082         uint32_t                anagrpmax;
1083
1084         /** Number of ANA Group Identifiers */
1085         uint32_t                nanagrpid;
1086
1087         /** Persistent Event Log Size */
1088         uint32_t                pels;
1089
1090         uint8_t                 reserved3[156];
1091         /* bytes 512-703: nvm command set attributes */
1092
1093         /** submission queue entry size */
1094         uint8_t                 sqes;
1095
1096         /** completion queue entry size */
1097         uint8_t                 cqes;
1098
1099         /** Maximum Outstanding Commands */
1100         uint16_t                maxcmd;
1101
1102         /** number of namespaces */
1103         uint32_t                nn;
1104
1105         /** optional nvm command support */
1106         uint16_t                oncs;
1107
1108         /** fused operation support */
1109         uint16_t                fuses;
1110
1111         /** format nvm attributes */
1112         uint8_t                 fna;
1113
1114         /** volatile write cache */
1115         uint8_t                 vwc;
1116
1117         /** Atomic Write Unit Normal */
1118         uint16_t                awun;
1119
1120         /** Atomic Write Unit Power Fail */
1121         uint16_t                awupf;
1122
1123         /** NVM Vendor Specific Command Configuration */
1124         uint8_t                 nvscc;
1125
1126         /** Namespace Write Protection Capabilities */
1127         uint8_t                 nwpc;
1128
1129         /** Atomic Compare & Write Unit */
1130         uint16_t                acwu;
1131         uint16_t                reserved6;
1132
1133         /** SGL Support */
1134         uint32_t                sgls;
1135
1136         /** Maximum Number of Allowed Namespaces */
1137         uint32_t                mnan;
1138
1139         /* bytes 540-767: Reserved */
1140         uint8_t                 reserved7[224];
1141
1142         /** NVM Subsystem NVMe Qualified Name */
1143         uint8_t                 subnqn[256];
1144
1145         /* bytes 1024-1791: Reserved */
1146         uint8_t                 reserved8[768];
1147
1148         /* bytes 1792-2047: NVMe over Fabrics specification */
1149         uint8_t                 reserved9[256];
1150
1151         /* bytes 2048-3071: power state descriptors */
1152         struct nvme_power_state power_state[32];
1153
1154         /* bytes 3072-4095: vendor specific */
1155         uint8_t                 vs[1024];
1156 } __packed __aligned(4);
1157
1158 _Static_assert(sizeof(struct nvme_controller_data) == 4096, "bad size for nvme_controller_data");
1159
1160 struct nvme_namespace_data {
1161         /** namespace size */
1162         uint64_t                nsze;
1163
1164         /** namespace capacity */
1165         uint64_t                ncap;
1166
1167         /** namespace utilization */
1168         uint64_t                nuse;
1169
1170         /** namespace features */
1171         uint8_t                 nsfeat;
1172
1173         /** number of lba formats */
1174         uint8_t                 nlbaf;
1175
1176         /** formatted lba size */
1177         uint8_t                 flbas;
1178
1179         /** metadata capabilities */
1180         uint8_t                 mc;
1181
1182         /** end-to-end data protection capabilities */
1183         uint8_t                 dpc;
1184
1185         /** end-to-end data protection type settings */
1186         uint8_t                 dps;
1187
1188         /** Namespace Multi-path I/O and Namespace Sharing Capabilities */
1189         uint8_t                 nmic;
1190
1191         /** Reservation Capabilities */
1192         uint8_t                 rescap;
1193
1194         /** Format Progress Indicator */
1195         uint8_t                 fpi;
1196
1197         /** Deallocate Logical Block Features */
1198         uint8_t                 dlfeat;
1199
1200         /** Namespace Atomic Write Unit Normal  */
1201         uint16_t                nawun;
1202
1203         /** Namespace Atomic Write Unit Power Fail */
1204         uint16_t                nawupf;
1205
1206         /** Namespace Atomic Compare & Write Unit */
1207         uint16_t                nacwu;
1208
1209         /** Namespace Atomic Boundary Size Normal */
1210         uint16_t                nabsn;
1211
1212         /** Namespace Atomic Boundary Offset */
1213         uint16_t                nabo;
1214
1215         /** Namespace Atomic Boundary Size Power Fail */
1216         uint16_t                nabspf;
1217
1218         /** Namespace Optimal IO Boundary */
1219         uint16_t                noiob;
1220
1221         /** NVM Capacity */
1222         uint8_t                 nvmcap[16];
1223
1224         /** Namespace Preferred Write Granularity  */
1225         uint16_t                npwg;
1226
1227         /** Namespace Preferred Write Alignment */
1228         uint16_t                npwa;
1229
1230         /** Namespace Preferred Deallocate Granularity */
1231         uint16_t                npdg;
1232
1233         /** Namespace Preferred Deallocate Alignment */
1234         uint16_t                npda;
1235
1236         /** Namespace Optimal Write Size */
1237         uint16_t                nows;
1238
1239         /* bytes 74-91: Reserved */
1240         uint8_t                 reserved5[18];
1241
1242         /** ANA Group Identifier */
1243         uint32_t                anagrpid;
1244
1245         /* bytes 96-98: Reserved */
1246         uint8_t                 reserved6[3];
1247
1248         /** Namespace Attributes */
1249         uint8_t                 nsattr;
1250
1251         /** NVM Set Identifier */
1252         uint16_t                nvmsetid;
1253
1254         /** Endurance Group Identifier */
1255         uint16_t                endgid;
1256
1257         /** Namespace Globally Unique Identifier */
1258         uint8_t                 nguid[16];
1259
1260         /** IEEE Extended Unique Identifier */
1261         uint8_t                 eui64[8];
1262
1263         /** lba format support */
1264         uint32_t                lbaf[16];
1265
1266         uint8_t                 reserved7[192];
1267
1268         uint8_t                 vendor_specific[3712];
1269 } __packed __aligned(4);
1270
1271 _Static_assert(sizeof(struct nvme_namespace_data) == 4096, "bad size for nvme_namepsace_data");
1272
1273 enum nvme_log_page {
1274         /* 0x00 - reserved */
1275         NVME_LOG_ERROR                  = 0x01,
1276         NVME_LOG_HEALTH_INFORMATION     = 0x02,
1277         NVME_LOG_FIRMWARE_SLOT          = 0x03,
1278         NVME_LOG_CHANGED_NAMESPACE      = 0x04,
1279         NVME_LOG_COMMAND_EFFECT         = 0x05,
1280         NVME_LOG_DEVICE_SELF_TEST       = 0x06,
1281         NVME_LOG_TELEMETRY_HOST_INITIATED = 0x07,
1282         NVME_LOG_TELEMETRY_CONTROLLER_INITIATED = 0x08,
1283         NVME_LOG_ENDURANCE_GROUP_INFORMATION = 0x09,
1284         NVME_LOG_PREDICTABLE_LATENCY_PER_NVM_SET = 0x0a,
1285         NVME_LOG_PREDICTABLE_LATENCY_EVENT_AGGREGATE = 0x0b,
1286         NVME_LOG_ASYMMETRIC_NAMESPAVE_ACCESS = 0x0c,
1287         NVME_LOG_PERSISTENT_EVENT_LOG   = 0x0d,
1288         NVME_LOG_LBA_STATUS_INFORMATION = 0x0e,
1289         NVME_LOG_ENDURANCE_GROUP_EVENT_AGGREGATE = 0x0f,
1290         /* 0x06-0x7F - reserved */
1291         /* 0x80-0xBF - I/O command set specific */
1292         NVME_LOG_RES_NOTIFICATION       = 0x80,
1293         NVME_LOG_SANITIZE_STATUS        = 0x81,
1294         /* 0x82-0xBF - reserved */
1295         /* 0xC0-0xFF - vendor specific */
1296
1297         /*
1298          * The following are Intel Specific log pages, but they seem
1299          * to be widely implemented.
1300          */
1301         INTEL_LOG_READ_LAT_LOG          = 0xc1,
1302         INTEL_LOG_WRITE_LAT_LOG         = 0xc2,
1303         INTEL_LOG_TEMP_STATS            = 0xc5,
1304         INTEL_LOG_ADD_SMART             = 0xca,
1305         INTEL_LOG_DRIVE_MKT_NAME        = 0xdd,
1306
1307         /*
1308          * HGST log page, with lots ofs sub pages.
1309          */
1310         HGST_INFO_LOG                   = 0xc1,
1311 };
1312
1313 struct nvme_error_information_entry {
1314         uint64_t                error_count;
1315         uint16_t                sqid;
1316         uint16_t                cid;
1317         uint16_t                status;
1318         uint16_t                error_location;
1319         uint64_t                lba;
1320         uint32_t                nsid;
1321         uint8_t                 vendor_specific;
1322         uint8_t                 trtype;
1323         uint16_t                reserved30;
1324         uint64_t                csi;
1325         uint16_t                ttsi;
1326         uint8_t                 reserved[22];
1327 } __packed __aligned(4);
1328
1329 _Static_assert(sizeof(struct nvme_error_information_entry) == 64, "bad size for nvme_error_information_entry");
1330
1331 struct nvme_health_information_page {
1332         uint8_t                 critical_warning;
1333         uint16_t                temperature;
1334         uint8_t                 available_spare;
1335         uint8_t                 available_spare_threshold;
1336         uint8_t                 percentage_used;
1337
1338         uint8_t                 reserved[26];
1339
1340         /*
1341          * Note that the following are 128-bit values, but are
1342          *  defined as an array of 2 64-bit values.
1343          */
1344         /* Data Units Read is always in 512-byte units. */
1345         uint64_t                data_units_read[2];
1346         /* Data Units Written is always in 512-byte units. */
1347         uint64_t                data_units_written[2];
1348         /* For NVM command set, this includes Compare commands. */
1349         uint64_t                host_read_commands[2];
1350         uint64_t                host_write_commands[2];
1351         /* Controller Busy Time is reported in minutes. */
1352         uint64_t                controller_busy_time[2];
1353         uint64_t                power_cycles[2];
1354         uint64_t                power_on_hours[2];
1355         uint64_t                unsafe_shutdowns[2];
1356         uint64_t                media_errors[2];
1357         uint64_t                num_error_info_log_entries[2];
1358         uint32_t                warning_temp_time;
1359         uint32_t                error_temp_time;
1360         uint16_t                temp_sensor[8];
1361         /* Thermal Management Temperature 1 Transition Count */
1362         uint32_t                tmt1tc;
1363         /* Thermal Management Temperature 2 Transition Count */
1364         uint32_t                tmt2tc;
1365         /* Total Time For Thermal Management Temperature 1 */
1366         uint32_t                ttftmt1;
1367         /* Total Time For Thermal Management Temperature 2 */
1368         uint32_t                ttftmt2;
1369
1370         uint8_t                 reserved2[280];
1371 } __packed __aligned(4);
1372
1373 _Static_assert(sizeof(struct nvme_health_information_page) == 512, "bad size for nvme_health_information_page");
1374
1375 struct nvme_firmware_page {
1376         uint8_t                 afi;
1377         uint8_t                 reserved[7];
1378         uint64_t                revision[7]; /* revisions for 7 slots */
1379         uint8_t                 reserved2[448];
1380 } __packed __aligned(4);
1381
1382 _Static_assert(sizeof(struct nvme_firmware_page) == 512, "bad size for nvme_firmware_page");
1383
1384 struct nvme_ns_list {
1385         uint32_t                ns[1024];
1386 } __packed __aligned(4);
1387
1388 _Static_assert(sizeof(struct nvme_ns_list) == 4096, "bad size for nvme_ns_list");
1389
1390 struct nvme_command_effects_page {
1391         uint32_t                acs[256];
1392         uint32_t                iocs[256];
1393         uint8_t                 reserved[2048];
1394 } __packed __aligned(4);
1395
1396 _Static_assert(sizeof(struct nvme_command_effects_page) == 4096,
1397     "bad size for nvme_command_effects_page");
1398
1399 struct nvme_res_notification_page {
1400         uint64_t                log_page_count;
1401         uint8_t                 log_page_type;
1402         uint8_t                 available_log_pages;
1403         uint8_t                 reserved2;
1404         uint32_t                nsid;
1405         uint8_t                 reserved[48];
1406 } __packed __aligned(4);
1407
1408 _Static_assert(sizeof(struct nvme_res_notification_page) == 64,
1409     "bad size for nvme_res_notification_page");
1410
1411 struct nvme_sanitize_status_page {
1412         uint16_t                sprog;
1413         uint16_t                sstat;
1414         uint32_t                scdw10;
1415         uint32_t                etfo;
1416         uint32_t                etfbe;
1417         uint32_t                etfce;
1418         uint32_t                etfownd;
1419         uint32_t                etfbewnd;
1420         uint32_t                etfcewnd;
1421         uint8_t                 reserved[480];
1422 } __packed __aligned(4);
1423
1424 _Static_assert(sizeof(struct nvme_sanitize_status_page) == 512,
1425     "bad size for nvme_sanitize_status_page");
1426
1427 struct intel_log_temp_stats
1428 {
1429         uint64_t        current;
1430         uint64_t        overtemp_flag_last;
1431         uint64_t        overtemp_flag_life;
1432         uint64_t        max_temp;
1433         uint64_t        min_temp;
1434         uint64_t        _rsvd[5];
1435         uint64_t        max_oper_temp;
1436         uint64_t        min_oper_temp;
1437         uint64_t        est_offset;
1438 } __packed __aligned(4);
1439
1440 _Static_assert(sizeof(struct intel_log_temp_stats) == 13 * 8, "bad size for intel_log_temp_stats");
1441
1442 struct nvme_resv_reg_ctrlr
1443 {
1444         uint16_t                ctrlr_id;       /* Controller ID */
1445         uint8_t                 rcsts;          /* Reservation Status */
1446         uint8_t                 reserved3[5];
1447         uint64_t                hostid;         /* Host Identifier */
1448         uint64_t                rkey;           /* Reservation Key */
1449 } __packed __aligned(4);
1450
1451 _Static_assert(sizeof(struct nvme_resv_reg_ctrlr) == 24, "bad size for nvme_resv_reg_ctrlr");
1452
1453 struct nvme_resv_reg_ctrlr_ext
1454 {
1455         uint16_t                ctrlr_id;       /* Controller ID */
1456         uint8_t                 rcsts;          /* Reservation Status */
1457         uint8_t                 reserved3[5];
1458         uint64_t                rkey;           /* Reservation Key */
1459         uint64_t                hostid[2];      /* Host Identifier */
1460         uint8_t                 reserved32[32];
1461 } __packed __aligned(4);
1462
1463 _Static_assert(sizeof(struct nvme_resv_reg_ctrlr_ext) == 64, "bad size for nvme_resv_reg_ctrlr_ext");
1464
1465 struct nvme_resv_status
1466 {
1467         uint32_t                gen;            /* Generation */
1468         uint8_t                 rtype;          /* Reservation Type */
1469         uint8_t                 regctl[2];      /* Number of Registered Controllers */
1470         uint8_t                 reserved7[2];
1471         uint8_t                 ptpls;          /* Persist Through Power Loss State */
1472         uint8_t                 reserved10[14];
1473         struct nvme_resv_reg_ctrlr      ctrlr[0];
1474 } __packed __aligned(4);
1475
1476 _Static_assert(sizeof(struct nvme_resv_status) == 24, "bad size for nvme_resv_status");
1477
1478 struct nvme_resv_status_ext
1479 {
1480         uint32_t                gen;            /* Generation */
1481         uint8_t                 rtype;          /* Reservation Type */
1482         uint8_t                 regctl[2];      /* Number of Registered Controllers */
1483         uint8_t                 reserved7[2];
1484         uint8_t                 ptpls;          /* Persist Through Power Loss State */
1485         uint8_t                 reserved10[14];
1486         uint8_t                 reserved24[40];
1487         struct nvme_resv_reg_ctrlr_ext  ctrlr[0];
1488 } __packed __aligned(4);
1489
1490 _Static_assert(sizeof(struct nvme_resv_status_ext) == 64, "bad size for nvme_resv_status_ext");
1491
1492 #define NVME_TEST_MAX_THREADS   128
1493
1494 struct nvme_io_test {
1495         enum nvme_nvm_opcode    opc;
1496         uint32_t                size;
1497         uint32_t                time;   /* in seconds */
1498         uint32_t                num_threads;
1499         uint32_t                flags;
1500         uint64_t                io_completed[NVME_TEST_MAX_THREADS];
1501 };
1502
1503 enum nvme_io_test_flags {
1504         /*
1505          * Specifies whether dev_refthread/dev_relthread should be
1506          *  called during NVME_BIO_TEST.  Ignored for other test
1507          *  types.
1508          */
1509         NVME_TEST_FLAG_REFTHREAD =      0x1,
1510 };
1511
1512 struct nvme_pt_command {
1513         /*
1514          * cmd is used to specify a passthrough command to a controller or
1515          *  namespace.
1516          *
1517          * The following fields from cmd may be specified by the caller:
1518          *      * opc  (opcode)
1519          *      * nsid (namespace id) - for admin commands only
1520          *      * cdw10-cdw15
1521          *
1522          * Remaining fields must be set to 0 by the caller.
1523          */
1524         struct nvme_command     cmd;
1525
1526         /*
1527          * cpl returns completion status for the passthrough command
1528          *  specified by cmd.
1529          *
1530          * The following fields will be filled out by the driver, for
1531          *  consumption by the caller:
1532          *      * cdw0
1533          *      * status (except for phase)
1534          *
1535          * Remaining fields will be set to 0 by the driver.
1536          */
1537         struct nvme_completion  cpl;
1538
1539         /* buf is the data buffer associated with this passthrough command. */
1540         void *                  buf;
1541
1542         /*
1543          * len is the length of the data buffer associated with this
1544          *  passthrough command.
1545          */
1546         uint32_t                len;
1547
1548         /*
1549          * is_read = 1 if the passthrough command will read data into the
1550          *  supplied buffer from the controller.
1551          *
1552          * is_read = 0 if the passthrough command will write data from the
1553          *  supplied buffer to the controller.
1554          */
1555         uint32_t                is_read;
1556
1557         /*
1558          * driver_lock is used by the driver only.  It must be set to 0
1559          *  by the caller.
1560          */
1561         struct mtx *            driver_lock;
1562 };
1563
1564 struct nvme_get_nsid {
1565         char            cdev[SPECNAMELEN + 1];
1566         uint32_t        nsid;
1567 };
1568
1569 struct nvme_hmb_desc {
1570         uint64_t        addr;
1571         uint32_t        size;
1572         uint32_t        reserved;
1573 };
1574
1575 #define nvme_completion_is_error(cpl)                                   \
1576         (NVME_STATUS_GET_SC((cpl)->status) != 0 || NVME_STATUS_GET_SCT((cpl)->status) != 0)
1577
1578 void    nvme_strvis(uint8_t *dst, const uint8_t *src, int dstlen, int srclen);
1579
1580 #ifdef _KERNEL
1581
1582 struct bio;
1583 struct thread;
1584
1585 struct nvme_namespace;
1586 struct nvme_controller;
1587 struct nvme_consumer;
1588
1589 typedef void (*nvme_cb_fn_t)(void *, const struct nvme_completion *);
1590
1591 typedef void *(*nvme_cons_ns_fn_t)(struct nvme_namespace *, void *);
1592 typedef void *(*nvme_cons_ctrlr_fn_t)(struct nvme_controller *);
1593 typedef void (*nvme_cons_async_fn_t)(void *, const struct nvme_completion *,
1594                                      uint32_t, void *, uint32_t);
1595 typedef void (*nvme_cons_fail_fn_t)(void *);
1596
1597 enum nvme_namespace_flags {
1598         NVME_NS_DEALLOCATE_SUPPORTED    = 0x1,
1599         NVME_NS_FLUSH_SUPPORTED         = 0x2,
1600 };
1601
1602 int     nvme_ctrlr_passthrough_cmd(struct nvme_controller *ctrlr,
1603                                    struct nvme_pt_command *pt,
1604                                    uint32_t nsid, int is_user_buffer,
1605                                    int is_admin_cmd);
1606
1607 /* Admin functions */
1608 void    nvme_ctrlr_cmd_set_feature(struct nvme_controller *ctrlr,
1609                                    uint8_t feature, uint32_t cdw11,
1610                                    uint32_t cdw12, uint32_t cdw13,
1611                                    uint32_t cdw14, uint32_t cdw15,
1612                                    void *payload, uint32_t payload_size,
1613                                    nvme_cb_fn_t cb_fn, void *cb_arg);
1614 void    nvme_ctrlr_cmd_get_feature(struct nvme_controller *ctrlr,
1615                                    uint8_t feature, uint32_t cdw11,
1616                                    void *payload, uint32_t payload_size,
1617                                    nvme_cb_fn_t cb_fn, void *cb_arg);
1618 void    nvme_ctrlr_cmd_get_log_page(struct nvme_controller *ctrlr,
1619                                     uint8_t log_page, uint32_t nsid,
1620                                     void *payload, uint32_t payload_size,
1621                                     nvme_cb_fn_t cb_fn, void *cb_arg);
1622
1623 /* NVM I/O functions */
1624 int     nvme_ns_cmd_write(struct nvme_namespace *ns, void *payload,
1625                           uint64_t lba, uint32_t lba_count, nvme_cb_fn_t cb_fn,
1626                           void *cb_arg);
1627 int     nvme_ns_cmd_write_bio(struct nvme_namespace *ns, struct bio *bp,
1628                               nvme_cb_fn_t cb_fn, void *cb_arg);
1629 int     nvme_ns_cmd_read(struct nvme_namespace *ns, void *payload,
1630                          uint64_t lba, uint32_t lba_count, nvme_cb_fn_t cb_fn,
1631                          void *cb_arg);
1632 int     nvme_ns_cmd_read_bio(struct nvme_namespace *ns, struct bio *bp,
1633                               nvme_cb_fn_t cb_fn, void *cb_arg);
1634 int     nvme_ns_cmd_deallocate(struct nvme_namespace *ns, void *payload,
1635                                uint8_t num_ranges, nvme_cb_fn_t cb_fn,
1636                                void *cb_arg);
1637 int     nvme_ns_cmd_flush(struct nvme_namespace *ns, nvme_cb_fn_t cb_fn,
1638                           void *cb_arg);
1639 int     nvme_ns_dump(struct nvme_namespace *ns, void *virt, off_t offset,
1640                      size_t len);
1641
1642 /* Registration functions */
1643 struct nvme_consumer *  nvme_register_consumer(nvme_cons_ns_fn_t    ns_fn,
1644                                                nvme_cons_ctrlr_fn_t ctrlr_fn,
1645                                                nvme_cons_async_fn_t async_fn,
1646                                                nvme_cons_fail_fn_t  fail_fn);
1647 void            nvme_unregister_consumer(struct nvme_consumer *consumer);
1648
1649 /* Controller helper functions */
1650 device_t        nvme_ctrlr_get_device(struct nvme_controller *ctrlr);
1651 const struct nvme_controller_data *
1652                 nvme_ctrlr_get_data(struct nvme_controller *ctrlr);
1653 static inline bool
1654 nvme_ctrlr_has_dataset_mgmt(const struct nvme_controller_data *cd)
1655 {
1656         /* Assumes cd was byte swapped by nvme_controller_data_swapbytes() */
1657         return ((cd->oncs >> NVME_CTRLR_DATA_ONCS_DSM_SHIFT) &
1658                 NVME_CTRLR_DATA_ONCS_DSM_MASK);
1659 }
1660
1661 /* Namespace helper functions */
1662 uint32_t        nvme_ns_get_max_io_xfer_size(struct nvme_namespace *ns);
1663 uint32_t        nvme_ns_get_sector_size(struct nvme_namespace *ns);
1664 uint64_t        nvme_ns_get_num_sectors(struct nvme_namespace *ns);
1665 uint64_t        nvme_ns_get_size(struct nvme_namespace *ns);
1666 uint32_t        nvme_ns_get_flags(struct nvme_namespace *ns);
1667 const char *    nvme_ns_get_serial_number(struct nvme_namespace *ns);
1668 const char *    nvme_ns_get_model_number(struct nvme_namespace *ns);
1669 const struct nvme_namespace_data *
1670                 nvme_ns_get_data(struct nvme_namespace *ns);
1671 uint32_t        nvme_ns_get_stripesize(struct nvme_namespace *ns);
1672
1673 int     nvme_ns_bio_process(struct nvme_namespace *ns, struct bio *bp,
1674                             nvme_cb_fn_t cb_fn);
1675 int     nvme_ns_ioctl_process(struct nvme_namespace *ns, u_long cmd,
1676     caddr_t arg, int flag, struct thread *td);
1677
1678 /*
1679  * Command building helper functions -- shared with CAM
1680  * These functions assume allocator zeros out cmd structure
1681  * CAM's xpt_get_ccb and the request allocator for nvme both
1682  * do zero'd allocations.
1683  */
1684 static inline
1685 void    nvme_ns_flush_cmd(struct nvme_command *cmd, uint32_t nsid)
1686 {
1687
1688         cmd->opc = NVME_OPC_FLUSH;
1689         cmd->nsid = htole32(nsid);
1690 }
1691
1692 static inline
1693 void    nvme_ns_rw_cmd(struct nvme_command *cmd, uint32_t rwcmd, uint32_t nsid,
1694     uint64_t lba, uint32_t count)
1695 {
1696         cmd->opc = rwcmd;
1697         cmd->nsid = htole32(nsid);
1698         cmd->cdw10 = htole32(lba & 0xffffffffu);
1699         cmd->cdw11 = htole32(lba >> 32);
1700         cmd->cdw12 = htole32(count-1);
1701 }
1702
1703 static inline
1704 void    nvme_ns_write_cmd(struct nvme_command *cmd, uint32_t nsid,
1705     uint64_t lba, uint32_t count)
1706 {
1707         nvme_ns_rw_cmd(cmd, NVME_OPC_WRITE, nsid, lba, count);
1708 }
1709
1710 static inline
1711 void    nvme_ns_read_cmd(struct nvme_command *cmd, uint32_t nsid,
1712     uint64_t lba, uint32_t count)
1713 {
1714         nvme_ns_rw_cmd(cmd, NVME_OPC_READ, nsid, lba, count);
1715 }
1716
1717 static inline
1718 void    nvme_ns_trim_cmd(struct nvme_command *cmd, uint32_t nsid,
1719     uint32_t num_ranges)
1720 {
1721         cmd->opc = NVME_OPC_DATASET_MANAGEMENT;
1722         cmd->nsid = htole32(nsid);
1723         cmd->cdw10 = htole32(num_ranges - 1);
1724         cmd->cdw11 = htole32(NVME_DSM_ATTR_DEALLOCATE);
1725 }
1726
1727 extern int nvme_use_nvd;
1728
1729 #endif /* _KERNEL */
1730
1731 /* Endianess conversion functions for NVMe structs */
1732 static inline
1733 void    nvme_completion_swapbytes(struct nvme_completion *s)
1734 {
1735
1736         s->cdw0 = le32toh(s->cdw0);
1737         /* omit rsvd1 */
1738         s->sqhd = le16toh(s->sqhd);
1739         s->sqid = le16toh(s->sqid);
1740         /* omit cid */
1741         s->status = le16toh(s->status);
1742 }
1743
1744 static inline
1745 void    nvme_power_state_swapbytes(struct nvme_power_state *s)
1746 {
1747
1748         s->mp = le16toh(s->mp);
1749         s->enlat = le32toh(s->enlat);
1750         s->exlat = le32toh(s->exlat);
1751         s->idlp = le16toh(s->idlp);
1752         s->actp = le16toh(s->actp);
1753 }
1754
1755 static inline
1756 void    nvme_controller_data_swapbytes(struct nvme_controller_data *s)
1757 {
1758         int i;
1759
1760         s->vid = le16toh(s->vid);
1761         s->ssvid = le16toh(s->ssvid);
1762         s->ctrlr_id = le16toh(s->ctrlr_id);
1763         s->ver = le32toh(s->ver);
1764         s->rtd3r = le32toh(s->rtd3r);
1765         s->rtd3e = le32toh(s->rtd3e);
1766         s->oaes = le32toh(s->oaes);
1767         s->ctratt = le32toh(s->ctratt);
1768         s->rrls = le16toh(s->rrls);
1769         s->crdt1 = le16toh(s->crdt1);
1770         s->crdt2 = le16toh(s->crdt2);
1771         s->crdt3 = le16toh(s->crdt3);
1772         s->oacs = le16toh(s->oacs);
1773         s->wctemp = le16toh(s->wctemp);
1774         s->cctemp = le16toh(s->cctemp);
1775         s->mtfa = le16toh(s->mtfa);
1776         s->hmpre = le32toh(s->hmpre);
1777         s->hmmin = le32toh(s->hmmin);
1778         s->rpmbs = le32toh(s->rpmbs);
1779         s->edstt = le16toh(s->edstt);
1780         s->kas = le16toh(s->kas);
1781         s->hctma = le16toh(s->hctma);
1782         s->mntmt = le16toh(s->mntmt);
1783         s->mxtmt = le16toh(s->mxtmt);
1784         s->sanicap = le32toh(s->sanicap);
1785         s->hmminds = le32toh(s->hmminds);
1786         s->hmmaxd = le16toh(s->hmmaxd);
1787         s->nsetidmax = le16toh(s->nsetidmax);
1788         s->endgidmax = le16toh(s->endgidmax);
1789         s->anagrpmax = le32toh(s->anagrpmax);
1790         s->nanagrpid = le32toh(s->nanagrpid);
1791         s->pels = le32toh(s->pels);
1792         s->maxcmd = le16toh(s->maxcmd);
1793         s->nn = le32toh(s->nn);
1794         s->oncs = le16toh(s->oncs);
1795         s->fuses = le16toh(s->fuses);
1796         s->awun = le16toh(s->awun);
1797         s->awupf = le16toh(s->awupf);
1798         s->acwu = le16toh(s->acwu);
1799         s->sgls = le32toh(s->sgls);
1800         s->mnan = le32toh(s->mnan);
1801         for (i = 0; i < 32; i++)
1802                 nvme_power_state_swapbytes(&s->power_state[i]);
1803 }
1804
1805 static inline
1806 void    nvme_namespace_data_swapbytes(struct nvme_namespace_data *s)
1807 {
1808         int i;
1809
1810         s->nsze = le64toh(s->nsze);
1811         s->ncap = le64toh(s->ncap);
1812         s->nuse = le64toh(s->nuse);
1813         s->nawun = le16toh(s->nawun);
1814         s->nawupf = le16toh(s->nawupf);
1815         s->nacwu = le16toh(s->nacwu);
1816         s->nabsn = le16toh(s->nabsn);
1817         s->nabo = le16toh(s->nabo);
1818         s->nabspf = le16toh(s->nabspf);
1819         s->noiob = le16toh(s->noiob);
1820         s->npwg = le16toh(s->npwg);
1821         s->npwa = le16toh(s->npwa);
1822         s->npdg = le16toh(s->npdg);
1823         s->npda = le16toh(s->npda);
1824         s->nows = le16toh(s->nows);
1825         s->anagrpid = le32toh(s->anagrpid);
1826         s->nvmsetid = le16toh(s->nvmsetid);
1827         s->endgid = le16toh(s->endgid);
1828         for (i = 0; i < 16; i++)
1829                 s->lbaf[i] = le32toh(s->lbaf[i]);
1830 }
1831
1832 static inline
1833 void    nvme_error_information_entry_swapbytes(struct nvme_error_information_entry *s)
1834 {
1835
1836         s->error_count = le64toh(s->error_count);
1837         s->sqid = le16toh(s->sqid);
1838         s->cid = le16toh(s->cid);
1839         s->status = le16toh(s->status);
1840         s->error_location = le16toh(s->error_location);
1841         s->lba = le64toh(s->lba);
1842         s->nsid = le32toh(s->nsid);
1843         s->csi = le64toh(s->csi);
1844         s->ttsi = le16toh(s->ttsi);
1845 }
1846
1847 static inline
1848 void    nvme_le128toh(void *p)
1849 {
1850 #if _BYTE_ORDER != _LITTLE_ENDIAN
1851         /* Swap 16 bytes in place */
1852         char *tmp = (char*)p;
1853         char b;
1854         int i;
1855         for (i = 0; i < 8; i++) {
1856                 b = tmp[i];
1857                 tmp[i] = tmp[15-i];
1858                 tmp[15-i] = b;
1859         }
1860 #else
1861         (void)p;
1862 #endif
1863 }
1864
1865 static inline
1866 void    nvme_health_information_page_swapbytes(struct nvme_health_information_page *s)
1867 {
1868         int i;
1869
1870         s->temperature = le16toh(s->temperature);
1871         nvme_le128toh((void *)s->data_units_read);
1872         nvme_le128toh((void *)s->data_units_written);
1873         nvme_le128toh((void *)s->host_read_commands);
1874         nvme_le128toh((void *)s->host_write_commands);
1875         nvme_le128toh((void *)s->controller_busy_time);
1876         nvme_le128toh((void *)s->power_cycles);
1877         nvme_le128toh((void *)s->power_on_hours);
1878         nvme_le128toh((void *)s->unsafe_shutdowns);
1879         nvme_le128toh((void *)s->media_errors);
1880         nvme_le128toh((void *)s->num_error_info_log_entries);
1881         s->warning_temp_time = le32toh(s->warning_temp_time);
1882         s->error_temp_time = le32toh(s->error_temp_time);
1883         for (i = 0; i < 8; i++)
1884                 s->temp_sensor[i] = le16toh(s->temp_sensor[i]);
1885         s->tmt1tc = le32toh(s->tmt1tc);
1886         s->tmt2tc = le32toh(s->tmt2tc);
1887         s->ttftmt1 = le32toh(s->ttftmt1);
1888         s->ttftmt2 = le32toh(s->ttftmt2);
1889 }
1890
1891 static inline
1892 void    nvme_firmware_page_swapbytes(struct nvme_firmware_page *s)
1893 {
1894         int i;
1895
1896         for (i = 0; i < 7; i++)
1897                 s->revision[i] = le64toh(s->revision[i]);
1898 }
1899
1900 static inline
1901 void    nvme_ns_list_swapbytes(struct nvme_ns_list *s)
1902 {
1903         int i;
1904
1905         for (i = 0; i < 1024; i++)
1906                 s->ns[i] = le32toh(s->ns[i]);
1907 }
1908
1909 static inline
1910 void    nvme_command_effects_page_swapbytes(struct nvme_command_effects_page *s)
1911 {
1912         int i;
1913
1914         for (i = 0; i < 256; i++)
1915                 s->acs[i] = le32toh(s->acs[i]);
1916         for (i = 0; i < 256; i++)
1917                 s->iocs[i] = le32toh(s->iocs[i]);
1918 }
1919
1920 static inline
1921 void    nvme_res_notification_page_swapbytes(struct nvme_res_notification_page *s)
1922 {
1923         s->log_page_count = le64toh(s->log_page_count);
1924         s->nsid = le32toh(s->nsid);
1925 }
1926
1927 static inline
1928 void    nvme_sanitize_status_page_swapbytes(struct nvme_sanitize_status_page *s)
1929 {
1930         s->sprog = le16toh(s->sprog);
1931         s->sstat = le16toh(s->sstat);
1932         s->scdw10 = le32toh(s->scdw10);
1933         s->etfo = le32toh(s->etfo);
1934         s->etfbe = le32toh(s->etfbe);
1935         s->etfce = le32toh(s->etfce);
1936         s->etfownd = le32toh(s->etfownd);
1937         s->etfbewnd = le32toh(s->etfbewnd);
1938         s->etfcewnd = le32toh(s->etfcewnd);
1939 }
1940
1941 static inline
1942 void    intel_log_temp_stats_swapbytes(struct intel_log_temp_stats *s)
1943 {
1944
1945         s->current = le64toh(s->current);
1946         s->overtemp_flag_last = le64toh(s->overtemp_flag_last);
1947         s->overtemp_flag_life = le64toh(s->overtemp_flag_life);
1948         s->max_temp = le64toh(s->max_temp);
1949         s->min_temp = le64toh(s->min_temp);
1950         /* omit _rsvd[] */
1951         s->max_oper_temp = le64toh(s->max_oper_temp);
1952         s->min_oper_temp = le64toh(s->min_oper_temp);
1953         s->est_offset = le64toh(s->est_offset);
1954 }
1955
1956 static inline
1957 void    nvme_resv_status_swapbytes(struct nvme_resv_status *s, size_t size)
1958 {
1959         u_int i, n;
1960
1961         s->gen = le32toh(s->gen);
1962         n = (s->regctl[1] << 8) | s->regctl[0];
1963         n = MIN(n, (size - sizeof(s)) / sizeof(s->ctrlr[0]));
1964         for (i = 0; i < n; i++) {
1965                 s->ctrlr[i].ctrlr_id = le16toh(s->ctrlr[i].ctrlr_id);
1966                 s->ctrlr[i].hostid = le64toh(s->ctrlr[i].hostid);
1967                 s->ctrlr[i].rkey = le64toh(s->ctrlr[i].rkey);
1968         }
1969 }
1970
1971 static inline
1972 void    nvme_resv_status_ext_swapbytes(struct nvme_resv_status_ext *s, size_t size)
1973 {
1974         u_int i, n;
1975
1976         s->gen = le32toh(s->gen);
1977         n = (s->regctl[1] << 8) | s->regctl[0];
1978         n = MIN(n, (size - sizeof(s)) / sizeof(s->ctrlr[0]));
1979         for (i = 0; i < n; i++) {
1980                 s->ctrlr[i].ctrlr_id = le16toh(s->ctrlr[i].ctrlr_id);
1981                 s->ctrlr[i].rkey = le64toh(s->ctrlr[i].rkey);
1982                 nvme_le128toh((void *)s->ctrlr[i].hostid);
1983         }
1984 }
1985
1986 #endif /* __NVME_H__ */