2 * Copyright (C) 2012 Intel Corporation
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 #include <sys/types.h>
36 #define NVME_IDENTIFY_CONTROLLER _IOR('n', 0, struct nvme_controller_data)
37 #define NVME_IDENTIFY_NAMESPACE _IOR('n', 1, struct nvme_namespace_data)
38 #define NVME_IO_TEST _IOWR('n', 2, struct nvme_io_test)
39 #define NVME_BIO_TEST _IOWR('n', 4, struct nvme_io_test)
42 * Use to mark a command to apply to all namespaces, or to retrieve global
45 #define NVME_GLOBAL_NAMESPACE_TAG ((uint32_t)0xFFFFFFFF)
47 union cap_lo_register {
50 /** maximum queue entries supported */
53 /** contiguous queues required */
56 /** arbitration mechanism supported */
59 uint32_t reserved1 : 5;
66 union cap_hi_register {
69 /** doorbell stride */
72 uint32_t reserved3 : 1;
74 /** command sets supported */
77 uint32_t css_reserved : 3;
78 uint32_t reserved2 : 7;
80 /** memory page size minimum */
83 /** memory page size maximum */
86 uint32_t reserved1 : 8;
96 uint32_t reserved1 : 3;
98 /** i/o command set selected */
101 /** memory page size */
104 /** arbitration mechanism selected */
107 /** shutdown notification */
110 /** i/o submission queue entry size */
113 /** i/o completion queue entry size */
116 uint32_t reserved2 : 8;
121 NVME_SHN_NORMAL = 0x1,
122 NVME_SHN_ABRUPT = 0x2,
125 union csts_register {
131 /** controller fatal status */
134 /** shutdown status */
137 uint32_t reserved1 : 28;
142 NVME_SHST_NORMAL = 0x0,
143 NVME_SHST_OCCURRING = 0x1,
144 NVME_SHST_COMPLETE = 0x2,
150 /** admin submission queue size */
153 uint32_t reserved1 : 4;
155 /** admin completion queue size */
158 uint32_t reserved2 : 4;
162 struct nvme_registers
164 /** controller capabilities */
165 union cap_lo_register cap_lo;
166 union cap_hi_register cap_hi;
168 uint32_t vs; /* version */
169 uint32_t intms; /* interrupt mask set */
170 uint32_t intmc; /* interrupt mask clear */
172 /** controller configuration */
173 union cc_register cc;
176 uint32_t csts; /* controller status */
179 /** admin queue attributes */
180 union aqa_register aqa;
182 uint64_t asq; /* admin submission queue base addr */
183 uint64_t acq; /* admin completion queue base addr */
184 uint32_t reserved3[0x3f2];
187 uint32_t sq_tdbl; /* submission queue tail doorbell */
188 uint32_t cq_hdbl; /* completion queue head doorbell */
189 } doorbell[1] __packed;
195 uint16_t opc : 8; /* opcode */
196 uint16_t fuse : 2; /* fused operation */
198 uint16_t cid; /* command identifier */
201 uint32_t nsid; /* namespace identifier */
208 uint64_t mptr; /* metadata pointer */
211 uint64_t prp1; /* prp entry 1 */
214 uint64_t prp2; /* prp entry 2 */
217 uint32_t cdw10; /* command-specific */
218 uint32_t cdw11; /* command-specific */
219 uint32_t cdw12; /* command-specific */
220 uint32_t cdw13; /* command-specific */
221 uint32_t cdw14; /* command-specific */
222 uint32_t cdw15; /* command-specific */
225 struct nvme_completion {
228 uint32_t cdw0; /* command-specific */
234 uint16_t sqhd; /* submission queue head pointer */
235 uint16_t sqid; /* submission queue identifier */
238 uint16_t cid; /* command identifier */
239 uint16_t p : 1; /* phase tag */
240 uint16_t sf_sc : 8; /* status field - status code */
241 uint16_t sf_sct : 3; /* status field - status code type */
243 uint16_t sf_m : 1; /* status field - more */
244 uint16_t sf_dnr : 1; /* status field - do not retry */
247 struct nvme_dsm_range {
251 uint64_t starting_lba;
254 /* status code types */
255 enum nvme_status_code_type {
256 NVME_SCT_GENERIC = 0x0,
257 NVME_SCT_COMMAND_SPECIFIC = 0x1,
258 NVME_SCT_MEDIA_ERROR = 0x2,
259 /* 0x3-0x6 - reserved */
260 NVME_SCT_VENDOR_SPECIFIC = 0x7,
263 /* generic command status codes */
264 enum nvme_generic_command_status_code {
265 NVME_SC_SUCCESS = 0x00,
266 NVME_SC_INVALID_OPCODE = 0x01,
267 NVME_SC_INVALID_FIELD = 0x02,
268 NVME_SC_COMMAND_ID_CONFLICT = 0x03,
269 NVME_SC_DATA_TRANSFER_ERROR = 0x04,
270 NVME_SC_ABORTED_POWER_LOSS = 0x05,
271 NVME_SC_INTERNAL_DEVICE_ERROR = 0x06,
272 NVME_SC_ABORTED_BY_REQUEST = 0x07,
273 NVME_SC_ABORTED_SQ_DELETION = 0x08,
274 NVME_SC_ABORTED_FAILED_FUSED = 0x09,
275 NVME_SC_ABORTED_MISSING_FUSED = 0x0a,
276 NVME_SC_INVALID_NAMESPACE_OR_FORMAT = 0x0b,
277 NVME_SC_COMMAND_SEQUENCE_ERROR = 0x0c,
279 NVME_SC_LBA_OUT_OF_RANGE = 0x80,
280 NVME_SC_CAPACITY_EXCEEDED = 0x81,
281 NVME_SC_NAMESPACE_NOT_READY = 0x82,
284 /* command specific status codes */
285 enum nvme_command_specific_status_code {
286 NVME_SC_COMPLETION_QUEUE_INVALID = 0x00,
287 NVME_SC_INVALID_QUEUE_IDENTIFIER = 0x01,
288 NVME_SC_MAXIMUM_QUEUE_SIZE_EXCEEDED = 0x02,
289 NVME_SC_ABORT_COMMAND_LIMIT_EXCEEDED = 0x03,
290 /* 0x04 - reserved */
291 NVME_SC_ASYNC_EVENT_REQUEST_LIMIT_EXCEEDED = 0x05,
292 NVME_SC_INVALID_FIRMWARE_SLOT = 0x06,
293 NVME_SC_INVALID_FIRMWARE_IMAGE = 0x07,
294 NVME_SC_INVALID_INTERRUPT_VECTOR = 0x08,
295 NVME_SC_INVALID_LOG_PAGE = 0x09,
296 NVME_SC_INVALID_FORMAT = 0x0a,
297 NVME_SC_FIRMWARE_REQUIRES_RESET = 0x0b,
299 NVME_SC_CONFLICTING_ATTRIBUTES = 0x80,
300 NVME_SC_INVALID_PROTECTION_INFO = 0x81,
301 NVME_SC_ATTEMPTED_WRITE_TO_RO_PAGE = 0x82,
304 /* media error status codes */
305 enum nvme_media_error_status_code {
306 NVME_SC_WRITE_FAULTS = 0x80,
307 NVME_SC_UNRECOVERED_READ_ERROR = 0x81,
308 NVME_SC_GUARD_CHECK_ERROR = 0x82,
309 NVME_SC_APPLICATION_TAG_CHECK_ERROR = 0x83,
310 NVME_SC_REFERENCE_TAG_CHECK_ERROR = 0x84,
311 NVME_SC_COMPARE_FAILURE = 0x85,
312 NVME_SC_ACCESS_DENIED = 0x86,
316 enum nvme_admin_opcode {
317 NVME_OPC_DELETE_IO_SQ = 0x00,
318 NVME_OPC_CREATE_IO_SQ = 0x01,
319 NVME_OPC_GET_LOG_PAGE = 0x02,
320 /* 0x03 - reserved */
321 NVME_OPC_DELETE_IO_CQ = 0x04,
322 NVME_OPC_CREATE_IO_CQ = 0x05,
323 NVME_OPC_IDENTIFY = 0x06,
324 /* 0x07 - reserved */
325 NVME_OPC_ABORT = 0x08,
326 NVME_OPC_SET_FEATURES = 0x09,
327 NVME_OPC_GET_FEATURES = 0x0a,
328 /* 0x0b - reserved */
329 NVME_OPC_ASYNC_EVENT_REQUEST = 0x0c,
330 /* 0x0d-0x0f - reserved */
331 NVME_OPC_FIRMWARE_ACTIVATE = 0x10,
332 NVME_OPC_FIRMWARE_IMAGE_DOWNLOAD = 0x11,
334 NVME_OPC_FORMAT_NVM = 0x80,
335 NVME_OPC_SECURITY_SEND = 0x81,
336 NVME_OPC_SECURITY_RECEIVE = 0x82,
339 /* nvme nvm opcodes */
340 enum nvme_nvm_opcode {
341 NVME_OPC_FLUSH = 0x00,
342 NVME_OPC_WRITE = 0x01,
343 NVME_OPC_READ = 0x02,
344 /* 0x03 - reserved */
345 NVME_OPC_WRITE_UNCORRECTABLE = 0x04,
346 NVME_OPC_COMPARE = 0x05,
347 /* 0x06-0x07 - reserved */
348 NVME_OPC_DATASET_MANAGEMENT = 0x09,
352 /* 0x00 - reserved */
353 NVME_FEAT_ARBITRATION = 0x01,
354 NVME_FEAT_POWER_MANAGEMENT = 0x02,
355 NVME_FEAT_LBA_RANGE_TYPE = 0x03,
356 NVME_FEAT_TEMPERATURE_THRESHOLD = 0x04,
357 NVME_FEAT_ERROR_RECOVERY = 0x05,
358 NVME_FEAT_VOLATILE_WRITE_CACHE = 0x06,
359 NVME_FEAT_NUMBER_OF_QUEUES = 0x07,
360 NVME_FEAT_INTERRUPT_COALESCING = 0x08,
361 NVME_FEAT_INTERRUPT_VECTOR_CONFIGURATION = 0x09,
362 NVME_FEAT_WRITE_ATOMICITY = 0x0A,
363 NVME_FEAT_ASYNCHRONOUS_EVENT_CONFIGURATION = 0x0B,
364 /* 0x0C-0x7F - reserved */
365 NVME_FEAT_SOFTWARE_PROGRESS_MARKER = 0x80,
366 /* 0x81-0xBF - command set specific (reserved) */
367 /* 0xC0-0xFF - vendor specific */
370 enum nvme_dsm_attribute {
371 NVME_DSM_ATTR_INTEGRAL_READ = 0x1,
372 NVME_DSM_ATTR_INTEGRAL_WRITE = 0x2,
373 NVME_DSM_ATTR_DEALLOCATE = 0x4,
376 struct nvme_controller_data {
378 /* bytes 0-255: controller capabilities and features */
383 /** pci subsystem vendor id */
392 /** firmware revision */
395 /** recommended arbitration burst */
398 /** ieee oui identifier */
401 /** multi-interface capabilities */
404 /** maximum data transfer size */
407 uint8_t reserved1[178];
409 /* bytes 256-511: admin command set attributes */
411 /** optional admin command support */
413 /* supports security send/receive commands */
414 uint16_t security : 1;
416 /* supports format nvm command */
419 /* supports firmware activate/download commands */
420 uint16_t firmware : 1;
422 uint16_t oacs_rsvd : 13;
425 /** abort command limit */
428 /** asynchronous event request limit */
431 /** firmware updates */
433 /* first slot is read-only */
434 uint8_t slot1_ro : 1;
436 /* number of firmware slots */
437 uint8_t num_slots : 3;
439 uint8_t frmw_rsvd : 4;
442 /** log page attributes */
444 /* per namespace smart/health log page */
445 uint8_t ns_smart : 1;
447 uint8_t lpa_rsvd : 7;
450 /** error log page entries */
453 /** number of power states supported */
456 /** admin vendor specific command configuration */
458 /* admin vendor specific commands use spec format */
459 uint8_t spec_format : 1;
461 uint8_t avscc_rsvd : 7;
464 uint8_t reserved2[247];
466 /* bytes 512-703: nvm command set attributes */
468 /** submission queue entry size */
474 /** completion queue entry size */
480 uint8_t reserved3[2];
482 /** number of namespaces */
485 /** optional nvm command support */
487 uint16_t compare : 1;
488 uint16_t write_unc : 1;
490 uint16_t reserved: 13;
493 /** fused operation support */
496 /** format nvm attributes */
499 /** volatile write cache */
502 uint8_t reserved : 7;
505 /* TODO: flesh out remaining nvm command set attributes */
506 uint8_t reserved4[178];
508 /* bytes 704-2047: i/o command set attributes */
509 uint8_t reserved5[1344];
511 /* bytes 2048-3071: power state descriptors */
512 uint8_t reserved6[1024];
514 /* bytes 3072-4095: vendor specific */
515 uint8_t reserved7[1024];
516 } __packed __aligned(4);
518 struct nvme_namespace_data {
520 /** namespace size */
523 /** namespace capacity */
526 /** namespace utilization */
529 /** namespace features */
531 /** thin provisioning */
532 uint8_t thin_prov : 1;
533 uint8_t reserved1 : 7;
536 /** number of lba formats */
539 /** formatted lba size */
542 uint8_t extended : 1;
543 uint8_t reserved2 : 3;
546 /** metadata capabilities */
548 /* metadata can be transferred as part of data prp list */
549 uint8_t extended : 1;
551 /* metadata can be transferred with separate metadata pointer */
554 uint8_t reserved3 : 6;
557 /** end-to-end data protection capabilities */
559 /* protection information type 1 */
562 /* protection information type 2 */
565 /* protection information type 3 */
568 /* first eight bytes of metadata */
569 uint8_t md_start : 1;
571 /* last eight bytes of metadata */
575 /** end-to-end data protection type settings */
577 /* protection information type */
580 /* 1 == protection info transferred at start of metadata */
581 /* 0 == protection info transferred at end of metadata */
582 uint8_t md_start : 1;
584 uint8_t reserved4 : 4;
587 uint8_t reserved5[98];
589 /** lba format support */
597 /** relative performance */
600 uint32_t reserved6 : 6;
603 uint8_t reserved6[192];
605 uint8_t vendor_specific[3712];
606 } __packed __aligned(4);
610 /* 0x00 - reserved */
611 NVME_LOG_ERROR = 0x01,
612 NVME_LOG_HEALTH_INFORMATION = 0x02,
613 NVME_LOG_FIRMWARE_SLOT = 0x03,
614 /* 0x04-0x7F - reserved */
615 /* 0x80-0xBF - I/O command set specific */
616 /* 0xC0-0xFF - vendor specific */
619 union nvme_critical_warning_state {
624 uint8_t available_spare : 1;
625 uint8_t temperature : 1;
626 uint8_t device_reliability : 1;
627 uint8_t read_only : 1;
628 uint8_t volatile_memory_backup : 1;
629 uint8_t reserved : 3;
633 struct nvme_health_information_page {
635 union nvme_critical_warning_state critical_warning;
637 uint16_t temperature;
638 uint8_t available_spare;
639 uint8_t available_spare_threshold;
640 uint8_t percentage_used;
642 uint8_t reserved[26];
645 * Note that the following are 128-bit values, but are
646 * defined as an array of 2 64-bit values.
648 /* Data Units Read is always in 512-byte units. */
649 uint64_t data_units_read[2];
650 /* Data Units Written is always in 512-byte units. */
651 uint64_t data_units_written[2];
652 /* For NVM command set, this includes Compare commands. */
653 uint64_t host_read_commands[2];
654 uint64_t host_write_commands[2];
655 /* Controller Busy Time is reported in minutes. */
656 uint64_t controller_busy_time[2];
657 uint64_t power_cycles[2];
658 uint64_t power_on_hours[2];
659 uint64_t unsafe_shutdowns[2];
660 uint64_t media_errors[2];
661 uint64_t num_error_info_log_entries[2];
663 uint8_t reserved2[320];
664 } __packed __aligned(4);
666 #define NVME_TEST_MAX_THREADS 128
668 struct nvme_io_test {
670 enum nvme_nvm_opcode opc;
672 uint32_t time; /* in seconds */
673 uint32_t num_threads;
675 uint32_t io_completed[NVME_TEST_MAX_THREADS];
678 enum nvme_io_test_flags {
681 * Specifies whether dev_refthread/dev_relthread should be
682 * called during NVME_BIO_TEST. Ignored for other test
685 NVME_TEST_FLAG_REFTHREAD = 0x1,
692 /* TODO: reassess this QD variable - its a workaround for Chatham2 issue */
693 #define NVME_QD (200)
695 struct nvme_namespace;
696 struct nvme_consumer;
698 typedef void (*nvme_cb_fn_t)(void *, const struct nvme_completion *);
699 typedef void (*nvme_consumer_cb_fn_t)(void *, struct nvme_namespace *);
701 enum nvme_namespace_flags {
702 NVME_NS_DEALLOCATE_SUPPORTED = 0x1,
703 NVME_NS_FLUSH_SUPPORTED = 0x2,
706 /* NVM I/O functions */
707 void nvme_ns_cmd_write(struct nvme_namespace *ns, void *payload,
708 uint64_t lba, uint32_t lba_count, nvme_cb_fn_t cb_fn,
710 void nvme_ns_cmd_read(struct nvme_namespace *ns, void *payload,
711 uint64_t lba, uint32_t lba_count, nvme_cb_fn_t cb_fn,
713 void nvme_ns_cmd_deallocate(struct nvme_namespace *ns, void *payload,
714 uint8_t num_ranges, nvme_cb_fn_t cb_fn,
716 void nvme_ns_cmd_flush(struct nvme_namespace *ns, nvme_cb_fn_t cb_fn,
719 /* Registration functions */
720 struct nvme_consumer * nvme_register_consumer(nvme_consumer_cb_fn_t cb_fn,
722 void nvme_unregister_consumer(struct nvme_consumer *consumer);
724 /* Namespace helper functions */
725 uint32_t nvme_ns_get_max_io_xfer_size(struct nvme_namespace *ns);
726 uint32_t nvme_ns_get_sector_size(struct nvme_namespace *ns);
727 uint64_t nvme_ns_get_num_sectors(struct nvme_namespace *ns);
728 uint64_t nvme_ns_get_size(struct nvme_namespace *ns);
729 uint32_t nvme_ns_get_flags(struct nvme_namespace *ns);
730 const char * nvme_ns_get_serial_number(struct nvme_namespace *ns);
731 const char * nvme_ns_get_model_number(struct nvme_namespace *ns);
733 int nvme_ns_bio_process(struct nvme_namespace *ns, struct bio *bp,
738 #endif /* __NVME_H__ */