sys/dev/nvme/nvme.h

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (C) 2012-2013 Intel Corporation
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  *
  28  * $FreeBSD$
  29  */
  30
  31 #ifndef __NVME_H__
  32 #define __NVME_H__
  33
  34 #ifdef _KERNEL
  35 #include <sys/types.h>
  36 #endif
  37
  38 #include <sys/param.h>
  39 #include <sys/endian.h>
  40
  41 #define NVME_PASSTHROUGH_CMD            _IOWR('n', 0, struct nvme_pt_command)
  42 #define NVME_RESET_CONTROLLER           _IO('n', 1)
  43 #define NVME_GET_NSID                   _IOR('n', 2, struct nvme_get_nsid)
  44 #define NVME_GET_MAX_XFER_SIZE          _IOR('n', 3, uint64_t)
  45
  46 #define NVME_IO_TEST                    _IOWR('n', 100, struct nvme_io_test)
  47 #define NVME_BIO_TEST                   _IOWR('n', 101, struct nvme_io_test)
  48
  49 /*
  50  * Macros to deal with NVME revisions, as defined VS register
  51  */
  52 #define NVME_REV(x, y)                  (((x) << 16) | ((y) << 8))
  53 #define NVME_MAJOR(r)                   (((r) >> 16) & 0xffff)
  54 #define NVME_MINOR(r)                   (((r) >> 8) & 0xff)
  55
  56 /*
  57  * Use to mark a command to apply to all namespaces, or to retrieve global
  58  *  log pages.
  59  */
  60 #define NVME_GLOBAL_NAMESPACE_TAG       ((uint32_t)0xFFFFFFFF)
  61
  62 /* Cap nvme to 1MB transfers driver explodes with larger sizes */
  63 #define NVME_MAX_XFER_SIZE              (MAXPHYS < (1<<20) ? MAXPHYS : (1<<20))
  64
  65 /* Register field definitions */
  66 #define NVME_CAP_LO_REG_MQES_SHIFT                      (0)
  67 #define NVME_CAP_LO_REG_MQES_MASK                       (0xFFFF)
  68 #define NVME_CAP_LO_REG_CQR_SHIFT                       (16)
  69 #define NVME_CAP_LO_REG_CQR_MASK                        (0x1)
  70 #define NVME_CAP_LO_REG_AMS_SHIFT                       (17)
  71 #define NVME_CAP_LO_REG_AMS_MASK                        (0x3)
  72 #define NVME_CAP_LO_REG_TO_SHIFT                        (24)
  73 #define NVME_CAP_LO_REG_TO_MASK                         (0xFF)
  74 #define NVME_CAP_LO_MQES(x) \
  75         (((x) >> NVME_CAP_LO_REG_MQES_SHIFT) & NVME_CAP_LO_REG_MQES_MASK)
  76 #define NVME_CAP_LO_CQR(x) \
  77         (((x) >> NVME_CAP_LO_REG_CQR_SHIFT) & NVME_CAP_LO_REG_CQR_MASK)
  78 #define NVME_CAP_LO_AMS(x) \
  79         (((x) >> NVME_CAP_LO_REG_AMS_SHIFT) & NVME_CAP_LO_REG_AMS_MASK)
  80 #define NVME_CAP_LO_TO(x) \
  81         (((x) >> NVME_CAP_LO_REG_TO_SHIFT) & NVME_CAP_LO_REG_TO_MASK)
  82
  83 #define NVME_CAP_HI_REG_DSTRD_SHIFT                     (0)
  84 #define NVME_CAP_HI_REG_DSTRD_MASK                      (0xF)
  85 #define NVME_CAP_HI_REG_NSSRS_SHIFT                     (4)
  86 #define NVME_CAP_HI_REG_NSSRS_MASK                      (0x1)
  87 #define NVME_CAP_HI_REG_CSS_NVM_SHIFT                   (5)
  88 #define NVME_CAP_HI_REG_CSS_NVM_MASK                    (0x1)
  89 #define NVME_CAP_HI_REG_BPS_SHIFT                       (13)
  90 #define NVME_CAP_HI_REG_BPS_MASK                        (0x1)
  91 #define NVME_CAP_HI_REG_MPSMIN_SHIFT                    (16)
  92 #define NVME_CAP_HI_REG_MPSMIN_MASK                     (0xF)
  93 #define NVME_CAP_HI_REG_MPSMAX_SHIFT                    (20)
  94 #define NVME_CAP_HI_REG_MPSMAX_MASK                     (0xF)
  95 #define NVME_CAP_HI_REG_PMRS_SHIFT                      (24)
  96 #define NVME_CAP_HI_REG_PMRS_MASK                       (0x1)
  97 #define NVME_CAP_HI_REG_CMBS_SHIFT                      (25)
  98 #define NVME_CAP_HI_REG_CMBS_MASK                       (0x1)
  99 #define NVME_CAP_HI_DSTRD(x) \
 100         (((x) >> NVME_CAP_HI_REG_DSTRD_SHIFT) & NVME_CAP_HI_REG_DSTRD_MASK)
 101 #define NVME_CAP_HI_CSS_NVM(x) \
 102         (((x) >> NVME_CAP_HI_REG_CSS_NVM_SHIFT) & NVME_CAP_HI_REG_CSS_NVM_MASK)
 103 #define NVME_CAP_HI_MPSMIN(x) \
 104         (((x) >> NVME_CAP_HI_REG_MPSMIN_SHIFT) & NVME_CAP_HI_REG_MPSMIN_MASK)
 105 #define NVME_CAP_HI_MPSMAX(x) \
 106         (((x) >> NVME_CAP_HI_REG_MPSMAX_SHIFT) & NVME_CAP_HI_REG_MPSMAX_MASK)
 107
 108 #define NVME_CC_REG_EN_SHIFT                            (0)
 109 #define NVME_CC_REG_EN_MASK                             (0x1)
 110 #define NVME_CC_REG_CSS_SHIFT                           (4)
 111 #define NVME_CC_REG_CSS_MASK                            (0x7)
 112 #define NVME_CC_REG_MPS_SHIFT                           (7)
 113 #define NVME_CC_REG_MPS_MASK                            (0xF)
 114 #define NVME_CC_REG_AMS_SHIFT                           (11)
 115 #define NVME_CC_REG_AMS_MASK                            (0x7)
 116 #define NVME_CC_REG_SHN_SHIFT                           (14)
 117 #define NVME_CC_REG_SHN_MASK                            (0x3)
 118 #define NVME_CC_REG_IOSQES_SHIFT                        (16)
 119 #define NVME_CC_REG_IOSQES_MASK                         (0xF)
 120 #define NVME_CC_REG_IOCQES_SHIFT                        (20)
 121 #define NVME_CC_REG_IOCQES_MASK                         (0xF)
 122
 123 #define NVME_CSTS_REG_RDY_SHIFT                         (0)
 124 #define NVME_CSTS_REG_RDY_MASK                          (0x1)
 125 #define NVME_CSTS_REG_CFS_SHIFT                         (1)
 126 #define NVME_CSTS_REG_CFS_MASK                          (0x1)
 127 #define NVME_CSTS_REG_SHST_SHIFT                        (2)
 128 #define NVME_CSTS_REG_SHST_MASK                         (0x3)
 129 #define NVME_CSTS_REG_NVSRO_SHIFT                       (4)
 130 #define NVME_CSTS_REG_NVSRO_MASK                        (0x1)
 131 #define NVME_CSTS_REG_PP_SHIFT                          (5)
 132 #define NVME_CSTS_REG_PP_MASK                           (0x1)
 133
 134 #define NVME_CSTS_GET_SHST(csts)                        (((csts) >> NVME_CSTS_REG_SHST_SHIFT) & NVME_CSTS_REG_SHST_MASK)
 135
 136 #define NVME_AQA_REG_ASQS_SHIFT                         (0)
 137 #define NVME_AQA_REG_ASQS_MASK                          (0xFFF)
 138 #define NVME_AQA_REG_ACQS_SHIFT                         (16)
 139 #define NVME_AQA_REG_ACQS_MASK                          (0xFFF)
 140
 141 /* Command field definitions */
 142
 143 #define NVME_CMD_FUSE_SHIFT                             (8)
 144 #define NVME_CMD_FUSE_MASK                              (0x3)
 145
 146 #define NVME_STATUS_P_SHIFT                             (0)
 147 #define NVME_STATUS_P_MASK                              (0x1)
 148 #define NVME_STATUS_SC_SHIFT                            (1)
 149 #define NVME_STATUS_SC_MASK                             (0xFF)
 150 #define NVME_STATUS_SCT_SHIFT                           (9)
 151 #define NVME_STATUS_SCT_MASK                            (0x7)
 152 #define NVME_STATUS_CRD_SHIFT                           (12)
 153 #define NVME_STATUS_CRD_MASK                            (0x3)
 154 #define NVME_STATUS_M_SHIFT                             (14)
 155 #define NVME_STATUS_M_MASK                              (0x1)
 156 #define NVME_STATUS_DNR_SHIFT                           (15)
 157 #define NVME_STATUS_DNR_MASK                            (0x1)
 158
 159 #define NVME_STATUS_GET_P(st)                           (((st) >> NVME_STATUS_P_SHIFT) & NVME_STATUS_P_MASK)
 160 #define NVME_STATUS_GET_SC(st)                          (((st) >> NVME_STATUS_SC_SHIFT) & NVME_STATUS_SC_MASK)
 161 #define NVME_STATUS_GET_SCT(st)                         (((st) >> NVME_STATUS_SCT_SHIFT) & NVME_STATUS_SCT_MASK)
 162 #define NVME_STATUS_GET_M(st)                           (((st) >> NVME_STATUS_M_SHIFT) & NVME_STATUS_M_MASK)
 163 #define NVME_STATUS_GET_DNR(st)                         (((st) >> NVME_STATUS_DNR_SHIFT) & NVME_STATUS_DNR_MASK)
 164
 165 #define NVME_PWR_ST_MPS_SHIFT                           (0)
 166 #define NVME_PWR_ST_MPS_MASK                            (0x1)
 167 #define NVME_PWR_ST_NOPS_SHIFT                          (1)
 168 #define NVME_PWR_ST_NOPS_MASK                           (0x1)
 169 #define NVME_PWR_ST_RRT_SHIFT                           (0)
 170 #define NVME_PWR_ST_RRT_MASK                            (0x1F)
 171 #define NVME_PWR_ST_RRL_SHIFT                           (0)
 172 #define NVME_PWR_ST_RRL_MASK                            (0x1F)
 173 #define NVME_PWR_ST_RWT_SHIFT                           (0)
 174 #define NVME_PWR_ST_RWT_MASK                            (0x1F)
 175 #define NVME_PWR_ST_RWL_SHIFT                           (0)
 176 #define NVME_PWR_ST_RWL_MASK                            (0x1F)
 177 #define NVME_PWR_ST_IPS_SHIFT                           (6)
 178 #define NVME_PWR_ST_IPS_MASK                            (0x3)
 179 #define NVME_PWR_ST_APW_SHIFT                           (0)
 180 #define NVME_PWR_ST_APW_MASK                            (0x7)
 181 #define NVME_PWR_ST_APS_SHIFT                           (6)
 182 #define NVME_PWR_ST_APS_MASK                            (0x3)
 183
 184 /** Controller Multi-path I/O and Namespace Sharing Capabilities */
 185 /* More then one port */
 186 #define NVME_CTRLR_DATA_MIC_MPORTS_SHIFT                (0)
 187 #define NVME_CTRLR_DATA_MIC_MPORTS_MASK                 (0x1)
 188 /* More then one controller */
 189 #define NVME_CTRLR_DATA_MIC_MCTRLRS_SHIFT               (1)
 190 #define NVME_CTRLR_DATA_MIC_MCTRLRS_MASK                (0x1)
 191 /* SR-IOV Virtual Function */
 192 #define NVME_CTRLR_DATA_MIC_SRIOVVF_SHIFT               (2)
 193 #define NVME_CTRLR_DATA_MIC_SRIOVVF_MASK                (0x1)
 194 /* Asymmetric Namespace Access Reporting */
 195 #define NVME_CTRLR_DATA_MIC_ANAR_SHIFT                  (3)
 196 #define NVME_CTRLR_DATA_MIC_ANAR_MASK                   (0x1)
 197
 198 /** OACS - optional admin command support */
 199 /* supports security send/receive commands */
 200 #define NVME_CTRLR_DATA_OACS_SECURITY_SHIFT             (0)
 201 #define NVME_CTRLR_DATA_OACS_SECURITY_MASK              (0x1)
 202 /* supports format nvm command */
 203 #define NVME_CTRLR_DATA_OACS_FORMAT_SHIFT               (1)
 204 #define NVME_CTRLR_DATA_OACS_FORMAT_MASK                (0x1)
 205 /* supports firmware activate/download commands */
 206 #define NVME_CTRLR_DATA_OACS_FIRMWARE_SHIFT             (2)
 207 #define NVME_CTRLR_DATA_OACS_FIRMWARE_MASK              (0x1)
 208 /* supports namespace management commands */
 209 #define NVME_CTRLR_DATA_OACS_NSMGMT_SHIFT               (3)
 210 #define NVME_CTRLR_DATA_OACS_NSMGMT_MASK                (0x1)
 211 /* supports Device Self-test command */
 212 #define NVME_CTRLR_DATA_OACS_SELFTEST_SHIFT             (4)
 213 #define NVME_CTRLR_DATA_OACS_SELFTEST_MASK              (0x1)
 214 /* supports Directives */
 215 #define NVME_CTRLR_DATA_OACS_DIRECTIVES_SHIFT           (5)
 216 #define NVME_CTRLR_DATA_OACS_DIRECTIVES_MASK            (0x1)
 217 /* supports NVMe-MI Send/Receive */
 218 #define NVME_CTRLR_DATA_OACS_NVMEMI_SHIFT               (6)
 219 #define NVME_CTRLR_DATA_OACS_NVMEMI_MASK                (0x1)
 220 /* supports Virtualization Management */
 221 #define NVME_CTRLR_DATA_OACS_VM_SHIFT                   (7)
 222 #define NVME_CTRLR_DATA_OACS_VM_MASK                    (0x1)
 223 /* supports Doorbell Buffer Config */
 224 #define NVME_CTRLR_DATA_OACS_DBBUFFER_SHIFT             (8)
 225 #define NVME_CTRLR_DATA_OACS_DBBUFFER_MASK              (0x1)
 226 /* supports Get LBA Status */
 227 #define NVME_CTRLR_DATA_OACS_GETLBA_SHIFT               (9)
 228 #define NVME_CTRLR_DATA_OACS_GETLBA_MASK                (0x1)
 229
 230 /** firmware updates */
 231 /* first slot is read-only */
 232 #define NVME_CTRLR_DATA_FRMW_SLOT1_RO_SHIFT             (0)
 233 #define NVME_CTRLR_DATA_FRMW_SLOT1_RO_MASK              (0x1)
 234 /* number of firmware slots */
 235 #define NVME_CTRLR_DATA_FRMW_NUM_SLOTS_SHIFT            (1)
 236 #define NVME_CTRLR_DATA_FRMW_NUM_SLOTS_MASK             (0x7)
 237 /* firmware activation without reset */
 238 #define NVME_CTRLR_DATA_FRMW_ACT_WO_RESET_SHIFT         (4)
 239 #define NVME_CTRLR_DATA_FRMW_ACT_WO_RESET_MASK          (0x1)
 240
 241 /** log page attributes */
 242 /* per namespace smart/health log page */
 243 #define NVME_CTRLR_DATA_LPA_NS_SMART_SHIFT              (0)
 244 #define NVME_CTRLR_DATA_LPA_NS_SMART_MASK               (0x1)
 245
 246 /** AVSCC - admin vendor specific command configuration */
 247 /* admin vendor specific commands use spec format */
 248 #define NVME_CTRLR_DATA_AVSCC_SPEC_FORMAT_SHIFT         (0)
 249 #define NVME_CTRLR_DATA_AVSCC_SPEC_FORMAT_MASK          (0x1)
 250
 251 /** Autonomous Power State Transition Attributes */
 252 /* Autonomous Power State Transitions supported */
 253 #define NVME_CTRLR_DATA_APSTA_APST_SUPP_SHIFT           (0)
 254 #define NVME_CTRLR_DATA_APSTA_APST_SUPP_MASK            (0x1)
 255
 256 /** Sanitize Capabilities */
 257 /* Crypto Erase Support  */
 258 #define NVME_CTRLR_DATA_SANICAP_CES_SHIFT               (0)
 259 #define NVME_CTRLR_DATA_SANICAP_CES_MASK                (0x1)
 260 /* Block Erase Support */
 261 #define NVME_CTRLR_DATA_SANICAP_BES_SHIFT               (1)
 262 #define NVME_CTRLR_DATA_SANICAP_BES_MASK                (0x1)
 263 /* Overwrite Support */
 264 #define NVME_CTRLR_DATA_SANICAP_OWS_SHIFT               (2)
 265 #define NVME_CTRLR_DATA_SANICAP_OWS_MASK                (0x1)
 266 /* No-Deallocate Inhibited  */
 267 #define NVME_CTRLR_DATA_SANICAP_NDI_SHIFT               (29)
 268 #define NVME_CTRLR_DATA_SANICAP_NDI_MASK                (0x1)
 269 /* No-Deallocate Modifies Media After Sanitize */
 270 #define NVME_CTRLR_DATA_SANICAP_NODMMAS_SHIFT           (30)
 271 #define NVME_CTRLR_DATA_SANICAP_NODMMAS_MASK            (0x3)
 272 #define NVME_CTRLR_DATA_SANICAP_NODMMAS_UNDEF           (0)
 273 #define NVME_CTRLR_DATA_SANICAP_NODMMAS_NO              (1)
 274 #define NVME_CTRLR_DATA_SANICAP_NODMMAS_YES             (2)
 275
 276 /** submission queue entry size */
 277 #define NVME_CTRLR_DATA_SQES_MIN_SHIFT                  (0)
 278 #define NVME_CTRLR_DATA_SQES_MIN_MASK                   (0xF)
 279 #define NVME_CTRLR_DATA_SQES_MAX_SHIFT                  (4)
 280 #define NVME_CTRLR_DATA_SQES_MAX_MASK                   (0xF)
 281
 282 /** completion queue entry size */
 283 #define NVME_CTRLR_DATA_CQES_MIN_SHIFT                  (0)
 284 #define NVME_CTRLR_DATA_CQES_MIN_MASK                   (0xF)
 285 #define NVME_CTRLR_DATA_CQES_MAX_SHIFT                  (4)
 286 #define NVME_CTRLR_DATA_CQES_MAX_MASK                   (0xF)
 287
 288 /** optional nvm command support */
 289 #define NVME_CTRLR_DATA_ONCS_COMPARE_SHIFT              (0)
 290 #define NVME_CTRLR_DATA_ONCS_COMPARE_MASK               (0x1)
 291 #define NVME_CTRLR_DATA_ONCS_WRITE_UNC_SHIFT            (1)
 292 #define NVME_CTRLR_DATA_ONCS_WRITE_UNC_MASK             (0x1)
 293 #define NVME_CTRLR_DATA_ONCS_DSM_SHIFT                  (2)
 294 #define NVME_CTRLR_DATA_ONCS_DSM_MASK                   (0x1)
 295 #define NVME_CTRLR_DATA_ONCS_WRZERO_SHIFT               (3)
 296 #define NVME_CTRLR_DATA_ONCS_WRZERO_MASK                (0x1)
 297 #define NVME_CTRLR_DATA_ONCS_SAVEFEAT_SHIFT             (4)
 298 #define NVME_CTRLR_DATA_ONCS_SAVEFEAT_MASK              (0x1)
 299 #define NVME_CTRLR_DATA_ONCS_RESERV_SHIFT               (5)
 300 #define NVME_CTRLR_DATA_ONCS_RESERV_MASK                (0x1)
 301 #define NVME_CTRLR_DATA_ONCS_TIMESTAMP_SHIFT            (6)
 302 #define NVME_CTRLR_DATA_ONCS_TIMESTAMP_MASK             (0x1)
 303 #define NVME_CTRLR_DATA_ONCS_VERIFY_SHIFT               (7)
 304 #define NVME_CTRLR_DATA_ONCS_VERIFY_MASK                (0x1)
 305
 306 /** Fused Operation Support */
 307 #define NVME_CTRLR_DATA_FUSES_CNW_SHIFT         (0)
 308 #define NVME_CTRLR_DATA_FUSES_CNW_MASK          (0x1)
 309
 310 /** Format NVM Attributes */
 311 #define NVME_CTRLR_DATA_FNA_FORMAT_ALL_SHIFT            (0)
 312 #define NVME_CTRLR_DATA_FNA_FORMAT_ALL_MASK             (0x1)
 313 #define NVME_CTRLR_DATA_FNA_ERASE_ALL_SHIFT             (1)
 314 #define NVME_CTRLR_DATA_FNA_ERASE_ALL_MASK              (0x1)
 315 #define NVME_CTRLR_DATA_FNA_CRYPTO_ERASE_SHIFT          (2)
 316 #define NVME_CTRLR_DATA_FNA_CRYPTO_ERASE_MASK           (0x1)
 317
 318 /** volatile write cache */
 319 /* volatile write cache present */
 320 #define NVME_CTRLR_DATA_VWC_PRESENT_SHIFT               (0)
 321 #define NVME_CTRLR_DATA_VWC_PRESENT_MASK                (0x1)
 322 /* flush all namespaces supported */
 323 #define NVME_CTRLR_DATA_VWC_ALL_SHIFT                   (1)
 324 #define NVME_CTRLR_DATA_VWC_ALL_MASK                    (0x3)
 325 #define NVME_CTRLR_DATA_VWC_ALL_UNKNOWN                 (0)
 326 #define NVME_CTRLR_DATA_VWC_ALL_NO                      (2)
 327 #define NVME_CTRLR_DATA_VWC_ALL_YES                     (3)
 328
 329 /** namespace features */
 330 /* thin provisioning */
 331 #define NVME_NS_DATA_NSFEAT_THIN_PROV_SHIFT             (0)
 332 #define NVME_NS_DATA_NSFEAT_THIN_PROV_MASK              (0x1)
 333 /* NAWUN, NAWUPF, and NACWU fields are valid */
 334 #define NVME_NS_DATA_NSFEAT_NA_FIELDS_SHIFT             (1)
 335 #define NVME_NS_DATA_NSFEAT_NA_FIELDS_MASK              (0x1)
 336 /* Deallocated or Unwritten Logical Block errors supported */
 337 #define NVME_NS_DATA_NSFEAT_DEALLOC_SHIFT               (2)
 338 #define NVME_NS_DATA_NSFEAT_DEALLOC_MASK                (0x1)
 339 /* NGUID and EUI64 fields are not reusable */
 340 #define NVME_NS_DATA_NSFEAT_NO_ID_REUSE_SHIFT           (3)
 341 #define NVME_NS_DATA_NSFEAT_NO_ID_REUSE_MASK            (0x1)
 342 /* NPWG, NPWA, NPDG, NPDA, and NOWS are valid */
 343 #define NVME_NS_DATA_NSFEAT_NPVALID_SHIFT               (4)
 344 #define NVME_NS_DATA_NSFEAT_NPVALID_MASK                (0x1)
 345
 346 /** formatted lba size */
 347 #define NVME_NS_DATA_FLBAS_FORMAT_SHIFT                 (0)
 348 #define NVME_NS_DATA_FLBAS_FORMAT_MASK                  (0xF)
 349 #define NVME_NS_DATA_FLBAS_EXTENDED_SHIFT               (4)
 350 #define NVME_NS_DATA_FLBAS_EXTENDED_MASK                (0x1)
 351
 352 /** metadata capabilities */
 353 /* metadata can be transferred as part of data prp list */
 354 #define NVME_NS_DATA_MC_EXTENDED_SHIFT                  (0)
 355 #define NVME_NS_DATA_MC_EXTENDED_MASK                   (0x1)
 356 /* metadata can be transferred with separate metadata pointer */
 357 #define NVME_NS_DATA_MC_POINTER_SHIFT                   (1)
 358 #define NVME_NS_DATA_MC_POINTER_MASK                    (0x1)
 359
 360 /** end-to-end data protection capabilities */
 361 /* protection information type 1 */
 362 #define NVME_NS_DATA_DPC_PIT1_SHIFT                     (0)
 363 #define NVME_NS_DATA_DPC_PIT1_MASK                      (0x1)
 364 /* protection information type 2 */
 365 #define NVME_NS_DATA_DPC_PIT2_SHIFT                     (1)
 366 #define NVME_NS_DATA_DPC_PIT2_MASK                      (0x1)
 367 /* protection information type 3 */
 368 #define NVME_NS_DATA_DPC_PIT3_SHIFT                     (2)
 369 #define NVME_NS_DATA_DPC_PIT3_MASK                      (0x1)
 370 /* first eight bytes of metadata */
 371 #define NVME_NS_DATA_DPC_MD_START_SHIFT                 (3)
 372 #define NVME_NS_DATA_DPC_MD_START_MASK                  (0x1)
 373 /* last eight bytes of metadata */
 374 #define NVME_NS_DATA_DPC_MD_END_SHIFT                   (4)
 375 #define NVME_NS_DATA_DPC_MD_END_MASK                    (0x1)
 376
 377 /** end-to-end data protection type settings */
 378 /* protection information type */
 379 #define NVME_NS_DATA_DPS_PIT_SHIFT                      (0)
 380 #define NVME_NS_DATA_DPS_PIT_MASK                       (0x7)
 381 /* 1 == protection info transferred at start of metadata */
 382 /* 0 == protection info transferred at end of metadata */
 383 #define NVME_NS_DATA_DPS_MD_START_SHIFT                 (3)
 384 #define NVME_NS_DATA_DPS_MD_START_MASK                  (0x1)
 385
 386 /** Namespace Multi-path I/O and Namespace Sharing Capabilities */
 387 /* the namespace may be attached to two or more controllers */
 388 #define NVME_NS_DATA_NMIC_MAY_BE_SHARED_SHIFT           (0)
 389 #define NVME_NS_DATA_NMIC_MAY_BE_SHARED_MASK            (0x1)
 390
 391 /** Reservation Capabilities */
 392 /* Persist Through Power Loss */
 393 #define NVME_NS_DATA_RESCAP_PTPL_SHIFT          (0)
 394 #define NVME_NS_DATA_RESCAP_PTPL_MASK           (0x1)
 395 /* supports the Write Exclusive */
 396 #define NVME_NS_DATA_RESCAP_WR_EX_SHIFT         (1)
 397 #define NVME_NS_DATA_RESCAP_WR_EX_MASK          (0x1)
 398 /* supports the Exclusive Access */
 399 #define NVME_NS_DATA_RESCAP_EX_AC_SHIFT         (2)
 400 #define NVME_NS_DATA_RESCAP_EX_AC_MASK          (0x1)
 401 /* supports the Write Exclusive – Registrants Only */
 402 #define NVME_NS_DATA_RESCAP_WR_EX_RO_SHIFT      (3)
 403 #define NVME_NS_DATA_RESCAP_WR_EX_RO_MASK       (0x1)
 404 /* supports the Exclusive Access - Registrants Only */
 405 #define NVME_NS_DATA_RESCAP_EX_AC_RO_SHIFT      (4)
 406 #define NVME_NS_DATA_RESCAP_EX_AC_RO_MASK       (0x1)
 407 /* supports the Write Exclusive – All Registrants */
 408 #define NVME_NS_DATA_RESCAP_WR_EX_AR_SHIFT      (5)
 409 #define NVME_NS_DATA_RESCAP_WR_EX_AR_MASK       (0x1)
 410 /* supports the Exclusive Access - All Registrants */
 411 #define NVME_NS_DATA_RESCAP_EX_AC_AR_SHIFT      (6)
 412 #define NVME_NS_DATA_RESCAP_EX_AC_AR_MASK       (0x1)
 413 /* Ignore Existing Key is used as defined in revision 1.3 or later */
 414 #define NVME_NS_DATA_RESCAP_IEKEY13_SHIFT       (7)
 415 #define NVME_NS_DATA_RESCAP_IEKEY13_MASK        (0x1)
 416
 417 /** Format Progress Indicator */
 418 /* percentage of the Format NVM command that remains to be completed */
 419 #define NVME_NS_DATA_FPI_PERC_SHIFT             (0)
 420 #define NVME_NS_DATA_FPI_PERC_MASK              (0x7f)
 421 /* namespace supports the Format Progress Indicator */
 422 #define NVME_NS_DATA_FPI_SUPP_SHIFT             (7)
 423 #define NVME_NS_DATA_FPI_SUPP_MASK              (0x1)
 424
 425 /** Deallocate Logical Block Features */
 426 /* deallocated logical block read behavior */
 427 #define NVME_NS_DATA_DLFEAT_READ_SHIFT          (0)
 428 #define NVME_NS_DATA_DLFEAT_READ_MASK           (0x07)
 429 #define NVME_NS_DATA_DLFEAT_READ_NR             (0x00)
 430 #define NVME_NS_DATA_DLFEAT_READ_00             (0x01)
 431 #define NVME_NS_DATA_DLFEAT_READ_FF             (0x02)
 432 /* supports the Deallocate bit in the Write Zeroes */
 433 #define NVME_NS_DATA_DLFEAT_DWZ_SHIFT           (3)
 434 #define NVME_NS_DATA_DLFEAT_DWZ_MASK            (0x01)
 435 /* Guard field for deallocated logical blocks is set to the CRC  */
 436 #define NVME_NS_DATA_DLFEAT_GCRC_SHIFT          (4)
 437 #define NVME_NS_DATA_DLFEAT_GCRC_MASK           (0x01)
 438
 439 /** lba format support */
 440 /* metadata size */
 441 #define NVME_NS_DATA_LBAF_MS_SHIFT                      (0)
 442 #define NVME_NS_DATA_LBAF_MS_MASK                       (0xFFFF)
 443 /* lba data size */
 444 #define NVME_NS_DATA_LBAF_LBADS_SHIFT                   (16)
 445 #define NVME_NS_DATA_LBAF_LBADS_MASK                    (0xFF)
 446 /* relative performance */
 447 #define NVME_NS_DATA_LBAF_RP_SHIFT                      (24)
 448 #define NVME_NS_DATA_LBAF_RP_MASK                       (0x3)
 449
 450 enum nvme_critical_warning_state {
 451         NVME_CRIT_WARN_ST_AVAILABLE_SPARE               = 0x1,
 452         NVME_CRIT_WARN_ST_TEMPERATURE                   = 0x2,
 453         NVME_CRIT_WARN_ST_DEVICE_RELIABILITY            = 0x4,
 454         NVME_CRIT_WARN_ST_READ_ONLY                     = 0x8,
 455         NVME_CRIT_WARN_ST_VOLATILE_MEMORY_BACKUP        = 0x10,
 456 };
 457 #define NVME_CRIT_WARN_ST_RESERVED_MASK                 (0xE0)
 458 #define NVME_ASYNC_EVENT_NS_ATTRIBUTE                   (0x100)
 459 #define NVME_ASYNC_EVENT_FW_ACTIVATE                    (0x200)
 460
 461 /* slot for current FW */
 462 #define NVME_FIRMWARE_PAGE_AFI_SLOT_SHIFT               (0)
 463 #define NVME_FIRMWARE_PAGE_AFI_SLOT_MASK                (0x7)
 464
 465 /* Commands Supported and Effects */
 466 #define NVME_CE_PAGE_CSUP_SHIFT                         (0)
 467 #define NVME_CE_PAGE_CSUP_MASK                          (0x1)
 468 #define NVME_CE_PAGE_LBCC_SHIFT                         (1)
 469 #define NVME_CE_PAGE_LBCC_MASK                          (0x1)
 470 #define NVME_CE_PAGE_NCC_SHIFT                          (2)
 471 #define NVME_CE_PAGE_NCC_MASK                           (0x1)
 472 #define NVME_CE_PAGE_NIC_SHIFT                          (3)
 473 #define NVME_CE_PAGE_NIC_MASK                           (0x1)
 474 #define NVME_CE_PAGE_CCC_SHIFT                          (4)
 475 #define NVME_CE_PAGE_CCC_MASK                           (0x1)
 476 #define NVME_CE_PAGE_CSE_SHIFT                          (16)
 477 #define NVME_CE_PAGE_CSE_MASK                           (0x7)
 478 #define NVME_CE_PAGE_UUID_SHIFT                         (19)
 479 #define NVME_CE_PAGE_UUID_MASK                          (0x1)
 480
 481 /* Sanitize Status */
 482 #define NVME_SS_PAGE_SSTAT_STATUS_SHIFT                 (0)
 483 #define NVME_SS_PAGE_SSTAT_STATUS_MASK                  (0x7)
 484 #define NVME_SS_PAGE_SSTAT_STATUS_NEVER                 (0)
 485 #define NVME_SS_PAGE_SSTAT_STATUS_COMPLETED             (1)
 486 #define NVME_SS_PAGE_SSTAT_STATUS_INPROG                (2)
 487 #define NVME_SS_PAGE_SSTAT_STATUS_FAILED                (3)
 488 #define NVME_SS_PAGE_SSTAT_STATUS_COMPLETEDWD           (4)
 489 #define NVME_SS_PAGE_SSTAT_PASSES_SHIFT                 (3)
 490 #define NVME_SS_PAGE_SSTAT_PASSES_MASK                  (0x1f)
 491 #define NVME_SS_PAGE_SSTAT_GDE_SHIFT                    (8)
 492 #define NVME_SS_PAGE_SSTAT_GDE_MASK                     (0x1)
 493
 494 /* CC register SHN field values */
 495 enum shn_value {
 496         NVME_SHN_NORMAL         = 0x1,
 497         NVME_SHN_ABRUPT         = 0x2,
 498 };
 499
 500 /* CSTS register SHST field values */
 501 enum shst_value {
 502         NVME_SHST_NORMAL        = 0x0,
 503         NVME_SHST_OCCURRING     = 0x1,
 504         NVME_SHST_COMPLETE      = 0x2,
 505 };
 506
 507 struct nvme_registers
 508 {
 509         uint32_t        cap_lo; /* controller capabilities */
 510         uint32_t        cap_hi;
 511         uint32_t        vs;     /* version */
 512         uint32_t        intms;  /* interrupt mask set */
 513         uint32_t        intmc;  /* interrupt mask clear */
 514         uint32_t        cc;     /* controller configuration */
 515         uint32_t        reserved1;
 516         uint32_t        csts;   /* controller status */
 517         uint32_t        nssr;   /* NVM Subsystem Reset */
 518         uint32_t        aqa;    /* admin queue attributes */
 519         uint64_t        asq;    /* admin submission queue base addr */
 520         uint64_t        acq;    /* admin completion queue base addr */
 521         uint32_t        cmbloc; /* Controller Memory Buffer Location */
 522         uint32_t        cmbsz;  /* Controller Memory Buffer Size */
 523         uint32_t        bpinfo; /* Boot Partition Information */
 524         uint32_t        bprsel; /* Boot Partition Read Select */
 525         uint64_t        bpmbl;  /* Boot Partition Memory Buffer Location */
 526         uint64_t        cmbmsc; /* Controller Memory Buffer Memory Space Control */
 527         uint32_t        cmbsts; /* Controller Memory Buffer Status */
 528         uint8_t         reserved3[3492]; /* 5Ch - DFFh */
 529         uint32_t        pmrcap; /* Persistent Memory Capabilities */
 530         uint32_t        pmrctl; /* Persistent Memory Region Control */
 531         uint32_t        pmrsts; /* Persistent Memory Region Status */
 532         uint32_t        pmrebs; /* Persistent Memory Region Elasticity Buffer Size */
 533         uint32_t        pmrswtp; /* Persistent Memory Region Sustained Write Throughput */
 534         uint32_t        pmrmsc_lo; /* Persistent Memory Region Controller Memory Space Control */
 535         uint32_t        pmrmsc_hi;
 536         uint8_t         reserved4[484]; /* E1Ch - FFFh */
 537         struct {
 538             uint32_t    sq_tdbl; /* submission queue tail doorbell */
 539             uint32_t    cq_hdbl; /* completion queue head doorbell */
 540         } doorbell[1] __packed;
 541 } __packed;
 542
 543 _Static_assert(sizeof(struct nvme_registers) == 0x1008, "bad size for nvme_registers");
 544
 545 struct nvme_command
 546 {
 547         /* dword 0 */
 548         uint8_t opc;            /* opcode */
 549         uint8_t fuse;           /* fused operation */
 550         uint16_t cid;           /* command identifier */
 551
 552         /* dword 1 */
 553         uint32_t nsid;          /* namespace identifier */
 554
 555         /* dword 2-3 */
 556         uint32_t rsvd2;
 557         uint32_t rsvd3;
 558
 559         /* dword 4-5 */
 560         uint64_t mptr;          /* metadata pointer */
 561
 562         /* dword 6-7 */
 563         uint64_t prp1;          /* prp entry 1 */
 564
 565         /* dword 8-9 */
 566         uint64_t prp2;          /* prp entry 2 */
 567
 568         /* dword 10-15 */
 569         uint32_t cdw10;         /* command-specific */
 570         uint32_t cdw11;         /* command-specific */
 571         uint32_t cdw12;         /* command-specific */
 572         uint32_t cdw13;         /* command-specific */
 573         uint32_t cdw14;         /* command-specific */
 574         uint32_t cdw15;         /* command-specific */
 575 } __packed;
 576
 577 _Static_assert(sizeof(struct nvme_command) == 16 * 4, "bad size for nvme_command");
 578
 579 struct nvme_completion {
 580         /* dword 0 */
 581         uint32_t                cdw0;   /* command-specific */
 582
 583         /* dword 1 */
 584         uint32_t                rsvd1;
 585
 586         /* dword 2 */
 587         uint16_t                sqhd;   /* submission queue head pointer */
 588         uint16_t                sqid;   /* submission queue identifier */
 589
 590         /* dword 3 */
 591         uint16_t                cid;    /* command identifier */
 592         uint16_t                status;
 593 } __packed;
 594
 595 _Static_assert(sizeof(struct nvme_completion) == 4 * 4, "bad size for nvme_completion");
 596
 597 struct nvme_dsm_range {
 598         uint32_t attributes;
 599         uint32_t length;
 600         uint64_t starting_lba;
 601 } __packed;
 602
 603 /* Largest DSM Trim that can be done */
 604 #define NVME_MAX_DSM_TRIM               4096
 605
 606 _Static_assert(sizeof(struct nvme_dsm_range) == 16, "bad size for nvme_dsm_ranage");
 607
 608 /* status code types */
 609 enum nvme_status_code_type {
 610         NVME_SCT_GENERIC                = 0x0,
 611         NVME_SCT_COMMAND_SPECIFIC       = 0x1,
 612         NVME_SCT_MEDIA_ERROR            = 0x2,
 613         NVME_SCT_PATH_RELATED           = 0x3,
 614         /* 0x3-0x6 - reserved */
 615         NVME_SCT_VENDOR_SPECIFIC        = 0x7,
 616 };
 617
 618 /* generic command status codes */
 619 enum nvme_generic_command_status_code {
 620         NVME_SC_SUCCESS                         = 0x00,
 621         NVME_SC_INVALID_OPCODE                  = 0x01,
 622         NVME_SC_INVALID_FIELD                   = 0x02,
 623         NVME_SC_COMMAND_ID_CONFLICT             = 0x03,
 624         NVME_SC_DATA_TRANSFER_ERROR             = 0x04,
 625         NVME_SC_ABORTED_POWER_LOSS              = 0x05,
 626         NVME_SC_INTERNAL_DEVICE_ERROR           = 0x06,
 627         NVME_SC_ABORTED_BY_REQUEST              = 0x07,
 628         NVME_SC_ABORTED_SQ_DELETION             = 0x08,
 629         NVME_SC_ABORTED_FAILED_FUSED            = 0x09,
 630         NVME_SC_ABORTED_MISSING_FUSED           = 0x0a,
 631         NVME_SC_INVALID_NAMESPACE_OR_FORMAT     = 0x0b,
 632         NVME_SC_COMMAND_SEQUENCE_ERROR          = 0x0c,
 633         NVME_SC_INVALID_SGL_SEGMENT_DESCR       = 0x0d,
 634         NVME_SC_INVALID_NUMBER_OF_SGL_DESCR     = 0x0e,
 635         NVME_SC_DATA_SGL_LENGTH_INVALID         = 0x0f,
 636         NVME_SC_METADATA_SGL_LENGTH_INVALID     = 0x10,
 637         NVME_SC_SGL_DESCRIPTOR_TYPE_INVALID     = 0x11,
 638         NVME_SC_INVALID_USE_OF_CMB              = 0x12,
 639         NVME_SC_PRP_OFFET_INVALID               = 0x13,
 640         NVME_SC_ATOMIC_WRITE_UNIT_EXCEEDED      = 0x14,
 641         NVME_SC_OPERATION_DENIED                = 0x15,
 642         NVME_SC_SGL_OFFSET_INVALID              = 0x16,
 643         /* 0x17 - reserved */
 644         NVME_SC_HOST_ID_INCONSISTENT_FORMAT     = 0x18,
 645         NVME_SC_KEEP_ALIVE_TIMEOUT_EXPIRED      = 0x19,
 646         NVME_SC_KEEP_ALIVE_TIMEOUT_INVALID      = 0x1a,
 647         NVME_SC_ABORTED_DUE_TO_PREEMPT          = 0x1b,
 648         NVME_SC_SANITIZE_FAILED                 = 0x1c,
 649         NVME_SC_SANITIZE_IN_PROGRESS            = 0x1d,
 650         NVME_SC_SGL_DATA_BLOCK_GRAN_INVALID     = 0x1e,
 651         NVME_SC_NOT_SUPPORTED_IN_CMB            = 0x1f,
 652         NVME_SC_NAMESPACE_IS_WRITE_PROTECTED    = 0x20,
 653         NVME_SC_COMMAND_INTERRUPTED             = 0x21,
 654         NVME_SC_TRANSIENT_TRANSPORT_ERROR       = 0x22,
 655
 656         NVME_SC_LBA_OUT_OF_RANGE                = 0x80,
 657         NVME_SC_CAPACITY_EXCEEDED               = 0x81,
 658         NVME_SC_NAMESPACE_NOT_READY             = 0x82,
 659         NVME_SC_RESERVATION_CONFLICT            = 0x83,
 660         NVME_SC_FORMAT_IN_PROGRESS              = 0x84,
 661 };
 662
 663 /* command specific status codes */
 664 enum nvme_command_specific_status_code {
 665         NVME_SC_COMPLETION_QUEUE_INVALID        = 0x00,
 666         NVME_SC_INVALID_QUEUE_IDENTIFIER        = 0x01,
 667         NVME_SC_MAXIMUM_QUEUE_SIZE_EXCEEDED     = 0x02,
 668         NVME_SC_ABORT_COMMAND_LIMIT_EXCEEDED    = 0x03,
 669         /* 0x04 - reserved */
 670         NVME_SC_ASYNC_EVENT_REQUEST_LIMIT_EXCEEDED = 0x05,
 671         NVME_SC_INVALID_FIRMWARE_SLOT           = 0x06,
 672         NVME_SC_INVALID_FIRMWARE_IMAGE          = 0x07,
 673         NVME_SC_INVALID_INTERRUPT_VECTOR        = 0x08,
 674         NVME_SC_INVALID_LOG_PAGE                = 0x09,
 675         NVME_SC_INVALID_FORMAT                  = 0x0a,
 676         NVME_SC_FIRMWARE_REQUIRES_RESET         = 0x0b,
 677         NVME_SC_INVALID_QUEUE_DELETION          = 0x0c,
 678         NVME_SC_FEATURE_NOT_SAVEABLE            = 0x0d,
 679         NVME_SC_FEATURE_NOT_CHANGEABLE          = 0x0e,
 680         NVME_SC_FEATURE_NOT_NS_SPECIFIC         = 0x0f,
 681         NVME_SC_FW_ACT_REQUIRES_NVMS_RESET      = 0x10,
 682         NVME_SC_FW_ACT_REQUIRES_RESET           = 0x11,
 683         NVME_SC_FW_ACT_REQUIRES_TIME            = 0x12,
 684         NVME_SC_FW_ACT_PROHIBITED               = 0x13,
 685         NVME_SC_OVERLAPPING_RANGE               = 0x14,
 686         NVME_SC_NS_INSUFFICIENT_CAPACITY        = 0x15,
 687         NVME_SC_NS_ID_UNAVAILABLE               = 0x16,
 688         /* 0x17 - reserved */
 689         NVME_SC_NS_ALREADY_ATTACHED             = 0x18,
 690         NVME_SC_NS_IS_PRIVATE                   = 0x19,
 691         NVME_SC_NS_NOT_ATTACHED                 = 0x1a,
 692         NVME_SC_THIN_PROV_NOT_SUPPORTED         = 0x1b,
 693         NVME_SC_CTRLR_LIST_INVALID              = 0x1c,
 694         NVME_SC_SELT_TEST_IN_PROGRESS           = 0x1d,
 695         NVME_SC_BOOT_PART_WRITE_PROHIB          = 0x1e,
 696         NVME_SC_INVALID_CTRLR_ID                = 0x1f,
 697         NVME_SC_INVALID_SEC_CTRLR_STATE         = 0x20,
 698         NVME_SC_INVALID_NUM_OF_CTRLR_RESRC      = 0x21,
 699         NVME_SC_INVALID_RESOURCE_ID             = 0x22,
 700         NVME_SC_SANITIZE_PROHIBITED_WPMRE       = 0x23,
 701         NVME_SC_ANA_GROUP_ID_INVALID            = 0x24,
 702         NVME_SC_ANA_ATTACH_FAILED               = 0x25,
 703
 704         NVME_SC_CONFLICTING_ATTRIBUTES          = 0x80,
 705         NVME_SC_INVALID_PROTECTION_INFO         = 0x81,
 706         NVME_SC_ATTEMPTED_WRITE_TO_RO_PAGE      = 0x82,
 707 };
 708
 709 /* media error status codes */
 710 enum nvme_media_error_status_code {
 711         NVME_SC_WRITE_FAULTS                    = 0x80,
 712         NVME_SC_UNRECOVERED_READ_ERROR          = 0x81,
 713         NVME_SC_GUARD_CHECK_ERROR               = 0x82,
 714         NVME_SC_APPLICATION_TAG_CHECK_ERROR     = 0x83,
 715         NVME_SC_REFERENCE_TAG_CHECK_ERROR       = 0x84,
 716         NVME_SC_COMPARE_FAILURE                 = 0x85,
 717         NVME_SC_ACCESS_DENIED                   = 0x86,
 718         NVME_SC_DEALLOCATED_OR_UNWRITTEN        = 0x87,
 719 };
 720
 721 /* path related status codes */
 722 enum nvme_path_related_status_code {
 723         NVME_SC_INTERNAL_PATH_ERROR             = 0x00,
 724         NVME_SC_ASYMMETRIC_ACCESS_PERSISTENT_LOSS = 0x01,
 725         NVME_SC_ASYMMETRIC_ACCESS_INACCESSIBLE  = 0x02,
 726         NVME_SC_ASYMMETRIC_ACCESS_TRANSITION    = 0x03,
 727         NVME_SC_CONTROLLER_PATHING_ERROR        = 0x60,
 728         NVME_SC_HOST_PATHING_ERROR              = 0x70,
 729         NVME_SC_COMMAND_ABOTHED_BY_HOST         = 0x71,
 730 };
 731
 732 /* admin opcodes */
 733 enum nvme_admin_opcode {
 734         NVME_OPC_DELETE_IO_SQ                   = 0x00,
 735         NVME_OPC_CREATE_IO_SQ                   = 0x01,
 736         NVME_OPC_GET_LOG_PAGE                   = 0x02,
 737         /* 0x03 - reserved */
 738         NVME_OPC_DELETE_IO_CQ                   = 0x04,
 739         NVME_OPC_CREATE_IO_CQ                   = 0x05,
 740         NVME_OPC_IDENTIFY                       = 0x06,
 741         /* 0x07 - reserved */
 742         NVME_OPC_ABORT                          = 0x08,
 743         NVME_OPC_SET_FEATURES                   = 0x09,
 744         NVME_OPC_GET_FEATURES                   = 0x0a,
 745         /* 0x0b - reserved */
 746         NVME_OPC_ASYNC_EVENT_REQUEST            = 0x0c,
 747         NVME_OPC_NAMESPACE_MANAGEMENT           = 0x0d,
 748         /* 0x0e-0x0f - reserved */
 749         NVME_OPC_FIRMWARE_ACTIVATE              = 0x10,
 750         NVME_OPC_FIRMWARE_IMAGE_DOWNLOAD        = 0x11,
 751         /* 0x12-0x13 - reserved */
 752         NVME_OPC_DEVICE_SELF_TEST               = 0x14,
 753         NVME_OPC_NAMESPACE_ATTACHMENT           = 0x15,
 754         /* 0x16-0x17 - reserved */
 755         NVME_OPC_KEEP_ALIVE                     = 0x18,
 756         NVME_OPC_DIRECTIVE_SEND                 = 0x19,
 757         NVME_OPC_DIRECTIVE_RECEIVE              = 0x1a,
 758         /* 0x1b - reserved */
 759         NVME_OPC_VIRTUALIZATION_MANAGEMENT      = 0x1c,
 760         NVME_OPC_NVME_MI_SEND                   = 0x1d,
 761         NVME_OPC_NVME_MI_RECEIVE                = 0x1e,
 762         /* 0x1f-0x7b - reserved */
 763         NVME_OPC_DOORBELL_BUFFER_CONFIG         = 0x7c,
 764
 765         NVME_OPC_FORMAT_NVM                     = 0x80,
 766         NVME_OPC_SECURITY_SEND                  = 0x81,
 767         NVME_OPC_SECURITY_RECEIVE               = 0x82,
 768         /* 0x83 - reserved */
 769         NVME_OPC_SANITIZE                       = 0x84,
 770         /* 0x85 - reserved */
 771         NVME_OPC_GET_LBA_STATUS                 = 0x86,
 772 };
 773
 774 /* nvme nvm opcodes */
 775 enum nvme_nvm_opcode {
 776         NVME_OPC_FLUSH                          = 0x00,
 777         NVME_OPC_WRITE                          = 0x01,
 778         NVME_OPC_READ                           = 0x02,
 779         /* 0x03 - reserved */
 780         NVME_OPC_WRITE_UNCORRECTABLE            = 0x04,
 781         NVME_OPC_COMPARE                        = 0x05,
 782         /* 0x06-0x07 - reserved */
 783         NVME_OPC_WRITE_ZEROES                   = 0x08,
 784         NVME_OPC_DATASET_MANAGEMENT             = 0x09,
 785         /* 0x0a-0x0b - reserved */
 786         NVME_OPC_VERIFY                         = 0x0c,
 787         NVME_OPC_RESERVATION_REGISTER           = 0x0d,
 788         NVME_OPC_RESERVATION_REPORT             = 0x0e,
 789         /* 0x0f-0x10 - reserved */
 790         NVME_OPC_RESERVATION_ACQUIRE            = 0x11,
 791         /* 0x12-0x14 - reserved */
 792         NVME_OPC_RESERVATION_RELEASE            = 0x15,
 793 };
 794
 795 enum nvme_feature {
 796         /* 0x00 - reserved */
 797         NVME_FEAT_ARBITRATION                   = 0x01,
 798         NVME_FEAT_POWER_MANAGEMENT              = 0x02,
 799         NVME_FEAT_LBA_RANGE_TYPE                = 0x03,
 800         NVME_FEAT_TEMPERATURE_THRESHOLD         = 0x04,
 801         NVME_FEAT_ERROR_RECOVERY                = 0x05,
 802         NVME_FEAT_VOLATILE_WRITE_CACHE          = 0x06,
 803         NVME_FEAT_NUMBER_OF_QUEUES              = 0x07,
 804         NVME_FEAT_INTERRUPT_COALESCING          = 0x08,
 805         NVME_FEAT_INTERRUPT_VECTOR_CONFIGURATION = 0x09,
 806         NVME_FEAT_WRITE_ATOMICITY               = 0x0A,
 807         NVME_FEAT_ASYNC_EVENT_CONFIGURATION     = 0x0B,
 808         NVME_FEAT_AUTONOMOUS_POWER_STATE_TRANSITION = 0x0C,
 809         NVME_FEAT_HOST_MEMORY_BUFFER            = 0x0D,
 810         NVME_FEAT_TIMESTAMP                     = 0x0E,
 811         NVME_FEAT_KEEP_ALIVE_TIMER              = 0x0F,
 812         NVME_FEAT_HOST_CONTROLLED_THERMAL_MGMT  = 0x10,
 813         NVME_FEAT_NON_OP_POWER_STATE_CONFIG     = 0x11,
 814         NVME_FEAT_READ_RECOVERY_LEVEL_CONFIG    = 0x12,
 815         NVME_FEAT_PREDICTABLE_LATENCY_MODE_CONFIG = 0x13,
 816         NVME_FEAT_PREDICTABLE_LATENCY_MODE_WINDOW = 0x14,
 817         NVME_FEAT_LBA_STATUS_INFORMATION_ATTRIBUTES = 0x15,
 818         NVME_FEAT_HOST_BEHAVIOR_SUPPORT         = 0x16,
 819         NVME_FEAT_SANITIZE_CONFIG               = 0x17,
 820         NVME_FEAT_ENDURANCE_GROUP_EVENT_CONFIGURATION = 0x18,
 821         /* 0x19-0x77 - reserved */
 822         /* 0x78-0x7f - NVMe Management Interface */
 823         NVME_FEAT_SOFTWARE_PROGRESS_MARKER      = 0x80,
 824         NVME_FEAT_HOST_IDENTIFIER               = 0x81,
 825         NVME_FEAT_RESERVATION_NOTIFICATION_MASK = 0x82,
 826         NVME_FEAT_RESERVATION_PERSISTENCE       = 0x83,
 827         NVME_FEAT_NAMESPACE_WRITE_PROTECTION_CONFIG = 0x84,
 828         /* 0x85-0xBF - command set specific (reserved) */
 829         /* 0xC0-0xFF - vendor specific */
 830 };
 831
 832 enum nvme_dsm_attribute {
 833         NVME_DSM_ATTR_INTEGRAL_READ             = 0x1,
 834         NVME_DSM_ATTR_INTEGRAL_WRITE            = 0x2,
 835         NVME_DSM_ATTR_DEALLOCATE                = 0x4,
 836 };
 837
 838 enum nvme_activate_action {
 839         NVME_AA_REPLACE_NO_ACTIVATE             = 0x0,
 840         NVME_AA_REPLACE_ACTIVATE                = 0x1,
 841         NVME_AA_ACTIVATE                        = 0x2,
 842 };
 843
 844 struct nvme_power_state {
 845         /** Maximum Power */
 846         uint16_t        mp;                     /* Maximum Power */
 847         uint8_t         ps_rsvd1;
 848         uint8_t         mps_nops;               /* Max Power Scale, Non-Operational State */
 849
 850         uint32_t        enlat;                  /* Entry Latency */
 851         uint32_t        exlat;                  /* Exit Latency */
 852
 853         uint8_t         rrt;                    /* Relative Read Throughput */
 854         uint8_t         rrl;                    /* Relative Read Latency */
 855         uint8_t         rwt;                    /* Relative Write Throughput */
 856         uint8_t         rwl;                    /* Relative Write Latency */
 857
 858         uint16_t        idlp;                   /* Idle Power */
 859         uint8_t         ips;                    /* Idle Power Scale */
 860         uint8_t         ps_rsvd8;
 861
 862         uint16_t        actp;                   /* Active Power */
 863         uint8_t         apw_aps;                /* Active Power Workload, Active Power Scale */
 864         uint8_t         ps_rsvd10[9];
 865 } __packed;
 866
 867 _Static_assert(sizeof(struct nvme_power_state) == 32, "bad size for nvme_power_state");
 868
 869 #define NVME_SERIAL_NUMBER_LENGTH       20
 870 #define NVME_MODEL_NUMBER_LENGTH        40
 871 #define NVME_FIRMWARE_REVISION_LENGTH   8
 872
 873 struct nvme_controller_data {
 874         /* bytes 0-255: controller capabilities and features */
 875
 876         /** pci vendor id */
 877         uint16_t                vid;
 878
 879         /** pci subsystem vendor id */
 880         uint16_t                ssvid;
 881
 882         /** serial number */
 883         uint8_t                 sn[NVME_SERIAL_NUMBER_LENGTH];
 884
 885         /** model number */
 886         uint8_t                 mn[NVME_MODEL_NUMBER_LENGTH];
 887
 888         /** firmware revision */
 889         uint8_t                 fr[NVME_FIRMWARE_REVISION_LENGTH];
 890
 891         /** recommended arbitration burst */
 892         uint8_t                 rab;
 893
 894         /** ieee oui identifier */
 895         uint8_t                 ieee[3];
 896
 897         /** multi-interface capabilities */
 898         uint8_t                 mic;
 899
 900         /** maximum data transfer size */
 901         uint8_t                 mdts;
 902
 903         /** Controller ID */
 904         uint16_t                ctrlr_id;
 905
 906         /** Version */
 907         uint32_t                ver;
 908
 909         /** RTD3 Resume Latency */
 910         uint32_t                rtd3r;
 911
 912         /** RTD3 Enter Latency */
 913         uint32_t                rtd3e;
 914
 915         /** Optional Asynchronous Events Supported */
 916         uint32_t                oaes;   /* bitfield really */
 917
 918         /** Controller Attributes */
 919         uint32_t                ctratt; /* bitfield really */
 920
 921         /** Read Recovery Levels Supported */
 922         uint16_t                rrls;
 923
 924         uint8_t                 reserved1[9];
 925
 926         /** Controller Type */
 927         uint8_t                 cntrltype;
 928
 929         /** FRU Globally Unique Identifier */
 930         uint8_t                 fguid[16];
 931
 932         /** Command Retry Delay Time 1 */
 933         uint16_t                crdt1;
 934
 935         /** Command Retry Delay Time 2 */
 936         uint16_t                crdt2;
 937
 938         /** Command Retry Delay Time 3 */
 939         uint16_t                crdt3;
 940
 941         uint8_t                 reserved2[122];
 942
 943         /* bytes 256-511: admin command set attributes */
 944
 945         /** optional admin command support */
 946         uint16_t                oacs;
 947
 948         /** abort command limit */
 949         uint8_t                 acl;
 950
 951         /** asynchronous event request limit */
 952         uint8_t                 aerl;
 953
 954         /** firmware updates */
 955         uint8_t                 frmw;
 956
 957         /** log page attributes */
 958         uint8_t                 lpa;
 959
 960         /** error log page entries */
 961         uint8_t                 elpe;
 962
 963         /** number of power states supported */
 964         uint8_t                 npss;
 965
 966         /** admin vendor specific command configuration */
 967         uint8_t                 avscc;
 968
 969         /** Autonomous Power State Transition Attributes */
 970         uint8_t                 apsta;
 971
 972         /** Warning Composite Temperature Threshold */
 973         uint16_t                wctemp;
 974
 975         /** Critical Composite Temperature Threshold */
 976         uint16_t                cctemp;
 977
 978         /** Maximum Time for Firmware Activation */
 979         uint16_t                mtfa;
 980
 981         /** Host Memory Buffer Preferred Size */
 982         uint32_t                hmpre;
 983
 984         /** Host Memory Buffer Minimum Size */
 985         uint32_t                hmmin;
 986
 987         /** Name space capabilities  */
 988         struct {
 989                 /* if nsmgmt, report tnvmcap and unvmcap */
 990                 uint8_t    tnvmcap[16];
 991                 uint8_t    unvmcap[16];
 992         } __packed untncap;
 993
 994         /** Replay Protected Memory Block Support */
 995         uint32_t                rpmbs; /* Really a bitfield */
 996
 997         /** Extended Device Self-test Time */
 998         uint16_t                edstt;
 999
1000         /** Device Self-test Options */
1001         uint8_t                 dsto; /* Really a bitfield */
1002
1003         /** Firmware Update Granularity */
1004         uint8_t                 fwug;
1005
1006         /** Keep Alive Support */
1007         uint16_t                kas;
1008
1009         /** Host Controlled Thermal Management Attributes */
1010         uint16_t                hctma; /* Really a bitfield */
1011
1012         /** Minimum Thermal Management Temperature */
1013         uint16_t                mntmt;
1014
1015         /** Maximum Thermal Management Temperature */
1016         uint16_t                mxtmt;
1017
1018         /** Sanitize Capabilities */
1019         uint32_t                sanicap; /* Really a bitfield */
1020
1021         /** Host Memory Buffer Minimum Descriptor Entry Size */
1022         uint32_t                hmminds;
1023
1024         /** Host Memory Maximum Descriptors Entries */
1025         uint16_t                hmmaxd;
1026
1027         /** NVM Set Identifier Maximum */
1028         uint16_t                nsetidmax;
1029
1030         /** Endurance Group Identifier Maximum */
1031         uint16_t                endgidmax;
1032
1033         /** ANA Transition Time */
1034         uint8_t                 anatt;
1035
1036         /** Asymmetric Namespace Access Capabilities */
1037         uint8_t                 anacap;
1038
1039         /** ANA Group Identifier Maximum */
1040         uint32_t                anagrpmax;
1041
1042         /** Number of ANA Group Identifiers */
1043         uint32_t                nanagrpid;
1044
1045         /** Persistent Event Log Size */
1046         uint32_t                pels;
1047
1048         uint8_t                 reserved3[156];
1049         /* bytes 512-703: nvm command set attributes */
1050
1051         /** submission queue entry size */
1052         uint8_t                 sqes;
1053
1054         /** completion queue entry size */
1055         uint8_t                 cqes;
1056
1057         /** Maximum Outstanding Commands */
1058         uint16_t                maxcmd;
1059
1060         /** number of namespaces */
1061         uint32_t                nn;
1062
1063         /** optional nvm command support */
1064         uint16_t                oncs;
1065
1066         /** fused operation support */
1067         uint16_t                fuses;
1068
1069         /** format nvm attributes */
1070         uint8_t                 fna;
1071
1072         /** volatile write cache */
1073         uint8_t                 vwc;
1074
1075         /** Atomic Write Unit Normal */
1076         uint16_t                awun;
1077
1078         /** Atomic Write Unit Power Fail */
1079         uint16_t                awupf;
1080
1081         /** NVM Vendor Specific Command Configuration */
1082         uint8_t                 nvscc;
1083
1084         /** Namespace Write Protection Capabilities */
1085         uint8_t                 nwpc;
1086
1087         /** Atomic Compare & Write Unit */
1088         uint16_t                acwu;
1089         uint16_t                reserved6;
1090
1091         /** SGL Support */
1092         uint32_t                sgls;
1093
1094         /** Maximum Number of Allowed Namespaces */
1095         uint32_t                mnan;
1096
1097         /* bytes 540-767: Reserved */
1098         uint8_t                 reserved7[224];
1099
1100         /** NVM Subsystem NVMe Qualified Name */
1101         uint8_t                 subnqn[256];
1102
1103         /* bytes 1024-1791: Reserved */
1104         uint8_t                 reserved8[768];
1105
1106         /* bytes 1792-2047: NVMe over Fabrics specification */
1107         uint8_t                 reserved9[256];
1108
1109         /* bytes 2048-3071: power state descriptors */
1110         struct nvme_power_state power_state[32];
1111
1112         /* bytes 3072-4095: vendor specific */
1113         uint8_t                 vs[1024];
1114 } __packed __aligned(4);
1115
1116 _Static_assert(sizeof(struct nvme_controller_data) == 4096, "bad size for nvme_controller_data");
1117
1118 struct nvme_namespace_data {
1119         /** namespace size */
1120         uint64_t                nsze;
1121
1122         /** namespace capacity */
1123         uint64_t                ncap;
1124
1125         /** namespace utilization */
1126         uint64_t                nuse;
1127
1128         /** namespace features */
1129         uint8_t                 nsfeat;
1130
1131         /** number of lba formats */
1132         uint8_t                 nlbaf;
1133
1134         /** formatted lba size */
1135         uint8_t                 flbas;
1136
1137         /** metadata capabilities */
1138         uint8_t                 mc;
1139
1140         /** end-to-end data protection capabilities */
1141         uint8_t                 dpc;
1142
1143         /** end-to-end data protection type settings */
1144         uint8_t                 dps;
1145
1146         /** Namespace Multi-path I/O and Namespace Sharing Capabilities */
1147         uint8_t                 nmic;
1148
1149         /** Reservation Capabilities */
1150         uint8_t                 rescap;
1151
1152         /** Format Progress Indicator */
1153         uint8_t                 fpi;
1154
1155         /** Deallocate Logical Block Features */
1156         uint8_t                 dlfeat;
1157
1158         /** Namespace Atomic Write Unit Normal  */
1159         uint16_t                nawun;
1160
1161         /** Namespace Atomic Write Unit Power Fail */
1162         uint16_t                nawupf;
1163
1164         /** Namespace Atomic Compare & Write Unit */
1165         uint16_t                nacwu;
1166
1167         /** Namespace Atomic Boundary Size Normal */
1168         uint16_t                nabsn;
1169
1170         /** Namespace Atomic Boundary Offset */
1171         uint16_t                nabo;
1172
1173         /** Namespace Atomic Boundary Size Power Fail */
1174         uint16_t                nabspf;
1175
1176         /** Namespace Optimal IO Boundary */
1177         uint16_t                noiob;
1178
1179         /** NVM Capacity */
1180         uint8_t                 nvmcap[16];
1181
1182         /** Namespace Preferred Write Granularity  */
1183         uint16_t                npwg;
1184
1185         /** Namespace Preferred Write Alignment */
1186         uint16_t                npwa;
1187
1188         /** Namespace Preferred Deallocate Granularity */
1189         uint16_t                npdg;
1190
1191         /** Namespace Preferred Deallocate Alignment */
1192         uint16_t                npda;
1193
1194         /** Namespace Optimal Write Size */
1195         uint16_t                nows;
1196
1197         /* bytes 74-91: Reserved */
1198         uint8_t                 reserved5[18];
1199
1200         /** ANA Group Identifier */
1201         uint32_t                anagrpid;
1202
1203         /* bytes 96-98: Reserved */
1204         uint8_t                 reserved6[3];
1205
1206         /** Namespace Attributes */
1207         uint8_t                 nsattr;
1208
1209         /** NVM Set Identifier */
1210         uint16_t                nvmsetid;
1211
1212         /** Endurance Group Identifier */
1213         uint16_t                endgid;
1214
1215         /** Namespace Globally Unique Identifier */
1216         uint8_t                 nguid[16];
1217
1218         /** IEEE Extended Unique Identifier */
1219         uint8_t                 eui64[8];
1220
1221         /** lba format support */
1222         uint32_t                lbaf[16];
1223
1224         uint8_t                 reserved7[192];
1225
1226         uint8_t                 vendor_specific[3712];
1227 } __packed __aligned(4);
1228
1229 _Static_assert(sizeof(struct nvme_namespace_data) == 4096, "bad size for nvme_namepsace_data");
1230
1231 enum nvme_log_page {
1232         /* 0x00 - reserved */
1233         NVME_LOG_ERROR                  = 0x01,
1234         NVME_LOG_HEALTH_INFORMATION     = 0x02,
1235         NVME_LOG_FIRMWARE_SLOT          = 0x03,
1236         NVME_LOG_CHANGED_NAMESPACE      = 0x04,
1237         NVME_LOG_COMMAND_EFFECT         = 0x05,
1238         NVME_LOG_DEVICE_SELF_TEST       = 0x06,
1239         NVME_LOG_TELEMETRY_HOST_INITIATED = 0x07,
1240         NVME_LOG_TELEMETRY_CONTROLLER_INITIATED = 0x08,
1241         NVME_LOG_ENDURANCE_GROUP_INFORMATION = 0x09,
1242         NVME_LOG_PREDICTABLE_LATENCY_PER_NVM_SET = 0x0a,
1243         NVME_LOG_PREDICTABLE_LATENCY_EVENT_AGGREGATE = 0x0b,
1244         NVME_LOG_ASYMMETRIC_NAMESPAVE_ACCESS = 0x0c,
1245         NVME_LOG_PERSISTENT_EVENT_LOG   = 0x0d,
1246         NVME_LOG_LBA_STATUS_INFORMATION = 0x0e,
1247         NVME_LOG_ENDURANCE_GROUP_EVENT_AGGREGATE = 0x0f,
1248         /* 0x06-0x7F - reserved */
1249         /* 0x80-0xBF - I/O command set specific */
1250         NVME_LOG_RES_NOTIFICATION       = 0x80,
1251         NVME_LOG_SANITIZE_STATUS        = 0x81,
1252         /* 0x82-0xBF - reserved */
1253         /* 0xC0-0xFF - vendor specific */
1254
1255         /*
1256          * The following are Intel Specific log pages, but they seem
1257          * to be widely implemented.
1258          */
1259         INTEL_LOG_READ_LAT_LOG          = 0xc1,
1260         INTEL_LOG_WRITE_LAT_LOG         = 0xc2,
1261         INTEL_LOG_TEMP_STATS            = 0xc5,
1262         INTEL_LOG_ADD_SMART             = 0xca,
1263         INTEL_LOG_DRIVE_MKT_NAME        = 0xdd,
1264
1265         /*
1266          * HGST log page, with lots ofs sub pages.
1267          */
1268         HGST_INFO_LOG                   = 0xc1,
1269 };
1270
1271 struct nvme_error_information_entry {
1272         uint64_t                error_count;
1273         uint16_t                sqid;
1274         uint16_t                cid;
1275         uint16_t                status;
1276         uint16_t                error_location;
1277         uint64_t                lba;
1278         uint32_t                nsid;
1279         uint8_t                 vendor_specific;
1280         uint8_t                 trtype;
1281         uint16_t                reserved30;
1282         uint64_t                csi;
1283         uint16_t                ttsi;
1284         uint8_t                 reserved[22];
1285 } __packed __aligned(4);
1286
1287 _Static_assert(sizeof(struct nvme_error_information_entry) == 64, "bad size for nvme_error_information_entry");
1288
1289 struct nvme_health_information_page {
1290         uint8_t                 critical_warning;
1291         uint16_t                temperature;
1292         uint8_t                 available_spare;
1293         uint8_t                 available_spare_threshold;
1294         uint8_t                 percentage_used;
1295
1296         uint8_t                 reserved[26];
1297
1298         /*
1299          * Note that the following are 128-bit values, but are
1300          *  defined as an array of 2 64-bit values.
1301          */
1302         /* Data Units Read is always in 512-byte units. */
1303         uint64_t                data_units_read[2];
1304         /* Data Units Written is always in 512-byte units. */
1305         uint64_t                data_units_written[2];
1306         /* For NVM command set, this includes Compare commands. */
1307         uint64_t                host_read_commands[2];
1308         uint64_t                host_write_commands[2];
1309         /* Controller Busy Time is reported in minutes. */
1310         uint64_t                controller_busy_time[2];
1311         uint64_t                power_cycles[2];
1312         uint64_t                power_on_hours[2];
1313         uint64_t                unsafe_shutdowns[2];
1314         uint64_t                media_errors[2];
1315         uint64_t                num_error_info_log_entries[2];
1316         uint32_t                warning_temp_time;
1317         uint32_t                error_temp_time;
1318         uint16_t                temp_sensor[8];
1319         /* Thermal Management Temperature 1 Transition Count */
1320         uint32_t                tmt1tc;
1321         /* Thermal Management Temperature 2 Transition Count */
1322         uint32_t                tmt2tc;
1323         /* Total Time For Thermal Management Temperature 1 */
1324         uint32_t                ttftmt1;
1325         /* Total Time For Thermal Management Temperature 2 */
1326         uint32_t                ttftmt2;
1327
1328         uint8_t                 reserved2[280];
1329 } __packed __aligned(4);
1330
1331 _Static_assert(sizeof(struct nvme_health_information_page) == 512, "bad size for nvme_health_information_page");
1332
1333 struct nvme_firmware_page {
1334         uint8_t                 afi;
1335         uint8_t                 reserved[7];
1336         uint64_t                revision[7]; /* revisions for 7 slots */
1337         uint8_t                 reserved2[448];
1338 } __packed __aligned(4);
1339
1340 _Static_assert(sizeof(struct nvme_firmware_page) == 512, "bad size for nvme_firmware_page");
1341
1342 struct nvme_ns_list {
1343         uint32_t                ns[1024];
1344 } __packed __aligned(4);
1345
1346 _Static_assert(sizeof(struct nvme_ns_list) == 4096, "bad size for nvme_ns_list");
1347
1348 struct nvme_command_effects_page {
1349         uint32_t                acs[256];
1350         uint32_t                iocs[256];
1351         uint8_t                 reserved[2048];
1352 } __packed __aligned(4);
1353
1354 _Static_assert(sizeof(struct nvme_command_effects_page) == 4096,
1355     "bad size for nvme_command_effects_page");
1356
1357 struct nvme_res_notification_page {
1358         uint64_t                log_page_count;
1359         uint8_t                 log_page_type;
1360         uint8_t                 available_log_pages;
1361         uint8_t                 reserved2;
1362         uint32_t                nsid;
1363         uint8_t                 reserved[48];
1364 } __packed __aligned(4);
1365
1366 _Static_assert(sizeof(struct nvme_res_notification_page) == 64,
1367     "bad size for nvme_res_notification_page");
1368
1369 struct nvme_sanitize_status_page {
1370         uint16_t                sprog;
1371         uint16_t                sstat;
1372         uint32_t                scdw10;
1373         uint32_t                etfo;
1374         uint32_t                etfbe;
1375         uint32_t                etfce;
1376         uint32_t                etfownd;
1377         uint32_t                etfbewnd;
1378         uint32_t                etfcewnd;
1379         uint8_t                 reserved[480];
1380 } __packed __aligned(4);
1381
1382 _Static_assert(sizeof(struct nvme_sanitize_status_page) == 512,
1383     "bad size for nvme_sanitize_status_page");
1384
1385 struct intel_log_temp_stats
1386 {
1387         uint64_t        current;
1388         uint64_t        overtemp_flag_last;
1389         uint64_t        overtemp_flag_life;
1390         uint64_t        max_temp;
1391         uint64_t        min_temp;
1392         uint64_t        _rsvd[5];
1393         uint64_t        max_oper_temp;
1394         uint64_t        min_oper_temp;
1395         uint64_t        est_offset;
1396 } __packed __aligned(4);
1397
1398 _Static_assert(sizeof(struct intel_log_temp_stats) == 13 * 8, "bad size for intel_log_temp_stats");
1399
1400 struct nvme_resv_reg_ctrlr
1401 {
1402         uint16_t                ctrlr_id;       /* Controller ID */
1403         uint8_t                 rcsts;          /* Reservation Status */
1404         uint8_t                 reserved3[5];
1405         uint64_t                hostid;         /* Host Identifier */
1406         uint64_t                rkey;           /* Reservation Key */
1407 } __packed __aligned(4);
1408
1409 _Static_assert(sizeof(struct nvme_resv_reg_ctrlr) == 24, "bad size for nvme_resv_reg_ctrlr");
1410
1411 struct nvme_resv_reg_ctrlr_ext
1412 {
1413         uint16_t                ctrlr_id;       /* Controller ID */
1414         uint8_t                 rcsts;          /* Reservation Status */
1415         uint8_t                 reserved3[5];
1416         uint64_t                rkey;           /* Reservation Key */
1417         uint64_t                hostid[2];      /* Host Identifier */
1418         uint8_t                 reserved32[32];
1419 } __packed __aligned(4);
1420
1421 _Static_assert(sizeof(struct nvme_resv_reg_ctrlr_ext) == 64, "bad size for nvme_resv_reg_ctrlr_ext");
1422
1423 struct nvme_resv_status
1424 {
1425         uint32_t                gen;            /* Generation */
1426         uint8_t                 rtype;          /* Reservation Type */
1427         uint8_t                 regctl[2];      /* Number of Registered Controllers */
1428         uint8_t                 reserved7[2];
1429         uint8_t                 ptpls;          /* Persist Through Power Loss State */
1430         uint8_t                 reserved10[14];
1431         struct nvme_resv_reg_ctrlr      ctrlr[0];
1432 } __packed __aligned(4);
1433
1434 _Static_assert(sizeof(struct nvme_resv_status) == 24, "bad size for nvme_resv_status");
1435
1436 struct nvme_resv_status_ext
1437 {
1438         uint32_t                gen;            /* Generation */
1439         uint8_t                 rtype;          /* Reservation Type */
1440         uint8_t                 regctl[2];      /* Number of Registered Controllers */
1441         uint8_t                 reserved7[2];
1442         uint8_t                 ptpls;          /* Persist Through Power Loss State */
1443         uint8_t                 reserved10[14];
1444         uint8_t                 reserved24[40];
1445         struct nvme_resv_reg_ctrlr_ext  ctrlr[0];
1446 } __packed __aligned(4);
1447
1448 _Static_assert(sizeof(struct nvme_resv_status_ext) == 64, "bad size for nvme_resv_status_ext");
1449
1450 #define NVME_TEST_MAX_THREADS   128
1451
1452 struct nvme_io_test {
1453         enum nvme_nvm_opcode    opc;
1454         uint32_t                size;
1455         uint32_t                time;   /* in seconds */
1456         uint32_t                num_threads;
1457         uint32_t                flags;
1458         uint64_t                io_completed[NVME_TEST_MAX_THREADS];
1459 };
1460
1461 enum nvme_io_test_flags {
1462         /*
1463          * Specifies whether dev_refthread/dev_relthread should be
1464          *  called during NVME_BIO_TEST.  Ignored for other test
1465          *  types.
1466          */
1467         NVME_TEST_FLAG_REFTHREAD =      0x1,
1468 };
1469
1470 struct nvme_pt_command {
1471         /*
1472          * cmd is used to specify a passthrough command to a controller or
1473          *  namespace.
1474          *
1475          * The following fields from cmd may be specified by the caller:
1476          *      * opc  (opcode)
1477          *      * nsid (namespace id) - for admin commands only
1478          *      * cdw10-cdw15
1479          *
1480          * Remaining fields must be set to 0 by the caller.
1481          */
1482         struct nvme_command     cmd;
1483
1484         /*
1485          * cpl returns completion status for the passthrough command
1486          *  specified by cmd.
1487          *
1488          * The following fields will be filled out by the driver, for
1489          *  consumption by the caller:
1490          *      * cdw0
1491          *      * status (except for phase)
1492          *
1493          * Remaining fields will be set to 0 by the driver.
1494          */
1495         struct nvme_completion  cpl;
1496
1497         /* buf is the data buffer associated with this passthrough command. */
1498         void *                  buf;
1499
1500         /*
1501          * len is the length of the data buffer associated with this
1502          *  passthrough command.
1503          */
1504         uint32_t                len;
1505
1506         /*
1507          * is_read = 1 if the passthrough command will read data into the
1508          *  supplied buffer from the controller.
1509          *
1510          * is_read = 0 if the passthrough command will write data from the
1511          *  supplied buffer to the controller.
1512          */
1513         uint32_t                is_read;
1514
1515         /*
1516          * driver_lock is used by the driver only.  It must be set to 0
1517          *  by the caller.
1518          */
1519         struct mtx *            driver_lock;
1520 };
1521
1522 struct nvme_get_nsid {
1523         char            cdev[SPECNAMELEN + 1];
1524         uint32_t        nsid;
1525 };
1526
1527 struct nvme_hmb_desc {
1528         uint64_t        addr;
1529         uint32_t        size;
1530         uint32_t        reserved;
1531 };
1532
1533 #define nvme_completion_is_error(cpl)                                   \
1534         (NVME_STATUS_GET_SC((cpl)->status) != 0 || NVME_STATUS_GET_SCT((cpl)->status) != 0)
1535
1536 void    nvme_strvis(uint8_t *dst, const uint8_t *src, int dstlen, int srclen);
1537
1538 #ifdef _KERNEL
1539
1540 struct bio;
1541 struct thread;
1542
1543 struct nvme_namespace;
1544 struct nvme_controller;
1545 struct nvme_consumer;
1546
1547 typedef void (*nvme_cb_fn_t)(void *, const struct nvme_completion *);
1548
1549 typedef void *(*nvme_cons_ns_fn_t)(struct nvme_namespace *, void *);
1550 typedef void *(*nvme_cons_ctrlr_fn_t)(struct nvme_controller *);
1551 typedef void (*nvme_cons_async_fn_t)(void *, const struct nvme_completion *,
1552                                      uint32_t, void *, uint32_t);
1553 typedef void (*nvme_cons_fail_fn_t)(void *);
1554
1555 enum nvme_namespace_flags {
1556         NVME_NS_DEALLOCATE_SUPPORTED    = 0x1,
1557         NVME_NS_FLUSH_SUPPORTED         = 0x2,
1558 };
1559
1560 int     nvme_ctrlr_passthrough_cmd(struct nvme_controller *ctrlr,
1561                                    struct nvme_pt_command *pt,
1562                                    uint32_t nsid, int is_user_buffer,
1563                                    int is_admin_cmd);
1564
1565 /* Admin functions */
1566 void    nvme_ctrlr_cmd_set_feature(struct nvme_controller *ctrlr,
1567                                    uint8_t feature, uint32_t cdw11,
1568                                    uint32_t cdw12, uint32_t cdw13,
1569                                    uint32_t cdw14, uint32_t cdw15,
1570                                    void *payload, uint32_t payload_size,
1571                                    nvme_cb_fn_t cb_fn, void *cb_arg);
1572 void    nvme_ctrlr_cmd_get_feature(struct nvme_controller *ctrlr,
1573                                    uint8_t feature, uint32_t cdw11,
1574                                    void *payload, uint32_t payload_size,
1575                                    nvme_cb_fn_t cb_fn, void *cb_arg);
1576 void    nvme_ctrlr_cmd_get_log_page(struct nvme_controller *ctrlr,
1577                                     uint8_t log_page, uint32_t nsid,
1578                                     void *payload, uint32_t payload_size,
1579                                     nvme_cb_fn_t cb_fn, void *cb_arg);
1580
1581 /* NVM I/O functions */
1582 int     nvme_ns_cmd_write(struct nvme_namespace *ns, void *payload,
1583                           uint64_t lba, uint32_t lba_count, nvme_cb_fn_t cb_fn,
1584                           void *cb_arg);
1585 int     nvme_ns_cmd_write_bio(struct nvme_namespace *ns, struct bio *bp,
1586                               nvme_cb_fn_t cb_fn, void *cb_arg);
1587 int     nvme_ns_cmd_read(struct nvme_namespace *ns, void *payload,
1588                          uint64_t lba, uint32_t lba_count, nvme_cb_fn_t cb_fn,
1589                          void *cb_arg);
1590 int     nvme_ns_cmd_read_bio(struct nvme_namespace *ns, struct bio *bp,
1591                               nvme_cb_fn_t cb_fn, void *cb_arg);
1592 int     nvme_ns_cmd_deallocate(struct nvme_namespace *ns, void *payload,
1593                                uint8_t num_ranges, nvme_cb_fn_t cb_fn,
1594                                void *cb_arg);
1595 int     nvme_ns_cmd_flush(struct nvme_namespace *ns, nvme_cb_fn_t cb_fn,
1596                           void *cb_arg);
1597 int     nvme_ns_dump(struct nvme_namespace *ns, void *virt, off_t offset,
1598                      size_t len);
1599
1600 /* Registration functions */
1601 struct nvme_consumer *  nvme_register_consumer(nvme_cons_ns_fn_t    ns_fn,
1602                                                nvme_cons_ctrlr_fn_t ctrlr_fn,
1603                                                nvme_cons_async_fn_t async_fn,
1604                                                nvme_cons_fail_fn_t  fail_fn);
1605 void            nvme_unregister_consumer(struct nvme_consumer *consumer);
1606
1607 /* Controller helper functions */
1608 device_t        nvme_ctrlr_get_device(struct nvme_controller *ctrlr);
1609 const struct nvme_controller_data *
1610                 nvme_ctrlr_get_data(struct nvme_controller *ctrlr);
1611 static inline bool
1612 nvme_ctrlr_has_dataset_mgmt(const struct nvme_controller_data *cd)
1613 {
1614         /* Assumes cd was byte swapped by nvme_controller_data_swapbytes() */
1615         return ((cd->oncs >> NVME_CTRLR_DATA_ONCS_DSM_SHIFT) &
1616                 NVME_CTRLR_DATA_ONCS_DSM_MASK);
1617 }
1618
1619 /* Namespace helper functions */
1620 uint32_t        nvme_ns_get_max_io_xfer_size(struct nvme_namespace *ns);
1621 uint32_t        nvme_ns_get_sector_size(struct nvme_namespace *ns);
1622 uint64_t        nvme_ns_get_num_sectors(struct nvme_namespace *ns);
1623 uint64_t        nvme_ns_get_size(struct nvme_namespace *ns);
1624 uint32_t        nvme_ns_get_flags(struct nvme_namespace *ns);
1625 const char *    nvme_ns_get_serial_number(struct nvme_namespace *ns);
1626 const char *    nvme_ns_get_model_number(struct nvme_namespace *ns);
1627 const struct nvme_namespace_data *
1628                 nvme_ns_get_data(struct nvme_namespace *ns);
1629 uint32_t        nvme_ns_get_stripesize(struct nvme_namespace *ns);
1630
1631 int     nvme_ns_bio_process(struct nvme_namespace *ns, struct bio *bp,
1632                             nvme_cb_fn_t cb_fn);
1633 int     nvme_ns_ioctl_process(struct nvme_namespace *ns, u_long cmd,
1634     caddr_t arg, int flag, struct thread *td);
1635
1636 /*
1637  * Command building helper functions -- shared with CAM
1638  * These functions assume allocator zeros out cmd structure
1639  * CAM's xpt_get_ccb and the request allocator for nvme both
1640  * do zero'd allocations.
1641  */
1642 static inline
1643 void    nvme_ns_flush_cmd(struct nvme_command *cmd, uint32_t nsid)
1644 {
1645
1646         cmd->opc = NVME_OPC_FLUSH;
1647         cmd->nsid = htole32(nsid);
1648 }
1649
1650 static inline
1651 void    nvme_ns_rw_cmd(struct nvme_command *cmd, uint32_t rwcmd, uint32_t nsid,
1652     uint64_t lba, uint32_t count)
1653 {
1654         cmd->opc = rwcmd;
1655         cmd->nsid = htole32(nsid);
1656         cmd->cdw10 = htole32(lba & 0xffffffffu);
1657         cmd->cdw11 = htole32(lba >> 32);
1658         cmd->cdw12 = htole32(count-1);
1659 }
1660
1661 static inline
1662 void    nvme_ns_write_cmd(struct nvme_command *cmd, uint32_t nsid,
1663     uint64_t lba, uint32_t count)
1664 {
1665         nvme_ns_rw_cmd(cmd, NVME_OPC_WRITE, nsid, lba, count);
1666 }
1667
1668 static inline
1669 void    nvme_ns_read_cmd(struct nvme_command *cmd, uint32_t nsid,
1670     uint64_t lba, uint32_t count)
1671 {
1672         nvme_ns_rw_cmd(cmd, NVME_OPC_READ, nsid, lba, count);
1673 }
1674
1675 static inline
1676 void    nvme_ns_trim_cmd(struct nvme_command *cmd, uint32_t nsid,
1677     uint32_t num_ranges)
1678 {
1679         cmd->opc = NVME_OPC_DATASET_MANAGEMENT;
1680         cmd->nsid = htole32(nsid);
1681         cmd->cdw10 = htole32(num_ranges - 1);
1682         cmd->cdw11 = htole32(NVME_DSM_ATTR_DEALLOCATE);
1683 }
1684
1685 extern int nvme_use_nvd;
1686
1687 #endif /* _KERNEL */
1688
1689 /* Endianess conversion functions for NVMe structs */
1690 static inline
1691 void    nvme_completion_swapbytes(struct nvme_completion *s)
1692 {
1693
1694         s->cdw0 = le32toh(s->cdw0);
1695         /* omit rsvd1 */
1696         s->sqhd = le16toh(s->sqhd);
1697         s->sqid = le16toh(s->sqid);
1698         /* omit cid */
1699         s->status = le16toh(s->status);
1700 }
1701
1702 static inline
1703 void    nvme_power_state_swapbytes(struct nvme_power_state *s)
1704 {
1705
1706         s->mp = le16toh(s->mp);
1707         s->enlat = le32toh(s->enlat);
1708         s->exlat = le32toh(s->exlat);
1709         s->idlp = le16toh(s->idlp);
1710         s->actp = le16toh(s->actp);
1711 }
1712
1713 static inline
1714 void    nvme_controller_data_swapbytes(struct nvme_controller_data *s)
1715 {
1716         int i;
1717
1718         s->vid = le16toh(s->vid);
1719         s->ssvid = le16toh(s->ssvid);
1720         s->ctrlr_id = le16toh(s->ctrlr_id);
1721         s->ver = le32toh(s->ver);
1722         s->rtd3r = le32toh(s->rtd3r);
1723         s->rtd3e = le32toh(s->rtd3e);
1724         s->oaes = le32toh(s->oaes);
1725         s->ctratt = le32toh(s->ctratt);
1726         s->rrls = le16toh(s->rrls);
1727         s->crdt1 = le16toh(s->crdt1);
1728         s->crdt2 = le16toh(s->crdt2);
1729         s->crdt3 = le16toh(s->crdt3);
1730         s->oacs = le16toh(s->oacs);
1731         s->wctemp = le16toh(s->wctemp);
1732         s->cctemp = le16toh(s->cctemp);
1733         s->mtfa = le16toh(s->mtfa);
1734         s->hmpre = le32toh(s->hmpre);
1735         s->hmmin = le32toh(s->hmmin);
1736         s->rpmbs = le32toh(s->rpmbs);
1737         s->edstt = le16toh(s->edstt);
1738         s->kas = le16toh(s->kas);
1739         s->hctma = le16toh(s->hctma);
1740         s->mntmt = le16toh(s->mntmt);
1741         s->mxtmt = le16toh(s->mxtmt);
1742         s->sanicap = le32toh(s->sanicap);
1743         s->hmminds = le32toh(s->hmminds);
1744         s->hmmaxd = le16toh(s->hmmaxd);
1745         s->nsetidmax = le16toh(s->nsetidmax);
1746         s->endgidmax = le16toh(s->endgidmax);
1747         s->anagrpmax = le32toh(s->anagrpmax);
1748         s->nanagrpid = le32toh(s->nanagrpid);
1749         s->pels = le32toh(s->pels);
1750         s->maxcmd = le16toh(s->maxcmd);
1751         s->nn = le32toh(s->nn);
1752         s->oncs = le16toh(s->oncs);
1753         s->fuses = le16toh(s->fuses);
1754         s->awun = le16toh(s->awun);
1755         s->awupf = le16toh(s->awupf);
1756         s->acwu = le16toh(s->acwu);
1757         s->sgls = le32toh(s->sgls);
1758         s->mnan = le32toh(s->mnan);
1759         for (i = 0; i < 32; i++)
1760                 nvme_power_state_swapbytes(&s->power_state[i]);
1761 }
1762
1763 static inline
1764 void    nvme_namespace_data_swapbytes(struct nvme_namespace_data *s)
1765 {
1766         int i;
1767
1768         s->nsze = le64toh(s->nsze);
1769         s->ncap = le64toh(s->ncap);
1770         s->nuse = le64toh(s->nuse);
1771         s->nawun = le16toh(s->nawun);
1772         s->nawupf = le16toh(s->nawupf);
1773         s->nacwu = le16toh(s->nacwu);
1774         s->nabsn = le16toh(s->nabsn);
1775         s->nabo = le16toh(s->nabo);
1776         s->nabspf = le16toh(s->nabspf);
1777         s->noiob = le16toh(s->noiob);
1778         s->npwg = le16toh(s->npwg);
1779         s->npwa = le16toh(s->npwa);
1780         s->npdg = le16toh(s->npdg);
1781         s->npda = le16toh(s->npda);
1782         s->nows = le16toh(s->nows);
1783         s->anagrpid = le32toh(s->anagrpid);
1784         s->nvmsetid = le16toh(s->nvmsetid);
1785         s->endgid = le16toh(s->endgid);
1786         for (i = 0; i < 16; i++)
1787                 s->lbaf[i] = le32toh(s->lbaf[i]);
1788 }
1789
1790 static inline
1791 void    nvme_error_information_entry_swapbytes(struct nvme_error_information_entry *s)
1792 {
1793
1794         s->error_count = le64toh(s->error_count);
1795         s->sqid = le16toh(s->sqid);
1796         s->cid = le16toh(s->cid);
1797         s->status = le16toh(s->status);
1798         s->error_location = le16toh(s->error_location);
1799         s->lba = le64toh(s->lba);
1800         s->nsid = le32toh(s->nsid);
1801         s->csi = le64toh(s->csi);
1802         s->ttsi = le16toh(s->ttsi);
1803 }
1804
1805 static inline
1806 void    nvme_le128toh(void *p)
1807 {
1808 #if _BYTE_ORDER != _LITTLE_ENDIAN
1809         /* Swap 16 bytes in place */
1810         char *tmp = (char*)p;
1811         char b;
1812         int i;
1813         for (i = 0; i < 8; i++) {
1814                 b = tmp[i];
1815                 tmp[i] = tmp[15-i];
1816                 tmp[15-i] = b;
1817         }
1818 #else
1819         (void)p;
1820 #endif
1821 }
1822
1823 static inline
1824 void    nvme_health_information_page_swapbytes(struct nvme_health_information_page *s)
1825 {
1826         int i;
1827
1828         s->temperature = le16toh(s->temperature);
1829         nvme_le128toh((void *)s->data_units_read);
1830         nvme_le128toh((void *)s->data_units_written);
1831         nvme_le128toh((void *)s->host_read_commands);
1832         nvme_le128toh((void *)s->host_write_commands);
1833         nvme_le128toh((void *)s->controller_busy_time);
1834         nvme_le128toh((void *)s->power_cycles);
1835         nvme_le128toh((void *)s->power_on_hours);
1836         nvme_le128toh((void *)s->unsafe_shutdowns);
1837         nvme_le128toh((void *)s->media_errors);
1838         nvme_le128toh((void *)s->num_error_info_log_entries);
1839         s->warning_temp_time = le32toh(s->warning_temp_time);
1840         s->error_temp_time = le32toh(s->error_temp_time);
1841         for (i = 0; i < 8; i++)
1842                 s->temp_sensor[i] = le16toh(s->temp_sensor[i]);
1843         s->tmt1tc = le32toh(s->tmt1tc);
1844         s->tmt2tc = le32toh(s->tmt2tc);
1845         s->ttftmt1 = le32toh(s->ttftmt1);
1846         s->ttftmt2 = le32toh(s->ttftmt2);
1847 }
1848
1849 static inline
1850 void    nvme_firmware_page_swapbytes(struct nvme_firmware_page *s)
1851 {
1852         int i;
1853
1854         for (i = 0; i < 7; i++)
1855                 s->revision[i] = le64toh(s->revision[i]);
1856 }
1857
1858 static inline
1859 void    nvme_ns_list_swapbytes(struct nvme_ns_list *s)
1860 {
1861         int i;
1862
1863         for (i = 0; i < 1024; i++)
1864                 s->ns[i] = le32toh(s->ns[i]);
1865 }
1866
1867 static inline
1868 void    nvme_command_effects_page_swapbytes(struct nvme_command_effects_page *s)
1869 {
1870         int i;
1871
1872         for (i = 0; i < 256; i++)
1873                 s->acs[i] = le32toh(s->acs[i]);
1874         for (i = 0; i < 256; i++)
1875                 s->iocs[i] = le32toh(s->iocs[i]);
1876 }
1877
1878 static inline
1879 void    nvme_res_notification_page_swapbytes(struct nvme_res_notification_page *s)
1880 {
1881         s->log_page_count = le64toh(s->log_page_count);
1882         s->nsid = le32toh(s->nsid);
1883 }
1884
1885 static inline
1886 void    nvme_sanitize_status_page_swapbytes(struct nvme_sanitize_status_page *s)
1887 {
1888         s->sprog = le16toh(s->sprog);
1889         s->sstat = le16toh(s->sstat);
1890         s->scdw10 = le32toh(s->scdw10);
1891         s->etfo = le32toh(s->etfo);
1892         s->etfbe = le32toh(s->etfbe);
1893         s->etfce = le32toh(s->etfce);
1894         s->etfownd = le32toh(s->etfownd);
1895         s->etfbewnd = le32toh(s->etfbewnd);
1896         s->etfcewnd = le32toh(s->etfcewnd);
1897 }
1898
1899 static inline
1900 void    intel_log_temp_stats_swapbytes(struct intel_log_temp_stats *s)
1901 {
1902
1903         s->current = le64toh(s->current);
1904         s->overtemp_flag_last = le64toh(s->overtemp_flag_last);
1905         s->overtemp_flag_life = le64toh(s->overtemp_flag_life);
1906         s->max_temp = le64toh(s->max_temp);
1907         s->min_temp = le64toh(s->min_temp);
1908         /* omit _rsvd[] */
1909         s->max_oper_temp = le64toh(s->max_oper_temp);
1910         s->min_oper_temp = le64toh(s->min_oper_temp);
1911         s->est_offset = le64toh(s->est_offset);
1912 }
1913
1914 static inline
1915 void    nvme_resv_status_swapbytes(struct nvme_resv_status *s, size_t size)
1916 {
1917         u_int i, n;
1918
1919         s->gen = le32toh(s->gen);
1920         n = (s->regctl[1] << 8) | s->regctl[0];
1921         n = MIN(n, (size - sizeof(s)) / sizeof(s->ctrlr[0]));
1922         for (i = 0; i < n; i++) {
1923                 s->ctrlr[i].ctrlr_id = le16toh(s->ctrlr[i].ctrlr_id);
1924                 s->ctrlr[i].hostid = le64toh(s->ctrlr[i].hostid);
1925                 s->ctrlr[i].rkey = le64toh(s->ctrlr[i].rkey);
1926         }
1927 }
1928
1929 static inline
1930 void    nvme_resv_status_ext_swapbytes(struct nvme_resv_status_ext *s, size_t size)
1931 {
1932         u_int i, n;
1933
1934         s->gen = le32toh(s->gen);
1935         n = (s->regctl[1] << 8) | s->regctl[0];
1936         n = MIN(n, (size - sizeof(s)) / sizeof(s->ctrlr[0]));
1937         for (i = 0; i < n; i++) {
1938                 s->ctrlr[i].ctrlr_id = le16toh(s->ctrlr[i].ctrlr_id);
1939                 s->ctrlr[i].rkey = le64toh(s->ctrlr[i].rkey);
1940                 nvme_le128toh((void *)s->ctrlr[i].hostid);
1941         }
1942 }
1943
1944 #endif /* __NVME_H__ */