sys/dev/nvme/nvme.h

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (C) 2012-2013 Intel Corporation
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  *
  28  * $FreeBSD$
  29  */
  30
  31 #ifndef __NVME_H__
  32 #define __NVME_H__
  33
  34 #ifdef _KERNEL
  35 #include <sys/types.h>
  36 #endif
  37
  38 #include <sys/param.h>
  39 #include <sys/endian.h>
  40
  41 #define NVME_PASSTHROUGH_CMD            _IOWR('n', 0, struct nvme_pt_command)
  42 #define NVME_RESET_CONTROLLER           _IO('n', 1)
  43 #define NVME_GET_NSID                   _IOR('n', 2, struct nvme_get_nsid)
  44 #define NVME_GET_MAX_XFER_SIZE          _IOR('n', 3, uint64_t)
  45
  46 #define NVME_IO_TEST                    _IOWR('n', 100, struct nvme_io_test)
  47 #define NVME_BIO_TEST                   _IOWR('n', 101, struct nvme_io_test)
  48
  49 /*
  50  * Macros to deal with NVME revisions, as defined VS register
  51  */
  52 #define NVME_REV(x, y)                  (((x) << 16) | ((y) << 8))
  53 #define NVME_MAJOR(r)                   (((r) >> 16) & 0xffff)
  54 #define NVME_MINOR(r)                   (((r) >> 8) & 0xff)
  55
  56 /*
  57  * Use to mark a command to apply to all namespaces, or to retrieve global
  58  *  log pages.
  59  */
  60 #define NVME_GLOBAL_NAMESPACE_TAG       ((uint32_t)0xFFFFFFFF)
  61
  62 /* Cap nvme to 1MB transfers driver explodes with larger sizes */
  63 #define NVME_MAX_XFER_SIZE              (MAXPHYS < (1<<20) ? MAXPHYS : (1<<20))
  64
  65 /* Register field definitions */
  66 #define NVME_CAP_LO_REG_MQES_SHIFT                      (0)
  67 #define NVME_CAP_LO_REG_MQES_MASK                       (0xFFFF)
  68 #define NVME_CAP_LO_REG_CQR_SHIFT                       (16)
  69 #define NVME_CAP_LO_REG_CQR_MASK                        (0x1)
  70 #define NVME_CAP_LO_REG_AMS_SHIFT                       (17)
  71 #define NVME_CAP_LO_REG_AMS_MASK                        (0x3)
  72 #define NVME_CAP_LO_REG_TO_SHIFT                        (24)
  73 #define NVME_CAP_LO_REG_TO_MASK                         (0xFF)
  74 #define NVME_CAP_LO_MQES(x) \
  75         (((x) >> NVME_CAP_LO_REG_MQES_SHIFT) & NVME_CAP_LO_REG_MQES_MASK)
  76 #define NVME_CAP_LO_CQR(x) \
  77         (((x) >> NVME_CAP_LO_REG_CQR_SHIFT) & NVME_CAP_LO_REG_CQR_MASK)
  78 #define NVME_CAP_LO_AMS(x) \
  79         (((x) >> NVME_CAP_LO_REG_AMS_SHIFT) & NVME_CAP_LO_REG_AMS_MASK)
  80 #define NVME_CAP_LO_TO(x) \
  81         (((x) >> NVME_CAP_LO_REG_TO_SHIFT) & NVME_CAP_LO_REG_TO_MASK)
  82
  83 #define NVME_CAP_HI_REG_DSTRD_SHIFT                     (0)
  84 #define NVME_CAP_HI_REG_DSTRD_MASK                      (0xF)
  85 #define NVME_CAP_HI_REG_NSSRS_SHIFT                     (4)
  86 #define NVME_CAP_HI_REG_NSSRS_MASK                      (0x1)
  87 #define NVME_CAP_HI_REG_CSS_NVM_SHIFT                   (5)
  88 #define NVME_CAP_HI_REG_CSS_NVM_MASK                    (0x1)
  89 #define NVME_CAP_HI_REG_BPS_SHIFT                       (13)
  90 #define NVME_CAP_HI_REG_BPS_MASK                        (0x1)
  91 #define NVME_CAP_HI_REG_MPSMIN_SHIFT                    (16)
  92 #define NVME_CAP_HI_REG_MPSMIN_MASK                     (0xF)
  93 #define NVME_CAP_HI_REG_MPSMAX_SHIFT                    (20)
  94 #define NVME_CAP_HI_REG_MPSMAX_MASK                     (0xF)
  95 #define NVME_CAP_HI_REG_PMRS_SHIFT                      (24)
  96 #define NVME_CAP_HI_REG_PMRS_MASK                       (0x1)
  97 #define NVME_CAP_HI_REG_CMBS_SHIFT                      (25)
  98 #define NVME_CAP_HI_REG_CMBS_MASK                       (0x1)
  99 #define NVME_CAP_HI_DSTRD(x) \
 100         (((x) >> NVME_CAP_HI_REG_DSTRD_SHIFT) & NVME_CAP_HI_REG_DSTRD_MASK)
 101 #define NVME_CAP_HI_NSSRS(x) \
 102         (((x) >> NVME_CAP_HI_REG_NSSRS_SHIFT) & NVME_CAP_HI_REG_NSSRS_MASK)
 103 #define NVME_CAP_HI_CSS(x) \
 104         (((x) >> NVME_CAP_HI_REG_CSS_NVM_SHIFT) & NVME_CAP_HI_REG_CSS_NVM_MASK)
 105 #define NVME_CAP_HI_BPS(x) \
 106         (((x) >> NVME_CAP_HI_REG_BPS_SHIFT) & NVME_CAP_HI_REG_BPS_MASK)
 107 #define NVME_CAP_HI_MPSMIN(x) \
 108         (((x) >> NVME_CAP_HI_REG_MPSMIN_SHIFT) & NVME_CAP_HI_REG_MPSMIN_MASK)
 109 #define NVME_CAP_HI_MPSMAX(x) \
 110         (((x) >> NVME_CAP_HI_REG_MPSMAX_SHIFT) & NVME_CAP_HI_REG_MPSMAX_MASK)
 111 #define NVME_CAP_HI_PMRS(x) \
 112         (((x) >> NVME_CAP_HI_REG_PMRS_SHIFT) & NVME_CAP_HI_REG_PMRS_MASK)
 113 #define NVME_CAP_HI_CMBS(x) \
 114         (((x) >> NVME_CAP_HI_REG_CMBS_SHIFT) & NVME_CAP_HI_REG_CMBS_MASK)
 115
 116 #define NVME_CC_REG_EN_SHIFT                            (0)
 117 #define NVME_CC_REG_EN_MASK                             (0x1)
 118 #define NVME_CC_REG_CSS_SHIFT                           (4)
 119 #define NVME_CC_REG_CSS_MASK                            (0x7)
 120 #define NVME_CC_REG_MPS_SHIFT                           (7)
 121 #define NVME_CC_REG_MPS_MASK                            (0xF)
 122 #define NVME_CC_REG_AMS_SHIFT                           (11)
 123 #define NVME_CC_REG_AMS_MASK                            (0x7)
 124 #define NVME_CC_REG_SHN_SHIFT                           (14)
 125 #define NVME_CC_REG_SHN_MASK                            (0x3)
 126 #define NVME_CC_REG_IOSQES_SHIFT                        (16)
 127 #define NVME_CC_REG_IOSQES_MASK                         (0xF)
 128 #define NVME_CC_REG_IOCQES_SHIFT                        (20)
 129 #define NVME_CC_REG_IOCQES_MASK                         (0xF)
 130
 131 #define NVME_CSTS_REG_RDY_SHIFT                         (0)
 132 #define NVME_CSTS_REG_RDY_MASK                          (0x1)
 133 #define NVME_CSTS_REG_CFS_SHIFT                         (1)
 134 #define NVME_CSTS_REG_CFS_MASK                          (0x1)
 135 #define NVME_CSTS_REG_SHST_SHIFT                        (2)
 136 #define NVME_CSTS_REG_SHST_MASK                         (0x3)
 137 #define NVME_CSTS_REG_NVSRO_SHIFT                       (4)
 138 #define NVME_CSTS_REG_NVSRO_MASK                        (0x1)
 139 #define NVME_CSTS_REG_PP_SHIFT                          (5)
 140 #define NVME_CSTS_REG_PP_MASK                           (0x1)
 141
 142 #define NVME_CSTS_GET_SHST(csts)                        (((csts) >> NVME_CSTS_REG_SHST_SHIFT) & NVME_CSTS_REG_SHST_MASK)
 143
 144 #define NVME_AQA_REG_ASQS_SHIFT                         (0)
 145 #define NVME_AQA_REG_ASQS_MASK                          (0xFFF)
 146 #define NVME_AQA_REG_ACQS_SHIFT                         (16)
 147 #define NVME_AQA_REG_ACQS_MASK                          (0xFFF)
 148
 149 /* Command field definitions */
 150
 151 #define NVME_CMD_FUSE_SHIFT                             (8)
 152 #define NVME_CMD_FUSE_MASK                              (0x3)
 153
 154 #define NVME_STATUS_P_SHIFT                             (0)
 155 #define NVME_STATUS_P_MASK                              (0x1)
 156 #define NVME_STATUS_SC_SHIFT                            (1)
 157 #define NVME_STATUS_SC_MASK                             (0xFF)
 158 #define NVME_STATUS_SCT_SHIFT                           (9)
 159 #define NVME_STATUS_SCT_MASK                            (0x7)
 160 #define NVME_STATUS_CRD_SHIFT                           (12)
 161 #define NVME_STATUS_CRD_MASK                            (0x3)
 162 #define NVME_STATUS_M_SHIFT                             (14)
 163 #define NVME_STATUS_M_MASK                              (0x1)
 164 #define NVME_STATUS_DNR_SHIFT                           (15)
 165 #define NVME_STATUS_DNR_MASK                            (0x1)
 166
 167 #define NVME_STATUS_GET_P(st)                           (((st) >> NVME_STATUS_P_SHIFT) & NVME_STATUS_P_MASK)
 168 #define NVME_STATUS_GET_SC(st)                          (((st) >> NVME_STATUS_SC_SHIFT) & NVME_STATUS_SC_MASK)
 169 #define NVME_STATUS_GET_SCT(st)                         (((st) >> NVME_STATUS_SCT_SHIFT) & NVME_STATUS_SCT_MASK)
 170 #define NVME_STATUS_GET_M(st)                           (((st) >> NVME_STATUS_M_SHIFT) & NVME_STATUS_M_MASK)
 171 #define NVME_STATUS_GET_DNR(st)                         (((st) >> NVME_STATUS_DNR_SHIFT) & NVME_STATUS_DNR_MASK)
 172
 173 #define NVME_PWR_ST_MPS_SHIFT                           (0)
 174 #define NVME_PWR_ST_MPS_MASK                            (0x1)
 175 #define NVME_PWR_ST_NOPS_SHIFT                          (1)
 176 #define NVME_PWR_ST_NOPS_MASK                           (0x1)
 177 #define NVME_PWR_ST_RRT_SHIFT                           (0)
 178 #define NVME_PWR_ST_RRT_MASK                            (0x1F)
 179 #define NVME_PWR_ST_RRL_SHIFT                           (0)
 180 #define NVME_PWR_ST_RRL_MASK                            (0x1F)
 181 #define NVME_PWR_ST_RWT_SHIFT                           (0)
 182 #define NVME_PWR_ST_RWT_MASK                            (0x1F)
 183 #define NVME_PWR_ST_RWL_SHIFT                           (0)
 184 #define NVME_PWR_ST_RWL_MASK                            (0x1F)
 185 #define NVME_PWR_ST_IPS_SHIFT                           (6)
 186 #define NVME_PWR_ST_IPS_MASK                            (0x3)
 187 #define NVME_PWR_ST_APW_SHIFT                           (0)
 188 #define NVME_PWR_ST_APW_MASK                            (0x7)
 189 #define NVME_PWR_ST_APS_SHIFT                           (6)
 190 #define NVME_PWR_ST_APS_MASK                            (0x3)
 191
 192 /** Controller Multi-path I/O and Namespace Sharing Capabilities */
 193 /* More then one port */
 194 #define NVME_CTRLR_DATA_MIC_MPORTS_SHIFT                (0)
 195 #define NVME_CTRLR_DATA_MIC_MPORTS_MASK                 (0x1)
 196 /* More then one controller */
 197 #define NVME_CTRLR_DATA_MIC_MCTRLRS_SHIFT               (1)
 198 #define NVME_CTRLR_DATA_MIC_MCTRLRS_MASK                (0x1)
 199 /* SR-IOV Virtual Function */
 200 #define NVME_CTRLR_DATA_MIC_SRIOVVF_SHIFT               (2)
 201 #define NVME_CTRLR_DATA_MIC_SRIOVVF_MASK                (0x1)
 202 /* Asymmetric Namespace Access Reporting */
 203 #define NVME_CTRLR_DATA_MIC_ANAR_SHIFT                  (3)
 204 #define NVME_CTRLR_DATA_MIC_ANAR_MASK                   (0x1)
 205
 206 /** OACS - optional admin command support */
 207 /* supports security send/receive commands */
 208 #define NVME_CTRLR_DATA_OACS_SECURITY_SHIFT             (0)
 209 #define NVME_CTRLR_DATA_OACS_SECURITY_MASK              (0x1)
 210 /* supports format nvm command */
 211 #define NVME_CTRLR_DATA_OACS_FORMAT_SHIFT               (1)
 212 #define NVME_CTRLR_DATA_OACS_FORMAT_MASK                (0x1)
 213 /* supports firmware activate/download commands */
 214 #define NVME_CTRLR_DATA_OACS_FIRMWARE_SHIFT             (2)
 215 #define NVME_CTRLR_DATA_OACS_FIRMWARE_MASK              (0x1)
 216 /* supports namespace management commands */
 217 #define NVME_CTRLR_DATA_OACS_NSMGMT_SHIFT               (3)
 218 #define NVME_CTRLR_DATA_OACS_NSMGMT_MASK                (0x1)
 219 /* supports Device Self-test command */
 220 #define NVME_CTRLR_DATA_OACS_SELFTEST_SHIFT             (4)
 221 #define NVME_CTRLR_DATA_OACS_SELFTEST_MASK              (0x1)
 222 /* supports Directives */
 223 #define NVME_CTRLR_DATA_OACS_DIRECTIVES_SHIFT           (5)
 224 #define NVME_CTRLR_DATA_OACS_DIRECTIVES_MASK            (0x1)
 225 /* supports NVMe-MI Send/Receive */
 226 #define NVME_CTRLR_DATA_OACS_NVMEMI_SHIFT               (6)
 227 #define NVME_CTRLR_DATA_OACS_NVMEMI_MASK                (0x1)
 228 /* supports Virtualization Management */
 229 #define NVME_CTRLR_DATA_OACS_VM_SHIFT                   (7)
 230 #define NVME_CTRLR_DATA_OACS_VM_MASK                    (0x1)
 231 /* supports Doorbell Buffer Config */
 232 #define NVME_CTRLR_DATA_OACS_DBBUFFER_SHIFT             (8)
 233 #define NVME_CTRLR_DATA_OACS_DBBUFFER_MASK              (0x1)
 234 /* supports Get LBA Status */
 235 #define NVME_CTRLR_DATA_OACS_GETLBA_SHIFT               (9)
 236 #define NVME_CTRLR_DATA_OACS_GETLBA_MASK                (0x1)
 237
 238 /** firmware updates */
 239 /* first slot is read-only */
 240 #define NVME_CTRLR_DATA_FRMW_SLOT1_RO_SHIFT             (0)
 241 #define NVME_CTRLR_DATA_FRMW_SLOT1_RO_MASK              (0x1)
 242 /* number of firmware slots */
 243 #define NVME_CTRLR_DATA_FRMW_NUM_SLOTS_SHIFT            (1)
 244 #define NVME_CTRLR_DATA_FRMW_NUM_SLOTS_MASK             (0x7)
 245 /* firmware activation without reset */
 246 #define NVME_CTRLR_DATA_FRMW_ACT_WO_RESET_SHIFT         (4)
 247 #define NVME_CTRLR_DATA_FRMW_ACT_WO_RESET_MASK          (0x1)
 248
 249 /** log page attributes */
 250 /* per namespace smart/health log page */
 251 #define NVME_CTRLR_DATA_LPA_NS_SMART_SHIFT              (0)
 252 #define NVME_CTRLR_DATA_LPA_NS_SMART_MASK               (0x1)
 253
 254 /** AVSCC - admin vendor specific command configuration */
 255 /* admin vendor specific commands use spec format */
 256 #define NVME_CTRLR_DATA_AVSCC_SPEC_FORMAT_SHIFT         (0)
 257 #define NVME_CTRLR_DATA_AVSCC_SPEC_FORMAT_MASK          (0x1)
 258
 259 /** Autonomous Power State Transition Attributes */
 260 /* Autonomous Power State Transitions supported */
 261 #define NVME_CTRLR_DATA_APSTA_APST_SUPP_SHIFT           (0)
 262 #define NVME_CTRLR_DATA_APSTA_APST_SUPP_MASK            (0x1)
 263
 264 /** Sanitize Capabilities */
 265 /* Crypto Erase Support  */
 266 #define NVME_CTRLR_DATA_SANICAP_CES_SHIFT               (0)
 267 #define NVME_CTRLR_DATA_SANICAP_CES_MASK                (0x1)
 268 /* Block Erase Support */
 269 #define NVME_CTRLR_DATA_SANICAP_BES_SHIFT               (1)
 270 #define NVME_CTRLR_DATA_SANICAP_BES_MASK                (0x1)
 271 /* Overwrite Support */
 272 #define NVME_CTRLR_DATA_SANICAP_OWS_SHIFT               (2)
 273 #define NVME_CTRLR_DATA_SANICAP_OWS_MASK                (0x1)
 274 /* No-Deallocate Inhibited  */
 275 #define NVME_CTRLR_DATA_SANICAP_NDI_SHIFT               (29)
 276 #define NVME_CTRLR_DATA_SANICAP_NDI_MASK                (0x1)
 277 /* No-Deallocate Modifies Media After Sanitize */
 278 #define NVME_CTRLR_DATA_SANICAP_NODMMAS_SHIFT           (30)
 279 #define NVME_CTRLR_DATA_SANICAP_NODMMAS_MASK            (0x3)
 280 #define NVME_CTRLR_DATA_SANICAP_NODMMAS_UNDEF           (0)
 281 #define NVME_CTRLR_DATA_SANICAP_NODMMAS_NO              (1)
 282 #define NVME_CTRLR_DATA_SANICAP_NODMMAS_YES             (2)
 283
 284 /** submission queue entry size */
 285 #define NVME_CTRLR_DATA_SQES_MIN_SHIFT                  (0)
 286 #define NVME_CTRLR_DATA_SQES_MIN_MASK                   (0xF)
 287 #define NVME_CTRLR_DATA_SQES_MAX_SHIFT                  (4)
 288 #define NVME_CTRLR_DATA_SQES_MAX_MASK                   (0xF)
 289
 290 /** completion queue entry size */
 291 #define NVME_CTRLR_DATA_CQES_MIN_SHIFT                  (0)
 292 #define NVME_CTRLR_DATA_CQES_MIN_MASK                   (0xF)
 293 #define NVME_CTRLR_DATA_CQES_MAX_SHIFT                  (4)
 294 #define NVME_CTRLR_DATA_CQES_MAX_MASK                   (0xF)
 295
 296 /** optional nvm command support */
 297 #define NVME_CTRLR_DATA_ONCS_COMPARE_SHIFT              (0)
 298 #define NVME_CTRLR_DATA_ONCS_COMPARE_MASK               (0x1)
 299 #define NVME_CTRLR_DATA_ONCS_WRITE_UNC_SHIFT            (1)
 300 #define NVME_CTRLR_DATA_ONCS_WRITE_UNC_MASK             (0x1)
 301 #define NVME_CTRLR_DATA_ONCS_DSM_SHIFT                  (2)
 302 #define NVME_CTRLR_DATA_ONCS_DSM_MASK                   (0x1)
 303 #define NVME_CTRLR_DATA_ONCS_WRZERO_SHIFT               (3)
 304 #define NVME_CTRLR_DATA_ONCS_WRZERO_MASK                (0x1)
 305 #define NVME_CTRLR_DATA_ONCS_SAVEFEAT_SHIFT             (4)
 306 #define NVME_CTRLR_DATA_ONCS_SAVEFEAT_MASK              (0x1)
 307 #define NVME_CTRLR_DATA_ONCS_RESERV_SHIFT               (5)
 308 #define NVME_CTRLR_DATA_ONCS_RESERV_MASK                (0x1)
 309 #define NVME_CTRLR_DATA_ONCS_TIMESTAMP_SHIFT            (6)
 310 #define NVME_CTRLR_DATA_ONCS_TIMESTAMP_MASK             (0x1)
 311 #define NVME_CTRLR_DATA_ONCS_VERIFY_SHIFT               (7)
 312 #define NVME_CTRLR_DATA_ONCS_VERIFY_MASK                (0x1)
 313
 314 /** Fused Operation Support */
 315 #define NVME_CTRLR_DATA_FUSES_CNW_SHIFT         (0)
 316 #define NVME_CTRLR_DATA_FUSES_CNW_MASK          (0x1)
 317
 318 /** Format NVM Attributes */
 319 #define NVME_CTRLR_DATA_FNA_FORMAT_ALL_SHIFT            (0)
 320 #define NVME_CTRLR_DATA_FNA_FORMAT_ALL_MASK             (0x1)
 321 #define NVME_CTRLR_DATA_FNA_ERASE_ALL_SHIFT             (1)
 322 #define NVME_CTRLR_DATA_FNA_ERASE_ALL_MASK              (0x1)
 323 #define NVME_CTRLR_DATA_FNA_CRYPTO_ERASE_SHIFT          (2)
 324 #define NVME_CTRLR_DATA_FNA_CRYPTO_ERASE_MASK           (0x1)
 325
 326 /** volatile write cache */
 327 /* volatile write cache present */
 328 #define NVME_CTRLR_DATA_VWC_PRESENT_SHIFT               (0)
 329 #define NVME_CTRLR_DATA_VWC_PRESENT_MASK                (0x1)
 330 /* flush all namespaces supported */
 331 #define NVME_CTRLR_DATA_VWC_ALL_SHIFT                   (1)
 332 #define NVME_CTRLR_DATA_VWC_ALL_MASK                    (0x3)
 333 #define NVME_CTRLR_DATA_VWC_ALL_UNKNOWN                 (0)
 334 #define NVME_CTRLR_DATA_VWC_ALL_NO                      (2)
 335 #define NVME_CTRLR_DATA_VWC_ALL_YES                     (3)
 336
 337 /** namespace features */
 338 /* thin provisioning */
 339 #define NVME_NS_DATA_NSFEAT_THIN_PROV_SHIFT             (0)
 340 #define NVME_NS_DATA_NSFEAT_THIN_PROV_MASK              (0x1)
 341 /* NAWUN, NAWUPF, and NACWU fields are valid */
 342 #define NVME_NS_DATA_NSFEAT_NA_FIELDS_SHIFT             (1)
 343 #define NVME_NS_DATA_NSFEAT_NA_FIELDS_MASK              (0x1)
 344 /* Deallocated or Unwritten Logical Block errors supported */
 345 #define NVME_NS_DATA_NSFEAT_DEALLOC_SHIFT               (2)
 346 #define NVME_NS_DATA_NSFEAT_DEALLOC_MASK                (0x1)
 347 /* NGUID and EUI64 fields are not reusable */
 348 #define NVME_NS_DATA_NSFEAT_NO_ID_REUSE_SHIFT           (3)
 349 #define NVME_NS_DATA_NSFEAT_NO_ID_REUSE_MASK            (0x1)
 350 /* NPWG, NPWA, NPDG, NPDA, and NOWS are valid */
 351 #define NVME_NS_DATA_NSFEAT_NPVALID_SHIFT               (4)
 352 #define NVME_NS_DATA_NSFEAT_NPVALID_MASK                (0x1)
 353
 354 /** formatted lba size */
 355 #define NVME_NS_DATA_FLBAS_FORMAT_SHIFT                 (0)
 356 #define NVME_NS_DATA_FLBAS_FORMAT_MASK                  (0xF)
 357 #define NVME_NS_DATA_FLBAS_EXTENDED_SHIFT               (4)
 358 #define NVME_NS_DATA_FLBAS_EXTENDED_MASK                (0x1)
 359
 360 /** metadata capabilities */
 361 /* metadata can be transferred as part of data prp list */
 362 #define NVME_NS_DATA_MC_EXTENDED_SHIFT                  (0)
 363 #define NVME_NS_DATA_MC_EXTENDED_MASK                   (0x1)
 364 /* metadata can be transferred with separate metadata pointer */
 365 #define NVME_NS_DATA_MC_POINTER_SHIFT                   (1)
 366 #define NVME_NS_DATA_MC_POINTER_MASK                    (0x1)
 367
 368 /** end-to-end data protection capabilities */
 369 /* protection information type 1 */
 370 #define NVME_NS_DATA_DPC_PIT1_SHIFT                     (0)
 371 #define NVME_NS_DATA_DPC_PIT1_MASK                      (0x1)
 372 /* protection information type 2 */
 373 #define NVME_NS_DATA_DPC_PIT2_SHIFT                     (1)
 374 #define NVME_NS_DATA_DPC_PIT2_MASK                      (0x1)
 375 /* protection information type 3 */
 376 #define NVME_NS_DATA_DPC_PIT3_SHIFT                     (2)
 377 #define NVME_NS_DATA_DPC_PIT3_MASK                      (0x1)
 378 /* first eight bytes of metadata */
 379 #define NVME_NS_DATA_DPC_MD_START_SHIFT                 (3)
 380 #define NVME_NS_DATA_DPC_MD_START_MASK                  (0x1)
 381 /* last eight bytes of metadata */
 382 #define NVME_NS_DATA_DPC_MD_END_SHIFT                   (4)
 383 #define NVME_NS_DATA_DPC_MD_END_MASK                    (0x1)
 384
 385 /** end-to-end data protection type settings */
 386 /* protection information type */
 387 #define NVME_NS_DATA_DPS_PIT_SHIFT                      (0)
 388 #define NVME_NS_DATA_DPS_PIT_MASK                       (0x7)
 389 /* 1 == protection info transferred at start of metadata */
 390 /* 0 == protection info transferred at end of metadata */
 391 #define NVME_NS_DATA_DPS_MD_START_SHIFT                 (3)
 392 #define NVME_NS_DATA_DPS_MD_START_MASK                  (0x1)
 393
 394 /** Namespace Multi-path I/O and Namespace Sharing Capabilities */
 395 /* the namespace may be attached to two or more controllers */
 396 #define NVME_NS_DATA_NMIC_MAY_BE_SHARED_SHIFT           (0)
 397 #define NVME_NS_DATA_NMIC_MAY_BE_SHARED_MASK            (0x1)
 398
 399 /** Reservation Capabilities */
 400 /* Persist Through Power Loss */
 401 #define NVME_NS_DATA_RESCAP_PTPL_SHIFT          (0)
 402 #define NVME_NS_DATA_RESCAP_PTPL_MASK           (0x1)
 403 /* supports the Write Exclusive */
 404 #define NVME_NS_DATA_RESCAP_WR_EX_SHIFT         (1)
 405 #define NVME_NS_DATA_RESCAP_WR_EX_MASK          (0x1)
 406 /* supports the Exclusive Access */
 407 #define NVME_NS_DATA_RESCAP_EX_AC_SHIFT         (2)
 408 #define NVME_NS_DATA_RESCAP_EX_AC_MASK          (0x1)
 409 /* supports the Write Exclusive – Registrants Only */
 410 #define NVME_NS_DATA_RESCAP_WR_EX_RO_SHIFT      (3)
 411 #define NVME_NS_DATA_RESCAP_WR_EX_RO_MASK       (0x1)
 412 /* supports the Exclusive Access - Registrants Only */
 413 #define NVME_NS_DATA_RESCAP_EX_AC_RO_SHIFT      (4)
 414 #define NVME_NS_DATA_RESCAP_EX_AC_RO_MASK       (0x1)
 415 /* supports the Write Exclusive – All Registrants */
 416 #define NVME_NS_DATA_RESCAP_WR_EX_AR_SHIFT      (5)
 417 #define NVME_NS_DATA_RESCAP_WR_EX_AR_MASK       (0x1)
 418 /* supports the Exclusive Access - All Registrants */
 419 #define NVME_NS_DATA_RESCAP_EX_AC_AR_SHIFT      (6)
 420 #define NVME_NS_DATA_RESCAP_EX_AC_AR_MASK       (0x1)
 421 /* Ignore Existing Key is used as defined in revision 1.3 or later */
 422 #define NVME_NS_DATA_RESCAP_IEKEY13_SHIFT       (7)
 423 #define NVME_NS_DATA_RESCAP_IEKEY13_MASK        (0x1)
 424
 425 /** Format Progress Indicator */
 426 /* percentage of the Format NVM command that remains to be completed */
 427 #define NVME_NS_DATA_FPI_PERC_SHIFT             (0)
 428 #define NVME_NS_DATA_FPI_PERC_MASK              (0x7f)
 429 /* namespace supports the Format Progress Indicator */
 430 #define NVME_NS_DATA_FPI_SUPP_SHIFT             (7)
 431 #define NVME_NS_DATA_FPI_SUPP_MASK              (0x1)
 432
 433 /** Deallocate Logical Block Features */
 434 /* deallocated logical block read behavior */
 435 #define NVME_NS_DATA_DLFEAT_READ_SHIFT          (0)
 436 #define NVME_NS_DATA_DLFEAT_READ_MASK           (0x07)
 437 #define NVME_NS_DATA_DLFEAT_READ_NR             (0x00)
 438 #define NVME_NS_DATA_DLFEAT_READ_00             (0x01)
 439 #define NVME_NS_DATA_DLFEAT_READ_FF             (0x02)
 440 /* supports the Deallocate bit in the Write Zeroes */
 441 #define NVME_NS_DATA_DLFEAT_DWZ_SHIFT           (3)
 442 #define NVME_NS_DATA_DLFEAT_DWZ_MASK            (0x01)
 443 /* Guard field for deallocated logical blocks is set to the CRC  */
 444 #define NVME_NS_DATA_DLFEAT_GCRC_SHIFT          (4)
 445 #define NVME_NS_DATA_DLFEAT_GCRC_MASK           (0x01)
 446
 447 /** lba format support */
 448 /* metadata size */
 449 #define NVME_NS_DATA_LBAF_MS_SHIFT                      (0)
 450 #define NVME_NS_DATA_LBAF_MS_MASK                       (0xFFFF)
 451 /* lba data size */
 452 #define NVME_NS_DATA_LBAF_LBADS_SHIFT                   (16)
 453 #define NVME_NS_DATA_LBAF_LBADS_MASK                    (0xFF)
 454 /* relative performance */
 455 #define NVME_NS_DATA_LBAF_RP_SHIFT                      (24)
 456 #define NVME_NS_DATA_LBAF_RP_MASK                       (0x3)
 457
 458 enum nvme_critical_warning_state {
 459         NVME_CRIT_WARN_ST_AVAILABLE_SPARE               = 0x1,
 460         NVME_CRIT_WARN_ST_TEMPERATURE                   = 0x2,
 461         NVME_CRIT_WARN_ST_DEVICE_RELIABILITY            = 0x4,
 462         NVME_CRIT_WARN_ST_READ_ONLY                     = 0x8,
 463         NVME_CRIT_WARN_ST_VOLATILE_MEMORY_BACKUP        = 0x10,
 464 };
 465 #define NVME_CRIT_WARN_ST_RESERVED_MASK                 (0xE0)
 466 #define NVME_ASYNC_EVENT_NS_ATTRIBUTE                   (0x100)
 467 #define NVME_ASYNC_EVENT_FW_ACTIVATE                    (0x200)
 468
 469 /* slot for current FW */
 470 #define NVME_FIRMWARE_PAGE_AFI_SLOT_SHIFT               (0)
 471 #define NVME_FIRMWARE_PAGE_AFI_SLOT_MASK                (0x7)
 472
 473 /* Commands Supported and Effects */
 474 #define NVME_CE_PAGE_CSUP_SHIFT                         (0)
 475 #define NVME_CE_PAGE_CSUP_MASK                          (0x1)
 476 #define NVME_CE_PAGE_LBCC_SHIFT                         (1)
 477 #define NVME_CE_PAGE_LBCC_MASK                          (0x1)
 478 #define NVME_CE_PAGE_NCC_SHIFT                          (2)
 479 #define NVME_CE_PAGE_NCC_MASK                           (0x1)
 480 #define NVME_CE_PAGE_NIC_SHIFT                          (3)
 481 #define NVME_CE_PAGE_NIC_MASK                           (0x1)
 482 #define NVME_CE_PAGE_CCC_SHIFT                          (4)
 483 #define NVME_CE_PAGE_CCC_MASK                           (0x1)
 484 #define NVME_CE_PAGE_CSE_SHIFT                          (16)
 485 #define NVME_CE_PAGE_CSE_MASK                           (0x7)
 486 #define NVME_CE_PAGE_UUID_SHIFT                         (19)
 487 #define NVME_CE_PAGE_UUID_MASK                          (0x1)
 488
 489 /* Sanitize Status */
 490 #define NVME_SS_PAGE_SSTAT_STATUS_SHIFT                 (0)
 491 #define NVME_SS_PAGE_SSTAT_STATUS_MASK                  (0x7)
 492 #define NVME_SS_PAGE_SSTAT_STATUS_NEVER                 (0)
 493 #define NVME_SS_PAGE_SSTAT_STATUS_COMPLETED             (1)
 494 #define NVME_SS_PAGE_SSTAT_STATUS_INPROG                (2)
 495 #define NVME_SS_PAGE_SSTAT_STATUS_FAILED                (3)
 496 #define NVME_SS_PAGE_SSTAT_STATUS_COMPLETEDWD           (4)
 497 #define NVME_SS_PAGE_SSTAT_PASSES_SHIFT                 (3)
 498 #define NVME_SS_PAGE_SSTAT_PASSES_MASK                  (0x1f)
 499 #define NVME_SS_PAGE_SSTAT_GDE_SHIFT                    (8)
 500 #define NVME_SS_PAGE_SSTAT_GDE_MASK                     (0x1)
 501
 502 /* CC register SHN field values */
 503 enum shn_value {
 504         NVME_SHN_NORMAL         = 0x1,
 505         NVME_SHN_ABRUPT         = 0x2,
 506 };
 507
 508 /* CSTS register SHST field values */
 509 enum shst_value {
 510         NVME_SHST_NORMAL        = 0x0,
 511         NVME_SHST_OCCURRING     = 0x1,
 512         NVME_SHST_COMPLETE      = 0x2,
 513 };
 514
 515 struct nvme_registers
 516 {
 517         uint32_t        cap_lo; /* controller capabilities */
 518         uint32_t        cap_hi;
 519         uint32_t        vs;     /* version */
 520         uint32_t        intms;  /* interrupt mask set */
 521         uint32_t        intmc;  /* interrupt mask clear */
 522         uint32_t        cc;     /* controller configuration */
 523         uint32_t        reserved1;
 524         uint32_t        csts;   /* controller status */
 525         uint32_t        nssr;   /* NVM Subsystem Reset */
 526         uint32_t        aqa;    /* admin queue attributes */
 527         uint64_t        asq;    /* admin submission queue base addr */
 528         uint64_t        acq;    /* admin completion queue base addr */
 529         uint32_t        cmbloc; /* Controller Memory Buffer Location */
 530         uint32_t        cmbsz;  /* Controller Memory Buffer Size */
 531         uint32_t        bpinfo; /* Boot Partition Information */
 532         uint32_t        bprsel; /* Boot Partition Read Select */
 533         uint64_t        bpmbl;  /* Boot Partition Memory Buffer Location */
 534         uint64_t        cmbmsc; /* Controller Memory Buffer Memory Space Control */
 535         uint32_t        cmbsts; /* Controller Memory Buffer Status */
 536         uint8_t         reserved3[3492]; /* 5Ch - DFFh */
 537         uint32_t        pmrcap; /* Persistent Memory Capabilities */
 538         uint32_t        pmrctl; /* Persistent Memory Region Control */
 539         uint32_t        pmrsts; /* Persistent Memory Region Status */
 540         uint32_t        pmrebs; /* Persistent Memory Region Elasticity Buffer Size */
 541         uint32_t        pmrswtp; /* Persistent Memory Region Sustained Write Throughput */
 542         uint32_t        pmrmsc_lo; /* Persistent Memory Region Controller Memory Space Control */
 543         uint32_t        pmrmsc_hi;
 544         uint8_t         reserved4[484]; /* E1Ch - FFFh */
 545         struct {
 546             uint32_t    sq_tdbl; /* submission queue tail doorbell */
 547             uint32_t    cq_hdbl; /* completion queue head doorbell */
 548         } doorbell[1] __packed;
 549 } __packed;
 550
 551 _Static_assert(sizeof(struct nvme_registers) == 0x1008, "bad size for nvme_registers");
 552
 553 struct nvme_command
 554 {
 555         /* dword 0 */
 556         uint8_t opc;            /* opcode */
 557         uint8_t fuse;           /* fused operation */
 558         uint16_t cid;           /* command identifier */
 559
 560         /* dword 1 */
 561         uint32_t nsid;          /* namespace identifier */
 562
 563         /* dword 2-3 */
 564         uint32_t rsvd2;
 565         uint32_t rsvd3;
 566
 567         /* dword 4-5 */
 568         uint64_t mptr;          /* metadata pointer */
 569
 570         /* dword 6-7 */
 571         uint64_t prp1;          /* prp entry 1 */
 572
 573         /* dword 8-9 */
 574         uint64_t prp2;          /* prp entry 2 */
 575
 576         /* dword 10-15 */
 577         uint32_t cdw10;         /* command-specific */
 578         uint32_t cdw11;         /* command-specific */
 579         uint32_t cdw12;         /* command-specific */
 580         uint32_t cdw13;         /* command-specific */
 581         uint32_t cdw14;         /* command-specific */
 582         uint32_t cdw15;         /* command-specific */
 583 } __packed;
 584
 585 _Static_assert(sizeof(struct nvme_command) == 16 * 4, "bad size for nvme_command");
 586
 587 struct nvme_completion {
 588         /* dword 0 */
 589         uint32_t                cdw0;   /* command-specific */
 590
 591         /* dword 1 */
 592         uint32_t                rsvd1;
 593
 594         /* dword 2 */
 595         uint16_t                sqhd;   /* submission queue head pointer */
 596         uint16_t                sqid;   /* submission queue identifier */
 597
 598         /* dword 3 */
 599         uint16_t                cid;    /* command identifier */
 600         uint16_t                status;
 601 } __packed;
 602
 603 _Static_assert(sizeof(struct nvme_completion) == 4 * 4, "bad size for nvme_completion");
 604
 605 struct nvme_dsm_range {
 606         uint32_t attributes;
 607         uint32_t length;
 608         uint64_t starting_lba;
 609 } __packed;
 610
 611 /* Largest DSM Trim that can be done */
 612 #define NVME_MAX_DSM_TRIM               4096
 613
 614 _Static_assert(sizeof(struct nvme_dsm_range) == 16, "bad size for nvme_dsm_ranage");
 615
 616 /* status code types */
 617 enum nvme_status_code_type {
 618         NVME_SCT_GENERIC                = 0x0,
 619         NVME_SCT_COMMAND_SPECIFIC       = 0x1,
 620         NVME_SCT_MEDIA_ERROR            = 0x2,
 621         NVME_SCT_PATH_RELATED           = 0x3,
 622         /* 0x3-0x6 - reserved */
 623         NVME_SCT_VENDOR_SPECIFIC        = 0x7,
 624 };
 625
 626 /* generic command status codes */
 627 enum nvme_generic_command_status_code {
 628         NVME_SC_SUCCESS                         = 0x00,
 629         NVME_SC_INVALID_OPCODE                  = 0x01,
 630         NVME_SC_INVALID_FIELD                   = 0x02,
 631         NVME_SC_COMMAND_ID_CONFLICT             = 0x03,
 632         NVME_SC_DATA_TRANSFER_ERROR             = 0x04,
 633         NVME_SC_ABORTED_POWER_LOSS              = 0x05,
 634         NVME_SC_INTERNAL_DEVICE_ERROR           = 0x06,
 635         NVME_SC_ABORTED_BY_REQUEST              = 0x07,
 636         NVME_SC_ABORTED_SQ_DELETION             = 0x08,
 637         NVME_SC_ABORTED_FAILED_FUSED            = 0x09,
 638         NVME_SC_ABORTED_MISSING_FUSED           = 0x0a,
 639         NVME_SC_INVALID_NAMESPACE_OR_FORMAT     = 0x0b,
 640         NVME_SC_COMMAND_SEQUENCE_ERROR          = 0x0c,
 641         NVME_SC_INVALID_SGL_SEGMENT_DESCR       = 0x0d,
 642         NVME_SC_INVALID_NUMBER_OF_SGL_DESCR     = 0x0e,
 643         NVME_SC_DATA_SGL_LENGTH_INVALID         = 0x0f,
 644         NVME_SC_METADATA_SGL_LENGTH_INVALID     = 0x10,
 645         NVME_SC_SGL_DESCRIPTOR_TYPE_INVALID     = 0x11,
 646         NVME_SC_INVALID_USE_OF_CMB              = 0x12,
 647         NVME_SC_PRP_OFFET_INVALID               = 0x13,
 648         NVME_SC_ATOMIC_WRITE_UNIT_EXCEEDED      = 0x14,
 649         NVME_SC_OPERATION_DENIED                = 0x15,
 650         NVME_SC_SGL_OFFSET_INVALID              = 0x16,
 651         /* 0x17 - reserved */
 652         NVME_SC_HOST_ID_INCONSISTENT_FORMAT     = 0x18,
 653         NVME_SC_KEEP_ALIVE_TIMEOUT_EXPIRED      = 0x19,
 654         NVME_SC_KEEP_ALIVE_TIMEOUT_INVALID      = 0x1a,
 655         NVME_SC_ABORTED_DUE_TO_PREEMPT          = 0x1b,
 656         NVME_SC_SANITIZE_FAILED                 = 0x1c,
 657         NVME_SC_SANITIZE_IN_PROGRESS            = 0x1d,
 658         NVME_SC_SGL_DATA_BLOCK_GRAN_INVALID     = 0x1e,
 659         NVME_SC_NOT_SUPPORTED_IN_CMB            = 0x1f,
 660         NVME_SC_NAMESPACE_IS_WRITE_PROTECTED    = 0x20,
 661         NVME_SC_COMMAND_INTERRUPTED             = 0x21,
 662         NVME_SC_TRANSIENT_TRANSPORT_ERROR       = 0x22,
 663
 664         NVME_SC_LBA_OUT_OF_RANGE                = 0x80,
 665         NVME_SC_CAPACITY_EXCEEDED               = 0x81,
 666         NVME_SC_NAMESPACE_NOT_READY             = 0x82,
 667         NVME_SC_RESERVATION_CONFLICT            = 0x83,
 668         NVME_SC_FORMAT_IN_PROGRESS              = 0x84,
 669 };
 670
 671 /* command specific status codes */
 672 enum nvme_command_specific_status_code {
 673         NVME_SC_COMPLETION_QUEUE_INVALID        = 0x00,
 674         NVME_SC_INVALID_QUEUE_IDENTIFIER        = 0x01,
 675         NVME_SC_MAXIMUM_QUEUE_SIZE_EXCEEDED     = 0x02,
 676         NVME_SC_ABORT_COMMAND_LIMIT_EXCEEDED    = 0x03,
 677         /* 0x04 - reserved */
 678         NVME_SC_ASYNC_EVENT_REQUEST_LIMIT_EXCEEDED = 0x05,
 679         NVME_SC_INVALID_FIRMWARE_SLOT           = 0x06,
 680         NVME_SC_INVALID_FIRMWARE_IMAGE          = 0x07,
 681         NVME_SC_INVALID_INTERRUPT_VECTOR        = 0x08,
 682         NVME_SC_INVALID_LOG_PAGE                = 0x09,
 683         NVME_SC_INVALID_FORMAT                  = 0x0a,
 684         NVME_SC_FIRMWARE_REQUIRES_RESET         = 0x0b,
 685         NVME_SC_INVALID_QUEUE_DELETION          = 0x0c,
 686         NVME_SC_FEATURE_NOT_SAVEABLE            = 0x0d,
 687         NVME_SC_FEATURE_NOT_CHANGEABLE          = 0x0e,
 688         NVME_SC_FEATURE_NOT_NS_SPECIFIC         = 0x0f,
 689         NVME_SC_FW_ACT_REQUIRES_NVMS_RESET      = 0x10,
 690         NVME_SC_FW_ACT_REQUIRES_RESET           = 0x11,
 691         NVME_SC_FW_ACT_REQUIRES_TIME            = 0x12,
 692         NVME_SC_FW_ACT_PROHIBITED               = 0x13,
 693         NVME_SC_OVERLAPPING_RANGE               = 0x14,
 694         NVME_SC_NS_INSUFFICIENT_CAPACITY        = 0x15,
 695         NVME_SC_NS_ID_UNAVAILABLE               = 0x16,
 696         /* 0x17 - reserved */
 697         NVME_SC_NS_ALREADY_ATTACHED             = 0x18,
 698         NVME_SC_NS_IS_PRIVATE                   = 0x19,
 699         NVME_SC_NS_NOT_ATTACHED                 = 0x1a,
 700         NVME_SC_THIN_PROV_NOT_SUPPORTED         = 0x1b,
 701         NVME_SC_CTRLR_LIST_INVALID              = 0x1c,
 702         NVME_SC_SELT_TEST_IN_PROGRESS           = 0x1d,
 703         NVME_SC_BOOT_PART_WRITE_PROHIB          = 0x1e,
 704         NVME_SC_INVALID_CTRLR_ID                = 0x1f,
 705         NVME_SC_INVALID_SEC_CTRLR_STATE         = 0x20,
 706         NVME_SC_INVALID_NUM_OF_CTRLR_RESRC      = 0x21,
 707         NVME_SC_INVALID_RESOURCE_ID             = 0x22,
 708         NVME_SC_SANITIZE_PROHIBITED_WPMRE       = 0x23,
 709         NVME_SC_ANA_GROUP_ID_INVALID            = 0x24,
 710         NVME_SC_ANA_ATTACH_FAILED               = 0x25,
 711
 712         NVME_SC_CONFLICTING_ATTRIBUTES          = 0x80,
 713         NVME_SC_INVALID_PROTECTION_INFO         = 0x81,
 714         NVME_SC_ATTEMPTED_WRITE_TO_RO_PAGE      = 0x82,
 715 };
 716
 717 /* media error status codes */
 718 enum nvme_media_error_status_code {
 719         NVME_SC_WRITE_FAULTS                    = 0x80,
 720         NVME_SC_UNRECOVERED_READ_ERROR          = 0x81,
 721         NVME_SC_GUARD_CHECK_ERROR               = 0x82,
 722         NVME_SC_APPLICATION_TAG_CHECK_ERROR     = 0x83,
 723         NVME_SC_REFERENCE_TAG_CHECK_ERROR       = 0x84,
 724         NVME_SC_COMPARE_FAILURE                 = 0x85,
 725         NVME_SC_ACCESS_DENIED                   = 0x86,
 726         NVME_SC_DEALLOCATED_OR_UNWRITTEN        = 0x87,
 727 };
 728
 729 /* path related status codes */
 730 enum nvme_path_related_status_code {
 731         NVME_SC_INTERNAL_PATH_ERROR             = 0x00,
 732         NVME_SC_ASYMMETRIC_ACCESS_PERSISTENT_LOSS = 0x01,
 733         NVME_SC_ASYMMETRIC_ACCESS_INACCESSIBLE  = 0x02,
 734         NVME_SC_ASYMMETRIC_ACCESS_TRANSITION    = 0x03,
 735         NVME_SC_CONTROLLER_PATHING_ERROR        = 0x60,
 736         NVME_SC_HOST_PATHING_ERROR              = 0x70,
 737         NVME_SC_COMMAND_ABOTHED_BY_HOST         = 0x71,
 738 };
 739
 740 /* admin opcodes */
 741 enum nvme_admin_opcode {
 742         NVME_OPC_DELETE_IO_SQ                   = 0x00,
 743         NVME_OPC_CREATE_IO_SQ                   = 0x01,
 744         NVME_OPC_GET_LOG_PAGE                   = 0x02,
 745         /* 0x03 - reserved */
 746         NVME_OPC_DELETE_IO_CQ                   = 0x04,
 747         NVME_OPC_CREATE_IO_CQ                   = 0x05,
 748         NVME_OPC_IDENTIFY                       = 0x06,
 749         /* 0x07 - reserved */
 750         NVME_OPC_ABORT                          = 0x08,
 751         NVME_OPC_SET_FEATURES                   = 0x09,
 752         NVME_OPC_GET_FEATURES                   = 0x0a,
 753         /* 0x0b - reserved */
 754         NVME_OPC_ASYNC_EVENT_REQUEST            = 0x0c,
 755         NVME_OPC_NAMESPACE_MANAGEMENT           = 0x0d,
 756         /* 0x0e-0x0f - reserved */
 757         NVME_OPC_FIRMWARE_ACTIVATE              = 0x10,
 758         NVME_OPC_FIRMWARE_IMAGE_DOWNLOAD        = 0x11,
 759         /* 0x12-0x13 - reserved */
 760         NVME_OPC_DEVICE_SELF_TEST               = 0x14,
 761         NVME_OPC_NAMESPACE_ATTACHMENT           = 0x15,
 762         /* 0x16-0x17 - reserved */
 763         NVME_OPC_KEEP_ALIVE                     = 0x18,
 764         NVME_OPC_DIRECTIVE_SEND                 = 0x19,
 765         NVME_OPC_DIRECTIVE_RECEIVE              = 0x1a,
 766         /* 0x1b - reserved */
 767         NVME_OPC_VIRTUALIZATION_MANAGEMENT      = 0x1c,
 768         NVME_OPC_NVME_MI_SEND                   = 0x1d,
 769         NVME_OPC_NVME_MI_RECEIVE                = 0x1e,
 770         /* 0x1f-0x7b - reserved */
 771         NVME_OPC_DOORBELL_BUFFER_CONFIG         = 0x7c,
 772
 773         NVME_OPC_FORMAT_NVM                     = 0x80,
 774         NVME_OPC_SECURITY_SEND                  = 0x81,
 775         NVME_OPC_SECURITY_RECEIVE               = 0x82,
 776         /* 0x83 - reserved */
 777         NVME_OPC_SANITIZE                       = 0x84,
 778         /* 0x85 - reserved */
 779         NVME_OPC_GET_LBA_STATUS                 = 0x86,
 780 };
 781
 782 /* nvme nvm opcodes */
 783 enum nvme_nvm_opcode {
 784         NVME_OPC_FLUSH                          = 0x00,
 785         NVME_OPC_WRITE                          = 0x01,
 786         NVME_OPC_READ                           = 0x02,
 787         /* 0x03 - reserved */
 788         NVME_OPC_WRITE_UNCORRECTABLE            = 0x04,
 789         NVME_OPC_COMPARE                        = 0x05,
 790         /* 0x06-0x07 - reserved */
 791         NVME_OPC_WRITE_ZEROES                   = 0x08,
 792         NVME_OPC_DATASET_MANAGEMENT             = 0x09,
 793         /* 0x0a-0x0b - reserved */
 794         NVME_OPC_VERIFY                         = 0x0c,
 795         NVME_OPC_RESERVATION_REGISTER           = 0x0d,
 796         NVME_OPC_RESERVATION_REPORT             = 0x0e,
 797         /* 0x0f-0x10 - reserved */
 798         NVME_OPC_RESERVATION_ACQUIRE            = 0x11,
 799         /* 0x12-0x14 - reserved */
 800         NVME_OPC_RESERVATION_RELEASE            = 0x15,
 801 };
 802
 803 enum nvme_feature {
 804         /* 0x00 - reserved */
 805         NVME_FEAT_ARBITRATION                   = 0x01,
 806         NVME_FEAT_POWER_MANAGEMENT              = 0x02,
 807         NVME_FEAT_LBA_RANGE_TYPE                = 0x03,
 808         NVME_FEAT_TEMPERATURE_THRESHOLD         = 0x04,
 809         NVME_FEAT_ERROR_RECOVERY                = 0x05,
 810         NVME_FEAT_VOLATILE_WRITE_CACHE          = 0x06,
 811         NVME_FEAT_NUMBER_OF_QUEUES              = 0x07,
 812         NVME_FEAT_INTERRUPT_COALESCING          = 0x08,
 813         NVME_FEAT_INTERRUPT_VECTOR_CONFIGURATION = 0x09,
 814         NVME_FEAT_WRITE_ATOMICITY               = 0x0A,
 815         NVME_FEAT_ASYNC_EVENT_CONFIGURATION     = 0x0B,
 816         NVME_FEAT_AUTONOMOUS_POWER_STATE_TRANSITION = 0x0C,
 817         NVME_FEAT_HOST_MEMORY_BUFFER            = 0x0D,
 818         NVME_FEAT_TIMESTAMP                     = 0x0E,
 819         NVME_FEAT_KEEP_ALIVE_TIMER              = 0x0F,
 820         NVME_FEAT_HOST_CONTROLLED_THERMAL_MGMT  = 0x10,
 821         NVME_FEAT_NON_OP_POWER_STATE_CONFIG     = 0x11,
 822         NVME_FEAT_READ_RECOVERY_LEVEL_CONFIG    = 0x12,
 823         NVME_FEAT_PREDICTABLE_LATENCY_MODE_CONFIG = 0x13,
 824         NVME_FEAT_PREDICTABLE_LATENCY_MODE_WINDOW = 0x14,
 825         NVME_FEAT_LBA_STATUS_INFORMATION_ATTRIBUTES = 0x15,
 826         NVME_FEAT_HOST_BEHAVIOR_SUPPORT         = 0x16,
 827         NVME_FEAT_SANITIZE_CONFIG               = 0x17,
 828         NVME_FEAT_ENDURANCE_GROUP_EVENT_CONFIGURATION = 0x18,
 829         /* 0x19-0x77 - reserved */
 830         /* 0x78-0x7f - NVMe Management Interface */
 831         NVME_FEAT_SOFTWARE_PROGRESS_MARKER      = 0x80,
 832         NVME_FEAT_HOST_IDENTIFIER               = 0x81,
 833         NVME_FEAT_RESERVATION_NOTIFICATION_MASK = 0x82,
 834         NVME_FEAT_RESERVATION_PERSISTENCE       = 0x83,
 835         NVME_FEAT_NAMESPACE_WRITE_PROTECTION_CONFIG = 0x84,
 836         /* 0x85-0xBF - command set specific (reserved) */
 837         /* 0xC0-0xFF - vendor specific */
 838 };
 839
 840 enum nvme_dsm_attribute {
 841         NVME_DSM_ATTR_INTEGRAL_READ             = 0x1,
 842         NVME_DSM_ATTR_INTEGRAL_WRITE            = 0x2,
 843         NVME_DSM_ATTR_DEALLOCATE                = 0x4,
 844 };
 845
 846 enum nvme_activate_action {
 847         NVME_AA_REPLACE_NO_ACTIVATE             = 0x0,
 848         NVME_AA_REPLACE_ACTIVATE                = 0x1,
 849         NVME_AA_ACTIVATE                        = 0x2,
 850 };
 851
 852 struct nvme_power_state {
 853         /** Maximum Power */
 854         uint16_t        mp;                     /* Maximum Power */
 855         uint8_t         ps_rsvd1;
 856         uint8_t         mps_nops;               /* Max Power Scale, Non-Operational State */
 857
 858         uint32_t        enlat;                  /* Entry Latency */
 859         uint32_t        exlat;                  /* Exit Latency */
 860
 861         uint8_t         rrt;                    /* Relative Read Throughput */
 862         uint8_t         rrl;                    /* Relative Read Latency */
 863         uint8_t         rwt;                    /* Relative Write Throughput */
 864         uint8_t         rwl;                    /* Relative Write Latency */
 865
 866         uint16_t        idlp;                   /* Idle Power */
 867         uint8_t         ips;                    /* Idle Power Scale */
 868         uint8_t         ps_rsvd8;
 869
 870         uint16_t        actp;                   /* Active Power */
 871         uint8_t         apw_aps;                /* Active Power Workload, Active Power Scale */
 872         uint8_t         ps_rsvd10[9];
 873 } __packed;
 874
 875 _Static_assert(sizeof(struct nvme_power_state) == 32, "bad size for nvme_power_state");
 876
 877 #define NVME_SERIAL_NUMBER_LENGTH       20
 878 #define NVME_MODEL_NUMBER_LENGTH        40
 879 #define NVME_FIRMWARE_REVISION_LENGTH   8
 880
 881 struct nvme_controller_data {
 882         /* bytes 0-255: controller capabilities and features */
 883
 884         /** pci vendor id */
 885         uint16_t                vid;
 886
 887         /** pci subsystem vendor id */
 888         uint16_t                ssvid;
 889
 890         /** serial number */
 891         uint8_t                 sn[NVME_SERIAL_NUMBER_LENGTH];
 892
 893         /** model number */
 894         uint8_t                 mn[NVME_MODEL_NUMBER_LENGTH];
 895
 896         /** firmware revision */
 897         uint8_t                 fr[NVME_FIRMWARE_REVISION_LENGTH];
 898
 899         /** recommended arbitration burst */
 900         uint8_t                 rab;
 901
 902         /** ieee oui identifier */
 903         uint8_t                 ieee[3];
 904
 905         /** multi-interface capabilities */
 906         uint8_t                 mic;
 907
 908         /** maximum data transfer size */
 909         uint8_t                 mdts;
 910
 911         /** Controller ID */
 912         uint16_t                ctrlr_id;
 913
 914         /** Version */
 915         uint32_t                ver;
 916
 917         /** RTD3 Resume Latency */
 918         uint32_t                rtd3r;
 919
 920         /** RTD3 Enter Latency */
 921         uint32_t                rtd3e;
 922
 923         /** Optional Asynchronous Events Supported */
 924         uint32_t                oaes;   /* bitfield really */
 925
 926         /** Controller Attributes */
 927         uint32_t                ctratt; /* bitfield really */
 928
 929         /** Read Recovery Levels Supported */
 930         uint16_t                rrls;
 931
 932         uint8_t                 reserved1[9];
 933
 934         /** Controller Type */
 935         uint8_t                 cntrltype;
 936
 937         /** FRU Globally Unique Identifier */
 938         uint8_t                 fguid[16];
 939
 940         /** Command Retry Delay Time 1 */
 941         uint16_t                crdt1;
 942
 943         /** Command Retry Delay Time 2 */
 944         uint16_t                crdt2;
 945
 946         /** Command Retry Delay Time 3 */
 947         uint16_t                crdt3;
 948
 949         uint8_t                 reserved2[122];
 950
 951         /* bytes 256-511: admin command set attributes */
 952
 953         /** optional admin command support */
 954         uint16_t                oacs;
 955
 956         /** abort command limit */
 957         uint8_t                 acl;
 958
 959         /** asynchronous event request limit */
 960         uint8_t                 aerl;
 961
 962         /** firmware updates */
 963         uint8_t                 frmw;
 964
 965         /** log page attributes */
 966         uint8_t                 lpa;
 967
 968         /** error log page entries */
 969         uint8_t                 elpe;
 970
 971         /** number of power states supported */
 972         uint8_t                 npss;
 973
 974         /** admin vendor specific command configuration */
 975         uint8_t                 avscc;
 976
 977         /** Autonomous Power State Transition Attributes */
 978         uint8_t                 apsta;
 979
 980         /** Warning Composite Temperature Threshold */
 981         uint16_t                wctemp;
 982
 983         /** Critical Composite Temperature Threshold */
 984         uint16_t                cctemp;
 985
 986         /** Maximum Time for Firmware Activation */
 987         uint16_t                mtfa;
 988
 989         /** Host Memory Buffer Preferred Size */
 990         uint32_t                hmpre;
 991
 992         /** Host Memory Buffer Minimum Size */
 993         uint32_t                hmmin;
 994
 995         /** Name space capabilities  */
 996         struct {
 997                 /* if nsmgmt, report tnvmcap and unvmcap */
 998                 uint8_t    tnvmcap[16];
 999                 uint8_t    unvmcap[16];
1000         } __packed untncap;
1001
1002         /** Replay Protected Memory Block Support */
1003         uint32_t                rpmbs; /* Really a bitfield */
1004
1005         /** Extended Device Self-test Time */
1006         uint16_t                edstt;
1007
1008         /** Device Self-test Options */
1009         uint8_t                 dsto; /* Really a bitfield */
1010
1011         /** Firmware Update Granularity */
1012         uint8_t                 fwug;
1013
1014         /** Keep Alive Support */
1015         uint16_t                kas;
1016
1017         /** Host Controlled Thermal Management Attributes */
1018         uint16_t                hctma; /* Really a bitfield */
1019
1020         /** Minimum Thermal Management Temperature */
1021         uint16_t                mntmt;
1022
1023         /** Maximum Thermal Management Temperature */
1024         uint16_t                mxtmt;
1025
1026         /** Sanitize Capabilities */
1027         uint32_t                sanicap; /* Really a bitfield */
1028
1029         /** Host Memory Buffer Minimum Descriptor Entry Size */
1030         uint32_t                hmminds;
1031
1032         /** Host Memory Maximum Descriptors Entries */
1033         uint16_t                hmmaxd;
1034
1035         /** NVM Set Identifier Maximum */
1036         uint16_t                nsetidmax;
1037
1038         /** Endurance Group Identifier Maximum */
1039         uint16_t                endgidmax;
1040
1041         /** ANA Transition Time */
1042         uint8_t                 anatt;
1043
1044         /** Asymmetric Namespace Access Capabilities */
1045         uint8_t                 anacap;
1046
1047         /** ANA Group Identifier Maximum */
1048         uint32_t                anagrpmax;
1049
1050         /** Number of ANA Group Identifiers */
1051         uint32_t                nanagrpid;
1052
1053         /** Persistent Event Log Size */
1054         uint32_t                pels;
1055
1056         uint8_t                 reserved3[156];
1057         /* bytes 512-703: nvm command set attributes */
1058
1059         /** submission queue entry size */
1060         uint8_t                 sqes;
1061
1062         /** completion queue entry size */
1063         uint8_t                 cqes;
1064
1065         /** Maximum Outstanding Commands */
1066         uint16_t                maxcmd;
1067
1068         /** number of namespaces */
1069         uint32_t                nn;
1070
1071         /** optional nvm command support */
1072         uint16_t                oncs;
1073
1074         /** fused operation support */
1075         uint16_t                fuses;
1076
1077         /** format nvm attributes */
1078         uint8_t                 fna;
1079
1080         /** volatile write cache */
1081         uint8_t                 vwc;
1082
1083         /** Atomic Write Unit Normal */
1084         uint16_t                awun;
1085
1086         /** Atomic Write Unit Power Fail */
1087         uint16_t                awupf;
1088
1089         /** NVM Vendor Specific Command Configuration */
1090         uint8_t                 nvscc;
1091
1092         /** Namespace Write Protection Capabilities */
1093         uint8_t                 nwpc;
1094
1095         /** Atomic Compare & Write Unit */
1096         uint16_t                acwu;
1097         uint16_t                reserved6;
1098
1099         /** SGL Support */
1100         uint32_t                sgls;
1101
1102         /** Maximum Number of Allowed Namespaces */
1103         uint32_t                mnan;
1104
1105         /* bytes 540-767: Reserved */
1106         uint8_t                 reserved7[224];
1107
1108         /** NVM Subsystem NVMe Qualified Name */
1109         uint8_t                 subnqn[256];
1110
1111         /* bytes 1024-1791: Reserved */
1112         uint8_t                 reserved8[768];
1113
1114         /* bytes 1792-2047: NVMe over Fabrics specification */
1115         uint8_t                 reserved9[256];
1116
1117         /* bytes 2048-3071: power state descriptors */
1118         struct nvme_power_state power_state[32];
1119
1120         /* bytes 3072-4095: vendor specific */
1121         uint8_t                 vs[1024];
1122 } __packed __aligned(4);
1123
1124 _Static_assert(sizeof(struct nvme_controller_data) == 4096, "bad size for nvme_controller_data");
1125
1126 struct nvme_namespace_data {
1127         /** namespace size */
1128         uint64_t                nsze;
1129
1130         /** namespace capacity */
1131         uint64_t                ncap;
1132
1133         /** namespace utilization */
1134         uint64_t                nuse;
1135
1136         /** namespace features */
1137         uint8_t                 nsfeat;
1138
1139         /** number of lba formats */
1140         uint8_t                 nlbaf;
1141
1142         /** formatted lba size */
1143         uint8_t                 flbas;
1144
1145         /** metadata capabilities */
1146         uint8_t                 mc;
1147
1148         /** end-to-end data protection capabilities */
1149         uint8_t                 dpc;
1150
1151         /** end-to-end data protection type settings */
1152         uint8_t                 dps;
1153
1154         /** Namespace Multi-path I/O and Namespace Sharing Capabilities */
1155         uint8_t                 nmic;
1156
1157         /** Reservation Capabilities */
1158         uint8_t                 rescap;
1159
1160         /** Format Progress Indicator */
1161         uint8_t                 fpi;
1162
1163         /** Deallocate Logical Block Features */
1164         uint8_t                 dlfeat;
1165
1166         /** Namespace Atomic Write Unit Normal  */
1167         uint16_t                nawun;
1168
1169         /** Namespace Atomic Write Unit Power Fail */
1170         uint16_t                nawupf;
1171
1172         /** Namespace Atomic Compare & Write Unit */
1173         uint16_t                nacwu;
1174
1175         /** Namespace Atomic Boundary Size Normal */
1176         uint16_t                nabsn;
1177
1178         /** Namespace Atomic Boundary Offset */
1179         uint16_t                nabo;
1180
1181         /** Namespace Atomic Boundary Size Power Fail */
1182         uint16_t                nabspf;
1183
1184         /** Namespace Optimal IO Boundary */
1185         uint16_t                noiob;
1186
1187         /** NVM Capacity */
1188         uint8_t                 nvmcap[16];
1189
1190         /** Namespace Preferred Write Granularity  */
1191         uint16_t                npwg;
1192
1193         /** Namespace Preferred Write Alignment */
1194         uint16_t                npwa;
1195
1196         /** Namespace Preferred Deallocate Granularity */
1197         uint16_t                npdg;
1198
1199         /** Namespace Preferred Deallocate Alignment */
1200         uint16_t                npda;
1201
1202         /** Namespace Optimal Write Size */
1203         uint16_t                nows;
1204
1205         /* bytes 74-91: Reserved */
1206         uint8_t                 reserved5[18];
1207
1208         /** ANA Group Identifier */
1209         uint32_t                anagrpid;
1210
1211         /* bytes 96-98: Reserved */
1212         uint8_t                 reserved6[3];
1213
1214         /** Namespace Attributes */
1215         uint8_t                 nsattr;
1216
1217         /** NVM Set Identifier */
1218         uint16_t                nvmsetid;
1219
1220         /** Endurance Group Identifier */
1221         uint16_t                endgid;
1222
1223         /** Namespace Globally Unique Identifier */
1224         uint8_t                 nguid[16];
1225
1226         /** IEEE Extended Unique Identifier */
1227         uint8_t                 eui64[8];
1228
1229         /** lba format support */
1230         uint32_t                lbaf[16];
1231
1232         uint8_t                 reserved7[192];
1233
1234         uint8_t                 vendor_specific[3712];
1235 } __packed __aligned(4);
1236
1237 _Static_assert(sizeof(struct nvme_namespace_data) == 4096, "bad size for nvme_namepsace_data");
1238
1239 enum nvme_log_page {
1240         /* 0x00 - reserved */
1241         NVME_LOG_ERROR                  = 0x01,
1242         NVME_LOG_HEALTH_INFORMATION     = 0x02,
1243         NVME_LOG_FIRMWARE_SLOT          = 0x03,
1244         NVME_LOG_CHANGED_NAMESPACE      = 0x04,
1245         NVME_LOG_COMMAND_EFFECT         = 0x05,
1246         NVME_LOG_DEVICE_SELF_TEST       = 0x06,
1247         NVME_LOG_TELEMETRY_HOST_INITIATED = 0x07,
1248         NVME_LOG_TELEMETRY_CONTROLLER_INITIATED = 0x08,
1249         NVME_LOG_ENDURANCE_GROUP_INFORMATION = 0x09,
1250         NVME_LOG_PREDICTABLE_LATENCY_PER_NVM_SET = 0x0a,
1251         NVME_LOG_PREDICTABLE_LATENCY_EVENT_AGGREGATE = 0x0b,
1252         NVME_LOG_ASYMMETRIC_NAMESPAVE_ACCESS = 0x0c,
1253         NVME_LOG_PERSISTENT_EVENT_LOG   = 0x0d,
1254         NVME_LOG_LBA_STATUS_INFORMATION = 0x0e,
1255         NVME_LOG_ENDURANCE_GROUP_EVENT_AGGREGATE = 0x0f,
1256         /* 0x06-0x7F - reserved */
1257         /* 0x80-0xBF - I/O command set specific */
1258         NVME_LOG_RES_NOTIFICATION       = 0x80,
1259         NVME_LOG_SANITIZE_STATUS        = 0x81,
1260         /* 0x82-0xBF - reserved */
1261         /* 0xC0-0xFF - vendor specific */
1262
1263         /*
1264          * The following are Intel Specific log pages, but they seem
1265          * to be widely implemented.
1266          */
1267         INTEL_LOG_READ_LAT_LOG          = 0xc1,
1268         INTEL_LOG_WRITE_LAT_LOG         = 0xc2,
1269         INTEL_LOG_TEMP_STATS            = 0xc5,
1270         INTEL_LOG_ADD_SMART             = 0xca,
1271         INTEL_LOG_DRIVE_MKT_NAME        = 0xdd,
1272
1273         /*
1274          * HGST log page, with lots ofs sub pages.
1275          */
1276         HGST_INFO_LOG                   = 0xc1,
1277 };
1278
1279 struct nvme_error_information_entry {
1280         uint64_t                error_count;
1281         uint16_t                sqid;
1282         uint16_t                cid;
1283         uint16_t                status;
1284         uint16_t                error_location;
1285         uint64_t                lba;
1286         uint32_t                nsid;
1287         uint8_t                 vendor_specific;
1288         uint8_t                 trtype;
1289         uint16_t                reserved30;
1290         uint64_t                csi;
1291         uint16_t                ttsi;
1292         uint8_t                 reserved[22];
1293 } __packed __aligned(4);
1294
1295 _Static_assert(sizeof(struct nvme_error_information_entry) == 64, "bad size for nvme_error_information_entry");
1296
1297 struct nvme_health_information_page {
1298         uint8_t                 critical_warning;
1299         uint16_t                temperature;
1300         uint8_t                 available_spare;
1301         uint8_t                 available_spare_threshold;
1302         uint8_t                 percentage_used;
1303
1304         uint8_t                 reserved[26];
1305
1306         /*
1307          * Note that the following are 128-bit values, but are
1308          *  defined as an array of 2 64-bit values.
1309          */
1310         /* Data Units Read is always in 512-byte units. */
1311         uint64_t                data_units_read[2];
1312         /* Data Units Written is always in 512-byte units. */
1313         uint64_t                data_units_written[2];
1314         /* For NVM command set, this includes Compare commands. */
1315         uint64_t                host_read_commands[2];
1316         uint64_t                host_write_commands[2];
1317         /* Controller Busy Time is reported in minutes. */
1318         uint64_t                controller_busy_time[2];
1319         uint64_t                power_cycles[2];
1320         uint64_t                power_on_hours[2];
1321         uint64_t                unsafe_shutdowns[2];
1322         uint64_t                media_errors[2];
1323         uint64_t                num_error_info_log_entries[2];
1324         uint32_t                warning_temp_time;
1325         uint32_t                error_temp_time;
1326         uint16_t                temp_sensor[8];
1327         /* Thermal Management Temperature 1 Transition Count */
1328         uint32_t                tmt1tc;
1329         /* Thermal Management Temperature 2 Transition Count */
1330         uint32_t                tmt2tc;
1331         /* Total Time For Thermal Management Temperature 1 */
1332         uint32_t                ttftmt1;
1333         /* Total Time For Thermal Management Temperature 2 */
1334         uint32_t                ttftmt2;
1335
1336         uint8_t                 reserved2[280];
1337 } __packed __aligned(4);
1338
1339 _Static_assert(sizeof(struct nvme_health_information_page) == 512, "bad size for nvme_health_information_page");
1340
1341 struct nvme_firmware_page {
1342         uint8_t                 afi;
1343         uint8_t                 reserved[7];
1344         uint64_t                revision[7]; /* revisions for 7 slots */
1345         uint8_t                 reserved2[448];
1346 } __packed __aligned(4);
1347
1348 _Static_assert(sizeof(struct nvme_firmware_page) == 512, "bad size for nvme_firmware_page");
1349
1350 struct nvme_ns_list {
1351         uint32_t                ns[1024];
1352 } __packed __aligned(4);
1353
1354 _Static_assert(sizeof(struct nvme_ns_list) == 4096, "bad size for nvme_ns_list");
1355
1356 struct nvme_command_effects_page {
1357         uint32_t                acs[256];
1358         uint32_t                iocs[256];
1359         uint8_t                 reserved[2048];
1360 } __packed __aligned(4);
1361
1362 _Static_assert(sizeof(struct nvme_command_effects_page) == 4096,
1363     "bad size for nvme_command_effects_page");
1364
1365 struct nvme_res_notification_page {
1366         uint64_t                log_page_count;
1367         uint8_t                 log_page_type;
1368         uint8_t                 available_log_pages;
1369         uint8_t                 reserved2;
1370         uint32_t                nsid;
1371         uint8_t                 reserved[48];
1372 } __packed __aligned(4);
1373
1374 _Static_assert(sizeof(struct nvme_res_notification_page) == 64,
1375     "bad size for nvme_res_notification_page");
1376
1377 struct nvme_sanitize_status_page {
1378         uint16_t                sprog;
1379         uint16_t                sstat;
1380         uint32_t                scdw10;
1381         uint32_t                etfo;
1382         uint32_t                etfbe;
1383         uint32_t                etfce;
1384         uint32_t                etfownd;
1385         uint32_t                etfbewnd;
1386         uint32_t                etfcewnd;
1387         uint8_t                 reserved[480];
1388 } __packed __aligned(4);
1389
1390 _Static_assert(sizeof(struct nvme_sanitize_status_page) == 512,
1391     "bad size for nvme_sanitize_status_page");
1392
1393 struct intel_log_temp_stats
1394 {
1395         uint64_t        current;
1396         uint64_t        overtemp_flag_last;
1397         uint64_t        overtemp_flag_life;
1398         uint64_t        max_temp;
1399         uint64_t        min_temp;
1400         uint64_t        _rsvd[5];
1401         uint64_t        max_oper_temp;
1402         uint64_t        min_oper_temp;
1403         uint64_t        est_offset;
1404 } __packed __aligned(4);
1405
1406 _Static_assert(sizeof(struct intel_log_temp_stats) == 13 * 8, "bad size for intel_log_temp_stats");
1407
1408 struct nvme_resv_reg_ctrlr
1409 {
1410         uint16_t                ctrlr_id;       /* Controller ID */
1411         uint8_t                 rcsts;          /* Reservation Status */
1412         uint8_t                 reserved3[5];
1413         uint64_t                hostid;         /* Host Identifier */
1414         uint64_t                rkey;           /* Reservation Key */
1415 } __packed __aligned(4);
1416
1417 _Static_assert(sizeof(struct nvme_resv_reg_ctrlr) == 24, "bad size for nvme_resv_reg_ctrlr");
1418
1419 struct nvme_resv_reg_ctrlr_ext
1420 {
1421         uint16_t                ctrlr_id;       /* Controller ID */
1422         uint8_t                 rcsts;          /* Reservation Status */
1423         uint8_t                 reserved3[5];
1424         uint64_t                rkey;           /* Reservation Key */
1425         uint64_t                hostid[2];      /* Host Identifier */
1426         uint8_t                 reserved32[32];
1427 } __packed __aligned(4);
1428
1429 _Static_assert(sizeof(struct nvme_resv_reg_ctrlr_ext) == 64, "bad size for nvme_resv_reg_ctrlr_ext");
1430
1431 struct nvme_resv_status
1432 {
1433         uint32_t                gen;            /* Generation */
1434         uint8_t                 rtype;          /* Reservation Type */
1435         uint8_t                 regctl[2];      /* Number of Registered Controllers */
1436         uint8_t                 reserved7[2];
1437         uint8_t                 ptpls;          /* Persist Through Power Loss State */
1438         uint8_t                 reserved10[14];
1439         struct nvme_resv_reg_ctrlr      ctrlr[0];
1440 } __packed __aligned(4);
1441
1442 _Static_assert(sizeof(struct nvme_resv_status) == 24, "bad size for nvme_resv_status");
1443
1444 struct nvme_resv_status_ext
1445 {
1446         uint32_t                gen;            /* Generation */
1447         uint8_t                 rtype;          /* Reservation Type */
1448         uint8_t                 regctl[2];      /* Number of Registered Controllers */
1449         uint8_t                 reserved7[2];
1450         uint8_t                 ptpls;          /* Persist Through Power Loss State */
1451         uint8_t                 reserved10[14];
1452         uint8_t                 reserved24[40];
1453         struct nvme_resv_reg_ctrlr_ext  ctrlr[0];
1454 } __packed __aligned(4);
1455
1456 _Static_assert(sizeof(struct nvme_resv_status_ext) == 64, "bad size for nvme_resv_status_ext");
1457
1458 #define NVME_TEST_MAX_THREADS   128
1459
1460 struct nvme_io_test {
1461         enum nvme_nvm_opcode    opc;
1462         uint32_t                size;
1463         uint32_t                time;   /* in seconds */
1464         uint32_t                num_threads;
1465         uint32_t                flags;
1466         uint64_t                io_completed[NVME_TEST_MAX_THREADS];
1467 };
1468
1469 enum nvme_io_test_flags {
1470         /*
1471          * Specifies whether dev_refthread/dev_relthread should be
1472          *  called during NVME_BIO_TEST.  Ignored for other test
1473          *  types.
1474          */
1475         NVME_TEST_FLAG_REFTHREAD =      0x1,
1476 };
1477
1478 struct nvme_pt_command {
1479         /*
1480          * cmd is used to specify a passthrough command to a controller or
1481          *  namespace.
1482          *
1483          * The following fields from cmd may be specified by the caller:
1484          *      * opc  (opcode)
1485          *      * nsid (namespace id) - for admin commands only
1486          *      * cdw10-cdw15
1487          *
1488          * Remaining fields must be set to 0 by the caller.
1489          */
1490         struct nvme_command     cmd;
1491
1492         /*
1493          * cpl returns completion status for the passthrough command
1494          *  specified by cmd.
1495          *
1496          * The following fields will be filled out by the driver, for
1497          *  consumption by the caller:
1498          *      * cdw0
1499          *      * status (except for phase)
1500          *
1501          * Remaining fields will be set to 0 by the driver.
1502          */
1503         struct nvme_completion  cpl;
1504
1505         /* buf is the data buffer associated with this passthrough command. */
1506         void *                  buf;
1507
1508         /*
1509          * len is the length of the data buffer associated with this
1510          *  passthrough command.
1511          */
1512         uint32_t                len;
1513
1514         /*
1515          * is_read = 1 if the passthrough command will read data into the
1516          *  supplied buffer from the controller.
1517          *
1518          * is_read = 0 if the passthrough command will write data from the
1519          *  supplied buffer to the controller.
1520          */
1521         uint32_t                is_read;
1522
1523         /*
1524          * driver_lock is used by the driver only.  It must be set to 0
1525          *  by the caller.
1526          */
1527         struct mtx *            driver_lock;
1528 };
1529
1530 struct nvme_get_nsid {
1531         char            cdev[SPECNAMELEN + 1];
1532         uint32_t        nsid;
1533 };
1534
1535 struct nvme_hmb_desc {
1536         uint64_t        addr;
1537         uint32_t        size;
1538         uint32_t        reserved;
1539 };
1540
1541 #define nvme_completion_is_error(cpl)                                   \
1542         (NVME_STATUS_GET_SC((cpl)->status) != 0 || NVME_STATUS_GET_SCT((cpl)->status) != 0)
1543
1544 void    nvme_strvis(uint8_t *dst, const uint8_t *src, int dstlen, int srclen);
1545
1546 #ifdef _KERNEL
1547
1548 struct bio;
1549 struct thread;
1550
1551 struct nvme_namespace;
1552 struct nvme_controller;
1553 struct nvme_consumer;
1554
1555 typedef void (*nvme_cb_fn_t)(void *, const struct nvme_completion *);
1556
1557 typedef void *(*nvme_cons_ns_fn_t)(struct nvme_namespace *, void *);
1558 typedef void *(*nvme_cons_ctrlr_fn_t)(struct nvme_controller *);
1559 typedef void (*nvme_cons_async_fn_t)(void *, const struct nvme_completion *,
1560                                      uint32_t, void *, uint32_t);
1561 typedef void (*nvme_cons_fail_fn_t)(void *);
1562
1563 enum nvme_namespace_flags {
1564         NVME_NS_DEALLOCATE_SUPPORTED    = 0x1,
1565         NVME_NS_FLUSH_SUPPORTED         = 0x2,
1566 };
1567
1568 int     nvme_ctrlr_passthrough_cmd(struct nvme_controller *ctrlr,
1569                                    struct nvme_pt_command *pt,
1570                                    uint32_t nsid, int is_user_buffer,
1571                                    int is_admin_cmd);
1572
1573 /* Admin functions */
1574 void    nvme_ctrlr_cmd_set_feature(struct nvme_controller *ctrlr,
1575                                    uint8_t feature, uint32_t cdw11,
1576                                    uint32_t cdw12, uint32_t cdw13,
1577                                    uint32_t cdw14, uint32_t cdw15,
1578                                    void *payload, uint32_t payload_size,
1579                                    nvme_cb_fn_t cb_fn, void *cb_arg);
1580 void    nvme_ctrlr_cmd_get_feature(struct nvme_controller *ctrlr,
1581                                    uint8_t feature, uint32_t cdw11,
1582                                    void *payload, uint32_t payload_size,
1583                                    nvme_cb_fn_t cb_fn, void *cb_arg);
1584 void    nvme_ctrlr_cmd_get_log_page(struct nvme_controller *ctrlr,
1585                                     uint8_t log_page, uint32_t nsid,
1586                                     void *payload, uint32_t payload_size,
1587                                     nvme_cb_fn_t cb_fn, void *cb_arg);
1588
1589 /* NVM I/O functions */
1590 int     nvme_ns_cmd_write(struct nvme_namespace *ns, void *payload,
1591                           uint64_t lba, uint32_t lba_count, nvme_cb_fn_t cb_fn,
1592                           void *cb_arg);
1593 int     nvme_ns_cmd_write_bio(struct nvme_namespace *ns, struct bio *bp,
1594                               nvme_cb_fn_t cb_fn, void *cb_arg);
1595 int     nvme_ns_cmd_read(struct nvme_namespace *ns, void *payload,
1596                          uint64_t lba, uint32_t lba_count, nvme_cb_fn_t cb_fn,
1597                          void *cb_arg);
1598 int     nvme_ns_cmd_read_bio(struct nvme_namespace *ns, struct bio *bp,
1599                               nvme_cb_fn_t cb_fn, void *cb_arg);
1600 int     nvme_ns_cmd_deallocate(struct nvme_namespace *ns, void *payload,
1601                                uint8_t num_ranges, nvme_cb_fn_t cb_fn,
1602                                void *cb_arg);
1603 int     nvme_ns_cmd_flush(struct nvme_namespace *ns, nvme_cb_fn_t cb_fn,
1604                           void *cb_arg);
1605 int     nvme_ns_dump(struct nvme_namespace *ns, void *virt, off_t offset,
1606                      size_t len);
1607
1608 /* Registration functions */
1609 struct nvme_consumer *  nvme_register_consumer(nvme_cons_ns_fn_t    ns_fn,
1610                                                nvme_cons_ctrlr_fn_t ctrlr_fn,
1611                                                nvme_cons_async_fn_t async_fn,
1612                                                nvme_cons_fail_fn_t  fail_fn);
1613 void            nvme_unregister_consumer(struct nvme_consumer *consumer);
1614
1615 /* Controller helper functions */
1616 device_t        nvme_ctrlr_get_device(struct nvme_controller *ctrlr);
1617 const struct nvme_controller_data *
1618                 nvme_ctrlr_get_data(struct nvme_controller *ctrlr);
1619 static inline bool
1620 nvme_ctrlr_has_dataset_mgmt(const struct nvme_controller_data *cd)
1621 {
1622         /* Assumes cd was byte swapped by nvme_controller_data_swapbytes() */
1623         return ((cd->oncs >> NVME_CTRLR_DATA_ONCS_DSM_SHIFT) &
1624                 NVME_CTRLR_DATA_ONCS_DSM_MASK);
1625 }
1626
1627 /* Namespace helper functions */
1628 uint32_t        nvme_ns_get_max_io_xfer_size(struct nvme_namespace *ns);
1629 uint32_t        nvme_ns_get_sector_size(struct nvme_namespace *ns);
1630 uint64_t        nvme_ns_get_num_sectors(struct nvme_namespace *ns);
1631 uint64_t        nvme_ns_get_size(struct nvme_namespace *ns);
1632 uint32_t        nvme_ns_get_flags(struct nvme_namespace *ns);
1633 const char *    nvme_ns_get_serial_number(struct nvme_namespace *ns);
1634 const char *    nvme_ns_get_model_number(struct nvme_namespace *ns);
1635 const struct nvme_namespace_data *
1636                 nvme_ns_get_data(struct nvme_namespace *ns);
1637 uint32_t        nvme_ns_get_stripesize(struct nvme_namespace *ns);
1638
1639 int     nvme_ns_bio_process(struct nvme_namespace *ns, struct bio *bp,
1640                             nvme_cb_fn_t cb_fn);
1641 int     nvme_ns_ioctl_process(struct nvme_namespace *ns, u_long cmd,
1642     caddr_t arg, int flag, struct thread *td);
1643
1644 /*
1645  * Command building helper functions -- shared with CAM
1646  * These functions assume allocator zeros out cmd structure
1647  * CAM's xpt_get_ccb and the request allocator for nvme both
1648  * do zero'd allocations.
1649  */
1650 static inline
1651 void    nvme_ns_flush_cmd(struct nvme_command *cmd, uint32_t nsid)
1652 {
1653
1654         cmd->opc = NVME_OPC_FLUSH;
1655         cmd->nsid = htole32(nsid);
1656 }
1657
1658 static inline
1659 void    nvme_ns_rw_cmd(struct nvme_command *cmd, uint32_t rwcmd, uint32_t nsid,
1660     uint64_t lba, uint32_t count)
1661 {
1662         cmd->opc = rwcmd;
1663         cmd->nsid = htole32(nsid);
1664         cmd->cdw10 = htole32(lba & 0xffffffffu);
1665         cmd->cdw11 = htole32(lba >> 32);
1666         cmd->cdw12 = htole32(count-1);
1667 }
1668
1669 static inline
1670 void    nvme_ns_write_cmd(struct nvme_command *cmd, uint32_t nsid,
1671     uint64_t lba, uint32_t count)
1672 {
1673         nvme_ns_rw_cmd(cmd, NVME_OPC_WRITE, nsid, lba, count);
1674 }
1675
1676 static inline
1677 void    nvme_ns_read_cmd(struct nvme_command *cmd, uint32_t nsid,
1678     uint64_t lba, uint32_t count)
1679 {
1680         nvme_ns_rw_cmd(cmd, NVME_OPC_READ, nsid, lba, count);
1681 }
1682
1683 static inline
1684 void    nvme_ns_trim_cmd(struct nvme_command *cmd, uint32_t nsid,
1685     uint32_t num_ranges)
1686 {
1687         cmd->opc = NVME_OPC_DATASET_MANAGEMENT;
1688         cmd->nsid = htole32(nsid);
1689         cmd->cdw10 = htole32(num_ranges - 1);
1690         cmd->cdw11 = htole32(NVME_DSM_ATTR_DEALLOCATE);
1691 }
1692
1693 extern int nvme_use_nvd;
1694
1695 #endif /* _KERNEL */
1696
1697 /* Endianess conversion functions for NVMe structs */
1698 static inline
1699 void    nvme_completion_swapbytes(struct nvme_completion *s)
1700 {
1701
1702         s->cdw0 = le32toh(s->cdw0);
1703         /* omit rsvd1 */
1704         s->sqhd = le16toh(s->sqhd);
1705         s->sqid = le16toh(s->sqid);
1706         /* omit cid */
1707         s->status = le16toh(s->status);
1708 }
1709
1710 static inline
1711 void    nvme_power_state_swapbytes(struct nvme_power_state *s)
1712 {
1713
1714         s->mp = le16toh(s->mp);
1715         s->enlat = le32toh(s->enlat);
1716         s->exlat = le32toh(s->exlat);
1717         s->idlp = le16toh(s->idlp);
1718         s->actp = le16toh(s->actp);
1719 }
1720
1721 static inline
1722 void    nvme_controller_data_swapbytes(struct nvme_controller_data *s)
1723 {
1724         int i;
1725
1726         s->vid = le16toh(s->vid);
1727         s->ssvid = le16toh(s->ssvid);
1728         s->ctrlr_id = le16toh(s->ctrlr_id);
1729         s->ver = le32toh(s->ver);
1730         s->rtd3r = le32toh(s->rtd3r);
1731         s->rtd3e = le32toh(s->rtd3e);
1732         s->oaes = le32toh(s->oaes);
1733         s->ctratt = le32toh(s->ctratt);
1734         s->rrls = le16toh(s->rrls);
1735         s->crdt1 = le16toh(s->crdt1);
1736         s->crdt2 = le16toh(s->crdt2);
1737         s->crdt3 = le16toh(s->crdt3);
1738         s->oacs = le16toh(s->oacs);
1739         s->wctemp = le16toh(s->wctemp);
1740         s->cctemp = le16toh(s->cctemp);
1741         s->mtfa = le16toh(s->mtfa);
1742         s->hmpre = le32toh(s->hmpre);
1743         s->hmmin = le32toh(s->hmmin);
1744         s->rpmbs = le32toh(s->rpmbs);
1745         s->edstt = le16toh(s->edstt);
1746         s->kas = le16toh(s->kas);
1747         s->hctma = le16toh(s->hctma);
1748         s->mntmt = le16toh(s->mntmt);
1749         s->mxtmt = le16toh(s->mxtmt);
1750         s->sanicap = le32toh(s->sanicap);
1751         s->hmminds = le32toh(s->hmminds);
1752         s->hmmaxd = le16toh(s->hmmaxd);
1753         s->nsetidmax = le16toh(s->nsetidmax);
1754         s->endgidmax = le16toh(s->endgidmax);
1755         s->anagrpmax = le32toh(s->anagrpmax);
1756         s->nanagrpid = le32toh(s->nanagrpid);
1757         s->pels = le32toh(s->pels);
1758         s->maxcmd = le16toh(s->maxcmd);
1759         s->nn = le32toh(s->nn);
1760         s->oncs = le16toh(s->oncs);
1761         s->fuses = le16toh(s->fuses);
1762         s->awun = le16toh(s->awun);
1763         s->awupf = le16toh(s->awupf);
1764         s->acwu = le16toh(s->acwu);
1765         s->sgls = le32toh(s->sgls);
1766         s->mnan = le32toh(s->mnan);
1767         for (i = 0; i < 32; i++)
1768                 nvme_power_state_swapbytes(&s->power_state[i]);
1769 }
1770
1771 static inline
1772 void    nvme_namespace_data_swapbytes(struct nvme_namespace_data *s)
1773 {
1774         int i;
1775
1776         s->nsze = le64toh(s->nsze);
1777         s->ncap = le64toh(s->ncap);
1778         s->nuse = le64toh(s->nuse);
1779         s->nawun = le16toh(s->nawun);
1780         s->nawupf = le16toh(s->nawupf);
1781         s->nacwu = le16toh(s->nacwu);
1782         s->nabsn = le16toh(s->nabsn);
1783         s->nabo = le16toh(s->nabo);
1784         s->nabspf = le16toh(s->nabspf);
1785         s->noiob = le16toh(s->noiob);
1786         s->npwg = le16toh(s->npwg);
1787         s->npwa = le16toh(s->npwa);
1788         s->npdg = le16toh(s->npdg);
1789         s->npda = le16toh(s->npda);
1790         s->nows = le16toh(s->nows);
1791         s->anagrpid = le32toh(s->anagrpid);
1792         s->nvmsetid = le16toh(s->nvmsetid);
1793         s->endgid = le16toh(s->endgid);
1794         for (i = 0; i < 16; i++)
1795                 s->lbaf[i] = le32toh(s->lbaf[i]);
1796 }
1797
1798 static inline
1799 void    nvme_error_information_entry_swapbytes(struct nvme_error_information_entry *s)
1800 {
1801
1802         s->error_count = le64toh(s->error_count);
1803         s->sqid = le16toh(s->sqid);
1804         s->cid = le16toh(s->cid);
1805         s->status = le16toh(s->status);
1806         s->error_location = le16toh(s->error_location);
1807         s->lba = le64toh(s->lba);
1808         s->nsid = le32toh(s->nsid);
1809         s->csi = le64toh(s->csi);
1810         s->ttsi = le16toh(s->ttsi);
1811 }
1812
1813 static inline
1814 void    nvme_le128toh(void *p)
1815 {
1816 #if _BYTE_ORDER != _LITTLE_ENDIAN
1817         /* Swap 16 bytes in place */
1818         char *tmp = (char*)p;
1819         char b;
1820         int i;
1821         for (i = 0; i < 8; i++) {
1822                 b = tmp[i];
1823                 tmp[i] = tmp[15-i];
1824                 tmp[15-i] = b;
1825         }
1826 #else
1827         (void)p;
1828 #endif
1829 }
1830
1831 static inline
1832 void    nvme_health_information_page_swapbytes(struct nvme_health_information_page *s)
1833 {
1834         int i;
1835
1836         s->temperature = le16toh(s->temperature);
1837         nvme_le128toh((void *)s->data_units_read);
1838         nvme_le128toh((void *)s->data_units_written);
1839         nvme_le128toh((void *)s->host_read_commands);
1840         nvme_le128toh((void *)s->host_write_commands);
1841         nvme_le128toh((void *)s->controller_busy_time);
1842         nvme_le128toh((void *)s->power_cycles);
1843         nvme_le128toh((void *)s->power_on_hours);
1844         nvme_le128toh((void *)s->unsafe_shutdowns);
1845         nvme_le128toh((void *)s->media_errors);
1846         nvme_le128toh((void *)s->num_error_info_log_entries);
1847         s->warning_temp_time = le32toh(s->warning_temp_time);
1848         s->error_temp_time = le32toh(s->error_temp_time);
1849         for (i = 0; i < 8; i++)
1850                 s->temp_sensor[i] = le16toh(s->temp_sensor[i]);
1851         s->tmt1tc = le32toh(s->tmt1tc);
1852         s->tmt2tc = le32toh(s->tmt2tc);
1853         s->ttftmt1 = le32toh(s->ttftmt1);
1854         s->ttftmt2 = le32toh(s->ttftmt2);
1855 }
1856
1857 static inline
1858 void    nvme_firmware_page_swapbytes(struct nvme_firmware_page *s)
1859 {
1860         int i;
1861
1862         for (i = 0; i < 7; i++)
1863                 s->revision[i] = le64toh(s->revision[i]);
1864 }
1865
1866 static inline
1867 void    nvme_ns_list_swapbytes(struct nvme_ns_list *s)
1868 {
1869         int i;
1870
1871         for (i = 0; i < 1024; i++)
1872                 s->ns[i] = le32toh(s->ns[i]);
1873 }
1874
1875 static inline
1876 void    nvme_command_effects_page_swapbytes(struct nvme_command_effects_page *s)
1877 {
1878         int i;
1879
1880         for (i = 0; i < 256; i++)
1881                 s->acs[i] = le32toh(s->acs[i]);
1882         for (i = 0; i < 256; i++)
1883                 s->iocs[i] = le32toh(s->iocs[i]);
1884 }
1885
1886 static inline
1887 void    nvme_res_notification_page_swapbytes(struct nvme_res_notification_page *s)
1888 {
1889         s->log_page_count = le64toh(s->log_page_count);
1890         s->nsid = le32toh(s->nsid);
1891 }
1892
1893 static inline
1894 void    nvme_sanitize_status_page_swapbytes(struct nvme_sanitize_status_page *s)
1895 {
1896         s->sprog = le16toh(s->sprog);
1897         s->sstat = le16toh(s->sstat);
1898         s->scdw10 = le32toh(s->scdw10);
1899         s->etfo = le32toh(s->etfo);
1900         s->etfbe = le32toh(s->etfbe);
1901         s->etfce = le32toh(s->etfce);
1902         s->etfownd = le32toh(s->etfownd);
1903         s->etfbewnd = le32toh(s->etfbewnd);
1904         s->etfcewnd = le32toh(s->etfcewnd);
1905 }
1906
1907 static inline
1908 void    intel_log_temp_stats_swapbytes(struct intel_log_temp_stats *s)
1909 {
1910
1911         s->current = le64toh(s->current);
1912         s->overtemp_flag_last = le64toh(s->overtemp_flag_last);
1913         s->overtemp_flag_life = le64toh(s->overtemp_flag_life);
1914         s->max_temp = le64toh(s->max_temp);
1915         s->min_temp = le64toh(s->min_temp);
1916         /* omit _rsvd[] */
1917         s->max_oper_temp = le64toh(s->max_oper_temp);
1918         s->min_oper_temp = le64toh(s->min_oper_temp);
1919         s->est_offset = le64toh(s->est_offset);
1920 }
1921
1922 static inline
1923 void    nvme_resv_status_swapbytes(struct nvme_resv_status *s, size_t size)
1924 {
1925         u_int i, n;
1926
1927         s->gen = le32toh(s->gen);
1928         n = (s->regctl[1] << 8) | s->regctl[0];
1929         n = MIN(n, (size - sizeof(s)) / sizeof(s->ctrlr[0]));
1930         for (i = 0; i < n; i++) {
1931                 s->ctrlr[i].ctrlr_id = le16toh(s->ctrlr[i].ctrlr_id);
1932                 s->ctrlr[i].hostid = le64toh(s->ctrlr[i].hostid);
1933                 s->ctrlr[i].rkey = le64toh(s->ctrlr[i].rkey);
1934         }
1935 }
1936
1937 static inline
1938 void    nvme_resv_status_ext_swapbytes(struct nvme_resv_status_ext *s, size_t size)
1939 {
1940         u_int i, n;
1941
1942         s->gen = le32toh(s->gen);
1943         n = (s->regctl[1] << 8) | s->regctl[0];
1944         n = MIN(n, (size - sizeof(s)) / sizeof(s->ctrlr[0]));
1945         for (i = 0; i < n; i++) {
1946                 s->ctrlr[i].ctrlr_id = le16toh(s->ctrlr[i].ctrlr_id);
1947                 s->ctrlr[i].rkey = le64toh(s->ctrlr[i].rkey);
1948                 nvme_le128toh((void *)s->ctrlr[i].hostid);
1949         }
1950 }
1951
1952 #endif /* __NVME_H__ */