sys/dev/nvme/nvme_ctrlr.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (C) 2012-2016 Intel Corporation
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  */
  28
  29 #include <sys/cdefs.h>
  30 __FBSDID("$FreeBSD$");
  31
  32 #include "opt_cam.h"
  33
  34 #include <sys/param.h>
  35 #include <sys/systm.h>
  36 #include <sys/buf.h>
  37 #include <sys/bus.h>
  38 #include <sys/conf.h>
  39 #include <sys/ioccom.h>
  40 #include <sys/proc.h>
  41 #include <sys/smp.h>
  42 #include <sys/uio.h>
  43 #include <sys/sbuf.h>
  44 #include <sys/endian.h>
  45 #include <machine/stdarg.h>
  46 #include <vm/vm.h>
  47
  48 #include "nvme_private.h"
  49
  50 #define B4_CHK_RDY_DELAY_MS     2300            /* work around controller bug */
  51
  52 static void nvme_ctrlr_construct_and_submit_aer(struct nvme_controller *ctrlr,
  53                                                 struct nvme_async_event_request *aer);
  54
  55 static void
  56 nvme_ctrlr_barrier(struct nvme_controller *ctrlr, int flags)
  57 {
  58         bus_barrier(ctrlr->resource, 0, rman_get_size(ctrlr->resource), flags);
  59 }
  60
  61 static void
  62 nvme_ctrlr_devctl_log(struct nvme_controller *ctrlr, const char *type, const char *msg, ...)
  63 {
  64         struct sbuf sb;
  65         va_list ap;
  66         int error;
  67
  68         if (sbuf_new(&sb, NULL, 0, SBUF_AUTOEXTEND | SBUF_NOWAIT) == NULL)
  69                 return;
  70         sbuf_printf(&sb, "%s: ", device_get_nameunit(ctrlr->dev));
  71         va_start(ap, msg);
  72         sbuf_vprintf(&sb, msg, ap);
  73         va_end(ap);
  74         error = sbuf_finish(&sb);
  75         if (error == 0)
  76                 printf("%s\n", sbuf_data(&sb));
  77
  78         sbuf_clear(&sb);
  79         sbuf_printf(&sb, "name=\"%s\" reason=\"", device_get_nameunit(ctrlr->dev));
  80         va_start(ap, msg);
  81         sbuf_vprintf(&sb, msg, ap);
  82         va_end(ap);
  83         sbuf_printf(&sb, "\"");
  84         error = sbuf_finish(&sb);
  85         if (error == 0)
  86                 devctl_notify("nvme", "controller", type, sbuf_data(&sb));
  87         sbuf_delete(&sb);
  88 }
  89
  90 static int
  91 nvme_ctrlr_construct_admin_qpair(struct nvme_controller *ctrlr)
  92 {
  93         struct nvme_qpair       *qpair;
  94         uint32_t                num_entries;
  95         int                     error;
  96
  97         qpair = &ctrlr->adminq;
  98         qpair->id = 0;
  99         qpair->cpu = CPU_FFS(&cpuset_domain[ctrlr->domain]) - 1;
 100         qpair->domain = ctrlr->domain;
 101
 102         num_entries = NVME_ADMIN_ENTRIES;
 103         TUNABLE_INT_FETCH("hw.nvme.admin_entries", &num_entries);
 104         /*
 105          * If admin_entries was overridden to an invalid value, revert it
 106          *  back to our default value.
 107          */
 108         if (num_entries < NVME_MIN_ADMIN_ENTRIES ||
 109             num_entries > NVME_MAX_ADMIN_ENTRIES) {
 110                 nvme_printf(ctrlr, "invalid hw.nvme.admin_entries=%d "
 111                     "specified\n", num_entries);
 112                 num_entries = NVME_ADMIN_ENTRIES;
 113         }
 114
 115         /*
 116          * The admin queue's max xfer size is treated differently than the
 117          *  max I/O xfer size.  16KB is sufficient here - maybe even less?
 118          */
 119         error = nvme_qpair_construct(qpair, num_entries, NVME_ADMIN_TRACKERS,
 120              ctrlr);
 121         return (error);
 122 }
 123
 124 #define QP(ctrlr, c)    ((c) * (ctrlr)->num_io_queues / mp_ncpus)
 125
 126 static int
 127 nvme_ctrlr_construct_io_qpairs(struct nvme_controller *ctrlr)
 128 {
 129         struct nvme_qpair       *qpair;
 130         uint32_t                cap_lo;
 131         uint16_t                mqes;
 132         int                     c, error, i, n;
 133         int                     num_entries, num_trackers, max_entries;
 134
 135         /*
 136          * NVMe spec sets a hard limit of 64K max entries, but devices may
 137          * specify a smaller limit, so we need to check the MQES field in the
 138          * capabilities register. We have to cap the number of entries to the
 139          * current stride allows for in BAR 0/1, otherwise the remainder entries
 140          * are inaccessable. MQES should reflect this, and this is just a
 141          * fail-safe.
 142          */
 143         max_entries =
 144             (rman_get_size(ctrlr->resource) - nvme_mmio_offsetof(doorbell[0])) /
 145             (1 << (ctrlr->dstrd + 1));
 146         num_entries = NVME_IO_ENTRIES;
 147         TUNABLE_INT_FETCH("hw.nvme.io_entries", &num_entries);
 148         cap_lo = nvme_mmio_read_4(ctrlr, cap_lo);
 149         mqes = NVME_CAP_LO_MQES(cap_lo);
 150         num_entries = min(num_entries, mqes + 1);
 151         num_entries = min(num_entries, max_entries);
 152
 153         num_trackers = NVME_IO_TRACKERS;
 154         TUNABLE_INT_FETCH("hw.nvme.io_trackers", &num_trackers);
 155
 156         num_trackers = max(num_trackers, NVME_MIN_IO_TRACKERS);
 157         num_trackers = min(num_trackers, NVME_MAX_IO_TRACKERS);
 158         /*
 159          * No need to have more trackers than entries in the submit queue.  Note
 160          * also that for a queue size of N, we can only have (N-1) commands
 161          * outstanding, hence the "-1" here.
 162          */
 163         num_trackers = min(num_trackers, (num_entries-1));
 164
 165         /*
 166          * Our best estimate for the maximum number of I/Os that we should
 167          * normally have in flight at one time. This should be viewed as a hint,
 168          * not a hard limit and will need to be revisited when the upper layers
 169          * of the storage system grows multi-queue support.
 170          */
 171         ctrlr->max_hw_pend_io = num_trackers * ctrlr->num_io_queues * 3 / 4;
 172
 173         ctrlr->ioq = malloc(ctrlr->num_io_queues * sizeof(struct nvme_qpair),
 174             M_NVME, M_ZERO | M_WAITOK);
 175
 176         for (i = c = n = 0; i < ctrlr->num_io_queues; i++, c += n) {
 177                 qpair = &ctrlr->ioq[i];
 178
 179                 /*
 180                  * Admin queue has ID=0. IO queues start at ID=1 -
 181                  *  hence the 'i+1' here.
 182                  */
 183                 qpair->id = i + 1;
 184                 if (ctrlr->num_io_queues > 1) {
 185                         /* Find number of CPUs served by this queue. */
 186                         for (n = 1; QP(ctrlr, c + n) == i; n++)
 187                                 ;
 188                         /* Shuffle multiple NVMe devices between CPUs. */
 189                         qpair->cpu = c + (device_get_unit(ctrlr->dev)+n/2) % n;
 190                         qpair->domain = pcpu_find(qpair->cpu)->pc_domain;
 191                 } else {
 192                         qpair->cpu = CPU_FFS(&cpuset_domain[ctrlr->domain]) - 1;
 193                         qpair->domain = ctrlr->domain;
 194                 }
 195
 196                 /*
 197                  * For I/O queues, use the controller-wide max_xfer_size
 198                  *  calculated in nvme_attach().
 199                  */
 200                 error = nvme_qpair_construct(qpair, num_entries, num_trackers,
 201                     ctrlr);
 202                 if (error)
 203                         return (error);
 204
 205                 /*
 206                  * Do not bother binding interrupts if we only have one I/O
 207                  *  interrupt thread for this controller.
 208                  */
 209                 if (ctrlr->num_io_queues > 1)
 210                         bus_bind_intr(ctrlr->dev, qpair->res, qpair->cpu);
 211         }
 212
 213         return (0);
 214 }
 215
 216 static void
 217 nvme_ctrlr_fail(struct nvme_controller *ctrlr)
 218 {
 219         int i;
 220
 221         ctrlr->is_failed = true;
 222         nvme_admin_qpair_disable(&ctrlr->adminq);
 223         nvme_qpair_fail(&ctrlr->adminq);
 224         if (ctrlr->ioq != NULL) {
 225                 for (i = 0; i < ctrlr->num_io_queues; i++) {
 226                         nvme_io_qpair_disable(&ctrlr->ioq[i]);
 227                         nvme_qpair_fail(&ctrlr->ioq[i]);
 228                 }
 229         }
 230         nvme_notify_fail_consumers(ctrlr);
 231 }
 232
 233 void
 234 nvme_ctrlr_post_failed_request(struct nvme_controller *ctrlr,
 235     struct nvme_request *req)
 236 {
 237
 238         mtx_lock(&ctrlr->lock);
 239         STAILQ_INSERT_TAIL(&ctrlr->fail_req, req, stailq);
 240         mtx_unlock(&ctrlr->lock);
 241         if (!ctrlr->is_dying)
 242                 taskqueue_enqueue(ctrlr->taskqueue, &ctrlr->fail_req_task);
 243 }
 244
 245 static void
 246 nvme_ctrlr_fail_req_task(void *arg, int pending)
 247 {
 248         struct nvme_controller  *ctrlr = arg;
 249         struct nvme_request     *req;
 250
 251         mtx_lock(&ctrlr->lock);
 252         while ((req = STAILQ_FIRST(&ctrlr->fail_req)) != NULL) {
 253                 STAILQ_REMOVE_HEAD(&ctrlr->fail_req, stailq);
 254                 mtx_unlock(&ctrlr->lock);
 255                 nvme_qpair_manual_complete_request(req->qpair, req,
 256                     NVME_SCT_GENERIC, NVME_SC_ABORTED_BY_REQUEST);
 257                 mtx_lock(&ctrlr->lock);
 258         }
 259         mtx_unlock(&ctrlr->lock);
 260 }
 261
 262 static int
 263 nvme_ctrlr_wait_for_ready(struct nvme_controller *ctrlr, int desired_val)
 264 {
 265         int timeout = ticks + (uint64_t)ctrlr->ready_timeout_in_ms * hz / 1000;
 266         uint32_t csts;
 267
 268         while (1) {
 269                 csts = nvme_mmio_read_4(ctrlr, csts);
 270                 if (csts == NVME_GONE)          /* Hot unplug. */
 271                         return (ENXIO);
 272                 if (((csts >> NVME_CSTS_REG_RDY_SHIFT) & NVME_CSTS_REG_RDY_MASK)
 273                     == desired_val)
 274                         break;
 275                 if (timeout - ticks < 0) {
 276                         nvme_printf(ctrlr, "controller ready did not become %d "
 277                             "within %d ms\n", desired_val, ctrlr->ready_timeout_in_ms);
 278                         return (ENXIO);
 279                 }
 280                 pause("nvmerdy", 1);
 281         }
 282
 283         return (0);
 284 }
 285
 286 static int
 287 nvme_ctrlr_disable(struct nvme_controller *ctrlr)
 288 {
 289         uint32_t cc;
 290         uint32_t csts;
 291         uint8_t  en, rdy;
 292         int err;
 293
 294         cc = nvme_mmio_read_4(ctrlr, cc);
 295         csts = nvme_mmio_read_4(ctrlr, csts);
 296
 297         en = (cc >> NVME_CC_REG_EN_SHIFT) & NVME_CC_REG_EN_MASK;
 298         rdy = (csts >> NVME_CSTS_REG_RDY_SHIFT) & NVME_CSTS_REG_RDY_MASK;
 299
 300         /*
 301          * Per 3.1.5 in NVME 1.3 spec, transitioning CC.EN from 0 to 1
 302          * when CSTS.RDY is 1 or transitioning CC.EN from 1 to 0 when
 303          * CSTS.RDY is 0 "has undefined results" So make sure that CSTS.RDY
 304          * isn't the desired value. Short circuit if we're already disabled.
 305          */
 306         if (en == 1) {
 307                 if (rdy == 0) {
 308                         /* EN == 1, wait for  RDY == 1 or fail */
 309                         err = nvme_ctrlr_wait_for_ready(ctrlr, 1);
 310                         if (err != 0)
 311                                 return (err);
 312                 }
 313         } else {
 314                 /* EN == 0 already wait for RDY == 0 */
 315                 if (rdy == 0)
 316                         return (0);
 317                 else
 318                         return (nvme_ctrlr_wait_for_ready(ctrlr, 0));
 319         }
 320
 321         cc &= ~NVME_CC_REG_EN_MASK;
 322         nvme_mmio_write_4(ctrlr, cc, cc);
 323         /*
 324          * Some drives have issues with accessing the mmio after we
 325          * disable, so delay for a bit after we write the bit to
 326          * cope with these issues.
 327          */
 328         if (ctrlr->quirks & QUIRK_DELAY_B4_CHK_RDY)
 329                 pause("nvmeR", B4_CHK_RDY_DELAY_MS * hz / 1000);
 330         return (nvme_ctrlr_wait_for_ready(ctrlr, 0));
 331 }
 332
 333 static int
 334 nvme_ctrlr_enable(struct nvme_controller *ctrlr)
 335 {
 336         uint32_t        cc;
 337         uint32_t        csts;
 338         uint32_t        aqa;
 339         uint32_t        qsize;
 340         uint8_t         en, rdy;
 341         int             err;
 342
 343         cc = nvme_mmio_read_4(ctrlr, cc);
 344         csts = nvme_mmio_read_4(ctrlr, csts);
 345
 346         en = (cc >> NVME_CC_REG_EN_SHIFT) & NVME_CC_REG_EN_MASK;
 347         rdy = (csts >> NVME_CSTS_REG_RDY_SHIFT) & NVME_CSTS_REG_RDY_MASK;
 348
 349         /*
 350          * See note in nvme_ctrlr_disable. Short circuit if we're already enabled.
 351          */
 352         if (en == 1) {
 353                 if (rdy == 1)
 354                         return (0);
 355                 else
 356                         return (nvme_ctrlr_wait_for_ready(ctrlr, 1));
 357         } else {
 358                 /* EN == 0 already wait for RDY == 0 or fail */
 359                 err = nvme_ctrlr_wait_for_ready(ctrlr, 0);
 360                 if (err != 0)
 361                         return (err);
 362         }
 363
 364         nvme_mmio_write_8(ctrlr, asq, ctrlr->adminq.cmd_bus_addr);
 365         nvme_mmio_write_8(ctrlr, acq, ctrlr->adminq.cpl_bus_addr);
 366
 367         /* acqs and asqs are 0-based. */
 368         qsize = ctrlr->adminq.num_entries - 1;
 369
 370         aqa = 0;
 371         aqa = (qsize & NVME_AQA_REG_ACQS_MASK) << NVME_AQA_REG_ACQS_SHIFT;
 372         aqa |= (qsize & NVME_AQA_REG_ASQS_MASK) << NVME_AQA_REG_ASQS_SHIFT;
 373         nvme_mmio_write_4(ctrlr, aqa, aqa);
 374
 375         /* Initialization values for CC */
 376         cc = 0;
 377         cc |= 1 << NVME_CC_REG_EN_SHIFT;
 378         cc |= 0 << NVME_CC_REG_CSS_SHIFT;
 379         cc |= 0 << NVME_CC_REG_AMS_SHIFT;
 380         cc |= 0 << NVME_CC_REG_SHN_SHIFT;
 381         cc |= 6 << NVME_CC_REG_IOSQES_SHIFT; /* SQ entry size == 64 == 2^6 */
 382         cc |= 4 << NVME_CC_REG_IOCQES_SHIFT; /* CQ entry size == 16 == 2^4 */
 383
 384         /* This evaluates to 0, which is according to spec. */
 385         cc |= (PAGE_SIZE >> 13) << NVME_CC_REG_MPS_SHIFT;
 386
 387         nvme_ctrlr_barrier(ctrlr, BUS_SPACE_BARRIER_WRITE);
 388         nvme_mmio_write_4(ctrlr, cc, cc);
 389
 390         return (nvme_ctrlr_wait_for_ready(ctrlr, 1));
 391 }
 392
 393 static void
 394 nvme_ctrlr_disable_qpairs(struct nvme_controller *ctrlr)
 395 {
 396         int i;
 397
 398         nvme_admin_qpair_disable(&ctrlr->adminq);
 399         /*
 400          * I/O queues are not allocated before the initial HW
 401          *  reset, so do not try to disable them.  Use is_initialized
 402          *  to determine if this is the initial HW reset.
 403          */
 404         if (ctrlr->is_initialized) {
 405                 for (i = 0; i < ctrlr->num_io_queues; i++)
 406                         nvme_io_qpair_disable(&ctrlr->ioq[i]);
 407         }
 408 }
 409
 410 static int
 411 nvme_ctrlr_hw_reset(struct nvme_controller *ctrlr)
 412 {
 413         int err;
 414
 415         TSENTER();
 416         nvme_ctrlr_disable_qpairs(ctrlr);
 417
 418         pause("nvmehwreset", hz / 10);
 419
 420         err = nvme_ctrlr_disable(ctrlr);
 421         if (err != 0)
 422                 return err;
 423         err = nvme_ctrlr_enable(ctrlr);
 424         TSEXIT();
 425         return (err);
 426 }
 427
 428 void
 429 nvme_ctrlr_reset(struct nvme_controller *ctrlr)
 430 {
 431         int cmpset;
 432
 433         cmpset = atomic_cmpset_32(&ctrlr->is_resetting, 0, 1);
 434
 435         if (cmpset == 0 || ctrlr->is_failed)
 436                 /*
 437                  * Controller is already resetting or has failed.  Return
 438                  *  immediately since there is no need to kick off another
 439                  *  reset in these cases.
 440                  */
 441                 return;
 442
 443         if (!ctrlr->is_dying)
 444                 taskqueue_enqueue(ctrlr->taskqueue, &ctrlr->reset_task);
 445 }
 446
 447 static int
 448 nvme_ctrlr_identify(struct nvme_controller *ctrlr)
 449 {
 450         struct nvme_completion_poll_status      status;
 451
 452         status.done = 0;
 453         nvme_ctrlr_cmd_identify_controller(ctrlr, &ctrlr->cdata,
 454             nvme_completion_poll_cb, &status);
 455         nvme_completion_poll(&status);
 456         if (nvme_completion_is_error(&status.cpl)) {
 457                 nvme_printf(ctrlr, "nvme_identify_controller failed!\n");
 458                 return (ENXIO);
 459         }
 460
 461         /* Convert data to host endian */
 462         nvme_controller_data_swapbytes(&ctrlr->cdata);
 463
 464         /*
 465          * Use MDTS to ensure our default max_xfer_size doesn't exceed what the
 466          *  controller supports.
 467          */
 468         if (ctrlr->cdata.mdts > 0)
 469                 ctrlr->max_xfer_size = min(ctrlr->max_xfer_size,
 470                     ctrlr->min_page_size * (1 << (ctrlr->cdata.mdts)));
 471
 472         return (0);
 473 }
 474
 475 static int
 476 nvme_ctrlr_set_num_qpairs(struct nvme_controller *ctrlr)
 477 {
 478         struct nvme_completion_poll_status      status;
 479         int                                     cq_allocated, sq_allocated;
 480
 481         status.done = 0;
 482         nvme_ctrlr_cmd_set_num_queues(ctrlr, ctrlr->num_io_queues,
 483             nvme_completion_poll_cb, &status);
 484         nvme_completion_poll(&status);
 485         if (nvme_completion_is_error(&status.cpl)) {
 486                 nvme_printf(ctrlr, "nvme_ctrlr_set_num_qpairs failed!\n");
 487                 return (ENXIO);
 488         }
 489
 490         /*
 491          * Data in cdw0 is 0-based.
 492          * Lower 16-bits indicate number of submission queues allocated.
 493          * Upper 16-bits indicate number of completion queues allocated.
 494          */
 495         sq_allocated = (status.cpl.cdw0 & 0xFFFF) + 1;
 496         cq_allocated = (status.cpl.cdw0 >> 16) + 1;
 497
 498         /*
 499          * Controller may allocate more queues than we requested,
 500          *  so use the minimum of the number requested and what was
 501          *  actually allocated.
 502          */
 503         ctrlr->num_io_queues = min(ctrlr->num_io_queues, sq_allocated);
 504         ctrlr->num_io_queues = min(ctrlr->num_io_queues, cq_allocated);
 505         if (ctrlr->num_io_queues > vm_ndomains)
 506                 ctrlr->num_io_queues -= ctrlr->num_io_queues % vm_ndomains;
 507
 508         return (0);
 509 }
 510
 511 static int
 512 nvme_ctrlr_create_qpairs(struct nvme_controller *ctrlr)
 513 {
 514         struct nvme_completion_poll_status      status;
 515         struct nvme_qpair                       *qpair;
 516         int                                     i;
 517
 518         for (i = 0; i < ctrlr->num_io_queues; i++) {
 519                 qpair = &ctrlr->ioq[i];
 520
 521                 status.done = 0;
 522                 nvme_ctrlr_cmd_create_io_cq(ctrlr, qpair,
 523                     nvme_completion_poll_cb, &status);
 524                 nvme_completion_poll(&status);
 525                 if (nvme_completion_is_error(&status.cpl)) {
 526                         nvme_printf(ctrlr, "nvme_create_io_cq failed!\n");
 527                         return (ENXIO);
 528                 }
 529
 530                 status.done = 0;
 531                 nvme_ctrlr_cmd_create_io_sq(ctrlr, qpair,
 532                     nvme_completion_poll_cb, &status);
 533                 nvme_completion_poll(&status);
 534                 if (nvme_completion_is_error(&status.cpl)) {
 535                         nvme_printf(ctrlr, "nvme_create_io_sq failed!\n");
 536                         return (ENXIO);
 537                 }
 538         }
 539
 540         return (0);
 541 }
 542
 543 static int
 544 nvme_ctrlr_delete_qpairs(struct nvme_controller *ctrlr)
 545 {
 546         struct nvme_completion_poll_status      status;
 547         struct nvme_qpair                       *qpair;
 548
 549         for (int i = 0; i < ctrlr->num_io_queues; i++) {
 550                 qpair = &ctrlr->ioq[i];
 551
 552                 status.done = 0;
 553                 nvme_ctrlr_cmd_delete_io_sq(ctrlr, qpair,
 554                     nvme_completion_poll_cb, &status);
 555                 nvme_completion_poll(&status);
 556                 if (nvme_completion_is_error(&status.cpl)) {
 557                         nvme_printf(ctrlr, "nvme_destroy_io_sq failed!\n");
 558                         return (ENXIO);
 559                 }
 560
 561                 status.done = 0;
 562                 nvme_ctrlr_cmd_delete_io_cq(ctrlr, qpair,
 563                     nvme_completion_poll_cb, &status);
 564                 nvme_completion_poll(&status);
 565                 if (nvme_completion_is_error(&status.cpl)) {
 566                         nvme_printf(ctrlr, "nvme_destroy_io_cq failed!\n");
 567                         return (ENXIO);
 568                 }
 569         }
 570
 571         return (0);
 572 }
 573
 574 static int
 575 nvme_ctrlr_construct_namespaces(struct nvme_controller *ctrlr)
 576 {
 577         struct nvme_namespace   *ns;
 578         uint32_t                i;
 579
 580         for (i = 0; i < min(ctrlr->cdata.nn, NVME_MAX_NAMESPACES); i++) {
 581                 ns = &ctrlr->ns[i];
 582                 nvme_ns_construct(ns, i+1, ctrlr);
 583         }
 584
 585         return (0);
 586 }
 587
 588 static bool
 589 is_log_page_id_valid(uint8_t page_id)
 590 {
 591
 592         switch (page_id) {
 593         case NVME_LOG_ERROR:
 594         case NVME_LOG_HEALTH_INFORMATION:
 595         case NVME_LOG_FIRMWARE_SLOT:
 596         case NVME_LOG_CHANGED_NAMESPACE:
 597         case NVME_LOG_COMMAND_EFFECT:
 598         case NVME_LOG_RES_NOTIFICATION:
 599         case NVME_LOG_SANITIZE_STATUS:
 600                 return (true);
 601         }
 602
 603         return (false);
 604 }
 605
 606 static uint32_t
 607 nvme_ctrlr_get_log_page_size(struct nvme_controller *ctrlr, uint8_t page_id)
 608 {
 609         uint32_t        log_page_size;
 610
 611         switch (page_id) {
 612         case NVME_LOG_ERROR:
 613                 log_page_size = min(
 614                     sizeof(struct nvme_error_information_entry) *
 615                     (ctrlr->cdata.elpe + 1), NVME_MAX_AER_LOG_SIZE);
 616                 break;
 617         case NVME_LOG_HEALTH_INFORMATION:
 618                 log_page_size = sizeof(struct nvme_health_information_page);
 619                 break;
 620         case NVME_LOG_FIRMWARE_SLOT:
 621                 log_page_size = sizeof(struct nvme_firmware_page);
 622                 break;
 623         case NVME_LOG_CHANGED_NAMESPACE:
 624                 log_page_size = sizeof(struct nvme_ns_list);
 625                 break;
 626         case NVME_LOG_COMMAND_EFFECT:
 627                 log_page_size = sizeof(struct nvme_command_effects_page);
 628                 break;
 629         case NVME_LOG_RES_NOTIFICATION:
 630                 log_page_size = sizeof(struct nvme_res_notification_page);
 631                 break;
 632         case NVME_LOG_SANITIZE_STATUS:
 633                 log_page_size = sizeof(struct nvme_sanitize_status_page);
 634                 break;
 635         default:
 636                 log_page_size = 0;
 637                 break;
 638         }
 639
 640         return (log_page_size);
 641 }
 642
 643 static void
 644 nvme_ctrlr_log_critical_warnings(struct nvme_controller *ctrlr,
 645     uint8_t state)
 646 {
 647
 648         if (state & NVME_CRIT_WARN_ST_AVAILABLE_SPARE)
 649                 nvme_ctrlr_devctl_log(ctrlr, "critical",
 650                     "available spare space below threshold");
 651
 652         if (state & NVME_CRIT_WARN_ST_TEMPERATURE)
 653                 nvme_ctrlr_devctl_log(ctrlr, "critical",
 654                     "temperature above threshold");
 655
 656         if (state & NVME_CRIT_WARN_ST_DEVICE_RELIABILITY)
 657                 nvme_ctrlr_devctl_log(ctrlr, "critical",
 658                     "device reliability degraded");
 659
 660         if (state & NVME_CRIT_WARN_ST_READ_ONLY)
 661                 nvme_ctrlr_devctl_log(ctrlr, "critical",
 662                     "media placed in read only mode");
 663
 664         if (state & NVME_CRIT_WARN_ST_VOLATILE_MEMORY_BACKUP)
 665                 nvme_ctrlr_devctl_log(ctrlr, "critical",
 666                     "volatile memory backup device failed");
 667
 668         if (state & NVME_CRIT_WARN_ST_RESERVED_MASK)
 669                 nvme_ctrlr_devctl_log(ctrlr, "critical",
 670                     "unknown critical warning(s): state = 0x%02x", state);
 671 }
 672
 673 static void
 674 nvme_ctrlr_async_event_log_page_cb(void *arg, const struct nvme_completion *cpl)
 675 {
 676         struct nvme_async_event_request         *aer = arg;
 677         struct nvme_health_information_page     *health_info;
 678         struct nvme_ns_list                     *nsl;
 679         struct nvme_error_information_entry     *err;
 680         int i;
 681
 682         /*
 683          * If the log page fetch for some reason completed with an error,
 684          *  don't pass log page data to the consumers.  In practice, this case
 685          *  should never happen.
 686          */
 687         if (nvme_completion_is_error(cpl))
 688                 nvme_notify_async_consumers(aer->ctrlr, &aer->cpl,
 689                     aer->log_page_id, NULL, 0);
 690         else {
 691                 /* Convert data to host endian */
 692                 switch (aer->log_page_id) {
 693                 case NVME_LOG_ERROR:
 694                         err = (struct nvme_error_information_entry *)aer->log_page_buffer;
 695                         for (i = 0; i < (aer->ctrlr->cdata.elpe + 1); i++)
 696                                 nvme_error_information_entry_swapbytes(err++);
 697                         break;
 698                 case NVME_LOG_HEALTH_INFORMATION:
 699                         nvme_health_information_page_swapbytes(
 700                             (struct nvme_health_information_page *)aer->log_page_buffer);
 701                         break;
 702                 case NVME_LOG_FIRMWARE_SLOT:
 703                         nvme_firmware_page_swapbytes(
 704                             (struct nvme_firmware_page *)aer->log_page_buffer);
 705                         break;
 706                 case NVME_LOG_CHANGED_NAMESPACE:
 707                         nvme_ns_list_swapbytes(
 708                             (struct nvme_ns_list *)aer->log_page_buffer);
 709                         break;
 710                 case NVME_LOG_COMMAND_EFFECT:
 711                         nvme_command_effects_page_swapbytes(
 712                             (struct nvme_command_effects_page *)aer->log_page_buffer);
 713                         break;
 714                 case NVME_LOG_RES_NOTIFICATION:
 715                         nvme_res_notification_page_swapbytes(
 716                             (struct nvme_res_notification_page *)aer->log_page_buffer);
 717                         break;
 718                 case NVME_LOG_SANITIZE_STATUS:
 719                         nvme_sanitize_status_page_swapbytes(
 720                             (struct nvme_sanitize_status_page *)aer->log_page_buffer);
 721                         break;
 722                 case INTEL_LOG_TEMP_STATS:
 723                         intel_log_temp_stats_swapbytes(
 724                             (struct intel_log_temp_stats *)aer->log_page_buffer);
 725                         break;
 726                 default:
 727                         break;
 728                 }
 729
 730                 if (aer->log_page_id == NVME_LOG_HEALTH_INFORMATION) {
 731                         health_info = (struct nvme_health_information_page *)
 732                             aer->log_page_buffer;
 733                         nvme_ctrlr_log_critical_warnings(aer->ctrlr,
 734                             health_info->critical_warning);
 735                         /*
 736                          * Critical warnings reported through the
 737                          *  SMART/health log page are persistent, so
 738                          *  clear the associated bits in the async event
 739                          *  config so that we do not receive repeated
 740                          *  notifications for the same event.
 741                          */
 742                         aer->ctrlr->async_event_config &=
 743                             ~health_info->critical_warning;
 744                         nvme_ctrlr_cmd_set_async_event_config(aer->ctrlr,
 745                             aer->ctrlr->async_event_config, NULL, NULL);
 746                 } else if (aer->log_page_id == NVME_LOG_CHANGED_NAMESPACE &&
 747                     !nvme_use_nvd) {
 748                         nsl = (struct nvme_ns_list *)aer->log_page_buffer;
 749                         for (i = 0; i < nitems(nsl->ns) && nsl->ns[i] != 0; i++) {
 750                                 if (nsl->ns[i] > NVME_MAX_NAMESPACES)
 751                                         break;
 752                                 nvme_notify_ns(aer->ctrlr, nsl->ns[i]);
 753                         }
 754                 }
 755
 756                 /*
 757                  * Pass the cpl data from the original async event completion,
 758                  *  not the log page fetch.
 759                  */
 760                 nvme_notify_async_consumers(aer->ctrlr, &aer->cpl,
 761                     aer->log_page_id, aer->log_page_buffer, aer->log_page_size);
 762         }
 763
 764         /*
 765          * Repost another asynchronous event request to replace the one
 766          *  that just completed.
 767          */
 768         nvme_ctrlr_construct_and_submit_aer(aer->ctrlr, aer);
 769 }
 770
 771 static void
 772 nvme_ctrlr_async_event_cb(void *arg, const struct nvme_completion *cpl)
 773 {
 774         struct nvme_async_event_request *aer = arg;
 775
 776         if (nvme_completion_is_error(cpl)) {
 777                 /*
 778                  *  Do not retry failed async event requests.  This avoids
 779                  *  infinite loops where a new async event request is submitted
 780                  *  to replace the one just failed, only to fail again and
 781                  *  perpetuate the loop.
 782                  */
 783                 return;
 784         }
 785
 786         /* Associated log page is in bits 23:16 of completion entry dw0. */
 787         aer->log_page_id = (cpl->cdw0 & 0xFF0000) >> 16;
 788
 789         nvme_printf(aer->ctrlr, "async event occurred (type 0x%x, info 0x%02x,"
 790             " page 0x%02x)\n", (cpl->cdw0 & 0x07), (cpl->cdw0 & 0xFF00) >> 8,
 791             aer->log_page_id);
 792
 793         if (is_log_page_id_valid(aer->log_page_id)) {
 794                 aer->log_page_size = nvme_ctrlr_get_log_page_size(aer->ctrlr,
 795                     aer->log_page_id);
 796                 memcpy(&aer->cpl, cpl, sizeof(*cpl));
 797                 nvme_ctrlr_cmd_get_log_page(aer->ctrlr, aer->log_page_id,
 798                     NVME_GLOBAL_NAMESPACE_TAG, aer->log_page_buffer,
 799                     aer->log_page_size, nvme_ctrlr_async_event_log_page_cb,
 800                     aer);
 801                 /* Wait to notify consumers until after log page is fetched. */
 802         } else {
 803                 nvme_notify_async_consumers(aer->ctrlr, cpl, aer->log_page_id,
 804                     NULL, 0);
 805
 806                 /*
 807                  * Repost another asynchronous event request to replace the one
 808                  *  that just completed.
 809                  */
 810                 nvme_ctrlr_construct_and_submit_aer(aer->ctrlr, aer);
 811         }
 812 }
 813
 814 static void
 815 nvme_ctrlr_construct_and_submit_aer(struct nvme_controller *ctrlr,
 816     struct nvme_async_event_request *aer)
 817 {
 818         struct nvme_request *req;
 819
 820         aer->ctrlr = ctrlr;
 821         req = nvme_allocate_request_null(nvme_ctrlr_async_event_cb, aer);
 822         aer->req = req;
 823
 824         /*
 825          * Disable timeout here, since asynchronous event requests should by
 826          *  nature never be timed out.
 827          */
 828         req->timeout = false;
 829         req->cmd.opc = NVME_OPC_ASYNC_EVENT_REQUEST;
 830         nvme_ctrlr_submit_admin_request(ctrlr, req);
 831 }
 832
 833 static void
 834 nvme_ctrlr_configure_aer(struct nvme_controller *ctrlr)
 835 {
 836         struct nvme_completion_poll_status      status;
 837         struct nvme_async_event_request         *aer;
 838         uint32_t                                i;
 839
 840         ctrlr->async_event_config = NVME_CRIT_WARN_ST_AVAILABLE_SPARE |
 841             NVME_CRIT_WARN_ST_DEVICE_RELIABILITY |
 842             NVME_CRIT_WARN_ST_READ_ONLY |
 843             NVME_CRIT_WARN_ST_VOLATILE_MEMORY_BACKUP;
 844         if (ctrlr->cdata.ver >= NVME_REV(1, 2))
 845                 ctrlr->async_event_config |= NVME_ASYNC_EVENT_NS_ATTRIBUTE |
 846                     NVME_ASYNC_EVENT_FW_ACTIVATE;
 847
 848         status.done = 0;
 849         nvme_ctrlr_cmd_get_feature(ctrlr, NVME_FEAT_TEMPERATURE_THRESHOLD,
 850             0, NULL, 0, nvme_completion_poll_cb, &status);
 851         nvme_completion_poll(&status);
 852         if (nvme_completion_is_error(&status.cpl) ||
 853             (status.cpl.cdw0 & 0xFFFF) == 0xFFFF ||
 854             (status.cpl.cdw0 & 0xFFFF) == 0x0000) {
 855                 nvme_printf(ctrlr, "temperature threshold not supported\n");
 856         } else
 857                 ctrlr->async_event_config |= NVME_CRIT_WARN_ST_TEMPERATURE;
 858
 859         nvme_ctrlr_cmd_set_async_event_config(ctrlr,
 860             ctrlr->async_event_config, NULL, NULL);
 861
 862         /* aerl is a zero-based value, so we need to add 1 here. */
 863         ctrlr->num_aers = min(NVME_MAX_ASYNC_EVENTS, (ctrlr->cdata.aerl+1));
 864
 865         for (i = 0; i < ctrlr->num_aers; i++) {
 866                 aer = &ctrlr->aer[i];
 867                 nvme_ctrlr_construct_and_submit_aer(ctrlr, aer);
 868         }
 869 }
 870
 871 static void
 872 nvme_ctrlr_configure_int_coalescing(struct nvme_controller *ctrlr)
 873 {
 874
 875         ctrlr->int_coal_time = 0;
 876         TUNABLE_INT_FETCH("hw.nvme.int_coal_time",
 877             &ctrlr->int_coal_time);
 878
 879         ctrlr->int_coal_threshold = 0;
 880         TUNABLE_INT_FETCH("hw.nvme.int_coal_threshold",
 881             &ctrlr->int_coal_threshold);
 882
 883         nvme_ctrlr_cmd_set_interrupt_coalescing(ctrlr, ctrlr->int_coal_time,
 884             ctrlr->int_coal_threshold, NULL, NULL);
 885 }
 886
 887 static void
 888 nvme_ctrlr_hmb_free(struct nvme_controller *ctrlr)
 889 {
 890         struct nvme_hmb_chunk *hmbc;
 891         int i;
 892
 893         if (ctrlr->hmb_desc_paddr) {
 894                 bus_dmamap_unload(ctrlr->hmb_desc_tag, ctrlr->hmb_desc_map);
 895                 bus_dmamem_free(ctrlr->hmb_desc_tag, ctrlr->hmb_desc_vaddr,
 896                     ctrlr->hmb_desc_map);
 897                 ctrlr->hmb_desc_paddr = 0;
 898         }
 899         if (ctrlr->hmb_desc_tag) {
 900                 bus_dma_tag_destroy(ctrlr->hmb_desc_tag);
 901                 ctrlr->hmb_desc_tag = NULL;
 902         }
 903         for (i = 0; i < ctrlr->hmb_nchunks; i++) {
 904                 hmbc = &ctrlr->hmb_chunks[i];
 905                 bus_dmamap_unload(ctrlr->hmb_tag, hmbc->hmbc_map);
 906                 bus_dmamem_free(ctrlr->hmb_tag, hmbc->hmbc_vaddr,
 907                     hmbc->hmbc_map);
 908         }
 909         ctrlr->hmb_nchunks = 0;
 910         if (ctrlr->hmb_tag) {
 911                 bus_dma_tag_destroy(ctrlr->hmb_tag);
 912                 ctrlr->hmb_tag = NULL;
 913         }
 914         if (ctrlr->hmb_chunks) {
 915                 free(ctrlr->hmb_chunks, M_NVME);
 916                 ctrlr->hmb_chunks = NULL;
 917         }
 918 }
 919
 920 static void
 921 nvme_ctrlr_hmb_alloc(struct nvme_controller *ctrlr)
 922 {
 923         struct nvme_hmb_chunk *hmbc;
 924         size_t pref, min, minc, size;
 925         int err, i;
 926         uint64_t max;
 927
 928         /* Limit HMB to 5% of RAM size per device by default. */
 929         max = (uint64_t)physmem * PAGE_SIZE / 20;
 930         TUNABLE_UINT64_FETCH("hw.nvme.hmb_max", &max);
 931
 932         min = (long long unsigned)ctrlr->cdata.hmmin * 4096;
 933         if (max == 0 || max < min)
 934                 return;
 935         pref = MIN((long long unsigned)ctrlr->cdata.hmpre * 4096, max);
 936         minc = MAX(ctrlr->cdata.hmminds * 4096, PAGE_SIZE);
 937         if (min > 0 && ctrlr->cdata.hmmaxd > 0)
 938                 minc = MAX(minc, min / ctrlr->cdata.hmmaxd);
 939         ctrlr->hmb_chunk = pref;
 940
 941 again:
 942         ctrlr->hmb_chunk = roundup2(ctrlr->hmb_chunk, PAGE_SIZE);
 943         ctrlr->hmb_nchunks = howmany(pref, ctrlr->hmb_chunk);
 944         if (ctrlr->cdata.hmmaxd > 0 && ctrlr->hmb_nchunks > ctrlr->cdata.hmmaxd)
 945                 ctrlr->hmb_nchunks = ctrlr->cdata.hmmaxd;
 946         ctrlr->hmb_chunks = malloc(sizeof(struct nvme_hmb_chunk) *
 947             ctrlr->hmb_nchunks, M_NVME, M_WAITOK);
 948         err = bus_dma_tag_create(bus_get_dma_tag(ctrlr->dev),
 949             PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
 950             ctrlr->hmb_chunk, 1, ctrlr->hmb_chunk, 0, NULL, NULL, &ctrlr->hmb_tag);
 951         if (err != 0) {
 952                 nvme_printf(ctrlr, "HMB tag create failed %d\n", err);
 953                 nvme_ctrlr_hmb_free(ctrlr);
 954                 return;
 955         }
 956
 957         for (i = 0; i < ctrlr->hmb_nchunks; i++) {
 958                 hmbc = &ctrlr->hmb_chunks[i];
 959                 if (bus_dmamem_alloc(ctrlr->hmb_tag,
 960                     (void **)&hmbc->hmbc_vaddr, BUS_DMA_NOWAIT,
 961                     &hmbc->hmbc_map)) {
 962                         nvme_printf(ctrlr, "failed to alloc HMB\n");
 963                         break;
 964                 }
 965                 if (bus_dmamap_load(ctrlr->hmb_tag, hmbc->hmbc_map,
 966                     hmbc->hmbc_vaddr, ctrlr->hmb_chunk, nvme_single_map,
 967                     &hmbc->hmbc_paddr, BUS_DMA_NOWAIT) != 0) {
 968                         bus_dmamem_free(ctrlr->hmb_tag, hmbc->hmbc_vaddr,
 969                             hmbc->hmbc_map);
 970                         nvme_printf(ctrlr, "failed to load HMB\n");
 971                         break;
 972                 }
 973                 bus_dmamap_sync(ctrlr->hmb_tag, hmbc->hmbc_map,
 974                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 975         }
 976
 977         if (i < ctrlr->hmb_nchunks && i * ctrlr->hmb_chunk < min &&
 978             ctrlr->hmb_chunk / 2 >= minc) {
 979                 ctrlr->hmb_nchunks = i;
 980                 nvme_ctrlr_hmb_free(ctrlr);
 981                 ctrlr->hmb_chunk /= 2;
 982                 goto again;
 983         }
 984         ctrlr->hmb_nchunks = i;
 985         if (ctrlr->hmb_nchunks * ctrlr->hmb_chunk < min) {
 986                 nvme_ctrlr_hmb_free(ctrlr);
 987                 return;
 988         }
 989
 990         size = sizeof(struct nvme_hmb_desc) * ctrlr->hmb_nchunks;
 991         err = bus_dma_tag_create(bus_get_dma_tag(ctrlr->dev),
 992             16, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
 993             size, 1, size, 0, NULL, NULL, &ctrlr->hmb_desc_tag);
 994         if (err != 0) {
 995                 nvme_printf(ctrlr, "HMB desc tag create failed %d\n", err);
 996                 nvme_ctrlr_hmb_free(ctrlr);
 997                 return;
 998         }
 999         if (bus_dmamem_alloc(ctrlr->hmb_desc_tag,
1000             (void **)&ctrlr->hmb_desc_vaddr, BUS_DMA_WAITOK,
1001             &ctrlr->hmb_desc_map)) {
1002                 nvme_printf(ctrlr, "failed to alloc HMB desc\n");
1003                 nvme_ctrlr_hmb_free(ctrlr);
1004                 return;
1005         }
1006         if (bus_dmamap_load(ctrlr->hmb_desc_tag, ctrlr->hmb_desc_map,
1007             ctrlr->hmb_desc_vaddr, size, nvme_single_map,
1008             &ctrlr->hmb_desc_paddr, BUS_DMA_NOWAIT) != 0) {
1009                 bus_dmamem_free(ctrlr->hmb_desc_tag, ctrlr->hmb_desc_vaddr,
1010                     ctrlr->hmb_desc_map);
1011                 nvme_printf(ctrlr, "failed to load HMB desc\n");
1012                 nvme_ctrlr_hmb_free(ctrlr);
1013                 return;
1014         }
1015
1016         for (i = 0; i < ctrlr->hmb_nchunks; i++) {
1017                 ctrlr->hmb_desc_vaddr[i].addr =
1018                     htole64(ctrlr->hmb_chunks[i].hmbc_paddr);
1019                 ctrlr->hmb_desc_vaddr[i].size = htole32(ctrlr->hmb_chunk / 4096);
1020         }
1021         bus_dmamap_sync(ctrlr->hmb_desc_tag, ctrlr->hmb_desc_map,
1022             BUS_DMASYNC_PREWRITE);
1023
1024         nvme_printf(ctrlr, "Allocated %lluMB host memory buffer\n",
1025             (long long unsigned)ctrlr->hmb_nchunks * ctrlr->hmb_chunk
1026             / 1024 / 1024);
1027 }
1028
1029 static void
1030 nvme_ctrlr_hmb_enable(struct nvme_controller *ctrlr, bool enable, bool memret)
1031 {
1032         struct nvme_completion_poll_status      status;
1033         uint32_t cdw11;
1034
1035         cdw11 = 0;
1036         if (enable)
1037                 cdw11 |= 1;
1038         if (memret)
1039                 cdw11 |= 2;
1040         status.done = 0;
1041         nvme_ctrlr_cmd_set_feature(ctrlr, NVME_FEAT_HOST_MEMORY_BUFFER, cdw11,
1042             ctrlr->hmb_nchunks * ctrlr->hmb_chunk / 4096, ctrlr->hmb_desc_paddr,
1043             ctrlr->hmb_desc_paddr >> 32, ctrlr->hmb_nchunks, NULL, 0,
1044             nvme_completion_poll_cb, &status);
1045         nvme_completion_poll(&status);
1046         if (nvme_completion_is_error(&status.cpl))
1047                 nvme_printf(ctrlr, "nvme_ctrlr_hmb_enable failed!\n");
1048 }
1049
1050 static void
1051 nvme_ctrlr_start(void *ctrlr_arg, bool resetting)
1052 {
1053         struct nvme_controller *ctrlr = ctrlr_arg;
1054         uint32_t old_num_io_queues;
1055         int i;
1056
1057         TSENTER();
1058
1059         /*
1060          * Only reset adminq here when we are restarting the
1061          *  controller after a reset.  During initialization,
1062          *  we have already submitted admin commands to get
1063          *  the number of I/O queues supported, so cannot reset
1064          *  the adminq again here.
1065          */
1066         if (resetting) {
1067                 nvme_qpair_reset(&ctrlr->adminq);
1068                 nvme_admin_qpair_enable(&ctrlr->adminq);
1069         }
1070
1071         if (ctrlr->ioq != NULL) {
1072                 for (i = 0; i < ctrlr->num_io_queues; i++)
1073                         nvme_qpair_reset(&ctrlr->ioq[i]);
1074         }
1075
1076         /*
1077          * If it was a reset on initialization command timeout, just
1078          * return here, letting initialization code fail gracefully.
1079          */
1080         if (resetting && !ctrlr->is_initialized)
1081                 return;
1082
1083         if (resetting && nvme_ctrlr_identify(ctrlr) != 0) {
1084                 nvme_ctrlr_fail(ctrlr);
1085                 return;
1086         }
1087
1088         /*
1089          * The number of qpairs are determined during controller initialization,
1090          *  including using NVMe SET_FEATURES/NUMBER_OF_QUEUES to determine the
1091          *  HW limit.  We call SET_FEATURES again here so that it gets called
1092          *  after any reset for controllers that depend on the driver to
1093          *  explicit specify how many queues it will use.  This value should
1094          *  never change between resets, so panic if somehow that does happen.
1095          */
1096         if (resetting) {
1097                 old_num_io_queues = ctrlr->num_io_queues;
1098                 if (nvme_ctrlr_set_num_qpairs(ctrlr) != 0) {
1099                         nvme_ctrlr_fail(ctrlr);
1100                         return;
1101                 }
1102
1103                 if (old_num_io_queues != ctrlr->num_io_queues) {
1104                         panic("num_io_queues changed from %u to %u",
1105                               old_num_io_queues, ctrlr->num_io_queues);
1106                 }
1107         }
1108
1109         if (ctrlr->cdata.hmpre > 0 && ctrlr->hmb_nchunks == 0) {
1110                 nvme_ctrlr_hmb_alloc(ctrlr);
1111                 if (ctrlr->hmb_nchunks > 0)
1112                         nvme_ctrlr_hmb_enable(ctrlr, true, false);
1113         } else if (ctrlr->hmb_nchunks > 0)
1114                 nvme_ctrlr_hmb_enable(ctrlr, true, true);
1115
1116         if (nvme_ctrlr_create_qpairs(ctrlr) != 0) {
1117                 nvme_ctrlr_fail(ctrlr);
1118                 return;
1119         }
1120
1121         if (nvme_ctrlr_construct_namespaces(ctrlr) != 0) {
1122                 nvme_ctrlr_fail(ctrlr);
1123                 return;
1124         }
1125
1126         nvme_ctrlr_configure_aer(ctrlr);
1127         nvme_ctrlr_configure_int_coalescing(ctrlr);
1128
1129         for (i = 0; i < ctrlr->num_io_queues; i++)
1130                 nvme_io_qpair_enable(&ctrlr->ioq[i]);
1131         TSEXIT();
1132 }
1133
1134 void
1135 nvme_ctrlr_start_config_hook(void *arg)
1136 {
1137         struct nvme_controller *ctrlr = arg;
1138
1139         TSENTER();
1140
1141         /*
1142          * Reset controller twice to ensure we do a transition from cc.en==1 to
1143          * cc.en==0.  This is because we don't really know what status the
1144          * controller was left in when boot handed off to OS.  Linux doesn't do
1145          * this, however. If we adopt that policy, see also nvme_ctrlr_resume().
1146          */
1147         if (nvme_ctrlr_hw_reset(ctrlr) != 0) {
1148 fail:
1149                 nvme_ctrlr_fail(ctrlr);
1150                 config_intrhook_disestablish(&ctrlr->config_hook);
1151                 return;
1152         }
1153
1154         if (nvme_ctrlr_hw_reset(ctrlr) != 0)
1155                 goto fail;
1156
1157         nvme_qpair_reset(&ctrlr->adminq);
1158         nvme_admin_qpair_enable(&ctrlr->adminq);
1159
1160         if (nvme_ctrlr_identify(ctrlr) == 0 &&
1161             nvme_ctrlr_set_num_qpairs(ctrlr) == 0 &&
1162             nvme_ctrlr_construct_io_qpairs(ctrlr) == 0)
1163                 nvme_ctrlr_start(ctrlr, false);
1164         else
1165                 goto fail;
1166
1167         nvme_sysctl_initialize_ctrlr(ctrlr);
1168         config_intrhook_disestablish(&ctrlr->config_hook);
1169
1170         ctrlr->is_initialized = 1;
1171         nvme_notify_new_controller(ctrlr);
1172         TSEXIT();
1173 }
1174
1175 static void
1176 nvme_ctrlr_reset_task(void *arg, int pending)
1177 {
1178         struct nvme_controller  *ctrlr = arg;
1179         int                     status;
1180
1181         nvme_ctrlr_devctl_log(ctrlr, "RESET", "resetting controller");
1182         status = nvme_ctrlr_hw_reset(ctrlr);
1183         /*
1184          * Use pause instead of DELAY, so that we yield to any nvme interrupt
1185          *  handlers on this CPU that were blocked on a qpair lock. We want
1186          *  all nvme interrupts completed before proceeding with restarting the
1187          *  controller.
1188          *
1189          * XXX - any way to guarantee the interrupt handlers have quiesced?
1190          */
1191         pause("nvmereset", hz / 10);
1192         if (status == 0)
1193                 nvme_ctrlr_start(ctrlr, true);
1194         else
1195                 nvme_ctrlr_fail(ctrlr);
1196
1197         atomic_cmpset_32(&ctrlr->is_resetting, 1, 0);
1198 }
1199
1200 /*
1201  * Poll all the queues enabled on the device for completion.
1202  */
1203 void
1204 nvme_ctrlr_poll(struct nvme_controller *ctrlr)
1205 {
1206         int i;
1207
1208         nvme_qpair_process_completions(&ctrlr->adminq);
1209
1210         for (i = 0; i < ctrlr->num_io_queues; i++)
1211                 if (ctrlr->ioq && ctrlr->ioq[i].cpl)
1212                         nvme_qpair_process_completions(&ctrlr->ioq[i]);
1213 }
1214
1215 /*
1216  * Poll the single-vector interrupt case: num_io_queues will be 1 and
1217  * there's only a single vector. While we're polling, we mask further
1218  * interrupts in the controller.
1219  */
1220 void
1221 nvme_ctrlr_shared_handler(void *arg)
1222 {
1223         struct nvme_controller *ctrlr = arg;
1224
1225         nvme_mmio_write_4(ctrlr, intms, 1);
1226         nvme_ctrlr_poll(ctrlr);
1227         nvme_mmio_write_4(ctrlr, intmc, 1);
1228 }
1229
1230 static void
1231 nvme_pt_done(void *arg, const struct nvme_completion *cpl)
1232 {
1233         struct nvme_pt_command *pt = arg;
1234         struct mtx *mtx = pt->driver_lock;
1235         uint16_t status;
1236
1237         bzero(&pt->cpl, sizeof(pt->cpl));
1238         pt->cpl.cdw0 = cpl->cdw0;
1239
1240         status = cpl->status;
1241         status &= ~NVME_STATUS_P_MASK;
1242         pt->cpl.status = status;
1243
1244         mtx_lock(mtx);
1245         pt->driver_lock = NULL;
1246         wakeup(pt);
1247         mtx_unlock(mtx);
1248 }
1249
1250 int
1251 nvme_ctrlr_passthrough_cmd(struct nvme_controller *ctrlr,
1252     struct nvme_pt_command *pt, uint32_t nsid, int is_user_buffer,
1253     int is_admin_cmd)
1254 {
1255         struct nvme_request     *req;
1256         struct mtx              *mtx;
1257         struct buf              *buf = NULL;
1258         int                     ret = 0;
1259
1260         if (pt->len > 0) {
1261                 if (pt->len > ctrlr->max_xfer_size) {
1262                         nvme_printf(ctrlr, "pt->len (%d) "
1263                             "exceeds max_xfer_size (%d)\n", pt->len,
1264                             ctrlr->max_xfer_size);
1265                         return EIO;
1266                 }
1267                 if (is_user_buffer) {
1268                         /*
1269                          * Ensure the user buffer is wired for the duration of
1270                          *  this pass-through command.
1271                          */
1272                         PHOLD(curproc);
1273                         buf = uma_zalloc(pbuf_zone, M_WAITOK);
1274                         buf->b_iocmd = pt->is_read ? BIO_READ : BIO_WRITE;
1275                         if (vmapbuf(buf, pt->buf, pt->len, 1) < 0) {
1276                                 ret = EFAULT;
1277                                 goto err;
1278                         }
1279                         req = nvme_allocate_request_vaddr(buf->b_data, pt->len,
1280                             nvme_pt_done, pt);
1281                 } else
1282                         req = nvme_allocate_request_vaddr(pt->buf, pt->len,
1283                             nvme_pt_done, pt);
1284         } else
1285                 req = nvme_allocate_request_null(nvme_pt_done, pt);
1286
1287         /* Assume user space already converted to little-endian */
1288         req->cmd.opc = pt->cmd.opc;
1289         req->cmd.fuse = pt->cmd.fuse;
1290         req->cmd.rsvd2 = pt->cmd.rsvd2;
1291         req->cmd.rsvd3 = pt->cmd.rsvd3;
1292         req->cmd.cdw10 = pt->cmd.cdw10;
1293         req->cmd.cdw11 = pt->cmd.cdw11;
1294         req->cmd.cdw12 = pt->cmd.cdw12;
1295         req->cmd.cdw13 = pt->cmd.cdw13;
1296         req->cmd.cdw14 = pt->cmd.cdw14;
1297         req->cmd.cdw15 = pt->cmd.cdw15;
1298
1299         req->cmd.nsid = htole32(nsid);
1300
1301         mtx = mtx_pool_find(mtxpool_sleep, pt);
1302         pt->driver_lock = mtx;
1303
1304         if (is_admin_cmd)
1305                 nvme_ctrlr_submit_admin_request(ctrlr, req);
1306         else
1307                 nvme_ctrlr_submit_io_request(ctrlr, req);
1308
1309         mtx_lock(mtx);
1310         while (pt->driver_lock != NULL)
1311                 mtx_sleep(pt, mtx, PRIBIO, "nvme_pt", 0);
1312         mtx_unlock(mtx);
1313
1314 err:
1315         if (buf != NULL) {
1316                 uma_zfree(pbuf_zone, buf);
1317                 PRELE(curproc);
1318         }
1319
1320         return (ret);
1321 }
1322
1323 static int
1324 nvme_ctrlr_ioctl(struct cdev *cdev, u_long cmd, caddr_t arg, int flag,
1325     struct thread *td)
1326 {
1327         struct nvme_controller                  *ctrlr;
1328         struct nvme_pt_command                  *pt;
1329
1330         ctrlr = cdev->si_drv1;
1331
1332         switch (cmd) {
1333         case NVME_RESET_CONTROLLER:
1334                 nvme_ctrlr_reset(ctrlr);
1335                 break;
1336         case NVME_PASSTHROUGH_CMD:
1337                 pt = (struct nvme_pt_command *)arg;
1338                 return (nvme_ctrlr_passthrough_cmd(ctrlr, pt, le32toh(pt->cmd.nsid),
1339                     1 /* is_user_buffer */, 1 /* is_admin_cmd */));
1340         case NVME_GET_NSID:
1341         {
1342                 struct nvme_get_nsid *gnsid = (struct nvme_get_nsid *)arg;
1343                 strncpy(gnsid->cdev, device_get_nameunit(ctrlr->dev),
1344                     sizeof(gnsid->cdev));
1345                 gnsid->cdev[sizeof(gnsid->cdev) - 1] = '\0';
1346                 gnsid->nsid = 0;
1347                 break;
1348         }
1349         case NVME_GET_MAX_XFER_SIZE:
1350                 *(uint64_t *)arg = ctrlr->max_xfer_size;
1351                 break;
1352         default:
1353                 return (ENOTTY);
1354         }
1355
1356         return (0);
1357 }
1358
1359 static struct cdevsw nvme_ctrlr_cdevsw = {
1360         .d_version =    D_VERSION,
1361         .d_flags =      0,
1362         .d_ioctl =      nvme_ctrlr_ioctl
1363 };
1364
1365 int
1366 nvme_ctrlr_construct(struct nvme_controller *ctrlr, device_t dev)
1367 {
1368         struct make_dev_args    md_args;
1369         uint32_t        cap_lo;
1370         uint32_t        cap_hi;
1371         uint32_t        to, vs, pmrcap;
1372         uint8_t         mpsmin;
1373         int             status, timeout_period;
1374
1375         ctrlr->dev = dev;
1376
1377         mtx_init(&ctrlr->lock, "nvme ctrlr lock", NULL, MTX_DEF);
1378         if (bus_get_domain(dev, &ctrlr->domain) != 0)
1379                 ctrlr->domain = 0;
1380
1381         cap_lo = nvme_mmio_read_4(ctrlr, cap_lo);
1382         if (bootverbose) {
1383                 device_printf(dev, "CapLo: 0x%08x: MQES %u%s%s%s%s, TO %u\n",
1384                     cap_lo, NVME_CAP_LO_MQES(cap_lo),
1385                     NVME_CAP_LO_CQR(cap_lo) ? ", CQR" : "",
1386                     NVME_CAP_LO_AMS(cap_lo) ? ", AMS" : "",
1387                     (NVME_CAP_LO_AMS(cap_lo) & 0x1) ? " WRRwUPC" : "",
1388                     (NVME_CAP_LO_AMS(cap_lo) & 0x2) ? " VS" : "",
1389                     NVME_CAP_LO_TO(cap_lo));
1390         }
1391         cap_hi = nvme_mmio_read_4(ctrlr, cap_hi);
1392         if (bootverbose) {
1393                 device_printf(dev, "CapHi: 0x%08x: DSTRD %u%s, CSS %x%s, "
1394                     "MPSMIN %u, MPSMAX %u%s%s\n", cap_hi,
1395                     NVME_CAP_HI_DSTRD(cap_hi),
1396                     NVME_CAP_HI_NSSRS(cap_hi) ? ", NSSRS" : "",
1397                     NVME_CAP_HI_CSS(cap_hi),
1398                     NVME_CAP_HI_BPS(cap_hi) ? ", BPS" : "",
1399                     NVME_CAP_HI_MPSMIN(cap_hi),
1400                     NVME_CAP_HI_MPSMAX(cap_hi),
1401                     NVME_CAP_HI_PMRS(cap_hi) ? ", PMRS" : "",
1402                     NVME_CAP_HI_CMBS(cap_hi) ? ", CMBS" : "");
1403         }
1404         if (bootverbose) {
1405                 vs = nvme_mmio_read_4(ctrlr, vs);
1406                 device_printf(dev, "Version: 0x%08x: %d.%d\n", vs,
1407                     NVME_MAJOR(vs), NVME_MINOR(vs));
1408         }
1409         if (bootverbose && NVME_CAP_HI_PMRS(cap_hi)) {
1410                 pmrcap = nvme_mmio_read_4(ctrlr, pmrcap);
1411                 device_printf(dev, "PMRCap: 0x%08x: BIR %u%s%s, PMRTU %u, "
1412                     "PMRWBM %x, PMRTO %u%s\n", pmrcap,
1413                     NVME_PMRCAP_BIR(pmrcap),
1414                     NVME_PMRCAP_RDS(pmrcap) ? ", RDS" : "",
1415                     NVME_PMRCAP_WDS(pmrcap) ? ", WDS" : "",
1416                     NVME_PMRCAP_PMRTU(pmrcap),
1417                     NVME_PMRCAP_PMRWBM(pmrcap),
1418                     NVME_PMRCAP_PMRTO(pmrcap),
1419                     NVME_PMRCAP_CMSS(pmrcap) ? ", CMSS" : "");
1420         }
1421
1422         ctrlr->dstrd = NVME_CAP_HI_DSTRD(cap_hi) + 2;
1423
1424         mpsmin = NVME_CAP_HI_MPSMIN(cap_hi);
1425         ctrlr->min_page_size = 1 << (12 + mpsmin);
1426
1427         /* Get ready timeout value from controller, in units of 500ms. */
1428         to = NVME_CAP_LO_TO(cap_lo) + 1;
1429         ctrlr->ready_timeout_in_ms = to * 500;
1430
1431         timeout_period = NVME_DEFAULT_TIMEOUT_PERIOD;
1432         TUNABLE_INT_FETCH("hw.nvme.timeout_period", &timeout_period);
1433         timeout_period = min(timeout_period, NVME_MAX_TIMEOUT_PERIOD);
1434         timeout_period = max(timeout_period, NVME_MIN_TIMEOUT_PERIOD);
1435         ctrlr->timeout_period = timeout_period;
1436
1437         nvme_retry_count = NVME_DEFAULT_RETRY_COUNT;
1438         TUNABLE_INT_FETCH("hw.nvme.retry_count", &nvme_retry_count);
1439
1440         ctrlr->enable_aborts = 0;
1441         TUNABLE_INT_FETCH("hw.nvme.enable_aborts", &ctrlr->enable_aborts);
1442
1443         ctrlr->max_xfer_size = NVME_MAX_XFER_SIZE;
1444         if (nvme_ctrlr_construct_admin_qpair(ctrlr) != 0)
1445                 return (ENXIO);
1446
1447         /*
1448          * Create 2 threads for the taskqueue. The reset thread will block when
1449          * it detects that the controller has failed until all I/O has been
1450          * failed up the stack. The fail_req task needs to be able to run in
1451          * this case to finish the request failure for some cases.
1452          *
1453          * We could partially solve this race by draining the failed requeust
1454          * queue before proceding to free the sim, though nothing would stop
1455          * new I/O from coming in after we do that drain, but before we reach
1456          * cam_sim_free, so this big hammer is used instead.
1457          */
1458         ctrlr->taskqueue = taskqueue_create("nvme_taskq", M_WAITOK,
1459             taskqueue_thread_enqueue, &ctrlr->taskqueue);
1460         taskqueue_start_threads(&ctrlr->taskqueue, 2, PI_DISK, "nvme taskq");
1461
1462         ctrlr->is_resetting = 0;
1463         ctrlr->is_initialized = 0;
1464         ctrlr->notification_sent = 0;
1465         TASK_INIT(&ctrlr->reset_task, 0, nvme_ctrlr_reset_task, ctrlr);
1466         TASK_INIT(&ctrlr->fail_req_task, 0, nvme_ctrlr_fail_req_task, ctrlr);
1467         STAILQ_INIT(&ctrlr->fail_req);
1468         ctrlr->is_failed = false;
1469
1470         make_dev_args_init(&md_args);
1471         md_args.mda_devsw = &nvme_ctrlr_cdevsw;
1472         md_args.mda_uid = UID_ROOT;
1473         md_args.mda_gid = GID_WHEEL;
1474         md_args.mda_mode = 0600;
1475         md_args.mda_unit = device_get_unit(dev);
1476         md_args.mda_si_drv1 = (void *)ctrlr;
1477         status = make_dev_s(&md_args, &ctrlr->cdev, "nvme%d",
1478             device_get_unit(dev));
1479         if (status != 0)
1480                 return (ENXIO);
1481
1482         return (0);
1483 }
1484
1485 void
1486 nvme_ctrlr_destruct(struct nvme_controller *ctrlr, device_t dev)
1487 {
1488         int     gone, i;
1489
1490         ctrlr->is_dying = true;
1491
1492         if (ctrlr->resource == NULL)
1493                 goto nores;
1494         if (!mtx_initialized(&ctrlr->adminq.lock))
1495                 goto noadminq;
1496
1497         /*
1498          * Check whether it is a hot unplug or a clean driver detach.
1499          * If device is not there any more, skip any shutdown commands.
1500          */
1501         gone = (nvme_mmio_read_4(ctrlr, csts) == NVME_GONE);
1502         if (gone)
1503                 nvme_ctrlr_fail(ctrlr);
1504         else
1505                 nvme_notify_fail_consumers(ctrlr);
1506
1507         for (i = 0; i < NVME_MAX_NAMESPACES; i++)
1508                 nvme_ns_destruct(&ctrlr->ns[i]);
1509
1510         if (ctrlr->cdev)
1511                 destroy_dev(ctrlr->cdev);
1512
1513         if (ctrlr->is_initialized) {
1514                 if (!gone) {
1515                         if (ctrlr->hmb_nchunks > 0)
1516                                 nvme_ctrlr_hmb_enable(ctrlr, false, false);
1517                         nvme_ctrlr_delete_qpairs(ctrlr);
1518                 }
1519                 nvme_ctrlr_hmb_free(ctrlr);
1520         }
1521         if (ctrlr->ioq != NULL) {
1522                 for (i = 0; i < ctrlr->num_io_queues; i++)
1523                         nvme_io_qpair_destroy(&ctrlr->ioq[i]);
1524                 free(ctrlr->ioq, M_NVME);
1525         }
1526         nvme_admin_qpair_destroy(&ctrlr->adminq);
1527
1528         /*
1529          *  Notify the controller of a shutdown, even though this is due to
1530          *   a driver unload, not a system shutdown (this path is not invoked
1531          *   during shutdown).  This ensures the controller receives a
1532          *   shutdown notification in case the system is shutdown before
1533          *   reloading the driver.
1534          */
1535         if (!gone)
1536                 nvme_ctrlr_shutdown(ctrlr);
1537
1538         if (!gone)
1539                 nvme_ctrlr_disable(ctrlr);
1540
1541 noadminq:
1542         if (ctrlr->taskqueue)
1543                 taskqueue_free(ctrlr->taskqueue);
1544
1545         if (ctrlr->tag)
1546                 bus_teardown_intr(ctrlr->dev, ctrlr->res, ctrlr->tag);
1547
1548         if (ctrlr->res)
1549                 bus_release_resource(ctrlr->dev, SYS_RES_IRQ,
1550                     rman_get_rid(ctrlr->res), ctrlr->res);
1551
1552         if (ctrlr->bar4_resource != NULL) {
1553                 bus_release_resource(dev, SYS_RES_MEMORY,
1554                     ctrlr->bar4_resource_id, ctrlr->bar4_resource);
1555         }
1556
1557         bus_release_resource(dev, SYS_RES_MEMORY,
1558             ctrlr->resource_id, ctrlr->resource);
1559
1560 nores:
1561         mtx_destroy(&ctrlr->lock);
1562 }
1563
1564 void
1565 nvme_ctrlr_shutdown(struct nvme_controller *ctrlr)
1566 {
1567         uint32_t        cc;
1568         uint32_t        csts;
1569         int             timeout;
1570
1571         cc = nvme_mmio_read_4(ctrlr, cc);
1572         cc &= ~(NVME_CC_REG_SHN_MASK << NVME_CC_REG_SHN_SHIFT);
1573         cc |= NVME_SHN_NORMAL << NVME_CC_REG_SHN_SHIFT;
1574         nvme_mmio_write_4(ctrlr, cc, cc);
1575
1576         timeout = ticks + (ctrlr->cdata.rtd3e == 0 ? 5 * hz :
1577             ((uint64_t)ctrlr->cdata.rtd3e * hz + 999999) / 1000000);
1578         while (1) {
1579                 csts = nvme_mmio_read_4(ctrlr, csts);
1580                 if (csts == NVME_GONE)          /* Hot unplug. */
1581                         break;
1582                 if (NVME_CSTS_GET_SHST(csts) == NVME_SHST_COMPLETE)
1583                         break;
1584                 if (timeout - ticks < 0) {
1585                         nvme_printf(ctrlr, "shutdown timeout\n");
1586                         break;
1587                 }
1588                 pause("nvmeshut", 1);
1589         }
1590 }
1591
1592 void
1593 nvme_ctrlr_submit_admin_request(struct nvme_controller *ctrlr,
1594     struct nvme_request *req)
1595 {
1596
1597         nvme_qpair_submit_request(&ctrlr->adminq, req);
1598 }
1599
1600 void
1601 nvme_ctrlr_submit_io_request(struct nvme_controller *ctrlr,
1602     struct nvme_request *req)
1603 {
1604         struct nvme_qpair       *qpair;
1605
1606         qpair = &ctrlr->ioq[QP(ctrlr, curcpu)];
1607         nvme_qpair_submit_request(qpair, req);
1608 }
1609
1610 device_t
1611 nvme_ctrlr_get_device(struct nvme_controller *ctrlr)
1612 {
1613
1614         return (ctrlr->dev);
1615 }
1616
1617 const struct nvme_controller_data *
1618 nvme_ctrlr_get_data(struct nvme_controller *ctrlr)
1619 {
1620
1621         return (&ctrlr->cdata);
1622 }
1623
1624 int
1625 nvme_ctrlr_suspend(struct nvme_controller *ctrlr)
1626 {
1627         int to = hz;
1628
1629         /*
1630          * Can't touch failed controllers, so it's already suspended.
1631          */
1632         if (ctrlr->is_failed)
1633                 return (0);
1634
1635         /*
1636          * We don't want the reset taskqueue running, since it does similar
1637          * things, so prevent it from running after we start. Wait for any reset
1638          * that may have been started to complete. The reset process we follow
1639          * will ensure that any new I/O will queue and be given to the hardware
1640          * after we resume (though there should be none).
1641          */
1642         while (atomic_cmpset_32(&ctrlr->is_resetting, 0, 1) == 0 && to-- > 0)
1643                 pause("nvmesusp", 1);
1644         if (to <= 0) {
1645                 nvme_printf(ctrlr,
1646                     "Competing reset task didn't finish. Try again later.\n");
1647                 return (EWOULDBLOCK);
1648         }
1649
1650         if (ctrlr->hmb_nchunks > 0)
1651                 nvme_ctrlr_hmb_enable(ctrlr, false, false);
1652
1653         /*
1654          * Per Section 7.6.2 of NVMe spec 1.4, to properly suspend, we need to
1655          * delete the hardware I/O queues, and then shutdown. This properly
1656          * flushes any metadata the drive may have stored so it can survive
1657          * having its power removed and prevents the unsafe shutdown count from
1658          * incriminating. Once we delete the qpairs, we have to disable them
1659          * before shutting down. The delay is out of paranoia in
1660          * nvme_ctrlr_hw_reset, and is repeated here (though we should have no
1661          * pending I/O that the delay copes with).
1662          */
1663         nvme_ctrlr_delete_qpairs(ctrlr);
1664         nvme_ctrlr_disable_qpairs(ctrlr);
1665         pause("nvmesusp", hz / 10);
1666         nvme_ctrlr_shutdown(ctrlr);
1667
1668         return (0);
1669 }
1670
1671 int
1672 nvme_ctrlr_resume(struct nvme_controller *ctrlr)
1673 {
1674
1675         /*
1676          * Can't touch failed controllers, so nothing to do to resume.
1677          */
1678         if (ctrlr->is_failed)
1679                 return (0);
1680
1681         /*
1682          * Have to reset the hardware twice, just like we do on attach. See
1683          * nmve_attach() for why.
1684          */
1685         if (nvme_ctrlr_hw_reset(ctrlr) != 0)
1686                 goto fail;
1687         if (nvme_ctrlr_hw_reset(ctrlr) != 0)
1688                 goto fail;
1689
1690         /*
1691          * Now that we've reset the hardware, we can restart the controller. Any
1692          * I/O that was pending is requeued. Any admin commands are aborted with
1693          * an error. Once we've restarted, take the controller out of reset.
1694          */
1695         nvme_ctrlr_start(ctrlr, true);
1696         (void)atomic_cmpset_32(&ctrlr->is_resetting, 1, 0);
1697
1698         return (0);
1699 fail:
1700         /*
1701          * Since we can't bring the controller out of reset, announce and fail
1702          * the controller. However, we have to return success for the resume
1703          * itself, due to questionable APIs.
1704          */
1705         nvme_printf(ctrlr, "Failed to reset on resume, failing.\n");
1706         nvme_ctrlr_fail(ctrlr);
1707         (void)atomic_cmpset_32(&ctrlr->is_resetting, 1, 0);
1708         return (0);
1709 }