2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (C) 2012-2016 Intel Corporation
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
33 #include <sys/param.h>
34 #include <sys/systm.h>
38 #include <sys/ioccom.h>
43 #include <sys/endian.h>
44 #include <machine/stdarg.h>
47 #include "nvme_private.h"
49 #define B4_CHK_RDY_DELAY_MS 2300 /* work around controller bug */
51 static void nvme_ctrlr_construct_and_submit_aer(struct nvme_controller *ctrlr,
52 struct nvme_async_event_request *aer);
55 nvme_ctrlr_barrier(struct nvme_controller *ctrlr, int flags)
57 bus_barrier(ctrlr->resource, 0, rman_get_size(ctrlr->resource), flags);
61 nvme_ctrlr_devctl_log(struct nvme_controller *ctrlr, const char *type, const char *msg, ...)
67 if (sbuf_new(&sb, NULL, 0, SBUF_AUTOEXTEND | SBUF_NOWAIT) == NULL)
69 sbuf_printf(&sb, "%s: ", device_get_nameunit(ctrlr->dev));
71 sbuf_vprintf(&sb, msg, ap);
73 error = sbuf_finish(&sb);
75 printf("%s\n", sbuf_data(&sb));
78 sbuf_printf(&sb, "name=\"%s\" reason=\"", device_get_nameunit(ctrlr->dev));
80 sbuf_vprintf(&sb, msg, ap);
82 sbuf_printf(&sb, "\"");
83 error = sbuf_finish(&sb);
85 devctl_notify("nvme", "controller", type, sbuf_data(&sb));
90 nvme_ctrlr_construct_admin_qpair(struct nvme_controller *ctrlr)
92 struct nvme_qpair *qpair;
96 qpair = &ctrlr->adminq;
98 qpair->cpu = CPU_FFS(&cpuset_domain[ctrlr->domain]) - 1;
99 qpair->domain = ctrlr->domain;
101 num_entries = NVME_ADMIN_ENTRIES;
102 TUNABLE_INT_FETCH("hw.nvme.admin_entries", &num_entries);
104 * If admin_entries was overridden to an invalid value, revert it
105 * back to our default value.
107 if (num_entries < NVME_MIN_ADMIN_ENTRIES ||
108 num_entries > NVME_MAX_ADMIN_ENTRIES) {
109 nvme_printf(ctrlr, "invalid hw.nvme.admin_entries=%d "
110 "specified\n", num_entries);
111 num_entries = NVME_ADMIN_ENTRIES;
115 * The admin queue's max xfer size is treated differently than the
116 * max I/O xfer size. 16KB is sufficient here - maybe even less?
118 error = nvme_qpair_construct(qpair, num_entries, NVME_ADMIN_TRACKERS,
123 #define QP(ctrlr, c) ((c) * (ctrlr)->num_io_queues / mp_ncpus)
126 nvme_ctrlr_construct_io_qpairs(struct nvme_controller *ctrlr)
128 struct nvme_qpair *qpair;
132 int num_entries, num_trackers, max_entries;
135 * NVMe spec sets a hard limit of 64K max entries, but devices may
136 * specify a smaller limit, so we need to check the MQES field in the
137 * capabilities register. We have to cap the number of entries to the
138 * current stride allows for in BAR 0/1, otherwise the remainder entries
139 * are inaccessible. MQES should reflect this, and this is just a
143 (rman_get_size(ctrlr->resource) - nvme_mmio_offsetof(doorbell[0])) /
144 (1 << (ctrlr->dstrd + 1));
145 num_entries = NVME_IO_ENTRIES;
146 TUNABLE_INT_FETCH("hw.nvme.io_entries", &num_entries);
147 cap_lo = nvme_mmio_read_4(ctrlr, cap_lo);
148 mqes = NVME_CAP_LO_MQES(cap_lo);
149 num_entries = min(num_entries, mqes + 1);
150 num_entries = min(num_entries, max_entries);
152 num_trackers = NVME_IO_TRACKERS;
153 TUNABLE_INT_FETCH("hw.nvme.io_trackers", &num_trackers);
155 num_trackers = max(num_trackers, NVME_MIN_IO_TRACKERS);
156 num_trackers = min(num_trackers, NVME_MAX_IO_TRACKERS);
158 * No need to have more trackers than entries in the submit queue. Note
159 * also that for a queue size of N, we can only have (N-1) commands
160 * outstanding, hence the "-1" here.
162 num_trackers = min(num_trackers, (num_entries-1));
165 * Our best estimate for the maximum number of I/Os that we should
166 * normally have in flight at one time. This should be viewed as a hint,
167 * not a hard limit and will need to be revisited when the upper layers
168 * of the storage system grows multi-queue support.
170 ctrlr->max_hw_pend_io = num_trackers * ctrlr->num_io_queues * 3 / 4;
172 ctrlr->ioq = malloc(ctrlr->num_io_queues * sizeof(struct nvme_qpair),
173 M_NVME, M_ZERO | M_WAITOK);
175 for (i = c = n = 0; i < ctrlr->num_io_queues; i++, c += n) {
176 qpair = &ctrlr->ioq[i];
179 * Admin queue has ID=0. IO queues start at ID=1 -
180 * hence the 'i+1' here.
183 if (ctrlr->num_io_queues > 1) {
184 /* Find number of CPUs served by this queue. */
185 for (n = 1; QP(ctrlr, c + n) == i; n++)
187 /* Shuffle multiple NVMe devices between CPUs. */
188 qpair->cpu = c + (device_get_unit(ctrlr->dev)+n/2) % n;
189 qpair->domain = pcpu_find(qpair->cpu)->pc_domain;
191 qpair->cpu = CPU_FFS(&cpuset_domain[ctrlr->domain]) - 1;
192 qpair->domain = ctrlr->domain;
196 * For I/O queues, use the controller-wide max_xfer_size
197 * calculated in nvme_attach().
199 error = nvme_qpair_construct(qpair, num_entries, num_trackers,
205 * Do not bother binding interrupts if we only have one I/O
206 * interrupt thread for this controller.
208 if (ctrlr->num_io_queues > 1)
209 bus_bind_intr(ctrlr->dev, qpair->res, qpair->cpu);
216 nvme_ctrlr_fail(struct nvme_controller *ctrlr)
221 * No need to disable queues before failing them. Failing is a superet
222 * of disabling (though pedantically we'd abort the AERs silently with
223 * a different error, though when we fail, that hardly matters).
225 ctrlr->is_failed = true;
226 nvme_qpair_fail(&ctrlr->adminq);
227 if (ctrlr->ioq != NULL) {
228 for (i = 0; i < ctrlr->num_io_queues; i++) {
229 nvme_qpair_fail(&ctrlr->ioq[i]);
232 nvme_notify_fail_consumers(ctrlr);
236 * Wait for RDY to change.
238 * Starts sleeping for 1us and geometrically increases it the longer we wait,
242 nvme_ctrlr_wait_for_ready(struct nvme_controller *ctrlr, int desired_val)
244 int timeout = ticks + MSEC_2_TICKS(ctrlr->ready_timeout_in_ms);
245 sbintime_t delta_t = SBT_1US;
249 csts = nvme_mmio_read_4(ctrlr, csts);
250 if (csts == NVME_GONE) /* Hot unplug. */
252 if (((csts >> NVME_CSTS_REG_RDY_SHIFT) & NVME_CSTS_REG_RDY_MASK)
255 if (timeout - ticks < 0) {
256 nvme_printf(ctrlr, "controller ready did not become %d "
257 "within %d ms\n", desired_val, ctrlr->ready_timeout_in_ms);
261 pause_sbt("nvmerdy", delta_t, 0, C_PREL(1));
262 delta_t = min(SBT_1MS, delta_t * 3 / 2);
269 nvme_ctrlr_disable(struct nvme_controller *ctrlr)
276 cc = nvme_mmio_read_4(ctrlr, cc);
277 csts = nvme_mmio_read_4(ctrlr, csts);
279 en = (cc >> NVME_CC_REG_EN_SHIFT) & NVME_CC_REG_EN_MASK;
280 rdy = (csts >> NVME_CSTS_REG_RDY_SHIFT) & NVME_CSTS_REG_RDY_MASK;
283 * Per 3.1.5 in NVME 1.3 spec, transitioning CC.EN from 0 to 1
284 * when CSTS.RDY is 1 or transitioning CC.EN from 1 to 0 when
285 * CSTS.RDY is 0 "has undefined results" So make sure that CSTS.RDY
286 * isn't the desired value. Short circuit if we're already disabled.
289 /* Wait for RDY == 0 or timeout & fail */
292 return (nvme_ctrlr_wait_for_ready(ctrlr, 0));
295 /* EN == 1, wait for RDY == 1 or timeout & fail */
296 err = nvme_ctrlr_wait_for_ready(ctrlr, 1);
301 cc &= ~NVME_CC_REG_EN_MASK;
302 nvme_mmio_write_4(ctrlr, cc, cc);
305 * A few drives have firmware bugs that freeze the drive if we access
306 * the mmio too soon after we disable.
308 if (ctrlr->quirks & QUIRK_DELAY_B4_CHK_RDY)
309 pause("nvmeR", MSEC_2_TICKS(B4_CHK_RDY_DELAY_MS));
310 return (nvme_ctrlr_wait_for_ready(ctrlr, 0));
314 nvme_ctrlr_enable(struct nvme_controller *ctrlr)
323 cc = nvme_mmio_read_4(ctrlr, cc);
324 csts = nvme_mmio_read_4(ctrlr, csts);
326 en = (cc >> NVME_CC_REG_EN_SHIFT) & NVME_CC_REG_EN_MASK;
327 rdy = (csts >> NVME_CSTS_REG_RDY_SHIFT) & NVME_CSTS_REG_RDY_MASK;
330 * See note in nvme_ctrlr_disable. Short circuit if we're already enabled.
335 return (nvme_ctrlr_wait_for_ready(ctrlr, 1));
338 /* EN == 0 already wait for RDY == 0 or timeout & fail */
339 err = nvme_ctrlr_wait_for_ready(ctrlr, 0);
343 nvme_mmio_write_8(ctrlr, asq, ctrlr->adminq.cmd_bus_addr);
344 nvme_mmio_write_8(ctrlr, acq, ctrlr->adminq.cpl_bus_addr);
346 /* acqs and asqs are 0-based. */
347 qsize = ctrlr->adminq.num_entries - 1;
350 aqa = (qsize & NVME_AQA_REG_ACQS_MASK) << NVME_AQA_REG_ACQS_SHIFT;
351 aqa |= (qsize & NVME_AQA_REG_ASQS_MASK) << NVME_AQA_REG_ASQS_SHIFT;
352 nvme_mmio_write_4(ctrlr, aqa, aqa);
354 /* Initialization values for CC */
356 cc |= 1 << NVME_CC_REG_EN_SHIFT;
357 cc |= 0 << NVME_CC_REG_CSS_SHIFT;
358 cc |= 0 << NVME_CC_REG_AMS_SHIFT;
359 cc |= 0 << NVME_CC_REG_SHN_SHIFT;
360 cc |= 6 << NVME_CC_REG_IOSQES_SHIFT; /* SQ entry size == 64 == 2^6 */
361 cc |= 4 << NVME_CC_REG_IOCQES_SHIFT; /* CQ entry size == 16 == 2^4 */
364 * Use the Memory Page Size selected during device initialization. Note
365 * that value stored in mps is suitable to use here without adjusting by
368 cc |= ctrlr->mps << NVME_CC_REG_MPS_SHIFT;
370 nvme_ctrlr_barrier(ctrlr, BUS_SPACE_BARRIER_WRITE);
371 nvme_mmio_write_4(ctrlr, cc, cc);
373 return (nvme_ctrlr_wait_for_ready(ctrlr, 1));
377 nvme_ctrlr_disable_qpairs(struct nvme_controller *ctrlr)
381 nvme_admin_qpair_disable(&ctrlr->adminq);
383 * I/O queues are not allocated before the initial HW
384 * reset, so do not try to disable them. Use is_initialized
385 * to determine if this is the initial HW reset.
387 if (ctrlr->is_initialized) {
388 for (i = 0; i < ctrlr->num_io_queues; i++)
389 nvme_io_qpair_disable(&ctrlr->ioq[i]);
394 nvme_ctrlr_hw_reset(struct nvme_controller *ctrlr)
400 nvme_ctrlr_disable_qpairs(ctrlr);
402 err = nvme_ctrlr_disable(ctrlr);
406 err = nvme_ctrlr_enable(ctrlr);
414 nvme_ctrlr_reset(struct nvme_controller *ctrlr)
418 cmpset = atomic_cmpset_32(&ctrlr->is_resetting, 0, 1);
420 if (cmpset == 0 || ctrlr->is_failed)
422 * Controller is already resetting or has failed. Return
423 * immediately since there is no need to kick off another
424 * reset in these cases.
428 if (!ctrlr->is_dying)
429 taskqueue_enqueue(ctrlr->taskqueue, &ctrlr->reset_task);
433 nvme_ctrlr_identify(struct nvme_controller *ctrlr)
435 struct nvme_completion_poll_status status;
438 nvme_ctrlr_cmd_identify_controller(ctrlr, &ctrlr->cdata,
439 nvme_completion_poll_cb, &status);
440 nvme_completion_poll(&status);
441 if (nvme_completion_is_error(&status.cpl)) {
442 nvme_printf(ctrlr, "nvme_identify_controller failed!\n");
446 /* Convert data to host endian */
447 nvme_controller_data_swapbytes(&ctrlr->cdata);
450 * Use MDTS to ensure our default max_xfer_size doesn't exceed what the
451 * controller supports.
453 if (ctrlr->cdata.mdts > 0)
454 ctrlr->max_xfer_size = min(ctrlr->max_xfer_size,
455 1 << (ctrlr->cdata.mdts + NVME_MPS_SHIFT +
456 NVME_CAP_HI_MPSMIN(ctrlr->cap_hi)));
462 nvme_ctrlr_set_num_qpairs(struct nvme_controller *ctrlr)
464 struct nvme_completion_poll_status status;
465 int cq_allocated, sq_allocated;
468 nvme_ctrlr_cmd_set_num_queues(ctrlr, ctrlr->num_io_queues,
469 nvme_completion_poll_cb, &status);
470 nvme_completion_poll(&status);
471 if (nvme_completion_is_error(&status.cpl)) {
472 nvme_printf(ctrlr, "nvme_ctrlr_set_num_qpairs failed!\n");
477 * Data in cdw0 is 0-based.
478 * Lower 16-bits indicate number of submission queues allocated.
479 * Upper 16-bits indicate number of completion queues allocated.
481 sq_allocated = (status.cpl.cdw0 & 0xFFFF) + 1;
482 cq_allocated = (status.cpl.cdw0 >> 16) + 1;
485 * Controller may allocate more queues than we requested,
486 * so use the minimum of the number requested and what was
487 * actually allocated.
489 ctrlr->num_io_queues = min(ctrlr->num_io_queues, sq_allocated);
490 ctrlr->num_io_queues = min(ctrlr->num_io_queues, cq_allocated);
491 if (ctrlr->num_io_queues > vm_ndomains)
492 ctrlr->num_io_queues -= ctrlr->num_io_queues % vm_ndomains;
498 nvme_ctrlr_create_qpairs(struct nvme_controller *ctrlr)
500 struct nvme_completion_poll_status status;
501 struct nvme_qpair *qpair;
504 for (i = 0; i < ctrlr->num_io_queues; i++) {
505 qpair = &ctrlr->ioq[i];
508 nvme_ctrlr_cmd_create_io_cq(ctrlr, qpair,
509 nvme_completion_poll_cb, &status);
510 nvme_completion_poll(&status);
511 if (nvme_completion_is_error(&status.cpl)) {
512 nvme_printf(ctrlr, "nvme_create_io_cq failed!\n");
517 nvme_ctrlr_cmd_create_io_sq(ctrlr, qpair,
518 nvme_completion_poll_cb, &status);
519 nvme_completion_poll(&status);
520 if (nvme_completion_is_error(&status.cpl)) {
521 nvme_printf(ctrlr, "nvme_create_io_sq failed!\n");
530 nvme_ctrlr_delete_qpairs(struct nvme_controller *ctrlr)
532 struct nvme_completion_poll_status status;
533 struct nvme_qpair *qpair;
535 for (int i = 0; i < ctrlr->num_io_queues; i++) {
536 qpair = &ctrlr->ioq[i];
539 nvme_ctrlr_cmd_delete_io_sq(ctrlr, qpair,
540 nvme_completion_poll_cb, &status);
541 nvme_completion_poll(&status);
542 if (nvme_completion_is_error(&status.cpl)) {
543 nvme_printf(ctrlr, "nvme_destroy_io_sq failed!\n");
548 nvme_ctrlr_cmd_delete_io_cq(ctrlr, qpair,
549 nvme_completion_poll_cb, &status);
550 nvme_completion_poll(&status);
551 if (nvme_completion_is_error(&status.cpl)) {
552 nvme_printf(ctrlr, "nvme_destroy_io_cq failed!\n");
561 nvme_ctrlr_construct_namespaces(struct nvme_controller *ctrlr)
563 struct nvme_namespace *ns;
566 for (i = 0; i < min(ctrlr->cdata.nn, NVME_MAX_NAMESPACES); i++) {
568 nvme_ns_construct(ns, i+1, ctrlr);
575 is_log_page_id_valid(uint8_t page_id)
580 case NVME_LOG_HEALTH_INFORMATION:
581 case NVME_LOG_FIRMWARE_SLOT:
582 case NVME_LOG_CHANGED_NAMESPACE:
583 case NVME_LOG_COMMAND_EFFECT:
584 case NVME_LOG_RES_NOTIFICATION:
585 case NVME_LOG_SANITIZE_STATUS:
593 nvme_ctrlr_get_log_page_size(struct nvme_controller *ctrlr, uint8_t page_id)
595 uint32_t log_page_size;
600 sizeof(struct nvme_error_information_entry) *
601 (ctrlr->cdata.elpe + 1), NVME_MAX_AER_LOG_SIZE);
603 case NVME_LOG_HEALTH_INFORMATION:
604 log_page_size = sizeof(struct nvme_health_information_page);
606 case NVME_LOG_FIRMWARE_SLOT:
607 log_page_size = sizeof(struct nvme_firmware_page);
609 case NVME_LOG_CHANGED_NAMESPACE:
610 log_page_size = sizeof(struct nvme_ns_list);
612 case NVME_LOG_COMMAND_EFFECT:
613 log_page_size = sizeof(struct nvme_command_effects_page);
615 case NVME_LOG_RES_NOTIFICATION:
616 log_page_size = sizeof(struct nvme_res_notification_page);
618 case NVME_LOG_SANITIZE_STATUS:
619 log_page_size = sizeof(struct nvme_sanitize_status_page);
626 return (log_page_size);
630 nvme_ctrlr_log_critical_warnings(struct nvme_controller *ctrlr,
634 if (state & NVME_CRIT_WARN_ST_AVAILABLE_SPARE)
635 nvme_ctrlr_devctl_log(ctrlr, "critical",
636 "available spare space below threshold");
638 if (state & NVME_CRIT_WARN_ST_TEMPERATURE)
639 nvme_ctrlr_devctl_log(ctrlr, "critical",
640 "temperature above threshold");
642 if (state & NVME_CRIT_WARN_ST_DEVICE_RELIABILITY)
643 nvme_ctrlr_devctl_log(ctrlr, "critical",
644 "device reliability degraded");
646 if (state & NVME_CRIT_WARN_ST_READ_ONLY)
647 nvme_ctrlr_devctl_log(ctrlr, "critical",
648 "media placed in read only mode");
650 if (state & NVME_CRIT_WARN_ST_VOLATILE_MEMORY_BACKUP)
651 nvme_ctrlr_devctl_log(ctrlr, "critical",
652 "volatile memory backup device failed");
654 if (state & NVME_CRIT_WARN_ST_RESERVED_MASK)
655 nvme_ctrlr_devctl_log(ctrlr, "critical",
656 "unknown critical warning(s): state = 0x%02x", state);
660 nvme_ctrlr_async_event_log_page_cb(void *arg, const struct nvme_completion *cpl)
662 struct nvme_async_event_request *aer = arg;
663 struct nvme_health_information_page *health_info;
664 struct nvme_ns_list *nsl;
665 struct nvme_error_information_entry *err;
669 * If the log page fetch for some reason completed with an error,
670 * don't pass log page data to the consumers. In practice, this case
671 * should never happen.
673 if (nvme_completion_is_error(cpl))
674 nvme_notify_async_consumers(aer->ctrlr, &aer->cpl,
675 aer->log_page_id, NULL, 0);
677 /* Convert data to host endian */
678 switch (aer->log_page_id) {
680 err = (struct nvme_error_information_entry *)aer->log_page_buffer;
681 for (i = 0; i < (aer->ctrlr->cdata.elpe + 1); i++)
682 nvme_error_information_entry_swapbytes(err++);
684 case NVME_LOG_HEALTH_INFORMATION:
685 nvme_health_information_page_swapbytes(
686 (struct nvme_health_information_page *)aer->log_page_buffer);
688 case NVME_LOG_FIRMWARE_SLOT:
689 nvme_firmware_page_swapbytes(
690 (struct nvme_firmware_page *)aer->log_page_buffer);
692 case NVME_LOG_CHANGED_NAMESPACE:
693 nvme_ns_list_swapbytes(
694 (struct nvme_ns_list *)aer->log_page_buffer);
696 case NVME_LOG_COMMAND_EFFECT:
697 nvme_command_effects_page_swapbytes(
698 (struct nvme_command_effects_page *)aer->log_page_buffer);
700 case NVME_LOG_RES_NOTIFICATION:
701 nvme_res_notification_page_swapbytes(
702 (struct nvme_res_notification_page *)aer->log_page_buffer);
704 case NVME_LOG_SANITIZE_STATUS:
705 nvme_sanitize_status_page_swapbytes(
706 (struct nvme_sanitize_status_page *)aer->log_page_buffer);
708 case INTEL_LOG_TEMP_STATS:
709 intel_log_temp_stats_swapbytes(
710 (struct intel_log_temp_stats *)aer->log_page_buffer);
716 if (aer->log_page_id == NVME_LOG_HEALTH_INFORMATION) {
717 health_info = (struct nvme_health_information_page *)
718 aer->log_page_buffer;
719 nvme_ctrlr_log_critical_warnings(aer->ctrlr,
720 health_info->critical_warning);
722 * Critical warnings reported through the
723 * SMART/health log page are persistent, so
724 * clear the associated bits in the async event
725 * config so that we do not receive repeated
726 * notifications for the same event.
728 aer->ctrlr->async_event_config &=
729 ~health_info->critical_warning;
730 nvme_ctrlr_cmd_set_async_event_config(aer->ctrlr,
731 aer->ctrlr->async_event_config, NULL, NULL);
732 } else if (aer->log_page_id == NVME_LOG_CHANGED_NAMESPACE &&
734 nsl = (struct nvme_ns_list *)aer->log_page_buffer;
735 for (i = 0; i < nitems(nsl->ns) && nsl->ns[i] != 0; i++) {
736 if (nsl->ns[i] > NVME_MAX_NAMESPACES)
738 nvme_notify_ns(aer->ctrlr, nsl->ns[i]);
743 * Pass the cpl data from the original async event completion,
744 * not the log page fetch.
746 nvme_notify_async_consumers(aer->ctrlr, &aer->cpl,
747 aer->log_page_id, aer->log_page_buffer, aer->log_page_size);
751 * Repost another asynchronous event request to replace the one
752 * that just completed.
754 nvme_ctrlr_construct_and_submit_aer(aer->ctrlr, aer);
758 nvme_ctrlr_async_event_cb(void *arg, const struct nvme_completion *cpl)
760 struct nvme_async_event_request *aer = arg;
762 if (nvme_completion_is_error(cpl)) {
764 * Do not retry failed async event requests. This avoids
765 * infinite loops where a new async event request is submitted
766 * to replace the one just failed, only to fail again and
767 * perpetuate the loop.
772 /* Associated log page is in bits 23:16 of completion entry dw0. */
773 aer->log_page_id = (cpl->cdw0 & 0xFF0000) >> 16;
775 nvme_printf(aer->ctrlr, "async event occurred (type 0x%x, info 0x%02x,"
776 " page 0x%02x)\n", (cpl->cdw0 & 0x07), (cpl->cdw0 & 0xFF00) >> 8,
779 if (is_log_page_id_valid(aer->log_page_id)) {
780 aer->log_page_size = nvme_ctrlr_get_log_page_size(aer->ctrlr,
782 memcpy(&aer->cpl, cpl, sizeof(*cpl));
783 nvme_ctrlr_cmd_get_log_page(aer->ctrlr, aer->log_page_id,
784 NVME_GLOBAL_NAMESPACE_TAG, aer->log_page_buffer,
785 aer->log_page_size, nvme_ctrlr_async_event_log_page_cb,
787 /* Wait to notify consumers until after log page is fetched. */
789 nvme_notify_async_consumers(aer->ctrlr, cpl, aer->log_page_id,
793 * Repost another asynchronous event request to replace the one
794 * that just completed.
796 nvme_ctrlr_construct_and_submit_aer(aer->ctrlr, aer);
801 nvme_ctrlr_construct_and_submit_aer(struct nvme_controller *ctrlr,
802 struct nvme_async_event_request *aer)
804 struct nvme_request *req;
807 req = nvme_allocate_request_null(nvme_ctrlr_async_event_cb, aer);
811 * Disable timeout here, since asynchronous event requests should by
812 * nature never be timed out.
814 req->timeout = false;
815 req->cmd.opc = NVME_OPC_ASYNC_EVENT_REQUEST;
816 nvme_ctrlr_submit_admin_request(ctrlr, req);
820 nvme_ctrlr_configure_aer(struct nvme_controller *ctrlr)
822 struct nvme_completion_poll_status status;
823 struct nvme_async_event_request *aer;
826 ctrlr->async_event_config = NVME_CRIT_WARN_ST_AVAILABLE_SPARE |
827 NVME_CRIT_WARN_ST_DEVICE_RELIABILITY |
828 NVME_CRIT_WARN_ST_READ_ONLY |
829 NVME_CRIT_WARN_ST_VOLATILE_MEMORY_BACKUP;
830 if (ctrlr->cdata.ver >= NVME_REV(1, 2))
831 ctrlr->async_event_config |= NVME_ASYNC_EVENT_NS_ATTRIBUTE |
832 NVME_ASYNC_EVENT_FW_ACTIVATE;
835 nvme_ctrlr_cmd_get_feature(ctrlr, NVME_FEAT_TEMPERATURE_THRESHOLD,
836 0, NULL, 0, nvme_completion_poll_cb, &status);
837 nvme_completion_poll(&status);
838 if (nvme_completion_is_error(&status.cpl) ||
839 (status.cpl.cdw0 & 0xFFFF) == 0xFFFF ||
840 (status.cpl.cdw0 & 0xFFFF) == 0x0000) {
841 nvme_printf(ctrlr, "temperature threshold not supported\n");
843 ctrlr->async_event_config |= NVME_CRIT_WARN_ST_TEMPERATURE;
845 nvme_ctrlr_cmd_set_async_event_config(ctrlr,
846 ctrlr->async_event_config, NULL, NULL);
848 /* aerl is a zero-based value, so we need to add 1 here. */
849 ctrlr->num_aers = min(NVME_MAX_ASYNC_EVENTS, (ctrlr->cdata.aerl+1));
851 for (i = 0; i < ctrlr->num_aers; i++) {
852 aer = &ctrlr->aer[i];
853 nvme_ctrlr_construct_and_submit_aer(ctrlr, aer);
858 nvme_ctrlr_configure_int_coalescing(struct nvme_controller *ctrlr)
861 ctrlr->int_coal_time = 0;
862 TUNABLE_INT_FETCH("hw.nvme.int_coal_time",
863 &ctrlr->int_coal_time);
865 ctrlr->int_coal_threshold = 0;
866 TUNABLE_INT_FETCH("hw.nvme.int_coal_threshold",
867 &ctrlr->int_coal_threshold);
869 nvme_ctrlr_cmd_set_interrupt_coalescing(ctrlr, ctrlr->int_coal_time,
870 ctrlr->int_coal_threshold, NULL, NULL);
874 nvme_ctrlr_hmb_free(struct nvme_controller *ctrlr)
876 struct nvme_hmb_chunk *hmbc;
879 if (ctrlr->hmb_desc_paddr) {
880 bus_dmamap_unload(ctrlr->hmb_desc_tag, ctrlr->hmb_desc_map);
881 bus_dmamem_free(ctrlr->hmb_desc_tag, ctrlr->hmb_desc_vaddr,
882 ctrlr->hmb_desc_map);
883 ctrlr->hmb_desc_paddr = 0;
885 if (ctrlr->hmb_desc_tag) {
886 bus_dma_tag_destroy(ctrlr->hmb_desc_tag);
887 ctrlr->hmb_desc_tag = NULL;
889 for (i = 0; i < ctrlr->hmb_nchunks; i++) {
890 hmbc = &ctrlr->hmb_chunks[i];
891 bus_dmamap_unload(ctrlr->hmb_tag, hmbc->hmbc_map);
892 bus_dmamem_free(ctrlr->hmb_tag, hmbc->hmbc_vaddr,
895 ctrlr->hmb_nchunks = 0;
896 if (ctrlr->hmb_tag) {
897 bus_dma_tag_destroy(ctrlr->hmb_tag);
898 ctrlr->hmb_tag = NULL;
900 if (ctrlr->hmb_chunks) {
901 free(ctrlr->hmb_chunks, M_NVME);
902 ctrlr->hmb_chunks = NULL;
907 nvme_ctrlr_hmb_alloc(struct nvme_controller *ctrlr)
909 struct nvme_hmb_chunk *hmbc;
910 size_t pref, min, minc, size;
914 /* Limit HMB to 5% of RAM size per device by default. */
915 max = (uint64_t)physmem * PAGE_SIZE / 20;
916 TUNABLE_UINT64_FETCH("hw.nvme.hmb_max", &max);
919 * Units of Host Memory Buffer in the Identify info are always in terms
922 min = (long long unsigned)ctrlr->cdata.hmmin * NVME_HMB_UNITS;
923 if (max == 0 || max < min)
925 pref = MIN((long long unsigned)ctrlr->cdata.hmpre * NVME_HMB_UNITS, max);
926 minc = MAX(ctrlr->cdata.hmminds * NVME_HMB_UNITS, ctrlr->page_size);
927 if (min > 0 && ctrlr->cdata.hmmaxd > 0)
928 minc = MAX(minc, min / ctrlr->cdata.hmmaxd);
929 ctrlr->hmb_chunk = pref;
933 * However, the chunk sizes, number of chunks, and alignment of chunks
934 * are all based on the current MPS (ctrlr->page_size).
936 ctrlr->hmb_chunk = roundup2(ctrlr->hmb_chunk, ctrlr->page_size);
937 ctrlr->hmb_nchunks = howmany(pref, ctrlr->hmb_chunk);
938 if (ctrlr->cdata.hmmaxd > 0 && ctrlr->hmb_nchunks > ctrlr->cdata.hmmaxd)
939 ctrlr->hmb_nchunks = ctrlr->cdata.hmmaxd;
940 ctrlr->hmb_chunks = malloc(sizeof(struct nvme_hmb_chunk) *
941 ctrlr->hmb_nchunks, M_NVME, M_WAITOK);
942 err = bus_dma_tag_create(bus_get_dma_tag(ctrlr->dev),
943 ctrlr->page_size, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
944 ctrlr->hmb_chunk, 1, ctrlr->hmb_chunk, 0, NULL, NULL, &ctrlr->hmb_tag);
946 nvme_printf(ctrlr, "HMB tag create failed %d\n", err);
947 nvme_ctrlr_hmb_free(ctrlr);
951 for (i = 0; i < ctrlr->hmb_nchunks; i++) {
952 hmbc = &ctrlr->hmb_chunks[i];
953 if (bus_dmamem_alloc(ctrlr->hmb_tag,
954 (void **)&hmbc->hmbc_vaddr, BUS_DMA_NOWAIT,
956 nvme_printf(ctrlr, "failed to alloc HMB\n");
959 if (bus_dmamap_load(ctrlr->hmb_tag, hmbc->hmbc_map,
960 hmbc->hmbc_vaddr, ctrlr->hmb_chunk, nvme_single_map,
961 &hmbc->hmbc_paddr, BUS_DMA_NOWAIT) != 0) {
962 bus_dmamem_free(ctrlr->hmb_tag, hmbc->hmbc_vaddr,
964 nvme_printf(ctrlr, "failed to load HMB\n");
967 bus_dmamap_sync(ctrlr->hmb_tag, hmbc->hmbc_map,
968 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
971 if (i < ctrlr->hmb_nchunks && i * ctrlr->hmb_chunk < min &&
972 ctrlr->hmb_chunk / 2 >= minc) {
973 ctrlr->hmb_nchunks = i;
974 nvme_ctrlr_hmb_free(ctrlr);
975 ctrlr->hmb_chunk /= 2;
978 ctrlr->hmb_nchunks = i;
979 if (ctrlr->hmb_nchunks * ctrlr->hmb_chunk < min) {
980 nvme_ctrlr_hmb_free(ctrlr);
984 size = sizeof(struct nvme_hmb_desc) * ctrlr->hmb_nchunks;
985 err = bus_dma_tag_create(bus_get_dma_tag(ctrlr->dev),
986 16, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
987 size, 1, size, 0, NULL, NULL, &ctrlr->hmb_desc_tag);
989 nvme_printf(ctrlr, "HMB desc tag create failed %d\n", err);
990 nvme_ctrlr_hmb_free(ctrlr);
993 if (bus_dmamem_alloc(ctrlr->hmb_desc_tag,
994 (void **)&ctrlr->hmb_desc_vaddr, BUS_DMA_WAITOK,
995 &ctrlr->hmb_desc_map)) {
996 nvme_printf(ctrlr, "failed to alloc HMB desc\n");
997 nvme_ctrlr_hmb_free(ctrlr);
1000 if (bus_dmamap_load(ctrlr->hmb_desc_tag, ctrlr->hmb_desc_map,
1001 ctrlr->hmb_desc_vaddr, size, nvme_single_map,
1002 &ctrlr->hmb_desc_paddr, BUS_DMA_NOWAIT) != 0) {
1003 bus_dmamem_free(ctrlr->hmb_desc_tag, ctrlr->hmb_desc_vaddr,
1004 ctrlr->hmb_desc_map);
1005 nvme_printf(ctrlr, "failed to load HMB desc\n");
1006 nvme_ctrlr_hmb_free(ctrlr);
1010 for (i = 0; i < ctrlr->hmb_nchunks; i++) {
1011 ctrlr->hmb_desc_vaddr[i].addr =
1012 htole64(ctrlr->hmb_chunks[i].hmbc_paddr);
1013 ctrlr->hmb_desc_vaddr[i].size = htole32(ctrlr->hmb_chunk / ctrlr->page_size);
1015 bus_dmamap_sync(ctrlr->hmb_desc_tag, ctrlr->hmb_desc_map,
1016 BUS_DMASYNC_PREWRITE);
1018 nvme_printf(ctrlr, "Allocated %lluMB host memory buffer\n",
1019 (long long unsigned)ctrlr->hmb_nchunks * ctrlr->hmb_chunk
1024 nvme_ctrlr_hmb_enable(struct nvme_controller *ctrlr, bool enable, bool memret)
1026 struct nvme_completion_poll_status status;
1035 nvme_ctrlr_cmd_set_feature(ctrlr, NVME_FEAT_HOST_MEMORY_BUFFER, cdw11,
1036 ctrlr->hmb_nchunks * ctrlr->hmb_chunk / ctrlr->page_size,
1037 ctrlr->hmb_desc_paddr, ctrlr->hmb_desc_paddr >> 32,
1038 ctrlr->hmb_nchunks, NULL, 0,
1039 nvme_completion_poll_cb, &status);
1040 nvme_completion_poll(&status);
1041 if (nvme_completion_is_error(&status.cpl))
1042 nvme_printf(ctrlr, "nvme_ctrlr_hmb_enable failed!\n");
1046 nvme_ctrlr_start(void *ctrlr_arg, bool resetting)
1048 struct nvme_controller *ctrlr = ctrlr_arg;
1049 uint32_t old_num_io_queues;
1055 * Only reset adminq here when we are restarting the
1056 * controller after a reset. During initialization,
1057 * we have already submitted admin commands to get
1058 * the number of I/O queues supported, so cannot reset
1059 * the adminq again here.
1062 nvme_qpair_reset(&ctrlr->adminq);
1063 nvme_admin_qpair_enable(&ctrlr->adminq);
1066 if (ctrlr->ioq != NULL) {
1067 for (i = 0; i < ctrlr->num_io_queues; i++)
1068 nvme_qpair_reset(&ctrlr->ioq[i]);
1072 * If it was a reset on initialization command timeout, just
1073 * return here, letting initialization code fail gracefully.
1075 if (resetting && !ctrlr->is_initialized)
1078 if (resetting && nvme_ctrlr_identify(ctrlr) != 0) {
1079 nvme_ctrlr_fail(ctrlr);
1084 * The number of qpairs are determined during controller initialization,
1085 * including using NVMe SET_FEATURES/NUMBER_OF_QUEUES to determine the
1086 * HW limit. We call SET_FEATURES again here so that it gets called
1087 * after any reset for controllers that depend on the driver to
1088 * explicit specify how many queues it will use. This value should
1089 * never change between resets, so panic if somehow that does happen.
1092 old_num_io_queues = ctrlr->num_io_queues;
1093 if (nvme_ctrlr_set_num_qpairs(ctrlr) != 0) {
1094 nvme_ctrlr_fail(ctrlr);
1098 if (old_num_io_queues != ctrlr->num_io_queues) {
1099 panic("num_io_queues changed from %u to %u",
1100 old_num_io_queues, ctrlr->num_io_queues);
1104 if (ctrlr->cdata.hmpre > 0 && ctrlr->hmb_nchunks == 0) {
1105 nvme_ctrlr_hmb_alloc(ctrlr);
1106 if (ctrlr->hmb_nchunks > 0)
1107 nvme_ctrlr_hmb_enable(ctrlr, true, false);
1108 } else if (ctrlr->hmb_nchunks > 0)
1109 nvme_ctrlr_hmb_enable(ctrlr, true, true);
1111 if (nvme_ctrlr_create_qpairs(ctrlr) != 0) {
1112 nvme_ctrlr_fail(ctrlr);
1116 if (nvme_ctrlr_construct_namespaces(ctrlr) != 0) {
1117 nvme_ctrlr_fail(ctrlr);
1121 nvme_ctrlr_configure_aer(ctrlr);
1122 nvme_ctrlr_configure_int_coalescing(ctrlr);
1124 for (i = 0; i < ctrlr->num_io_queues; i++)
1125 nvme_io_qpair_enable(&ctrlr->ioq[i]);
1130 nvme_ctrlr_start_config_hook(void *arg)
1132 struct nvme_controller *ctrlr = arg;
1136 if (nvme_ctrlr_hw_reset(ctrlr) != 0) {
1138 nvme_ctrlr_fail(ctrlr);
1139 config_intrhook_disestablish(&ctrlr->config_hook);
1143 nvme_qpair_reset(&ctrlr->adminq);
1144 nvme_admin_qpair_enable(&ctrlr->adminq);
1146 if (nvme_ctrlr_identify(ctrlr) == 0 &&
1147 nvme_ctrlr_set_num_qpairs(ctrlr) == 0 &&
1148 nvme_ctrlr_construct_io_qpairs(ctrlr) == 0)
1149 nvme_ctrlr_start(ctrlr, false);
1153 nvme_sysctl_initialize_ctrlr(ctrlr);
1154 config_intrhook_disestablish(&ctrlr->config_hook);
1156 ctrlr->is_initialized = 1;
1157 nvme_notify_new_controller(ctrlr);
1162 nvme_ctrlr_reset_task(void *arg, int pending)
1164 struct nvme_controller *ctrlr = arg;
1167 nvme_ctrlr_devctl_log(ctrlr, "RESET", "resetting controller");
1168 status = nvme_ctrlr_hw_reset(ctrlr);
1170 nvme_ctrlr_start(ctrlr, true);
1172 nvme_ctrlr_fail(ctrlr);
1174 atomic_cmpset_32(&ctrlr->is_resetting, 1, 0);
1178 * Poll all the queues enabled on the device for completion.
1181 nvme_ctrlr_poll(struct nvme_controller *ctrlr)
1185 nvme_qpair_process_completions(&ctrlr->adminq);
1187 for (i = 0; i < ctrlr->num_io_queues; i++)
1188 if (ctrlr->ioq && ctrlr->ioq[i].cpl)
1189 nvme_qpair_process_completions(&ctrlr->ioq[i]);
1193 * Poll the single-vector interrupt case: num_io_queues will be 1 and
1194 * there's only a single vector. While we're polling, we mask further
1195 * interrupts in the controller.
1198 nvme_ctrlr_shared_handler(void *arg)
1200 struct nvme_controller *ctrlr = arg;
1202 nvme_mmio_write_4(ctrlr, intms, 1);
1203 nvme_ctrlr_poll(ctrlr);
1204 nvme_mmio_write_4(ctrlr, intmc, 1);
1208 nvme_pt_done(void *arg, const struct nvme_completion *cpl)
1210 struct nvme_pt_command *pt = arg;
1211 struct mtx *mtx = pt->driver_lock;
1214 bzero(&pt->cpl, sizeof(pt->cpl));
1215 pt->cpl.cdw0 = cpl->cdw0;
1217 status = cpl->status;
1218 status &= ~NVME_STATUS_P_MASK;
1219 pt->cpl.status = status;
1222 pt->driver_lock = NULL;
1228 nvme_ctrlr_passthrough_cmd(struct nvme_controller *ctrlr,
1229 struct nvme_pt_command *pt, uint32_t nsid, int is_user_buffer,
1232 struct nvme_request *req;
1234 struct buf *buf = NULL;
1238 if (pt->len > ctrlr->max_xfer_size) {
1239 nvme_printf(ctrlr, "pt->len (%d) "
1240 "exceeds max_xfer_size (%d)\n", pt->len,
1241 ctrlr->max_xfer_size);
1244 if (is_user_buffer) {
1246 * Ensure the user buffer is wired for the duration of
1247 * this pass-through command.
1250 buf = uma_zalloc(pbuf_zone, M_WAITOK);
1251 buf->b_iocmd = pt->is_read ? BIO_READ : BIO_WRITE;
1252 if (vmapbuf(buf, pt->buf, pt->len, 1) < 0) {
1256 req = nvme_allocate_request_vaddr(buf->b_data, pt->len,
1259 req = nvme_allocate_request_vaddr(pt->buf, pt->len,
1262 req = nvme_allocate_request_null(nvme_pt_done, pt);
1264 /* Assume user space already converted to little-endian */
1265 req->cmd.opc = pt->cmd.opc;
1266 req->cmd.fuse = pt->cmd.fuse;
1267 req->cmd.rsvd2 = pt->cmd.rsvd2;
1268 req->cmd.rsvd3 = pt->cmd.rsvd3;
1269 req->cmd.cdw10 = pt->cmd.cdw10;
1270 req->cmd.cdw11 = pt->cmd.cdw11;
1271 req->cmd.cdw12 = pt->cmd.cdw12;
1272 req->cmd.cdw13 = pt->cmd.cdw13;
1273 req->cmd.cdw14 = pt->cmd.cdw14;
1274 req->cmd.cdw15 = pt->cmd.cdw15;
1276 req->cmd.nsid = htole32(nsid);
1278 mtx = mtx_pool_find(mtxpool_sleep, pt);
1279 pt->driver_lock = mtx;
1282 nvme_ctrlr_submit_admin_request(ctrlr, req);
1284 nvme_ctrlr_submit_io_request(ctrlr, req);
1287 while (pt->driver_lock != NULL)
1288 mtx_sleep(pt, mtx, PRIBIO, "nvme_pt", 0);
1294 uma_zfree(pbuf_zone, buf);
1302 nvme_ctrlr_ioctl(struct cdev *cdev, u_long cmd, caddr_t arg, int flag,
1305 struct nvme_controller *ctrlr;
1306 struct nvme_pt_command *pt;
1308 ctrlr = cdev->si_drv1;
1311 case NVME_RESET_CONTROLLER:
1312 nvme_ctrlr_reset(ctrlr);
1314 case NVME_PASSTHROUGH_CMD:
1315 pt = (struct nvme_pt_command *)arg;
1316 return (nvme_ctrlr_passthrough_cmd(ctrlr, pt, le32toh(pt->cmd.nsid),
1317 1 /* is_user_buffer */, 1 /* is_admin_cmd */));
1320 struct nvme_get_nsid *gnsid = (struct nvme_get_nsid *)arg;
1321 strncpy(gnsid->cdev, device_get_nameunit(ctrlr->dev),
1322 sizeof(gnsid->cdev));
1323 gnsid->cdev[sizeof(gnsid->cdev) - 1] = '\0';
1327 case NVME_GET_MAX_XFER_SIZE:
1328 *(uint64_t *)arg = ctrlr->max_xfer_size;
1337 static struct cdevsw nvme_ctrlr_cdevsw = {
1338 .d_version = D_VERSION,
1340 .d_ioctl = nvme_ctrlr_ioctl
1344 nvme_ctrlr_construct(struct nvme_controller *ctrlr, device_t dev)
1346 struct make_dev_args md_args;
1349 uint32_t to, vs, pmrcap;
1350 int status, timeout_period;
1354 mtx_init(&ctrlr->lock, "nvme ctrlr lock", NULL, MTX_DEF);
1355 if (bus_get_domain(dev, &ctrlr->domain) != 0)
1358 ctrlr->cap_lo = cap_lo = nvme_mmio_read_4(ctrlr, cap_lo);
1360 device_printf(dev, "CapLo: 0x%08x: MQES %u%s%s%s%s, TO %u\n",
1361 cap_lo, NVME_CAP_LO_MQES(cap_lo),
1362 NVME_CAP_LO_CQR(cap_lo) ? ", CQR" : "",
1363 NVME_CAP_LO_AMS(cap_lo) ? ", AMS" : "",
1364 (NVME_CAP_LO_AMS(cap_lo) & 0x1) ? " WRRwUPC" : "",
1365 (NVME_CAP_LO_AMS(cap_lo) & 0x2) ? " VS" : "",
1366 NVME_CAP_LO_TO(cap_lo));
1368 ctrlr->cap_hi = cap_hi = nvme_mmio_read_4(ctrlr, cap_hi);
1370 device_printf(dev, "CapHi: 0x%08x: DSTRD %u%s, CSS %x%s, "
1371 "MPSMIN %u, MPSMAX %u%s%s\n", cap_hi,
1372 NVME_CAP_HI_DSTRD(cap_hi),
1373 NVME_CAP_HI_NSSRS(cap_hi) ? ", NSSRS" : "",
1374 NVME_CAP_HI_CSS(cap_hi),
1375 NVME_CAP_HI_BPS(cap_hi) ? ", BPS" : "",
1376 NVME_CAP_HI_MPSMIN(cap_hi),
1377 NVME_CAP_HI_MPSMAX(cap_hi),
1378 NVME_CAP_HI_PMRS(cap_hi) ? ", PMRS" : "",
1379 NVME_CAP_HI_CMBS(cap_hi) ? ", CMBS" : "");
1382 vs = nvme_mmio_read_4(ctrlr, vs);
1383 device_printf(dev, "Version: 0x%08x: %d.%d\n", vs,
1384 NVME_MAJOR(vs), NVME_MINOR(vs));
1386 if (bootverbose && NVME_CAP_HI_PMRS(cap_hi)) {
1387 pmrcap = nvme_mmio_read_4(ctrlr, pmrcap);
1388 device_printf(dev, "PMRCap: 0x%08x: BIR %u%s%s, PMRTU %u, "
1389 "PMRWBM %x, PMRTO %u%s\n", pmrcap,
1390 NVME_PMRCAP_BIR(pmrcap),
1391 NVME_PMRCAP_RDS(pmrcap) ? ", RDS" : "",
1392 NVME_PMRCAP_WDS(pmrcap) ? ", WDS" : "",
1393 NVME_PMRCAP_PMRTU(pmrcap),
1394 NVME_PMRCAP_PMRWBM(pmrcap),
1395 NVME_PMRCAP_PMRTO(pmrcap),
1396 NVME_PMRCAP_CMSS(pmrcap) ? ", CMSS" : "");
1399 ctrlr->dstrd = NVME_CAP_HI_DSTRD(cap_hi) + 2;
1401 ctrlr->mps = NVME_CAP_HI_MPSMIN(cap_hi);
1402 ctrlr->page_size = 1 << (NVME_MPS_SHIFT + ctrlr->mps);
1404 /* Get ready timeout value from controller, in units of 500ms. */
1405 to = NVME_CAP_LO_TO(cap_lo) + 1;
1406 ctrlr->ready_timeout_in_ms = to * 500;
1408 timeout_period = NVME_DEFAULT_TIMEOUT_PERIOD;
1409 TUNABLE_INT_FETCH("hw.nvme.timeout_period", &timeout_period);
1410 timeout_period = min(timeout_period, NVME_MAX_TIMEOUT_PERIOD);
1411 timeout_period = max(timeout_period, NVME_MIN_TIMEOUT_PERIOD);
1412 ctrlr->timeout_period = timeout_period;
1414 nvme_retry_count = NVME_DEFAULT_RETRY_COUNT;
1415 TUNABLE_INT_FETCH("hw.nvme.retry_count", &nvme_retry_count);
1417 ctrlr->enable_aborts = 0;
1418 TUNABLE_INT_FETCH("hw.nvme.enable_aborts", &ctrlr->enable_aborts);
1420 /* Cap transfers by the maximum addressable by page-sized PRP (4KB pages -> 2MB). */
1421 ctrlr->max_xfer_size = MIN(maxphys, (ctrlr->page_size / 8 * ctrlr->page_size));
1422 if (nvme_ctrlr_construct_admin_qpair(ctrlr) != 0)
1426 * Create 2 threads for the taskqueue. The reset thread will block when
1427 * it detects that the controller has failed until all I/O has been
1428 * failed up the stack. The fail_req task needs to be able to run in
1429 * this case to finish the request failure for some cases.
1431 * We could partially solve this race by draining the failed requeust
1432 * queue before proceding to free the sim, though nothing would stop
1433 * new I/O from coming in after we do that drain, but before we reach
1434 * cam_sim_free, so this big hammer is used instead.
1436 ctrlr->taskqueue = taskqueue_create("nvme_taskq", M_WAITOK,
1437 taskqueue_thread_enqueue, &ctrlr->taskqueue);
1438 taskqueue_start_threads(&ctrlr->taskqueue, 2, PI_DISK, "nvme taskq");
1440 ctrlr->is_resetting = 0;
1441 ctrlr->is_initialized = 0;
1442 ctrlr->notification_sent = 0;
1443 TASK_INIT(&ctrlr->reset_task, 0, nvme_ctrlr_reset_task, ctrlr);
1444 STAILQ_INIT(&ctrlr->fail_req);
1445 ctrlr->is_failed = false;
1447 make_dev_args_init(&md_args);
1448 md_args.mda_devsw = &nvme_ctrlr_cdevsw;
1449 md_args.mda_uid = UID_ROOT;
1450 md_args.mda_gid = GID_WHEEL;
1451 md_args.mda_mode = 0600;
1452 md_args.mda_unit = device_get_unit(dev);
1453 md_args.mda_si_drv1 = (void *)ctrlr;
1454 status = make_dev_s(&md_args, &ctrlr->cdev, "nvme%d",
1455 device_get_unit(dev));
1463 nvme_ctrlr_destruct(struct nvme_controller *ctrlr, device_t dev)
1467 ctrlr->is_dying = true;
1469 if (ctrlr->resource == NULL)
1471 if (!mtx_initialized(&ctrlr->adminq.lock))
1475 * Check whether it is a hot unplug or a clean driver detach.
1476 * If device is not there any more, skip any shutdown commands.
1478 gone = (nvme_mmio_read_4(ctrlr, csts) == NVME_GONE);
1480 nvme_ctrlr_fail(ctrlr);
1482 nvme_notify_fail_consumers(ctrlr);
1484 for (i = 0; i < NVME_MAX_NAMESPACES; i++)
1485 nvme_ns_destruct(&ctrlr->ns[i]);
1488 destroy_dev(ctrlr->cdev);
1490 if (ctrlr->is_initialized) {
1492 if (ctrlr->hmb_nchunks > 0)
1493 nvme_ctrlr_hmb_enable(ctrlr, false, false);
1494 nvme_ctrlr_delete_qpairs(ctrlr);
1496 nvme_ctrlr_hmb_free(ctrlr);
1498 if (ctrlr->ioq != NULL) {
1499 for (i = 0; i < ctrlr->num_io_queues; i++)
1500 nvme_io_qpair_destroy(&ctrlr->ioq[i]);
1501 free(ctrlr->ioq, M_NVME);
1503 nvme_admin_qpair_destroy(&ctrlr->adminq);
1506 * Notify the controller of a shutdown, even though this is due to
1507 * a driver unload, not a system shutdown (this path is not invoked
1508 * during shutdown). This ensures the controller receives a
1509 * shutdown notification in case the system is shutdown before
1510 * reloading the driver.
1513 nvme_ctrlr_shutdown(ctrlr);
1516 nvme_ctrlr_disable(ctrlr);
1519 if (ctrlr->taskqueue)
1520 taskqueue_free(ctrlr->taskqueue);
1523 bus_teardown_intr(ctrlr->dev, ctrlr->res, ctrlr->tag);
1526 bus_release_resource(ctrlr->dev, SYS_RES_IRQ,
1527 rman_get_rid(ctrlr->res), ctrlr->res);
1529 if (ctrlr->bar4_resource != NULL) {
1530 bus_release_resource(dev, SYS_RES_MEMORY,
1531 ctrlr->bar4_resource_id, ctrlr->bar4_resource);
1534 bus_release_resource(dev, SYS_RES_MEMORY,
1535 ctrlr->resource_id, ctrlr->resource);
1538 mtx_destroy(&ctrlr->lock);
1542 nvme_ctrlr_shutdown(struct nvme_controller *ctrlr)
1548 cc = nvme_mmio_read_4(ctrlr, cc);
1549 cc &= ~(NVME_CC_REG_SHN_MASK << NVME_CC_REG_SHN_SHIFT);
1550 cc |= NVME_SHN_NORMAL << NVME_CC_REG_SHN_SHIFT;
1551 nvme_mmio_write_4(ctrlr, cc, cc);
1553 timeout = ticks + (ctrlr->cdata.rtd3e == 0 ? 5 * hz :
1554 ((uint64_t)ctrlr->cdata.rtd3e * hz + 999999) / 1000000);
1556 csts = nvme_mmio_read_4(ctrlr, csts);
1557 if (csts == NVME_GONE) /* Hot unplug. */
1559 if (NVME_CSTS_GET_SHST(csts) == NVME_SHST_COMPLETE)
1561 if (timeout - ticks < 0) {
1562 nvme_printf(ctrlr, "shutdown timeout\n");
1565 pause("nvmeshut", 1);
1570 nvme_ctrlr_submit_admin_request(struct nvme_controller *ctrlr,
1571 struct nvme_request *req)
1574 nvme_qpair_submit_request(&ctrlr->adminq, req);
1578 nvme_ctrlr_submit_io_request(struct nvme_controller *ctrlr,
1579 struct nvme_request *req)
1581 struct nvme_qpair *qpair;
1583 qpair = &ctrlr->ioq[QP(ctrlr, curcpu)];
1584 nvme_qpair_submit_request(qpair, req);
1588 nvme_ctrlr_get_device(struct nvme_controller *ctrlr)
1591 return (ctrlr->dev);
1594 const struct nvme_controller_data *
1595 nvme_ctrlr_get_data(struct nvme_controller *ctrlr)
1598 return (&ctrlr->cdata);
1602 nvme_ctrlr_suspend(struct nvme_controller *ctrlr)
1607 * Can't touch failed controllers, so it's already suspended.
1609 if (ctrlr->is_failed)
1613 * We don't want the reset taskqueue running, since it does similar
1614 * things, so prevent it from running after we start. Wait for any reset
1615 * that may have been started to complete. The reset process we follow
1616 * will ensure that any new I/O will queue and be given to the hardware
1617 * after we resume (though there should be none).
1619 while (atomic_cmpset_32(&ctrlr->is_resetting, 0, 1) == 0 && to-- > 0)
1620 pause("nvmesusp", 1);
1623 "Competing reset task didn't finish. Try again later.\n");
1624 return (EWOULDBLOCK);
1627 if (ctrlr->hmb_nchunks > 0)
1628 nvme_ctrlr_hmb_enable(ctrlr, false, false);
1631 * Per Section 7.6.2 of NVMe spec 1.4, to properly suspend, we need to
1632 * delete the hardware I/O queues, and then shutdown. This properly
1633 * flushes any metadata the drive may have stored so it can survive
1634 * having its power removed and prevents the unsafe shutdown count from
1635 * incriminating. Once we delete the qpairs, we have to disable them
1636 * before shutting down.
1638 nvme_ctrlr_delete_qpairs(ctrlr);
1639 nvme_ctrlr_disable_qpairs(ctrlr);
1640 nvme_ctrlr_shutdown(ctrlr);
1646 nvme_ctrlr_resume(struct nvme_controller *ctrlr)
1650 * Can't touch failed controllers, so nothing to do to resume.
1652 if (ctrlr->is_failed)
1655 if (nvme_ctrlr_hw_reset(ctrlr) != 0)
1659 * Now that we've reset the hardware, we can restart the controller. Any
1660 * I/O that was pending is requeued. Any admin commands are aborted with
1661 * an error. Once we've restarted, take the controller out of reset.
1663 nvme_ctrlr_start(ctrlr, true);
1664 (void)atomic_cmpset_32(&ctrlr->is_resetting, 1, 0);
1669 * Since we can't bring the controller out of reset, announce and fail
1670 * the controller. However, we have to return success for the resume
1671 * itself, due to questionable APIs.
1673 nvme_printf(ctrlr, "Failed to reset on resume, failing.\n");
1674 nvme_ctrlr_fail(ctrlr);
1675 (void)atomic_cmpset_32(&ctrlr->is_resetting, 1, 0);