2 * Copyright (C) 2012-2016 Intel Corporation
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
37 #include <sys/ioccom.h>
42 #include <dev/pci/pcireg.h>
43 #include <dev/pci/pcivar.h>
45 #include "nvme_private.h"
47 static void nvme_ctrlr_construct_and_submit_aer(struct nvme_controller *ctrlr,
48 struct nvme_async_event_request *aer);
49 static void nvme_ctrlr_setup_interrupts(struct nvme_controller *ctrlr);
52 nvme_ctrlr_allocate_bar(struct nvme_controller *ctrlr)
55 ctrlr->resource_id = PCIR_BAR(0);
57 ctrlr->resource = bus_alloc_resource_any(ctrlr->dev, SYS_RES_MEMORY,
58 &ctrlr->resource_id, RF_ACTIVE);
60 if(ctrlr->resource == NULL) {
61 nvme_printf(ctrlr, "unable to allocate pci resource\n");
65 ctrlr->bus_tag = rman_get_bustag(ctrlr->resource);
66 ctrlr->bus_handle = rman_get_bushandle(ctrlr->resource);
67 ctrlr->regs = (struct nvme_registers *)ctrlr->bus_handle;
70 * The NVMe spec allows for the MSI-X table to be placed behind
71 * BAR 4/5, separate from the control/doorbell registers. Always
72 * try to map this bar, because it must be mapped prior to calling
73 * pci_alloc_msix(). If the table isn't behind BAR 4/5,
74 * bus_alloc_resource() will just return NULL which is OK.
76 ctrlr->bar4_resource_id = PCIR_BAR(4);
77 ctrlr->bar4_resource = bus_alloc_resource_any(ctrlr->dev, SYS_RES_MEMORY,
78 &ctrlr->bar4_resource_id, RF_ACTIVE);
84 nvme_ctrlr_construct_admin_qpair(struct nvme_controller *ctrlr)
86 struct nvme_qpair *qpair;
89 qpair = &ctrlr->adminq;
91 num_entries = NVME_ADMIN_ENTRIES;
92 TUNABLE_INT_FETCH("hw.nvme.admin_entries", &num_entries);
94 * If admin_entries was overridden to an invalid value, revert it
95 * back to our default value.
97 if (num_entries < NVME_MIN_ADMIN_ENTRIES ||
98 num_entries > NVME_MAX_ADMIN_ENTRIES) {
99 nvme_printf(ctrlr, "invalid hw.nvme.admin_entries=%d "
100 "specified\n", num_entries);
101 num_entries = NVME_ADMIN_ENTRIES;
105 * The admin queue's max xfer size is treated differently than the
106 * max I/O xfer size. 16KB is sufficient here - maybe even less?
108 nvme_qpair_construct(qpair,
117 nvme_ctrlr_construct_io_qpairs(struct nvme_controller *ctrlr)
119 struct nvme_qpair *qpair;
120 union cap_lo_register cap_lo;
121 int i, num_entries, num_trackers;
123 num_entries = NVME_IO_ENTRIES;
124 TUNABLE_INT_FETCH("hw.nvme.io_entries", &num_entries);
127 * NVMe spec sets a hard limit of 64K max entries, but
128 * devices may specify a smaller limit, so we need to check
129 * the MQES field in the capabilities register.
131 cap_lo.raw = nvme_mmio_read_4(ctrlr, cap_lo);
132 num_entries = min(num_entries, cap_lo.bits.mqes+1);
134 num_trackers = NVME_IO_TRACKERS;
135 TUNABLE_INT_FETCH("hw.nvme.io_trackers", &num_trackers);
137 num_trackers = max(num_trackers, NVME_MIN_IO_TRACKERS);
138 num_trackers = min(num_trackers, NVME_MAX_IO_TRACKERS);
140 * No need to have more trackers than entries in the submit queue.
141 * Note also that for a queue size of N, we can only have (N-1)
142 * commands outstanding, hence the "-1" here.
144 num_trackers = min(num_trackers, (num_entries-1));
147 * This was calculated previously when setting up interrupts, but
148 * a controller could theoretically support fewer I/O queues than
149 * MSI-X vectors. So calculate again here just to be safe.
151 ctrlr->num_cpus_per_ioq = howmany(mp_ncpus, ctrlr->num_io_queues);
153 ctrlr->ioq = malloc(ctrlr->num_io_queues * sizeof(struct nvme_qpair),
154 M_NVME, M_ZERO | M_WAITOK);
156 for (i = 0; i < ctrlr->num_io_queues; i++) {
157 qpair = &ctrlr->ioq[i];
160 * Admin queue has ID=0. IO queues start at ID=1 -
161 * hence the 'i+1' here.
163 * For I/O queues, use the controller-wide max_xfer_size
164 * calculated in nvme_attach().
166 nvme_qpair_construct(qpair,
168 ctrlr->msix_enabled ? i+1 : 0, /* vector */
174 * Do not bother binding interrupts if we only have one I/O
175 * interrupt thread for this controller.
177 if (ctrlr->num_io_queues > 1)
178 bus_bind_intr(ctrlr->dev, qpair->res,
179 i * ctrlr->num_cpus_per_ioq);
186 nvme_ctrlr_fail(struct nvme_controller *ctrlr)
190 ctrlr->is_failed = TRUE;
191 nvme_qpair_fail(&ctrlr->adminq);
192 for (i = 0; i < ctrlr->num_io_queues; i++)
193 nvme_qpair_fail(&ctrlr->ioq[i]);
194 nvme_notify_fail_consumers(ctrlr);
198 nvme_ctrlr_post_failed_request(struct nvme_controller *ctrlr,
199 struct nvme_request *req)
202 mtx_lock(&ctrlr->lock);
203 STAILQ_INSERT_TAIL(&ctrlr->fail_req, req, stailq);
204 mtx_unlock(&ctrlr->lock);
205 taskqueue_enqueue(ctrlr->taskqueue, &ctrlr->fail_req_task);
209 nvme_ctrlr_fail_req_task(void *arg, int pending)
211 struct nvme_controller *ctrlr = arg;
212 struct nvme_request *req;
214 mtx_lock(&ctrlr->lock);
215 while (!STAILQ_EMPTY(&ctrlr->fail_req)) {
216 req = STAILQ_FIRST(&ctrlr->fail_req);
217 STAILQ_REMOVE_HEAD(&ctrlr->fail_req, stailq);
218 nvme_qpair_manual_complete_request(req->qpair, req,
219 NVME_SCT_GENERIC, NVME_SC_ABORTED_BY_REQUEST, TRUE);
221 mtx_unlock(&ctrlr->lock);
225 nvme_ctrlr_wait_for_ready(struct nvme_controller *ctrlr, int desired_val)
228 union cc_register cc;
229 union csts_register csts;
231 cc.raw = nvme_mmio_read_4(ctrlr, cc);
232 csts.raw = nvme_mmio_read_4(ctrlr, csts);
234 if (cc.bits.en != desired_val) {
235 nvme_printf(ctrlr, "%s called with desired_val = %d "
236 "but cc.en = %d\n", __func__, desired_val, cc.bits.en);
242 while (csts.bits.rdy != desired_val) {
244 if (ms_waited++ > ctrlr->ready_timeout_in_ms) {
245 nvme_printf(ctrlr, "controller ready did not become %d "
246 "within %d ms\n", desired_val, ctrlr->ready_timeout_in_ms);
249 csts.raw = nvme_mmio_read_4(ctrlr, csts);
256 nvme_ctrlr_disable(struct nvme_controller *ctrlr)
258 union cc_register cc;
259 union csts_register csts;
261 cc.raw = nvme_mmio_read_4(ctrlr, cc);
262 csts.raw = nvme_mmio_read_4(ctrlr, csts);
264 if (cc.bits.en == 1 && csts.bits.rdy == 0)
265 nvme_ctrlr_wait_for_ready(ctrlr, 1);
268 nvme_mmio_write_4(ctrlr, cc, cc.raw);
270 nvme_ctrlr_wait_for_ready(ctrlr, 0);
274 nvme_ctrlr_enable(struct nvme_controller *ctrlr)
276 union cc_register cc;
277 union csts_register csts;
278 union aqa_register aqa;
280 cc.raw = nvme_mmio_read_4(ctrlr, cc);
281 csts.raw = nvme_mmio_read_4(ctrlr, csts);
283 if (cc.bits.en == 1) {
284 if (csts.bits.rdy == 1)
287 return (nvme_ctrlr_wait_for_ready(ctrlr, 1));
290 nvme_mmio_write_8(ctrlr, asq, ctrlr->adminq.cmd_bus_addr);
292 nvme_mmio_write_8(ctrlr, acq, ctrlr->adminq.cpl_bus_addr);
296 /* acqs and asqs are 0-based. */
297 aqa.bits.acqs = ctrlr->adminq.num_entries-1;
298 aqa.bits.asqs = ctrlr->adminq.num_entries-1;
299 nvme_mmio_write_4(ctrlr, aqa, aqa.raw);
306 cc.bits.iosqes = 6; /* SQ entry size == 64 == 2^6 */
307 cc.bits.iocqes = 4; /* CQ entry size == 16 == 2^4 */
309 /* This evaluates to 0, which is according to spec. */
310 cc.bits.mps = (PAGE_SIZE >> 13);
312 nvme_mmio_write_4(ctrlr, cc, cc.raw);
315 return (nvme_ctrlr_wait_for_ready(ctrlr, 1));
319 nvme_ctrlr_hw_reset(struct nvme_controller *ctrlr)
323 nvme_admin_qpair_disable(&ctrlr->adminq);
325 * I/O queues are not allocated before the initial HW
326 * reset, so do not try to disable them. Use is_initialized
327 * to determine if this is the initial HW reset.
329 if (ctrlr->is_initialized) {
330 for (i = 0; i < ctrlr->num_io_queues; i++)
331 nvme_io_qpair_disable(&ctrlr->ioq[i]);
336 nvme_ctrlr_disable(ctrlr);
337 return (nvme_ctrlr_enable(ctrlr));
341 nvme_ctrlr_reset(struct nvme_controller *ctrlr)
345 cmpset = atomic_cmpset_32(&ctrlr->is_resetting, 0, 1);
347 if (cmpset == 0 || ctrlr->is_failed)
349 * Controller is already resetting or has failed. Return
350 * immediately since there is no need to kick off another
351 * reset in these cases.
355 taskqueue_enqueue(ctrlr->taskqueue, &ctrlr->reset_task);
359 nvme_ctrlr_identify(struct nvme_controller *ctrlr)
361 struct nvme_completion_poll_status status;
364 nvme_ctrlr_cmd_identify_controller(ctrlr, &ctrlr->cdata,
365 nvme_completion_poll_cb, &status);
366 while (status.done == FALSE)
368 if (nvme_completion_is_error(&status.cpl)) {
369 nvme_printf(ctrlr, "nvme_identify_controller failed!\n");
374 * Use MDTS to ensure our default max_xfer_size doesn't exceed what the
375 * controller supports.
377 if (ctrlr->cdata.mdts > 0)
378 ctrlr->max_xfer_size = min(ctrlr->max_xfer_size,
379 ctrlr->min_page_size * (1 << (ctrlr->cdata.mdts)));
385 nvme_ctrlr_set_num_qpairs(struct nvme_controller *ctrlr)
387 struct nvme_completion_poll_status status;
388 int cq_allocated, sq_allocated;
391 nvme_ctrlr_cmd_set_num_queues(ctrlr, ctrlr->num_io_queues,
392 nvme_completion_poll_cb, &status);
393 while (status.done == FALSE)
395 if (nvme_completion_is_error(&status.cpl)) {
396 nvme_printf(ctrlr, "nvme_set_num_queues failed!\n");
401 * Data in cdw0 is 0-based.
402 * Lower 16-bits indicate number of submission queues allocated.
403 * Upper 16-bits indicate number of completion queues allocated.
405 sq_allocated = (status.cpl.cdw0 & 0xFFFF) + 1;
406 cq_allocated = (status.cpl.cdw0 >> 16) + 1;
409 * Controller may allocate more queues than we requested,
410 * so use the minimum of the number requested and what was
411 * actually allocated.
413 ctrlr->num_io_queues = min(ctrlr->num_io_queues, sq_allocated);
414 ctrlr->num_io_queues = min(ctrlr->num_io_queues, cq_allocated);
420 nvme_ctrlr_create_qpairs(struct nvme_controller *ctrlr)
422 struct nvme_completion_poll_status status;
423 struct nvme_qpair *qpair;
426 for (i = 0; i < ctrlr->num_io_queues; i++) {
427 qpair = &ctrlr->ioq[i];
430 nvme_ctrlr_cmd_create_io_cq(ctrlr, qpair, qpair->vector,
431 nvme_completion_poll_cb, &status);
432 while (status.done == FALSE)
434 if (nvme_completion_is_error(&status.cpl)) {
435 nvme_printf(ctrlr, "nvme_create_io_cq failed!\n");
440 nvme_ctrlr_cmd_create_io_sq(qpair->ctrlr, qpair,
441 nvme_completion_poll_cb, &status);
442 while (status.done == FALSE)
444 if (nvme_completion_is_error(&status.cpl)) {
445 nvme_printf(ctrlr, "nvme_create_io_sq failed!\n");
454 nvme_ctrlr_construct_namespaces(struct nvme_controller *ctrlr)
456 struct nvme_namespace *ns;
459 for (i = 0; i < ctrlr->cdata.nn; i++) {
461 status = nvme_ns_construct(ns, i+1, ctrlr);
470 is_log_page_id_valid(uint8_t page_id)
475 case NVME_LOG_HEALTH_INFORMATION:
476 case NVME_LOG_FIRMWARE_SLOT:
484 nvme_ctrlr_get_log_page_size(struct nvme_controller *ctrlr, uint8_t page_id)
486 uint32_t log_page_size;
491 sizeof(struct nvme_error_information_entry) *
493 NVME_MAX_AER_LOG_SIZE);
495 case NVME_LOG_HEALTH_INFORMATION:
496 log_page_size = sizeof(struct nvme_health_information_page);
498 case NVME_LOG_FIRMWARE_SLOT:
499 log_page_size = sizeof(struct nvme_firmware_page);
506 return (log_page_size);
510 nvme_ctrlr_log_critical_warnings(struct nvme_controller *ctrlr,
511 union nvme_critical_warning_state state)
514 if (state.bits.available_spare == 1)
515 nvme_printf(ctrlr, "available spare space below threshold\n");
517 if (state.bits.temperature == 1)
518 nvme_printf(ctrlr, "temperature above threshold\n");
520 if (state.bits.device_reliability == 1)
521 nvme_printf(ctrlr, "device reliability degraded\n");
523 if (state.bits.read_only == 1)
524 nvme_printf(ctrlr, "media placed in read only mode\n");
526 if (state.bits.volatile_memory_backup == 1)
527 nvme_printf(ctrlr, "volatile memory backup device failed\n");
529 if (state.bits.reserved != 0)
531 "unknown critical warning(s): state = 0x%02x\n", state.raw);
535 nvme_ctrlr_async_event_log_page_cb(void *arg, const struct nvme_completion *cpl)
537 struct nvme_async_event_request *aer = arg;
538 struct nvme_health_information_page *health_info;
541 * If the log page fetch for some reason completed with an error,
542 * don't pass log page data to the consumers. In practice, this case
543 * should never happen.
545 if (nvme_completion_is_error(cpl))
546 nvme_notify_async_consumers(aer->ctrlr, &aer->cpl,
547 aer->log_page_id, NULL, 0);
549 if (aer->log_page_id == NVME_LOG_HEALTH_INFORMATION) {
550 health_info = (struct nvme_health_information_page *)
551 aer->log_page_buffer;
552 nvme_ctrlr_log_critical_warnings(aer->ctrlr,
553 health_info->critical_warning);
555 * Critical warnings reported through the
556 * SMART/health log page are persistent, so
557 * clear the associated bits in the async event
558 * config so that we do not receive repeated
559 * notifications for the same event.
561 aer->ctrlr->async_event_config.raw &=
562 ~health_info->critical_warning.raw;
563 nvme_ctrlr_cmd_set_async_event_config(aer->ctrlr,
564 aer->ctrlr->async_event_config, NULL, NULL);
569 * Pass the cpl data from the original async event completion,
570 * not the log page fetch.
572 nvme_notify_async_consumers(aer->ctrlr, &aer->cpl,
573 aer->log_page_id, aer->log_page_buffer, aer->log_page_size);
577 * Repost another asynchronous event request to replace the one
578 * that just completed.
580 nvme_ctrlr_construct_and_submit_aer(aer->ctrlr, aer);
584 nvme_ctrlr_async_event_cb(void *arg, const struct nvme_completion *cpl)
586 struct nvme_async_event_request *aer = arg;
588 if (nvme_completion_is_error(cpl)) {
590 * Do not retry failed async event requests. This avoids
591 * infinite loops where a new async event request is submitted
592 * to replace the one just failed, only to fail again and
593 * perpetuate the loop.
598 /* Associated log page is in bits 23:16 of completion entry dw0. */
599 aer->log_page_id = (cpl->cdw0 & 0xFF0000) >> 16;
601 nvme_printf(aer->ctrlr, "async event occurred (log page id=0x%x)\n",
604 if (is_log_page_id_valid(aer->log_page_id)) {
605 aer->log_page_size = nvme_ctrlr_get_log_page_size(aer->ctrlr,
607 memcpy(&aer->cpl, cpl, sizeof(*cpl));
608 nvme_ctrlr_cmd_get_log_page(aer->ctrlr, aer->log_page_id,
609 NVME_GLOBAL_NAMESPACE_TAG, aer->log_page_buffer,
610 aer->log_page_size, nvme_ctrlr_async_event_log_page_cb,
612 /* Wait to notify consumers until after log page is fetched. */
614 nvme_notify_async_consumers(aer->ctrlr, cpl, aer->log_page_id,
618 * Repost another asynchronous event request to replace the one
619 * that just completed.
621 nvme_ctrlr_construct_and_submit_aer(aer->ctrlr, aer);
626 nvme_ctrlr_construct_and_submit_aer(struct nvme_controller *ctrlr,
627 struct nvme_async_event_request *aer)
629 struct nvme_request *req;
632 req = nvme_allocate_request_null(nvme_ctrlr_async_event_cb, aer);
636 * Disable timeout here, since asynchronous event requests should by
637 * nature never be timed out.
639 req->timeout = FALSE;
640 req->cmd.opc = NVME_OPC_ASYNC_EVENT_REQUEST;
641 nvme_ctrlr_submit_admin_request(ctrlr, req);
645 nvme_ctrlr_configure_aer(struct nvme_controller *ctrlr)
647 struct nvme_completion_poll_status status;
648 struct nvme_async_event_request *aer;
651 ctrlr->async_event_config.raw = 0xFF;
652 ctrlr->async_event_config.bits.reserved = 0;
655 nvme_ctrlr_cmd_get_feature(ctrlr, NVME_FEAT_TEMPERATURE_THRESHOLD,
656 0, NULL, 0, nvme_completion_poll_cb, &status);
657 while (status.done == FALSE)
659 if (nvme_completion_is_error(&status.cpl) ||
660 (status.cpl.cdw0 & 0xFFFF) == 0xFFFF ||
661 (status.cpl.cdw0 & 0xFFFF) == 0x0000) {
662 nvme_printf(ctrlr, "temperature threshold not supported\n");
663 ctrlr->async_event_config.bits.temperature = 0;
666 nvme_ctrlr_cmd_set_async_event_config(ctrlr,
667 ctrlr->async_event_config, NULL, NULL);
669 /* aerl is a zero-based value, so we need to add 1 here. */
670 ctrlr->num_aers = min(NVME_MAX_ASYNC_EVENTS, (ctrlr->cdata.aerl+1));
672 for (i = 0; i < ctrlr->num_aers; i++) {
673 aer = &ctrlr->aer[i];
674 nvme_ctrlr_construct_and_submit_aer(ctrlr, aer);
679 nvme_ctrlr_configure_int_coalescing(struct nvme_controller *ctrlr)
682 ctrlr->int_coal_time = 0;
683 TUNABLE_INT_FETCH("hw.nvme.int_coal_time",
684 &ctrlr->int_coal_time);
686 ctrlr->int_coal_threshold = 0;
687 TUNABLE_INT_FETCH("hw.nvme.int_coal_threshold",
688 &ctrlr->int_coal_threshold);
690 nvme_ctrlr_cmd_set_interrupt_coalescing(ctrlr, ctrlr->int_coal_time,
691 ctrlr->int_coal_threshold, NULL, NULL);
695 nvme_ctrlr_start(void *ctrlr_arg)
697 struct nvme_controller *ctrlr = ctrlr_arg;
698 uint32_t old_num_io_queues;
702 * Only reset adminq here when we are restarting the
703 * controller after a reset. During initialization,
704 * we have already submitted admin commands to get
705 * the number of I/O queues supported, so cannot reset
706 * the adminq again here.
708 if (ctrlr->is_resetting) {
709 nvme_qpair_reset(&ctrlr->adminq);
712 for (i = 0; i < ctrlr->num_io_queues; i++)
713 nvme_qpair_reset(&ctrlr->ioq[i]);
715 nvme_admin_qpair_enable(&ctrlr->adminq);
717 if (nvme_ctrlr_identify(ctrlr) != 0) {
718 nvme_ctrlr_fail(ctrlr);
723 * The number of qpairs are determined during controller initialization,
724 * including using NVMe SET_FEATURES/NUMBER_OF_QUEUES to determine the
725 * HW limit. We call SET_FEATURES again here so that it gets called
726 * after any reset for controllers that depend on the driver to
727 * explicit specify how many queues it will use. This value should
728 * never change between resets, so panic if somehow that does happen.
730 if (ctrlr->is_resetting) {
731 old_num_io_queues = ctrlr->num_io_queues;
732 if (nvme_ctrlr_set_num_qpairs(ctrlr) != 0) {
733 nvme_ctrlr_fail(ctrlr);
737 if (old_num_io_queues != ctrlr->num_io_queues) {
738 panic("num_io_queues changed from %u to %u",
739 old_num_io_queues, ctrlr->num_io_queues);
743 if (nvme_ctrlr_create_qpairs(ctrlr) != 0) {
744 nvme_ctrlr_fail(ctrlr);
748 if (nvme_ctrlr_construct_namespaces(ctrlr) != 0) {
749 nvme_ctrlr_fail(ctrlr);
753 nvme_ctrlr_configure_aer(ctrlr);
754 nvme_ctrlr_configure_int_coalescing(ctrlr);
756 for (i = 0; i < ctrlr->num_io_queues; i++)
757 nvme_io_qpair_enable(&ctrlr->ioq[i]);
761 nvme_ctrlr_start_config_hook(void *arg)
763 struct nvme_controller *ctrlr = arg;
765 nvme_qpair_reset(&ctrlr->adminq);
766 nvme_admin_qpair_enable(&ctrlr->adminq);
768 if (nvme_ctrlr_set_num_qpairs(ctrlr) == 0 &&
769 nvme_ctrlr_construct_io_qpairs(ctrlr) == 0)
770 nvme_ctrlr_start(ctrlr);
772 nvme_ctrlr_fail(ctrlr);
774 nvme_sysctl_initialize_ctrlr(ctrlr);
775 config_intrhook_disestablish(&ctrlr->config_hook);
777 ctrlr->is_initialized = 1;
778 nvme_notify_new_controller(ctrlr);
782 nvme_ctrlr_reset_task(void *arg, int pending)
784 struct nvme_controller *ctrlr = arg;
787 nvme_printf(ctrlr, "resetting controller\n");
788 status = nvme_ctrlr_hw_reset(ctrlr);
790 * Use pause instead of DELAY, so that we yield to any nvme interrupt
791 * handlers on this CPU that were blocked on a qpair lock. We want
792 * all nvme interrupts completed before proceeding with restarting the
795 * XXX - any way to guarantee the interrupt handlers have quiesced?
797 pause("nvmereset", hz / 10);
799 nvme_ctrlr_start(ctrlr);
801 nvme_ctrlr_fail(ctrlr);
803 atomic_cmpset_32(&ctrlr->is_resetting, 1, 0);
807 nvme_ctrlr_intx_handler(void *arg)
809 struct nvme_controller *ctrlr = arg;
811 nvme_mmio_write_4(ctrlr, intms, 1);
813 nvme_qpair_process_completions(&ctrlr->adminq);
815 if (ctrlr->ioq && ctrlr->ioq[0].cpl)
816 nvme_qpair_process_completions(&ctrlr->ioq[0]);
818 nvme_mmio_write_4(ctrlr, intmc, 1);
822 nvme_ctrlr_configure_intx(struct nvme_controller *ctrlr)
825 ctrlr->msix_enabled = 0;
826 ctrlr->num_io_queues = 1;
827 ctrlr->num_cpus_per_ioq = mp_ncpus;
829 ctrlr->res = bus_alloc_resource_any(ctrlr->dev, SYS_RES_IRQ,
830 &ctrlr->rid, RF_SHAREABLE | RF_ACTIVE);
832 if (ctrlr->res == NULL) {
833 nvme_printf(ctrlr, "unable to allocate shared IRQ\n");
837 bus_setup_intr(ctrlr->dev, ctrlr->res,
838 INTR_TYPE_MISC | INTR_MPSAFE, NULL, nvme_ctrlr_intx_handler,
841 if (ctrlr->tag == NULL) {
842 nvme_printf(ctrlr, "unable to setup intx handler\n");
850 nvme_pt_done(void *arg, const struct nvme_completion *cpl)
852 struct nvme_pt_command *pt = arg;
854 bzero(&pt->cpl, sizeof(pt->cpl));
855 pt->cpl.cdw0 = cpl->cdw0;
856 pt->cpl.status = cpl->status;
857 pt->cpl.status.p = 0;
859 mtx_lock(pt->driver_lock);
861 mtx_unlock(pt->driver_lock);
865 nvme_ctrlr_passthrough_cmd(struct nvme_controller *ctrlr,
866 struct nvme_pt_command *pt, uint32_t nsid, int is_user_buffer,
869 struct nvme_request *req;
871 struct buf *buf = NULL;
875 if (pt->len > ctrlr->max_xfer_size) {
876 nvme_printf(ctrlr, "pt->len (%d) "
877 "exceeds max_xfer_size (%d)\n", pt->len,
878 ctrlr->max_xfer_size);
881 if (is_user_buffer) {
883 * Ensure the user buffer is wired for the duration of
884 * this passthrough command.
888 buf->b_data = pt->buf;
889 buf->b_bufsize = pt->len;
890 buf->b_iocmd = pt->is_read ? BIO_READ : BIO_WRITE;
891 #ifdef NVME_UNMAPPED_BIO_SUPPORT
892 if (vmapbuf(buf, 1) < 0) {
894 if (vmapbuf(buf) < 0) {
899 req = nvme_allocate_request_vaddr(buf->b_data, pt->len,
902 req = nvme_allocate_request_vaddr(pt->buf, pt->len,
905 req = nvme_allocate_request_null(nvme_pt_done, pt);
907 req->cmd.opc = pt->cmd.opc;
908 req->cmd.cdw10 = pt->cmd.cdw10;
909 req->cmd.cdw11 = pt->cmd.cdw11;
910 req->cmd.cdw12 = pt->cmd.cdw12;
911 req->cmd.cdw13 = pt->cmd.cdw13;
912 req->cmd.cdw14 = pt->cmd.cdw14;
913 req->cmd.cdw15 = pt->cmd.cdw15;
915 req->cmd.nsid = nsid;
920 mtx = &ctrlr->ns[nsid-1].lock;
923 pt->driver_lock = mtx;
926 nvme_ctrlr_submit_admin_request(ctrlr, req);
928 nvme_ctrlr_submit_io_request(ctrlr, req);
930 mtx_sleep(pt, mtx, PRIBIO, "nvme_pt", 0);
933 pt->driver_lock = NULL;
945 nvme_ctrlr_ioctl(struct cdev *cdev, u_long cmd, caddr_t arg, int flag,
948 struct nvme_controller *ctrlr;
949 struct nvme_pt_command *pt;
951 ctrlr = cdev->si_drv1;
954 case NVME_RESET_CONTROLLER:
955 nvme_ctrlr_reset(ctrlr);
957 case NVME_PASSTHROUGH_CMD:
958 pt = (struct nvme_pt_command *)arg;
959 return (nvme_ctrlr_passthrough_cmd(ctrlr, pt, pt->cmd.nsid,
960 1 /* is_user_buffer */, 1 /* is_admin_cmd */));
968 static struct cdevsw nvme_ctrlr_cdevsw = {
969 .d_version = D_VERSION,
971 .d_ioctl = nvme_ctrlr_ioctl
975 nvme_ctrlr_setup_interrupts(struct nvme_controller *ctrlr)
978 int per_cpu_io_queues;
979 int min_cpus_per_ioq;
980 int num_vectors_requested, num_vectors_allocated;
981 int num_vectors_available;
984 min_cpus_per_ioq = 1;
985 TUNABLE_INT_FETCH("hw.nvme.min_cpus_per_ioq", &min_cpus_per_ioq);
987 if (min_cpus_per_ioq < 1) {
988 min_cpus_per_ioq = 1;
989 } else if (min_cpus_per_ioq > mp_ncpus) {
990 min_cpus_per_ioq = mp_ncpus;
993 per_cpu_io_queues = 1;
994 TUNABLE_INT_FETCH("hw.nvme.per_cpu_io_queues", &per_cpu_io_queues);
996 if (per_cpu_io_queues == 0) {
997 min_cpus_per_ioq = mp_ncpus;
1000 ctrlr->force_intx = 0;
1001 TUNABLE_INT_FETCH("hw.nvme.force_intx", &ctrlr->force_intx);
1004 * FreeBSD currently cannot allocate more than about 190 vectors at
1005 * boot, meaning that systems with high core count and many devices
1006 * requesting per-CPU interrupt vectors will not get their full
1007 * allotment. So first, try to allocate as many as we may need to
1008 * understand what is available, then immediately release them.
1009 * Then figure out how many of those we will actually use, based on
1010 * assigning an equal number of cores to each I/O queue.
1013 /* One vector for per core I/O queue, plus one vector for admin queue. */
1014 num_vectors_available = min(pci_msix_count(dev), mp_ncpus + 1);
1015 if (pci_alloc_msix(dev, &num_vectors_available) != 0) {
1016 num_vectors_available = 0;
1018 pci_release_msi(dev);
1020 if (ctrlr->force_intx || num_vectors_available < 2) {
1021 nvme_ctrlr_configure_intx(ctrlr);
1026 * Do not use all vectors for I/O queues - one must be saved for the
1029 ctrlr->num_cpus_per_ioq = max(min_cpus_per_ioq,
1030 howmany(mp_ncpus, num_vectors_available - 1));
1032 ctrlr->num_io_queues = howmany(mp_ncpus, ctrlr->num_cpus_per_ioq);
1033 num_vectors_requested = ctrlr->num_io_queues + 1;
1034 num_vectors_allocated = num_vectors_requested;
1037 * Now just allocate the number of vectors we need. This should
1038 * succeed, since we previously called pci_alloc_msix()
1039 * successfully returning at least this many vectors, but just to
1040 * be safe, if something goes wrong just revert to INTx.
1042 if (pci_alloc_msix(dev, &num_vectors_allocated) != 0) {
1043 nvme_ctrlr_configure_intx(ctrlr);
1047 if (num_vectors_allocated < num_vectors_requested) {
1048 pci_release_msi(dev);
1049 nvme_ctrlr_configure_intx(ctrlr);
1053 ctrlr->msix_enabled = 1;
1057 nvme_ctrlr_construct(struct nvme_controller *ctrlr, device_t dev)
1059 union cap_lo_register cap_lo;
1060 union cap_hi_register cap_hi;
1061 int status, timeout_period;
1065 mtx_init(&ctrlr->lock, "nvme ctrlr lock", NULL, MTX_DEF);
1067 status = nvme_ctrlr_allocate_bar(ctrlr);
1073 * Software emulators may set the doorbell stride to something
1074 * other than zero, but this driver is not set up to handle that.
1076 cap_hi.raw = nvme_mmio_read_4(ctrlr, cap_hi);
1077 if (cap_hi.bits.dstrd != 0)
1080 ctrlr->min_page_size = 1 << (12 + cap_hi.bits.mpsmin);
1082 /* Get ready timeout value from controller, in units of 500ms. */
1083 cap_lo.raw = nvme_mmio_read_4(ctrlr, cap_lo);
1084 ctrlr->ready_timeout_in_ms = cap_lo.bits.to * 500;
1086 timeout_period = NVME_DEFAULT_TIMEOUT_PERIOD;
1087 TUNABLE_INT_FETCH("hw.nvme.timeout_period", &timeout_period);
1088 timeout_period = min(timeout_period, NVME_MAX_TIMEOUT_PERIOD);
1089 timeout_period = max(timeout_period, NVME_MIN_TIMEOUT_PERIOD);
1090 ctrlr->timeout_period = timeout_period;
1092 nvme_retry_count = NVME_DEFAULT_RETRY_COUNT;
1093 TUNABLE_INT_FETCH("hw.nvme.retry_count", &nvme_retry_count);
1095 ctrlr->enable_aborts = 0;
1096 TUNABLE_INT_FETCH("hw.nvme.enable_aborts", &ctrlr->enable_aborts);
1098 nvme_ctrlr_setup_interrupts(ctrlr);
1100 ctrlr->max_xfer_size = NVME_MAX_XFER_SIZE;
1101 nvme_ctrlr_construct_admin_qpair(ctrlr);
1103 ctrlr->cdev = make_dev(&nvme_ctrlr_cdevsw, device_get_unit(dev),
1104 UID_ROOT, GID_WHEEL, 0600, "nvme%d", device_get_unit(dev));
1106 if (ctrlr->cdev == NULL)
1109 ctrlr->cdev->si_drv1 = (void *)ctrlr;
1111 ctrlr->taskqueue = taskqueue_create("nvme_taskq", M_WAITOK,
1112 taskqueue_thread_enqueue, &ctrlr->taskqueue);
1113 taskqueue_start_threads(&ctrlr->taskqueue, 1, PI_DISK, "nvme taskq");
1115 ctrlr->is_resetting = 0;
1116 ctrlr->is_initialized = 0;
1117 ctrlr->notification_sent = 0;
1118 TASK_INIT(&ctrlr->reset_task, 0, nvme_ctrlr_reset_task, ctrlr);
1120 TASK_INIT(&ctrlr->fail_req_task, 0, nvme_ctrlr_fail_req_task, ctrlr);
1121 STAILQ_INIT(&ctrlr->fail_req);
1122 ctrlr->is_failed = FALSE;
1128 nvme_ctrlr_destruct(struct nvme_controller *ctrlr, device_t dev)
1133 * Notify the controller of a shutdown, even though this is due to
1134 * a driver unload, not a system shutdown (this path is not invoked
1135 * during shutdown). This ensures the controller receives a
1136 * shutdown notification in case the system is shutdown before
1137 * reloading the driver.
1139 nvme_ctrlr_shutdown(ctrlr);
1141 nvme_ctrlr_disable(ctrlr);
1142 taskqueue_free(ctrlr->taskqueue);
1144 for (i = 0; i < NVME_MAX_NAMESPACES; i++)
1145 nvme_ns_destruct(&ctrlr->ns[i]);
1148 destroy_dev(ctrlr->cdev);
1150 for (i = 0; i < ctrlr->num_io_queues; i++) {
1151 nvme_io_qpair_destroy(&ctrlr->ioq[i]);
1154 free(ctrlr->ioq, M_NVME);
1156 nvme_admin_qpair_destroy(&ctrlr->adminq);
1158 if (ctrlr->resource != NULL) {
1159 bus_release_resource(dev, SYS_RES_MEMORY,
1160 ctrlr->resource_id, ctrlr->resource);
1163 if (ctrlr->bar4_resource != NULL) {
1164 bus_release_resource(dev, SYS_RES_MEMORY,
1165 ctrlr->bar4_resource_id, ctrlr->bar4_resource);
1169 bus_teardown_intr(ctrlr->dev, ctrlr->res, ctrlr->tag);
1172 bus_release_resource(ctrlr->dev, SYS_RES_IRQ,
1173 rman_get_rid(ctrlr->res), ctrlr->res);
1175 if (ctrlr->msix_enabled)
1176 pci_release_msi(dev);
1180 nvme_ctrlr_shutdown(struct nvme_controller *ctrlr)
1182 union cc_register cc;
1183 union csts_register csts;
1186 cc.raw = nvme_mmio_read_4(ctrlr, cc);
1187 cc.bits.shn = NVME_SHN_NORMAL;
1188 nvme_mmio_write_4(ctrlr, cc, cc.raw);
1189 csts.raw = nvme_mmio_read_4(ctrlr, csts);
1190 while ((csts.bits.shst != NVME_SHST_COMPLETE) && (ticks++ < 5*hz)) {
1191 pause("nvme shn", 1);
1192 csts.raw = nvme_mmio_read_4(ctrlr, csts);
1194 if (csts.bits.shst != NVME_SHST_COMPLETE)
1195 nvme_printf(ctrlr, "did not complete shutdown within 5 seconds "
1196 "of notification\n");
1200 nvme_ctrlr_submit_admin_request(struct nvme_controller *ctrlr,
1201 struct nvme_request *req)
1204 nvme_qpair_submit_request(&ctrlr->adminq, req);
1208 nvme_ctrlr_submit_io_request(struct nvme_controller *ctrlr,
1209 struct nvme_request *req)
1211 struct nvme_qpair *qpair;
1213 qpair = &ctrlr->ioq[curcpu / ctrlr->num_cpus_per_ioq];
1214 nvme_qpair_submit_request(qpair, req);
1218 nvme_ctrlr_get_device(struct nvme_controller *ctrlr)
1221 return (ctrlr->dev);
1224 const struct nvme_controller_data *
1225 nvme_ctrlr_get_data(struct nvme_controller *ctrlr)
1228 return (&ctrlr->cdata);