2 * Copyright (C) 2012-2016 Intel Corporation
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
39 #include <dev/pci/pcireg.h>
40 #include <dev/pci/pcivar.h>
42 #include "nvme_private.h"
44 static int nvme_pci_probe(device_t);
45 static int nvme_pci_attach(device_t);
46 static int nvme_pci_detach(device_t);
47 static int nvme_pci_suspend(device_t);
48 static int nvme_pci_resume(device_t);
50 static void nvme_ctrlr_setup_interrupts(struct nvme_controller *ctrlr);
52 static device_method_t nvme_pci_methods[] = {
53 /* Device interface */
54 DEVMETHOD(device_probe, nvme_pci_probe),
55 DEVMETHOD(device_attach, nvme_pci_attach),
56 DEVMETHOD(device_detach, nvme_pci_detach),
57 DEVMETHOD(device_suspend, nvme_pci_suspend),
58 DEVMETHOD(device_resume, nvme_pci_resume),
59 DEVMETHOD(device_shutdown, nvme_shutdown),
63 static driver_t nvme_pci_driver = {
66 sizeof(struct nvme_controller),
69 DRIVER_MODULE(nvme, pci, nvme_pci_driver, nvme_devclass, NULL, 0);
79 { 0x01118086, 0, 0, "NVMe Controller" },
80 { IDT32_PCI_ID, 0, 0, "IDT NVMe Controller (32 channel)" },
81 { IDT8_PCI_ID, 0, 0, "IDT NVMe Controller (8 channel)" },
82 { 0x09538086, 1, 0x3702, "DC P3700 SSD" },
83 { 0x09538086, 1, 0x3703, "DC P3700 SSD [2.5\" SFF]" },
84 { 0x09538086, 1, 0x3704, "DC P3500 SSD [Add-in Card]" },
85 { 0x09538086, 1, 0x3705, "DC P3500 SSD [2.5\" SFF]" },
86 { 0x09538086, 1, 0x3709, "DC P3600 SSD [Add-in Card]" },
87 { 0x09538086, 1, 0x370a, "DC P3600 SSD [2.5\" SFF]" },
88 { 0x00031c58, 0, 0, "HGST SN100", QUIRK_DELAY_B4_CHK_RDY },
89 { 0x00231c58, 0, 0, "WDC SN200", QUIRK_DELAY_B4_CHK_RDY },
90 { 0x05401c5f, 0, 0, "Memblaze Pblaze4", QUIRK_DELAY_B4_CHK_RDY },
91 { 0xa821144d, 0, 0, "Samsung PM1725", QUIRK_DELAY_B4_CHK_RDY },
92 { 0xa822144d, 0, 0, "Samsung PM1725a", QUIRK_DELAY_B4_CHK_RDY },
93 { 0x00000000, 0, 0, NULL }
98 nvme_match(uint32_t devid, uint16_t subdevice, struct _pcsid *ep)
100 if (devid != ep->devid)
103 if (!ep->match_subdevice)
106 if (subdevice == ep->subdevice)
113 nvme_pci_probe (device_t device)
115 struct nvme_controller *ctrlr = DEVICE2SOFTC(device);
120 devid = pci_get_devid(device);
121 subdevice = pci_get_subdevice(device);
125 if (nvme_match(devid, subdevice, ep))
130 ctrlr->quirks = ep->quirks;
133 device_set_desc(device, ep->desc);
134 return (BUS_PROBE_DEFAULT);
137 #if defined(PCIS_STORAGE_NVM)
138 if (pci_get_class(device) == PCIC_STORAGE &&
139 pci_get_subclass(device) == PCIS_STORAGE_NVM &&
140 pci_get_progif(device) == PCIP_STORAGE_NVM_ENTERPRISE_NVMHCI_1_0) {
141 device_set_desc(device, "Generic NVMe Device");
142 return (BUS_PROBE_GENERIC);
150 nvme_ctrlr_allocate_bar(struct nvme_controller *ctrlr)
153 ctrlr->resource_id = PCIR_BAR(0);
155 ctrlr->resource = bus_alloc_resource_any(ctrlr->dev, SYS_RES_MEMORY,
156 &ctrlr->resource_id, RF_ACTIVE);
158 if(ctrlr->resource == NULL) {
159 nvme_printf(ctrlr, "unable to allocate pci resource\n");
163 ctrlr->bus_tag = rman_get_bustag(ctrlr->resource);
164 ctrlr->bus_handle = rman_get_bushandle(ctrlr->resource);
165 ctrlr->regs = (struct nvme_registers *)ctrlr->bus_handle;
168 * The NVMe spec allows for the MSI-X table to be placed behind
169 * BAR 4/5, separate from the control/doorbell registers. Always
170 * try to map this bar, because it must be mapped prior to calling
171 * pci_alloc_msix(). If the table isn't behind BAR 4/5,
172 * bus_alloc_resource() will just return NULL which is OK.
174 ctrlr->bar4_resource_id = PCIR_BAR(4);
175 ctrlr->bar4_resource = bus_alloc_resource_any(ctrlr->dev, SYS_RES_MEMORY,
176 &ctrlr->bar4_resource_id, RF_ACTIVE);
182 nvme_pci_attach(device_t dev)
184 struct nvme_controller*ctrlr = DEVICE2SOFTC(dev);
188 status = nvme_ctrlr_allocate_bar(ctrlr);
191 pci_enable_busmaster(dev);
192 nvme_ctrlr_setup_interrupts(ctrlr);
193 return nvme_attach(dev);
195 if (ctrlr->resource != NULL) {
196 bus_release_resource(dev, SYS_RES_MEMORY,
197 ctrlr->resource_id, ctrlr->resource);
200 if (ctrlr->bar4_resource != NULL) {
201 bus_release_resource(dev, SYS_RES_MEMORY,
202 ctrlr->bar4_resource_id, ctrlr->bar4_resource);
206 bus_teardown_intr(dev, ctrlr->res, ctrlr->tag);
209 bus_release_resource(dev, SYS_RES_IRQ,
210 rman_get_rid(ctrlr->res), ctrlr->res);
212 if (ctrlr->msix_enabled)
213 pci_release_msi(dev);
219 nvme_pci_detach(device_t dev)
221 struct nvme_controller*ctrlr = DEVICE2SOFTC(dev);
224 rv = nvme_detach(dev);
225 if (ctrlr->msix_enabled)
226 pci_release_msi(dev);
227 pci_disable_busmaster(dev);
232 nvme_ctrlr_configure_intx(struct nvme_controller *ctrlr)
235 ctrlr->msix_enabled = 0;
236 ctrlr->num_io_queues = 1;
238 ctrlr->res = bus_alloc_resource_any(ctrlr->dev, SYS_RES_IRQ,
239 &ctrlr->rid, RF_SHAREABLE | RF_ACTIVE);
241 if (ctrlr->res == NULL) {
242 nvme_printf(ctrlr, "unable to allocate shared IRQ\n");
246 bus_setup_intr(ctrlr->dev, ctrlr->res,
247 INTR_TYPE_MISC | INTR_MPSAFE, NULL, nvme_ctrlr_intx_handler,
250 if (ctrlr->tag == NULL) {
251 nvme_printf(ctrlr, "unable to setup intx handler\n");
259 nvme_ctrlr_setup_interrupts(struct nvme_controller *ctrlr)
262 int force_intx, num_io_queues, per_cpu_io_queues;
263 int min_cpus_per_ioq;
264 int num_vectors_requested, num_vectors_allocated;
269 TUNABLE_INT_FETCH("hw.nvme.force_intx", &force_intx);
270 if (force_intx || pci_msix_count(dev) < 2) {
271 nvme_ctrlr_configure_intx(ctrlr);
275 num_io_queues = mp_ncpus;
276 TUNABLE_INT_FETCH("hw.nvme.num_io_queues", &num_io_queues);
277 if (num_io_queues < 1 || num_io_queues > mp_ncpus)
278 num_io_queues = mp_ncpus;
280 per_cpu_io_queues = 1;
281 TUNABLE_INT_FETCH("hw.nvme.per_cpu_io_queues", &per_cpu_io_queues);
282 if (per_cpu_io_queues == 0)
285 min_cpus_per_ioq = smp_threads_per_core;
286 TUNABLE_INT_FETCH("hw.nvme.min_cpus_per_ioq", &min_cpus_per_ioq);
287 if (min_cpus_per_ioq > 1) {
288 num_io_queues = min(num_io_queues,
289 max(1, mp_ncpus / min_cpus_per_ioq));
292 num_io_queues = min(num_io_queues, pci_msix_count(dev) - 1);
295 if (num_io_queues > vm_ndomains)
296 num_io_queues -= num_io_queues % vm_ndomains;
297 /* One vector for per core I/O queue, plus one vector for admin queue. */
298 num_vectors_requested = num_io_queues + 1;
299 num_vectors_allocated = num_vectors_requested;
300 if (pci_alloc_msix(dev, &num_vectors_allocated) != 0) {
301 nvme_ctrlr_configure_intx(ctrlr);
304 if (num_vectors_allocated < 2) {
305 pci_release_msi(dev);
306 nvme_ctrlr_configure_intx(ctrlr);
309 if (num_vectors_allocated != num_vectors_requested) {
310 pci_release_msi(dev);
311 num_io_queues = num_vectors_allocated - 1;
315 ctrlr->msix_enabled = 1;
316 ctrlr->num_io_queues = num_io_queues;
320 nvme_pci_suspend(device_t dev)
322 struct nvme_controller *ctrlr;
324 ctrlr = DEVICE2SOFTC(dev);
325 return (nvme_ctrlr_suspend(ctrlr));
329 nvme_pci_resume(device_t dev)
331 struct nvme_controller *ctrlr;
333 ctrlr = DEVICE2SOFTC(dev);
334 return (nvme_ctrlr_resume(ctrlr));