2 * Copyright (C) 2012-2016 Intel Corporation
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
39 #include <dev/pci/pcireg.h>
40 #include <dev/pci/pcivar.h>
42 #include "nvme_private.h"
44 static int nvme_pci_probe(device_t);
45 static int nvme_pci_attach(device_t);
46 static int nvme_pci_detach(device_t);
47 static int nvme_pci_suspend(device_t);
48 static int nvme_pci_resume(device_t);
50 static int nvme_ctrlr_setup_interrupts(struct nvme_controller *ctrlr);
52 static device_method_t nvme_pci_methods[] = {
53 /* Device interface */
54 DEVMETHOD(device_probe, nvme_pci_probe),
55 DEVMETHOD(device_attach, nvme_pci_attach),
56 DEVMETHOD(device_detach, nvme_pci_detach),
57 DEVMETHOD(device_suspend, nvme_pci_suspend),
58 DEVMETHOD(device_resume, nvme_pci_resume),
59 DEVMETHOD(device_shutdown, nvme_shutdown),
63 static driver_t nvme_pci_driver = {
66 sizeof(struct nvme_controller),
69 DRIVER_MODULE(nvme, pci, nvme_pci_driver, nvme_devclass, NULL, 0);
79 { 0x01118086, 0, 0, "NVMe Controller" },
80 { IDT32_PCI_ID, 0, 0, "IDT NVMe Controller (32 channel)" },
81 { IDT8_PCI_ID, 0, 0, "IDT NVMe Controller (8 channel)" },
82 { 0x09538086, 1, 0x3702, "DC P3700 SSD" },
83 { 0x09538086, 1, 0x3703, "DC P3700 SSD [2.5\" SFF]" },
84 { 0x09538086, 1, 0x3704, "DC P3500 SSD [Add-in Card]" },
85 { 0x09538086, 1, 0x3705, "DC P3500 SSD [2.5\" SFF]" },
86 { 0x09538086, 1, 0x3709, "DC P3600 SSD [Add-in Card]" },
87 { 0x09538086, 1, 0x370a, "DC P3600 SSD [2.5\" SFF]" },
88 { 0x00031c58, 0, 0, "HGST SN100", QUIRK_DELAY_B4_CHK_RDY },
89 { 0x00231c58, 0, 0, "WDC SN200", QUIRK_DELAY_B4_CHK_RDY },
90 { 0x05401c5f, 0, 0, "Memblaze Pblaze4", QUIRK_DELAY_B4_CHK_RDY },
91 { 0xa821144d, 0, 0, "Samsung PM1725", QUIRK_DELAY_B4_CHK_RDY },
92 { 0xa822144d, 0, 0, "Samsung PM1725a", QUIRK_DELAY_B4_CHK_RDY },
93 { 0x00000000, 0, 0, NULL }
97 nvme_match(uint32_t devid, uint16_t subdevice, struct _pcsid *ep)
99 if (devid != ep->devid)
102 if (!ep->match_subdevice)
105 if (subdevice == ep->subdevice)
112 nvme_pci_probe (device_t device)
114 struct nvme_controller *ctrlr = DEVICE2SOFTC(device);
119 devid = pci_get_devid(device);
120 subdevice = pci_get_subdevice(device);
124 if (nvme_match(devid, subdevice, ep))
129 ctrlr->quirks = ep->quirks;
132 device_set_desc(device, ep->desc);
133 return (BUS_PROBE_DEFAULT);
136 #if defined(PCIS_STORAGE_NVM)
137 if (pci_get_class(device) == PCIC_STORAGE &&
138 pci_get_subclass(device) == PCIS_STORAGE_NVM &&
139 pci_get_progif(device) == PCIP_STORAGE_NVM_ENTERPRISE_NVMHCI_1_0) {
140 device_set_desc(device, "Generic NVMe Device");
141 return (BUS_PROBE_GENERIC);
149 nvme_ctrlr_allocate_bar(struct nvme_controller *ctrlr)
152 ctrlr->resource_id = PCIR_BAR(0);
154 ctrlr->resource = bus_alloc_resource_any(ctrlr->dev, SYS_RES_MEMORY,
155 &ctrlr->resource_id, RF_ACTIVE);
157 if(ctrlr->resource == NULL) {
158 nvme_printf(ctrlr, "unable to allocate pci resource\n");
162 ctrlr->bus_tag = rman_get_bustag(ctrlr->resource);
163 ctrlr->bus_handle = rman_get_bushandle(ctrlr->resource);
164 ctrlr->regs = (struct nvme_registers *)ctrlr->bus_handle;
167 * The NVMe spec allows for the MSI-X table to be placed behind
168 * BAR 4/5, separate from the control/doorbell registers. Always
169 * try to map this bar, because it must be mapped prior to calling
170 * pci_alloc_msix(). If the table isn't behind BAR 4/5,
171 * bus_alloc_resource() will just return NULL which is OK.
173 ctrlr->bar4_resource_id = PCIR_BAR(4);
174 ctrlr->bar4_resource = bus_alloc_resource_any(ctrlr->dev, SYS_RES_MEMORY,
175 &ctrlr->bar4_resource_id, RF_ACTIVE);
181 nvme_pci_attach(device_t dev)
183 struct nvme_controller*ctrlr = DEVICE2SOFTC(dev);
187 status = nvme_ctrlr_allocate_bar(ctrlr);
190 pci_enable_busmaster(dev);
191 status = nvme_ctrlr_setup_interrupts(ctrlr);
194 return nvme_attach(dev);
196 if (ctrlr->resource != NULL) {
197 bus_release_resource(dev, SYS_RES_MEMORY,
198 ctrlr->resource_id, ctrlr->resource);
201 if (ctrlr->bar4_resource != NULL) {
202 bus_release_resource(dev, SYS_RES_MEMORY,
203 ctrlr->bar4_resource_id, ctrlr->bar4_resource);
207 bus_teardown_intr(dev, ctrlr->res, ctrlr->tag);
210 bus_release_resource(dev, SYS_RES_IRQ,
211 rman_get_rid(ctrlr->res), ctrlr->res);
213 if (ctrlr->msi_count > 0)
214 pci_release_msi(dev);
220 nvme_pci_detach(device_t dev)
222 struct nvme_controller*ctrlr = DEVICE2SOFTC(dev);
225 rv = nvme_detach(dev);
226 if (ctrlr->msi_count > 0)
227 pci_release_msi(dev);
228 pci_disable_busmaster(dev);
233 nvme_ctrlr_setup_shared(struct nvme_controller *ctrlr, int rid)
237 ctrlr->num_io_queues = 1;
239 ctrlr->res = bus_alloc_resource_any(ctrlr->dev, SYS_RES_IRQ,
240 &ctrlr->rid, RF_SHAREABLE | RF_ACTIVE);
241 if (ctrlr->res == NULL) {
242 nvme_printf(ctrlr, "unable to allocate shared interrupt\n");
246 error = bus_setup_intr(ctrlr->dev, ctrlr->res,
247 INTR_TYPE_MISC | INTR_MPSAFE, NULL, nvme_ctrlr_shared_handler,
250 nvme_printf(ctrlr, "unable to setup shared interrupt\n");
258 nvme_ctrlr_setup_interrupts(struct nvme_controller *ctrlr)
261 int force_intx, num_io_queues, per_cpu_io_queues;
262 int min_cpus_per_ioq;
263 int num_vectors_requested;
268 TUNABLE_INT_FETCH("hw.nvme.force_intx", &force_intx);
270 return (nvme_ctrlr_setup_shared(ctrlr, 0));
272 if (pci_msix_count(dev) == 0)
276 * Try to allocate one MSI-X per core for I/O queues, plus one
277 * for admin queue, but accept single shared MSI-X if have to.
278 * Fall back to MSI if can't get any MSI-X.
280 num_io_queues = mp_ncpus;
281 TUNABLE_INT_FETCH("hw.nvme.num_io_queues", &num_io_queues);
282 if (num_io_queues < 1 || num_io_queues > mp_ncpus)
283 num_io_queues = mp_ncpus;
285 per_cpu_io_queues = 1;
286 TUNABLE_INT_FETCH("hw.nvme.per_cpu_io_queues", &per_cpu_io_queues);
287 if (per_cpu_io_queues == 0)
290 min_cpus_per_ioq = smp_threads_per_core;
291 TUNABLE_INT_FETCH("hw.nvme.min_cpus_per_ioq", &min_cpus_per_ioq);
292 if (min_cpus_per_ioq > 1) {
293 num_io_queues = min(num_io_queues,
294 max(1, mp_ncpus / min_cpus_per_ioq));
297 num_io_queues = min(num_io_queues, max(1, pci_msix_count(dev) - 1));
300 if (num_io_queues > vm_ndomains)
301 num_io_queues -= num_io_queues % vm_ndomains;
302 num_vectors_requested = min(num_io_queues + 1, pci_msix_count(dev));
303 ctrlr->msi_count = num_vectors_requested;
304 if (pci_alloc_msix(dev, &ctrlr->msi_count) != 0) {
305 nvme_printf(ctrlr, "unable to allocate MSI-X\n");
306 ctrlr->msi_count = 0;
309 if (ctrlr->msi_count == 1)
310 return (nvme_ctrlr_setup_shared(ctrlr, 1));
311 if (ctrlr->msi_count != num_vectors_requested) {
312 pci_release_msi(dev);
313 num_io_queues = ctrlr->msi_count - 1;
317 ctrlr->num_io_queues = num_io_queues;
322 * Try to allocate 2 MSIs (admin and I/O queues), but accept single
323 * shared if have to. Fall back to INTx if can't get any MSI.
325 ctrlr->msi_count = min(pci_msi_count(dev), 2);
326 if (ctrlr->msi_count > 0) {
327 if (pci_alloc_msi(dev, &ctrlr->msi_count) != 0) {
328 nvme_printf(ctrlr, "unable to allocate MSI\n");
329 ctrlr->msi_count = 0;
330 } else if (ctrlr->msi_count == 2) {
331 ctrlr->num_io_queues = 1;
335 return (nvme_ctrlr_setup_shared(ctrlr, ctrlr->msi_count > 0 ? 1 : 0));
339 nvme_pci_suspend(device_t dev)
341 struct nvme_controller *ctrlr;
343 ctrlr = DEVICE2SOFTC(dev);
344 return (nvme_ctrlr_suspend(ctrlr));
348 nvme_pci_resume(device_t dev)
350 struct nvme_controller *ctrlr;
352 ctrlr = DEVICE2SOFTC(dev);
353 return (nvme_ctrlr_resume(ctrlr));