sys/dev/nvme/nvme_private.h

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (C) 2012-2014 Intel Corporation
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  *
  28  * $FreeBSD$
  29  */
  30
  31 #ifndef __NVME_PRIVATE_H__
  32 #define __NVME_PRIVATE_H__
  33
  34 #include <sys/param.h>
  35 #include <sys/bio.h>
  36 #include <sys/bus.h>
  37 #include <sys/kernel.h>
  38 #include <sys/lock.h>
  39 #include <sys/malloc.h>
  40 #include <sys/mutex.h>
  41 #include <sys/rman.h>
  42 #include <sys/systm.h>
  43 #include <sys/taskqueue.h>
  44
  45 #include <vm/uma.h>
  46
  47 #include <machine/bus.h>
  48
  49 #include "nvme.h"
  50
  51 #define DEVICE2SOFTC(dev) ((struct nvme_controller *) device_get_softc(dev))
  52
  53 MALLOC_DECLARE(M_NVME);
  54
  55 #define IDT32_PCI_ID            0x80d0111d /* 32 channel board */
  56 #define IDT8_PCI_ID             0x80d2111d /* 8 channel board */
  57
  58 /*
  59  * For commands requiring more than 2 PRP entries, one PRP will be
  60  *  embedded in the command (prp1), and the rest of the PRP entries
  61  *  will be in a list pointed to by the command (prp2).  This means
  62  *  that real max number of PRP entries we support is 32+1, which
  63  *  results in a max xfer size of 32*PAGE_SIZE.
  64  */
  65 #define NVME_MAX_PRP_LIST_ENTRIES       (NVME_MAX_XFER_SIZE / PAGE_SIZE)
  66
  67 #define NVME_ADMIN_TRACKERS     (16)
  68 #define NVME_ADMIN_ENTRIES      (128)
  69 /* min and max are defined in admin queue attributes section of spec */
  70 #define NVME_MIN_ADMIN_ENTRIES  (2)
  71 #define NVME_MAX_ADMIN_ENTRIES  (4096)
  72
  73 /*
  74  * NVME_IO_ENTRIES defines the size of an I/O qpair's submission and completion
  75  *  queues, while NVME_IO_TRACKERS defines the maximum number of I/O that we
  76  *  will allow outstanding on an I/O qpair at any time.  The only advantage in
  77  *  having IO_ENTRIES > IO_TRACKERS is for debugging purposes - when dumping
  78  *  the contents of the submission and completion queues, it will show a longer
  79  *  history of data.
  80  */
  81 #define NVME_IO_ENTRIES         (256)
  82 #define NVME_IO_TRACKERS        (128)
  83 #define NVME_MIN_IO_TRACKERS    (4)
  84 #define NVME_MAX_IO_TRACKERS    (1024)
  85
  86 /*
  87  * NVME_MAX_IO_ENTRIES is not defined, since it is specified in CC.MQES
  88  *  for each controller.
  89  */
  90
  91 #define NVME_INT_COAL_TIME      (0)     /* disabled */
  92 #define NVME_INT_COAL_THRESHOLD (0)     /* 0-based */
  93
  94 #define NVME_MAX_NAMESPACES     (16)
  95 #define NVME_MAX_CONSUMERS      (2)
  96 #define NVME_MAX_ASYNC_EVENTS   (8)
  97
  98 #define NVME_DEFAULT_TIMEOUT_PERIOD     (30)    /* in seconds */
  99 #define NVME_MIN_TIMEOUT_PERIOD         (5)
 100 #define NVME_MAX_TIMEOUT_PERIOD         (120)
 101
 102 #define NVME_DEFAULT_RETRY_COUNT        (4)
 103
 104 /* Maximum log page size to fetch for AERs. */
 105 #define NVME_MAX_AER_LOG_SIZE           (4096)
 106
 107 /*
 108  * Define CACHE_LINE_SIZE here for older FreeBSD versions that do not define
 109  *  it.
 110  */
 111 #ifndef CACHE_LINE_SIZE
 112 #define CACHE_LINE_SIZE         (64)
 113 #endif
 114
 115 extern uma_zone_t       nvme_request_zone;
 116 extern int32_t          nvme_retry_count;
 117
 118 struct nvme_completion_poll_status {
 119
 120         struct nvme_completion  cpl;
 121         int                     done;
 122 };
 123
 124 #define NVME_REQUEST_VADDR      1
 125 #define NVME_REQUEST_NULL       2 /* For requests with no payload. */
 126 #define NVME_REQUEST_UIO        3
 127 #define NVME_REQUEST_BIO        4
 128 #define NVME_REQUEST_CCB        5
 129
 130 struct nvme_request {
 131
 132         struct nvme_command             cmd;
 133         struct nvme_qpair               *qpair;
 134         union {
 135                 void                    *payload;
 136                 struct bio              *bio;
 137         } u;
 138         uint32_t                        type;
 139         uint32_t                        payload_size;
 140         boolean_t                       timeout;
 141         nvme_cb_fn_t                    cb_fn;
 142         void                            *cb_arg;
 143         int32_t                         retries;
 144         STAILQ_ENTRY(nvme_request)      stailq;
 145 };
 146
 147 struct nvme_async_event_request {
 148
 149         struct nvme_controller          *ctrlr;
 150         struct nvme_request             *req;
 151         struct nvme_completion          cpl;
 152         uint32_t                        log_page_id;
 153         uint32_t                        log_page_size;
 154         uint8_t                         log_page_buffer[NVME_MAX_AER_LOG_SIZE];
 155 };
 156
 157 struct nvme_tracker {
 158
 159         TAILQ_ENTRY(nvme_tracker)       tailq;
 160         struct nvme_request             *req;
 161         struct nvme_qpair               *qpair;
 162         struct callout                  timer;
 163         bus_dmamap_t                    payload_dma_map;
 164         uint16_t                        cid;
 165
 166         uint64_t                        *prp;
 167         bus_addr_t                      prp_bus_addr;
 168 };
 169
 170 struct nvme_qpair {
 171
 172         struct nvme_controller  *ctrlr;
 173         uint32_t                id;
 174         uint32_t                phase;
 175
 176         uint16_t                vector;
 177         int                     rid;
 178         struct resource         *res;
 179         void                    *tag;
 180
 181         uint32_t                num_entries;
 182         uint32_t                num_trackers;
 183         uint32_t                sq_tdbl_off;
 184         uint32_t                cq_hdbl_off;
 185
 186         uint32_t                sq_head;
 187         uint32_t                sq_tail;
 188         uint32_t                cq_head;
 189
 190         int64_t                 num_cmds;
 191         int64_t                 num_intr_handler_calls;
 192
 193         struct nvme_command     *cmd;
 194         struct nvme_completion  *cpl;
 195
 196         bus_dma_tag_t           dma_tag;
 197         bus_dma_tag_t           dma_tag_payload;
 198
 199         bus_dmamap_t            queuemem_map;
 200         uint64_t                cmd_bus_addr;
 201         uint64_t                cpl_bus_addr;
 202
 203         TAILQ_HEAD(, nvme_tracker)      free_tr;
 204         TAILQ_HEAD(, nvme_tracker)      outstanding_tr;
 205         STAILQ_HEAD(, nvme_request)     queued_req;
 206
 207         struct nvme_tracker     **act_tr;
 208
 209         boolean_t               is_enabled;
 210
 211         struct mtx              lock __aligned(CACHE_LINE_SIZE);
 212
 213 } __aligned(CACHE_LINE_SIZE);
 214
 215 struct nvme_namespace {
 216
 217         struct nvme_controller          *ctrlr;
 218         struct nvme_namespace_data      data;
 219         uint32_t                        id;
 220         uint32_t                        flags;
 221         struct cdev                     *cdev;
 222         void                            *cons_cookie[NVME_MAX_CONSUMERS];
 223         uint32_t                        stripesize;
 224         struct mtx                      lock;
 225 };
 226
 227 /*
 228  * One of these per allocated PCI device.
 229  */
 230 struct nvme_controller {
 231
 232         device_t                dev;
 233
 234         struct mtx              lock;
 235
 236         uint32_t                ready_timeout_in_ms;
 237         uint32_t                quirks;
 238 #define QUIRK_DELAY_B4_CHK_RDY  1               /* Can't touch MMIO on disable */
 239 #define QUIRK_DISABLE_TIMEOUT   2               /* Disable broken completion timeout feature */
 240
 241         bus_space_tag_t         bus_tag;
 242         bus_space_handle_t      bus_handle;
 243         int                     resource_id;
 244         struct resource         *resource;
 245
 246         /*
 247          * The NVMe spec allows for the MSI-X table to be placed in BAR 4/5,
 248          *  separate from the control registers which are in BAR 0/1.  These
 249          *  members track the mapping of BAR 4/5 for that reason.
 250          */
 251         int                     bar4_resource_id;
 252         struct resource         *bar4_resource;
 253
 254         uint32_t                msix_enabled;
 255         uint32_t                force_intx;
 256         uint32_t                enable_aborts;
 257
 258         uint32_t                num_io_queues;
 259         uint32_t                num_cpus_per_ioq;
 260         uint32_t                max_hw_pend_io;
 261
 262         /* Fields for tracking progress during controller initialization. */
 263         struct intr_config_hook config_hook;
 264         uint32_t                ns_identified;
 265         uint32_t                queues_created;
 266
 267         struct task             reset_task;
 268         struct task             fail_req_task;
 269         struct taskqueue        *taskqueue;
 270
 271         /* For shared legacy interrupt. */
 272         int                     rid;
 273         struct resource         *res;
 274         void                    *tag;
 275
 276         bus_dma_tag_t           hw_desc_tag;
 277         bus_dmamap_t            hw_desc_map;
 278
 279         /** maximum i/o size in bytes */
 280         uint32_t                max_xfer_size;
 281
 282         /** minimum page size supported by this controller in bytes */
 283         uint32_t                min_page_size;
 284
 285         /** interrupt coalescing time period (in microseconds) */
 286         uint32_t                int_coal_time;
 287
 288         /** interrupt coalescing threshold */
 289         uint32_t                int_coal_threshold;
 290
 291         /** timeout period in seconds */
 292         uint32_t                timeout_period;
 293
 294         struct nvme_qpair       adminq;
 295         struct nvme_qpair       *ioq;
 296
 297         struct nvme_registers           *regs;
 298
 299         struct nvme_controller_data     cdata;
 300         struct nvme_namespace           ns[NVME_MAX_NAMESPACES];
 301
 302         struct cdev                     *cdev;
 303
 304         /** bit mask of event types currently enabled for async events */
 305         uint32_t                        async_event_config;
 306
 307         uint32_t                        num_aers;
 308         struct nvme_async_event_request aer[NVME_MAX_ASYNC_EVENTS];
 309
 310         void                            *cons_cookie[NVME_MAX_CONSUMERS];
 311
 312         uint32_t                        is_resetting;
 313         uint32_t                        is_initialized;
 314         uint32_t                        notification_sent;
 315
 316         boolean_t                       is_failed;
 317         STAILQ_HEAD(, nvme_request)     fail_req;
 318 };
 319
 320 #define nvme_mmio_offsetof(reg)                                                \
 321         offsetof(struct nvme_registers, reg)
 322
 323 #define nvme_mmio_read_4(sc, reg)                                              \
 324         bus_space_read_4((sc)->bus_tag, (sc)->bus_handle,                      \
 325             nvme_mmio_offsetof(reg))
 326
 327 #define nvme_mmio_write_4(sc, reg, val)                                        \
 328         bus_space_write_4((sc)->bus_tag, (sc)->bus_handle,                     \
 329             nvme_mmio_offsetof(reg), val)
 330
 331 #define nvme_mmio_write_8(sc, reg, val)                                        \
 332         do {                                                                   \
 333                 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle,             \
 334                     nvme_mmio_offsetof(reg), val & 0xFFFFFFFF);                \
 335                 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle,             \
 336                     nvme_mmio_offsetof(reg)+4,                                 \
 337                     (val & 0xFFFFFFFF00000000ULL) >> 32);                      \
 338         } while (0);
 339
 340 #define nvme_printf(ctrlr, fmt, args...)        \
 341     device_printf(ctrlr->dev, fmt, ##args)
 342
 343 void    nvme_ns_test(struct nvme_namespace *ns, u_long cmd, caddr_t arg);
 344
 345 void    nvme_ctrlr_cmd_identify_controller(struct nvme_controller *ctrlr,
 346                                            void *payload,
 347                                            nvme_cb_fn_t cb_fn, void *cb_arg);
 348 void    nvme_ctrlr_cmd_identify_namespace(struct nvme_controller *ctrlr,
 349                                           uint32_t nsid, void *payload,
 350                                           nvme_cb_fn_t cb_fn, void *cb_arg);
 351 void    nvme_ctrlr_cmd_set_interrupt_coalescing(struct nvme_controller *ctrlr,
 352                                                 uint32_t microseconds,
 353                                                 uint32_t threshold,
 354                                                 nvme_cb_fn_t cb_fn,
 355                                                 void *cb_arg);
 356 void    nvme_ctrlr_cmd_get_error_page(struct nvme_controller *ctrlr,
 357                                       struct nvme_error_information_entry *payload,
 358                                       uint32_t num_entries, /* 0 = max */
 359                                       nvme_cb_fn_t cb_fn,
 360                                       void *cb_arg);
 361 void    nvme_ctrlr_cmd_get_health_information_page(struct nvme_controller *ctrlr,
 362                                                    uint32_t nsid,
 363                                                    struct nvme_health_information_page *payload,
 364                                                    nvme_cb_fn_t cb_fn,
 365                                                    void *cb_arg);
 366 void    nvme_ctrlr_cmd_get_firmware_page(struct nvme_controller *ctrlr,
 367                                          struct nvme_firmware_page *payload,
 368                                          nvme_cb_fn_t cb_fn,
 369                                          void *cb_arg);
 370 void    nvme_ctrlr_cmd_create_io_cq(struct nvme_controller *ctrlr,
 371                                     struct nvme_qpair *io_que, uint16_t vector,
 372                                     nvme_cb_fn_t cb_fn, void *cb_arg);
 373 void    nvme_ctrlr_cmd_create_io_sq(struct nvme_controller *ctrlr,
 374                                     struct nvme_qpair *io_que,
 375                                     nvme_cb_fn_t cb_fn, void *cb_arg);
 376 void    nvme_ctrlr_cmd_delete_io_cq(struct nvme_controller *ctrlr,
 377                                     struct nvme_qpair *io_que,
 378                                     nvme_cb_fn_t cb_fn, void *cb_arg);
 379 void    nvme_ctrlr_cmd_delete_io_sq(struct nvme_controller *ctrlr,
 380                                     struct nvme_qpair *io_que,
 381                                     nvme_cb_fn_t cb_fn, void *cb_arg);
 382 void    nvme_ctrlr_cmd_set_num_queues(struct nvme_controller *ctrlr,
 383                                       uint32_t num_queues, nvme_cb_fn_t cb_fn,
 384                                       void *cb_arg);
 385 void    nvme_ctrlr_cmd_set_async_event_config(struct nvme_controller *ctrlr,
 386                                               uint32_t state,
 387                                               nvme_cb_fn_t cb_fn, void *cb_arg);
 388 void    nvme_ctrlr_cmd_abort(struct nvme_controller *ctrlr, uint16_t cid,
 389                              uint16_t sqid, nvme_cb_fn_t cb_fn, void *cb_arg);
 390
 391 void    nvme_completion_poll_cb(void *arg, const struct nvme_completion *cpl);
 392
 393 int     nvme_ctrlr_construct(struct nvme_controller *ctrlr, device_t dev);
 394 void    nvme_ctrlr_destruct(struct nvme_controller *ctrlr, device_t dev);
 395 void    nvme_ctrlr_shutdown(struct nvme_controller *ctrlr);
 396 int     nvme_ctrlr_hw_reset(struct nvme_controller *ctrlr);
 397 void    nvme_ctrlr_reset(struct nvme_controller *ctrlr);
 398 /* ctrlr defined as void * to allow use with config_intrhook. */
 399 void    nvme_ctrlr_start_config_hook(void *ctrlr_arg);
 400 void    nvme_ctrlr_submit_admin_request(struct nvme_controller *ctrlr,
 401                                         struct nvme_request *req);
 402 void    nvme_ctrlr_submit_io_request(struct nvme_controller *ctrlr,
 403                                      struct nvme_request *req);
 404 void    nvme_ctrlr_post_failed_request(struct nvme_controller *ctrlr,
 405                                        struct nvme_request *req);
 406
 407 int     nvme_qpair_construct(struct nvme_qpair *qpair, uint32_t id,
 408                              uint16_t vector, uint32_t num_entries,
 409                              uint32_t num_trackers,
 410                              struct nvme_controller *ctrlr);
 411 void    nvme_qpair_submit_tracker(struct nvme_qpair *qpair,
 412                                   struct nvme_tracker *tr);
 413 bool    nvme_qpair_process_completions(struct nvme_qpair *qpair);
 414 void    nvme_qpair_submit_request(struct nvme_qpair *qpair,
 415                                   struct nvme_request *req);
 416 void    nvme_qpair_reset(struct nvme_qpair *qpair);
 417 void    nvme_qpair_fail(struct nvme_qpair *qpair);
 418 void    nvme_qpair_manual_complete_request(struct nvme_qpair *qpair,
 419                                            struct nvme_request *req,
 420                                            uint32_t sct, uint32_t sc);
 421
 422 void    nvme_admin_qpair_enable(struct nvme_qpair *qpair);
 423 void    nvme_admin_qpair_disable(struct nvme_qpair *qpair);
 424 void    nvme_admin_qpair_destroy(struct nvme_qpair *qpair);
 425
 426 void    nvme_io_qpair_enable(struct nvme_qpair *qpair);
 427 void    nvme_io_qpair_disable(struct nvme_qpair *qpair);
 428 void    nvme_io_qpair_destroy(struct nvme_qpair *qpair);
 429
 430 int     nvme_ns_construct(struct nvme_namespace *ns, uint32_t id,
 431                           struct nvme_controller *ctrlr);
 432 void    nvme_ns_destruct(struct nvme_namespace *ns);
 433
 434 void    nvme_sysctl_initialize_ctrlr(struct nvme_controller *ctrlr);
 435
 436 void    nvme_dump_command(struct nvme_command *cmd);
 437 void    nvme_dump_completion(struct nvme_completion *cpl);
 438
 439 static __inline void
 440 nvme_single_map(void *arg, bus_dma_segment_t *seg, int nseg, int error)
 441 {
 442         uint64_t *bus_addr = (uint64_t *)arg;
 443
 444         if (error != 0)
 445                 printf("nvme_single_map err %d\n", error);
 446         *bus_addr = seg[0].ds_addr;
 447 }
 448
 449 static __inline struct nvme_request *
 450 _nvme_allocate_request(nvme_cb_fn_t cb_fn, void *cb_arg)
 451 {
 452         struct nvme_request *req;
 453
 454         req = uma_zalloc(nvme_request_zone, M_NOWAIT | M_ZERO);
 455         if (req != NULL) {
 456                 req->cb_fn = cb_fn;
 457                 req->cb_arg = cb_arg;
 458                 req->timeout = TRUE;
 459         }
 460         return (req);
 461 }
 462
 463 static __inline struct nvme_request *
 464 nvme_allocate_request_vaddr(void *payload, uint32_t payload_size,
 465     nvme_cb_fn_t cb_fn, void *cb_arg)
 466 {
 467         struct nvme_request *req;
 468
 469         req = _nvme_allocate_request(cb_fn, cb_arg);
 470         if (req != NULL) {
 471                 req->type = NVME_REQUEST_VADDR;
 472                 req->u.payload = payload;
 473                 req->payload_size = payload_size;
 474         }
 475         return (req);
 476 }
 477
 478 static __inline struct nvme_request *
 479 nvme_allocate_request_null(nvme_cb_fn_t cb_fn, void *cb_arg)
 480 {
 481         struct nvme_request *req;
 482
 483         req = _nvme_allocate_request(cb_fn, cb_arg);
 484         if (req != NULL)
 485                 req->type = NVME_REQUEST_NULL;
 486         return (req);
 487 }
 488
 489 static __inline struct nvme_request *
 490 nvme_allocate_request_bio(struct bio *bio, nvme_cb_fn_t cb_fn, void *cb_arg)
 491 {
 492         struct nvme_request *req;
 493
 494         req = _nvme_allocate_request(cb_fn, cb_arg);
 495         if (req != NULL) {
 496                 req->type = NVME_REQUEST_BIO;
 497                 req->u.bio = bio;
 498         }
 499         return (req);
 500 }
 501
 502 static __inline struct nvme_request *
 503 nvme_allocate_request_ccb(union ccb *ccb, nvme_cb_fn_t cb_fn, void *cb_arg)
 504 {
 505         struct nvme_request *req;
 506
 507         req = _nvme_allocate_request(cb_fn, cb_arg);
 508         if (req != NULL) {
 509                 req->type = NVME_REQUEST_CCB;
 510                 req->u.payload = ccb;
 511         }
 512
 513         return (req);
 514 }
 515
 516 #define nvme_free_request(req)  uma_zfree(nvme_request_zone, req)
 517
 518 void    nvme_notify_async_consumers(struct nvme_controller *ctrlr,
 519                                     const struct nvme_completion *async_cpl,
 520                                     uint32_t log_page_id, void *log_page_buffer,
 521                                     uint32_t log_page_size);
 522 void    nvme_notify_fail_consumers(struct nvme_controller *ctrlr);
 523 void    nvme_notify_new_controller(struct nvme_controller *ctrlr);
 524 void    nvme_notify_ns(struct nvme_controller *ctrlr, int nsid);
 525
 526 void    nvme_ctrlr_intx_handler(void *arg);
 527 void    nvme_ctrlr_poll(struct nvme_controller *ctrlr);
 528
 529 #endif /* __NVME_PRIVATE_H__ */