2 * Copyright (C) 2012-2014 Intel Corporation
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #ifndef __NVME_PRIVATE_H__
30 #define __NVME_PRIVATE_H__
32 #include <sys/param.h>
35 #include <sys/kernel.h>
37 #include <sys/malloc.h>
38 #include <sys/mutex.h>
40 #include <sys/systm.h>
41 #include <sys/taskqueue.h>
45 #include <machine/bus.h>
49 #define DEVICE2SOFTC(dev) ((struct nvme_controller *) device_get_softc(dev))
51 MALLOC_DECLARE(M_NVME);
53 #define IDT32_PCI_ID 0x80d0111d /* 32 channel board */
54 #define IDT8_PCI_ID 0x80d2111d /* 8 channel board */
57 * For commands requiring more than 2 PRP entries, one PRP will be
58 * embedded in the command (prp1), and the rest of the PRP entries
59 * will be in a list pointed to by the command (prp2). This means
60 * that real max number of PRP entries we support is 32+1, which
61 * results in a max xfer size of 32*PAGE_SIZE.
63 #define NVME_MAX_PRP_LIST_ENTRIES (NVME_MAX_XFER_SIZE / PAGE_SIZE)
65 #define NVME_ADMIN_TRACKERS (16)
66 #define NVME_ADMIN_ENTRIES (128)
67 /* min and max are defined in admin queue attributes section of spec */
68 #define NVME_MIN_ADMIN_ENTRIES (2)
69 #define NVME_MAX_ADMIN_ENTRIES (4096)
72 * NVME_IO_ENTRIES defines the size of an I/O qpair's submission and completion
73 * queues, while NVME_IO_TRACKERS defines the maximum number of I/O that we
74 * will allow outstanding on an I/O qpair at any time. The only advantage in
75 * having IO_ENTRIES > IO_TRACKERS is for debugging purposes - when dumping
76 * the contents of the submission and completion queues, it will show a longer
79 #define NVME_IO_ENTRIES (256)
80 #define NVME_IO_TRACKERS (128)
81 #define NVME_MIN_IO_TRACKERS (4)
82 #define NVME_MAX_IO_TRACKERS (1024)
85 * NVME_MAX_IO_ENTRIES is not defined, since it is specified in CC.MQES
86 * for each controller.
89 #define NVME_INT_COAL_TIME (0) /* disabled */
90 #define NVME_INT_COAL_THRESHOLD (0) /* 0-based */
92 #define NVME_MAX_NAMESPACES (16)
93 #define NVME_MAX_CONSUMERS (2)
94 #define NVME_MAX_ASYNC_EVENTS (8)
96 #define NVME_DEFAULT_TIMEOUT_PERIOD (30) /* in seconds */
97 #define NVME_MIN_TIMEOUT_PERIOD (5)
98 #define NVME_MAX_TIMEOUT_PERIOD (120)
100 #define NVME_DEFAULT_RETRY_COUNT (4)
102 /* Maximum log page size to fetch for AERs. */
103 #define NVME_MAX_AER_LOG_SIZE (4096)
106 * Define CACHE_LINE_SIZE here for older FreeBSD versions that do not define
109 #ifndef CACHE_LINE_SIZE
110 #define CACHE_LINE_SIZE (64)
114 * Use presence of the BIO_UNMAPPED flag to determine whether unmapped I/O
115 * support and the bus_dmamap_load_bio API are available on the target
116 * kernel. This will ease porting back to earlier stable branches at a
120 #define NVME_UNMAPPED_BIO_SUPPORT
123 extern uma_zone_t nvme_request_zone;
124 extern int32_t nvme_retry_count;
126 struct nvme_completion_poll_status {
128 struct nvme_completion cpl;
132 #define NVME_REQUEST_VADDR 1
133 #define NVME_REQUEST_NULL 2 /* For requests with no payload. */
134 #define NVME_REQUEST_UIO 3
135 #ifdef NVME_UNMAPPED_BIO_SUPPORT
136 #define NVME_REQUEST_BIO 4
139 struct nvme_request {
141 struct nvme_command cmd;
142 struct nvme_qpair *qpair;
148 uint32_t payload_size;
153 STAILQ_ENTRY(nvme_request) stailq;
156 struct nvme_async_event_request {
158 struct nvme_controller *ctrlr;
159 struct nvme_request *req;
160 struct nvme_completion cpl;
161 uint32_t log_page_id;
162 uint32_t log_page_size;
163 uint8_t log_page_buffer[NVME_MAX_AER_LOG_SIZE];
166 struct nvme_tracker {
168 TAILQ_ENTRY(nvme_tracker) tailq;
169 struct nvme_request *req;
170 struct nvme_qpair *qpair;
171 struct callout timer;
172 bus_dmamap_t payload_dma_map;
176 bus_addr_t prp_bus_addr;
181 struct nvme_controller *ctrlr;
187 struct resource *res;
190 uint32_t num_entries;
191 uint32_t num_trackers;
192 uint32_t sq_tdbl_off;
193 uint32_t cq_hdbl_off;
200 int64_t num_intr_handler_calls;
202 struct nvme_command *cmd;
203 struct nvme_completion *cpl;
205 bus_dma_tag_t dma_tag;
206 bus_dma_tag_t dma_tag_payload;
208 bus_dmamap_t queuemem_map;
209 uint64_t cmd_bus_addr;
210 uint64_t cpl_bus_addr;
212 TAILQ_HEAD(, nvme_tracker) free_tr;
213 TAILQ_HEAD(, nvme_tracker) outstanding_tr;
214 STAILQ_HEAD(, nvme_request) queued_req;
216 struct nvme_tracker **act_tr;
218 boolean_t is_enabled;
220 struct mtx lock __aligned(CACHE_LINE_SIZE);
222 } __aligned(CACHE_LINE_SIZE);
224 struct nvme_namespace {
226 struct nvme_controller *ctrlr;
227 struct nvme_namespace_data data;
231 void *cons_cookie[NVME_MAX_CONSUMERS];
237 * One of these per allocated PCI device.
239 struct nvme_controller {
245 uint32_t ready_timeout_in_ms;
247 bus_space_tag_t bus_tag;
248 bus_space_handle_t bus_handle;
250 struct resource *resource;
253 * The NVMe spec allows for the MSI-X table to be placed in BAR 4/5,
254 * separate from the control registers which are in BAR 0/1. These
255 * members track the mapping of BAR 4/5 for that reason.
257 int bar4_resource_id;
258 struct resource *bar4_resource;
260 uint32_t msix_enabled;
262 uint32_t enable_aborts;
264 uint32_t num_io_queues;
265 uint32_t num_cpus_per_ioq;
267 /* Fields for tracking progress during controller initialization. */
268 struct intr_config_hook config_hook;
269 uint32_t ns_identified;
270 uint32_t queues_created;
272 struct task reset_task;
273 struct task fail_req_task;
274 struct taskqueue *taskqueue;
276 /* For shared legacy interrupt. */
278 struct resource *res;
281 bus_dma_tag_t hw_desc_tag;
282 bus_dmamap_t hw_desc_map;
284 /** maximum i/o size in bytes */
285 uint32_t max_xfer_size;
287 /** minimum page size supported by this controller in bytes */
288 uint32_t min_page_size;
290 /** interrupt coalescing time period (in microseconds) */
291 uint32_t int_coal_time;
293 /** interrupt coalescing threshold */
294 uint32_t int_coal_threshold;
296 /** timeout period in seconds */
297 uint32_t timeout_period;
299 struct nvme_qpair adminq;
300 struct nvme_qpair *ioq;
302 struct nvme_registers *regs;
304 struct nvme_controller_data cdata;
305 struct nvme_namespace ns[NVME_MAX_NAMESPACES];
309 /** bit mask of warning types currently enabled for async events */
310 union nvme_critical_warning_state async_event_config;
313 struct nvme_async_event_request aer[NVME_MAX_ASYNC_EVENTS];
315 void *cons_cookie[NVME_MAX_CONSUMERS];
317 uint32_t is_resetting;
318 uint32_t is_initialized;
319 uint32_t notification_sent;
322 STAILQ_HEAD(, nvme_request) fail_req;
325 #define nvme_mmio_offsetof(reg) \
326 offsetof(struct nvme_registers, reg)
328 #define nvme_mmio_read_4(sc, reg) \
329 bus_space_read_4((sc)->bus_tag, (sc)->bus_handle, \
330 nvme_mmio_offsetof(reg))
332 #define nvme_mmio_write_4(sc, reg, val) \
333 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \
334 nvme_mmio_offsetof(reg), val)
336 #define nvme_mmio_write_8(sc, reg, val) \
338 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \
339 nvme_mmio_offsetof(reg), val & 0xFFFFFFFF); \
340 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \
341 nvme_mmio_offsetof(reg)+4, \
342 (val & 0xFFFFFFFF00000000UL) >> 32); \
345 #if __FreeBSD_version < 800054
346 #define wmb() __asm volatile("sfence" ::: "memory")
347 #define mb() __asm volatile("mfence" ::: "memory")
350 #define nvme_printf(ctrlr, fmt, args...) \
351 device_printf(ctrlr->dev, fmt, ##args)
353 void nvme_ns_test(struct nvme_namespace *ns, u_long cmd, caddr_t arg);
355 void nvme_ctrlr_cmd_identify_controller(struct nvme_controller *ctrlr,
357 nvme_cb_fn_t cb_fn, void *cb_arg);
358 void nvme_ctrlr_cmd_identify_namespace(struct nvme_controller *ctrlr,
359 uint16_t nsid, void *payload,
360 nvme_cb_fn_t cb_fn, void *cb_arg);
361 void nvme_ctrlr_cmd_set_interrupt_coalescing(struct nvme_controller *ctrlr,
362 uint32_t microseconds,
366 void nvme_ctrlr_cmd_get_error_page(struct nvme_controller *ctrlr,
367 struct nvme_error_information_entry *payload,
368 uint32_t num_entries, /* 0 = max */
371 void nvme_ctrlr_cmd_get_health_information_page(struct nvme_controller *ctrlr,
373 struct nvme_health_information_page *payload,
376 void nvme_ctrlr_cmd_get_firmware_page(struct nvme_controller *ctrlr,
377 struct nvme_firmware_page *payload,
380 void nvme_ctrlr_cmd_create_io_cq(struct nvme_controller *ctrlr,
381 struct nvme_qpair *io_que, uint16_t vector,
382 nvme_cb_fn_t cb_fn, void *cb_arg);
383 void nvme_ctrlr_cmd_create_io_sq(struct nvme_controller *ctrlr,
384 struct nvme_qpair *io_que,
385 nvme_cb_fn_t cb_fn, void *cb_arg);
386 void nvme_ctrlr_cmd_delete_io_cq(struct nvme_controller *ctrlr,
387 struct nvme_qpair *io_que,
388 nvme_cb_fn_t cb_fn, void *cb_arg);
389 void nvme_ctrlr_cmd_delete_io_sq(struct nvme_controller *ctrlr,
390 struct nvme_qpair *io_que,
391 nvme_cb_fn_t cb_fn, void *cb_arg);
392 void nvme_ctrlr_cmd_set_num_queues(struct nvme_controller *ctrlr,
393 uint32_t num_queues, nvme_cb_fn_t cb_fn,
395 void nvme_ctrlr_cmd_set_async_event_config(struct nvme_controller *ctrlr,
396 union nvme_critical_warning_state state,
397 nvme_cb_fn_t cb_fn, void *cb_arg);
398 void nvme_ctrlr_cmd_abort(struct nvme_controller *ctrlr, uint16_t cid,
399 uint16_t sqid, nvme_cb_fn_t cb_fn, void *cb_arg);
401 void nvme_completion_poll_cb(void *arg, const struct nvme_completion *cpl);
403 int nvme_ctrlr_construct(struct nvme_controller *ctrlr, device_t dev);
404 void nvme_ctrlr_destruct(struct nvme_controller *ctrlr, device_t dev);
405 void nvme_ctrlr_shutdown(struct nvme_controller *ctrlr);
406 int nvme_ctrlr_hw_reset(struct nvme_controller *ctrlr);
407 void nvme_ctrlr_reset(struct nvme_controller *ctrlr);
408 /* ctrlr defined as void * to allow use with config_intrhook. */
409 void nvme_ctrlr_start_config_hook(void *ctrlr_arg);
410 void nvme_ctrlr_submit_admin_request(struct nvme_controller *ctrlr,
411 struct nvme_request *req);
412 void nvme_ctrlr_submit_io_request(struct nvme_controller *ctrlr,
413 struct nvme_request *req);
414 void nvme_ctrlr_post_failed_request(struct nvme_controller *ctrlr,
415 struct nvme_request *req);
417 int nvme_qpair_construct(struct nvme_qpair *qpair, uint32_t id,
418 uint16_t vector, uint32_t num_entries,
419 uint32_t num_trackers,
420 struct nvme_controller *ctrlr);
421 void nvme_qpair_submit_tracker(struct nvme_qpair *qpair,
422 struct nvme_tracker *tr);
423 void nvme_qpair_process_completions(struct nvme_qpair *qpair);
424 void nvme_qpair_submit_request(struct nvme_qpair *qpair,
425 struct nvme_request *req);
426 void nvme_qpair_reset(struct nvme_qpair *qpair);
427 void nvme_qpair_fail(struct nvme_qpair *qpair);
428 void nvme_qpair_manual_complete_request(struct nvme_qpair *qpair,
429 struct nvme_request *req,
430 uint32_t sct, uint32_t sc,
431 boolean_t print_on_error);
433 void nvme_admin_qpair_enable(struct nvme_qpair *qpair);
434 void nvme_admin_qpair_disable(struct nvme_qpair *qpair);
435 void nvme_admin_qpair_destroy(struct nvme_qpair *qpair);
437 void nvme_io_qpair_enable(struct nvme_qpair *qpair);
438 void nvme_io_qpair_disable(struct nvme_qpair *qpair);
439 void nvme_io_qpair_destroy(struct nvme_qpair *qpair);
441 int nvme_ns_construct(struct nvme_namespace *ns, uint16_t id,
442 struct nvme_controller *ctrlr);
443 void nvme_ns_destruct(struct nvme_namespace *ns);
445 void nvme_sysctl_initialize_ctrlr(struct nvme_controller *ctrlr);
447 void nvme_dump_command(struct nvme_command *cmd);
448 void nvme_dump_completion(struct nvme_completion *cpl);
451 nvme_single_map(void *arg, bus_dma_segment_t *seg, int nseg, int error)
453 uint64_t *bus_addr = (uint64_t *)arg;
456 printf("nvme_single_map err %d\n", error);
457 *bus_addr = seg[0].ds_addr;
460 static __inline struct nvme_request *
461 _nvme_allocate_request(nvme_cb_fn_t cb_fn, void *cb_arg)
463 struct nvme_request *req;
465 req = uma_zalloc(nvme_request_zone, M_NOWAIT | M_ZERO);
468 req->cb_arg = cb_arg;
474 static __inline struct nvme_request *
475 nvme_allocate_request_vaddr(void *payload, uint32_t payload_size,
476 nvme_cb_fn_t cb_fn, void *cb_arg)
478 struct nvme_request *req;
480 req = _nvme_allocate_request(cb_fn, cb_arg);
482 req->type = NVME_REQUEST_VADDR;
483 req->u.payload = payload;
484 req->payload_size = payload_size;
489 static __inline struct nvme_request *
490 nvme_allocate_request_null(nvme_cb_fn_t cb_fn, void *cb_arg)
492 struct nvme_request *req;
494 req = _nvme_allocate_request(cb_fn, cb_arg);
496 req->type = NVME_REQUEST_NULL;
500 static __inline struct nvme_request *
501 nvme_allocate_request_bio(struct bio *bio, nvme_cb_fn_t cb_fn, void *cb_arg)
503 struct nvme_request *req;
505 req = _nvme_allocate_request(cb_fn, cb_arg);
507 #ifdef NVME_UNMAPPED_BIO_SUPPORT
508 req->type = NVME_REQUEST_BIO;
511 req->type = NVME_REQUEST_VADDR;
512 req->u.payload = bio->bio_data;
513 req->payload_size = bio->bio_bcount;
519 #define nvme_free_request(req) uma_zfree(nvme_request_zone, req)
521 void nvme_notify_async_consumers(struct nvme_controller *ctrlr,
522 const struct nvme_completion *async_cpl,
523 uint32_t log_page_id, void *log_page_buffer,
524 uint32_t log_page_size);
525 void nvme_notify_fail_consumers(struct nvme_controller *ctrlr);
526 void nvme_notify_new_controller(struct nvme_controller *ctrlr);
528 void nvme_ctrlr_intx_handler(void *arg);
530 #endif /* __NVME_PRIVATE_H__ */