2 * Copyright (C) 2012 Intel Corporation
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #ifndef __NVME_PRIVATE_H__
30 #define __NVME_PRIVATE_H__
32 #include <sys/param.h>
33 #include <sys/kernel.h>
35 #include <sys/malloc.h>
36 #include <sys/mutex.h>
38 #include <sys/systm.h>
42 #include <machine/bus.h>
46 #define DEVICE2SOFTC(dev) ((struct nvme_controller *) device_get_softc(dev))
48 MALLOC_DECLARE(M_NVME);
53 #define CHATHAM_PCI_ID 0x20118086
54 #define CHATHAM_CONTROL_BAR 0
57 #define IDT32_PCI_ID 0x80d0111d /* 32 channel board */
58 #define IDT8_PCI_ID 0x80d2111d /* 8 channel board */
60 #define NVME_MAX_PRP_LIST_ENTRIES (32)
63 * For commands requiring more than 2 PRP entries, one PRP will be
64 * embedded in the command (prp1), and the rest of the PRP entries
65 * will be in a list pointed to by the command (prp2). This means
66 * that real max number of PRP entries we support is 32+1, which
67 * results in a max xfer size of 32*PAGE_SIZE.
69 #define NVME_MAX_XFER_SIZE NVME_MAX_PRP_LIST_ENTRIES * PAGE_SIZE
71 #define NVME_ADMIN_TRACKERS (16)
72 #define NVME_ADMIN_ENTRIES (128)
73 /* min and max are defined in admin queue attributes section of spec */
74 #define NVME_MIN_ADMIN_ENTRIES (2)
75 #define NVME_MAX_ADMIN_ENTRIES (4096)
78 * NVME_IO_ENTRIES defines the size of an I/O qpair's submission and completion
79 * queues, while NVME_IO_TRACKERS defines the maximum number of I/O that we
80 * will allow outstanding on an I/O qpair at any time. The only advantage in
81 * having IO_ENTRIES > IO_TRACKERS is for debugging purposes - when dumping
82 * the contents of the submission and completion queues, it will show a longer
85 #define NVME_IO_ENTRIES (256)
86 #define NVME_IO_TRACKERS (128)
87 #define NVME_MIN_IO_TRACKERS (16)
88 #define NVME_MAX_IO_TRACKERS (1024)
91 * NVME_MAX_IO_ENTRIES is not defined, since it is specified in CC.MQES
92 * for each controller.
95 #define NVME_INT_COAL_TIME (0) /* disabled */
96 #define NVME_INT_COAL_THRESHOLD (0) /* 0-based */
98 #define NVME_MAX_NAMESPACES (16)
99 #define NVME_MAX_CONSUMERS (2)
100 #define NVME_MAX_ASYNC_EVENTS (8)
102 #define NVME_TIMEOUT_IN_SEC (30)
104 #ifndef CACHE_LINE_SIZE
105 #define CACHE_LINE_SIZE (64)
108 extern uma_zone_t nvme_request_zone;
110 struct nvme_request {
112 struct nvme_command cmd;
114 uint32_t payload_size;
119 STAILQ_ENTRY(nvme_request) stailq;
122 struct nvme_async_event_request {
124 struct nvme_controller *ctrlr;
125 struct nvme_request *req;
128 struct nvme_tracker {
130 SLIST_ENTRY(nvme_tracker) slist;
131 struct nvme_request *req;
132 struct nvme_qpair *qpair;
133 struct callout timer;
134 bus_dmamap_t payload_dma_map;
137 uint64_t prp[NVME_MAX_PRP_LIST_ENTRIES];
138 bus_addr_t prp_bus_addr;
139 bus_dmamap_t prp_dma_map;
144 struct nvme_controller *ctrlr;
150 struct resource *res;
153 uint32_t max_xfer_size;
154 uint32_t num_entries;
155 uint32_t num_trackers;
156 uint32_t sq_tdbl_off;
157 uint32_t cq_hdbl_off;
164 int64_t num_intr_handler_calls;
166 struct nvme_command *cmd;
167 struct nvme_completion *cpl;
169 bus_dma_tag_t dma_tag;
171 bus_dmamap_t cmd_dma_map;
172 uint64_t cmd_bus_addr;
174 bus_dmamap_t cpl_dma_map;
175 uint64_t cpl_bus_addr;
177 SLIST_HEAD(, nvme_tracker) free_tr;
178 STAILQ_HEAD(, nvme_request) queued_req;
180 struct nvme_tracker **act_tr;
182 struct mtx lock __aligned(CACHE_LINE_SIZE);
184 } __aligned(CACHE_LINE_SIZE);
186 struct nvme_namespace {
188 struct nvme_controller *ctrlr;
189 struct nvme_namespace_data data;
193 void *cons_cookie[NVME_MAX_CONSUMERS];
197 * One of these per allocated PCI device.
199 struct nvme_controller {
203 uint32_t ready_timeout_in_ms;
205 bus_space_tag_t bus_tag;
206 bus_space_handle_t bus_handle;
208 struct resource *resource;
211 * The NVMe spec allows for the MSI-X table to be placed in BAR 4/5,
212 * separate from the control registers which are in BAR 0/1. These
213 * members track the mapping of BAR 4/5 for that reason.
215 int bar4_resource_id;
216 struct resource *bar4_resource;
219 bus_space_tag_t chatham_bus_tag;
220 bus_space_handle_t chatham_bus_handle;
221 int chatham_resource_id;
222 struct resource *chatham_resource;
225 uint32_t msix_enabled;
228 uint32_t num_io_queues;
229 boolean_t per_cpu_io_queues;
231 /* Fields for tracking progress during controller initialization. */
232 struct intr_config_hook config_hook;
233 uint32_t ns_identified;
234 uint32_t queues_created;
236 /* For shared legacy interrupt. */
238 struct resource *res;
241 bus_dma_tag_t hw_desc_tag;
242 bus_dmamap_t hw_desc_map;
244 /** maximum i/o size in bytes */
245 uint32_t max_xfer_size;
247 /** interrupt coalescing time period (in microseconds) */
248 uint32_t int_coal_time;
250 /** interrupt coalescing threshold */
251 uint32_t int_coal_threshold;
253 struct nvme_qpair adminq;
254 struct nvme_qpair *ioq;
256 struct nvme_registers *regs;
258 struct nvme_controller_data cdata;
259 struct nvme_namespace ns[NVME_MAX_NAMESPACES];
263 boolean_t is_started;
266 struct nvme_async_event_request aer[NVME_MAX_ASYNC_EVENTS];
268 void *cons_cookie[NVME_MAX_CONSUMERS];
271 uint64_t chatham_size;
272 uint64_t chatham_lbas;
276 #define nvme_mmio_offsetof(reg) \
277 offsetof(struct nvme_registers, reg)
279 #define nvme_mmio_read_4(sc, reg) \
280 bus_space_read_4((sc)->bus_tag, (sc)->bus_handle, \
281 nvme_mmio_offsetof(reg))
283 #define nvme_mmio_write_4(sc, reg, val) \
284 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \
285 nvme_mmio_offsetof(reg), val)
287 #define nvme_mmio_write_8(sc, reg, val) \
289 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \
290 nvme_mmio_offsetof(reg), val & 0xFFFFFFFF); \
291 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \
292 nvme_mmio_offsetof(reg)+4, \
293 (val & 0xFFFFFFFF00000000UL) >> 32); \
297 #define chatham_read_4(softc, reg) \
298 bus_space_read_4((softc)->chatham_bus_tag, \
299 (softc)->chatham_bus_handle, reg)
301 #define chatham_write_8(sc, reg, val) \
303 bus_space_write_4((sc)->chatham_bus_tag, \
304 (sc)->chatham_bus_handle, reg, val & 0xffffffff); \
305 bus_space_write_4((sc)->chatham_bus_tag, \
306 (sc)->chatham_bus_handle, reg+4, \
307 (val & 0xFFFFFFFF00000000UL) >> 32); \
310 #endif /* CHATHAM2 */
312 #if __FreeBSD_version < 800054
313 #define wmb() __asm volatile("sfence" ::: "memory")
314 #define mb() __asm volatile("mfence" ::: "memory")
317 void nvme_ns_test(struct nvme_namespace *ns, u_long cmd, caddr_t arg);
319 void nvme_ctrlr_cmd_identify_controller(struct nvme_controller *ctrlr,
321 nvme_cb_fn_t cb_fn, void *cb_arg);
322 void nvme_ctrlr_cmd_identify_namespace(struct nvme_controller *ctrlr,
323 uint16_t nsid, void *payload,
324 nvme_cb_fn_t cb_fn, void *cb_arg);
325 void nvme_ctrlr_cmd_set_interrupt_coalescing(struct nvme_controller *ctrlr,
326 uint32_t microseconds,
330 void nvme_ctrlr_cmd_get_health_information_page(struct nvme_controller *ctrlr,
332 struct nvme_health_information_page *payload,
335 void nvme_ctrlr_cmd_create_io_cq(struct nvme_controller *ctrlr,
336 struct nvme_qpair *io_que, uint16_t vector,
337 nvme_cb_fn_t cb_fn, void *cb_arg);
338 void nvme_ctrlr_cmd_create_io_sq(struct nvme_controller *ctrlr,
339 struct nvme_qpair *io_que,
340 nvme_cb_fn_t cb_fn, void *cb_arg);
341 void nvme_ctrlr_cmd_delete_io_cq(struct nvme_controller *ctrlr,
342 struct nvme_qpair *io_que,
343 nvme_cb_fn_t cb_fn, void *cb_arg);
344 void nvme_ctrlr_cmd_delete_io_sq(struct nvme_controller *ctrlr,
345 struct nvme_qpair *io_que,
346 nvme_cb_fn_t cb_fn, void *cb_arg);
347 void nvme_ctrlr_cmd_set_num_queues(struct nvme_controller *ctrlr,
348 uint32_t num_queues, nvme_cb_fn_t cb_fn,
350 void nvme_ctrlr_cmd_set_async_event_config(struct nvme_controller *ctrlr,
351 union nvme_critical_warning_state state,
352 nvme_cb_fn_t cb_fn, void *cb_arg);
353 void nvme_ctrlr_cmd_abort(struct nvme_controller *ctrlr, uint16_t cid,
354 uint16_t sqid, nvme_cb_fn_t cb_fn, void *cb_arg);
356 void nvme_payload_map(void *arg, bus_dma_segment_t *seg, int nseg,
358 void nvme_payload_map_uio(void *arg, bus_dma_segment_t *seg, int nseg,
359 bus_size_t mapsize, int error);
361 int nvme_ctrlr_construct(struct nvme_controller *ctrlr, device_t dev);
362 void nvme_ctrlr_destruct(struct nvme_controller *ctrlr, device_t dev);
363 int nvme_ctrlr_reset(struct nvme_controller *ctrlr);
364 /* ctrlr defined as void * to allow use with config_intrhook. */
365 void nvme_ctrlr_start(void *ctrlr_arg);
366 void nvme_ctrlr_submit_admin_request(struct nvme_controller *ctrlr,
367 struct nvme_request *req);
368 void nvme_ctrlr_submit_io_request(struct nvme_controller *ctrlr,
369 struct nvme_request *req);
371 void nvme_qpair_construct(struct nvme_qpair *qpair, uint32_t id,
372 uint16_t vector, uint32_t num_entries,
373 uint32_t num_trackers, uint32_t max_xfer_size,
374 struct nvme_controller *ctrlr);
375 void nvme_qpair_submit_cmd(struct nvme_qpair *qpair,
376 struct nvme_tracker *tr);
377 void nvme_qpair_process_completions(struct nvme_qpair *qpair);
378 void nvme_qpair_submit_request(struct nvme_qpair *qpair,
379 struct nvme_request *req);
380 void nvme_qpair_manual_abort_request(struct nvme_qpair *qpair,
381 struct nvme_request *req, uint32_t sct,
382 uint32_t sc, boolean_t print_on_error);
384 void nvme_admin_qpair_destroy(struct nvme_qpair *qpair);
386 void nvme_io_qpair_destroy(struct nvme_qpair *qpair);
388 int nvme_ns_construct(struct nvme_namespace *ns, uint16_t id,
389 struct nvme_controller *ctrlr);
391 int nvme_ns_physio(struct cdev *dev, struct uio *uio, int ioflag);
393 void nvme_sysctl_initialize_ctrlr(struct nvme_controller *ctrlr);
395 void nvme_dump_command(struct nvme_command *cmd);
396 void nvme_dump_completion(struct nvme_completion *cpl);
399 nvme_single_map(void *arg, bus_dma_segment_t *seg, int nseg, int error)
401 uint64_t *bus_addr = (uint64_t *)arg;
403 *bus_addr = seg[0].ds_addr;
406 static __inline struct nvme_request *
407 nvme_allocate_request(void *payload, uint32_t payload_size, nvme_cb_fn_t cb_fn,
410 struct nvme_request *req;
412 req = uma_zalloc(nvme_request_zone, M_NOWAIT | M_ZERO);
416 req->payload = payload;
417 req->payload_size = payload_size;
419 req->cb_arg = cb_arg;
420 req->timeout = NVME_TIMEOUT_IN_SEC;
425 static __inline struct nvme_request *
426 nvme_allocate_request_uio(struct uio *uio, nvme_cb_fn_t cb_fn, void *cb_arg)
428 struct nvme_request *req;
430 req = uma_zalloc(nvme_request_zone, M_NOWAIT | M_ZERO);
436 req->cb_arg = cb_arg;
437 req->timeout = NVME_TIMEOUT_IN_SEC;
442 #define nvme_free_request(req) uma_zfree(nvme_request_zone, req)
444 void nvme_notify_async_consumers(struct nvme_controller *ctrlr,
445 const struct nvme_completion *async_cpl);
447 #endif /* __NVME_PRIVATE_H__ */